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113 <li class="toctree-l3 current"><a class="current reference internal" href="#">AM64X Devices Descriptions</a><ul>
114 <li class="toctree-l4"><a class="reference internal" href="#introduction">Introduction</a></li>
115 <li class="toctree-l4"><a class="reference internal" href="#enumeration-of-device-ids">Enumeration of Device IDs</a></li>
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122 <li class="toctree-l3"><a class="reference internal" href="ra_cfg.html">AM64X Ring Accelerator Device Descriptions</a></li>
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183 <div class="section" id="am64x-devices-descriptions">
184 <h1>AM64X Devices Descriptions<a class="headerlink" href="#am64x-devices-descriptions" title="Permalink to this headline">¶</a></h1>
185 <div class="section" id="introduction">
186 <span id="soc-doc-am64x-public-devices-desc-intro"></span><h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
187 <p>This chapter provides information on Device IDs that are permitted in the am64x
188 SoC. The device IDs represent SoC subsystems that can be modified via DMSC
189 TISCI message APIs. Some Secure, Power, and Resource Management DMSC subsystem
190 TISCI message APIs define a device ID as a parameter allowing a user to specify
191 management of a particular SoC subsystem.</p>
192 </div>
193 <div class="section" id="enumeration-of-device-ids">
194 <span id="soc-doc-am64x-public-devices-desc-device-list"></span><h2>Enumeration of Device IDs<a class="headerlink" href="#enumeration-of-device-ids" title="Permalink to this headline">¶</a></h2>
195 <table border="1" class="docutils">
196 <colgroup>
197 <col width="25%" />
198 <col width="75%" />
199 </colgroup>
200 <thead valign="bottom">
201 <tr class="row-odd"><th class="head">Device ID</th>
202 <th class="head">Device Name</th>
203 </tr>
204 </thead>
205 <tbody valign="top">
206 <tr class="row-even"><td>0</td>
207 <td>AM64X_DEV_ADC0</td>
208 </tr>
209 <tr class="row-odd"><td>1</td>
210 <td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
211 </tr>
212 <tr class="row-even"><td>2</td>
213 <td>AM64X_DEV_DBGSUSPENDROUTER0</td>
214 </tr>
215 <tr class="row-odd"><td>3</td>
216 <td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
217 </tr>
218 <tr class="row-even"><td>5</td>
219 <td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
220 </tr>
221 <tr class="row-odd"><td>6</td>
222 <td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
223 </tr>
224 <tr class="row-even"><td>7</td>
225 <td>AM64X_DEV_MCU_M4FSS0</td>
226 </tr>
227 <tr class="row-odd"><td>9</td>
228 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
229 </tr>
230 <tr class="row-even"><td>13</td>
231 <td>AM64X_DEV_CPSW0</td>
232 </tr>
233 <tr class="row-odd"><td>14</td>
234 <td>AM64X_DEV_CPT2_AGGR0</td>
235 </tr>
236 <tr class="row-even"><td>15</td>
237 <td>AM64X_DEV_STM0</td>
238 </tr>
239 <tr class="row-odd"><td>16</td>
240 <td>AM64X_DEV_DCC0</td>
241 </tr>
242 <tr class="row-even"><td>17</td>
243 <td>AM64X_DEV_DCC1</td>
244 </tr>
245 <tr class="row-odd"><td>18</td>
246 <td>AM64X_DEV_DCC2</td>
247 </tr>
248 <tr class="row-even"><td>19</td>
249 <td>AM64X_DEV_DCC3</td>
250 </tr>
251 <tr class="row-odd"><td>20</td>
252 <td>AM64X_DEV_DCC4</td>
253 </tr>
254 <tr class="row-even"><td>21</td>
255 <td>AM64X_DEV_DCC5</td>
256 </tr>
257 <tr class="row-odd"><td>22</td>
258 <td>AM64X_DEV_DMSC0</td>
259 </tr>
260 <tr class="row-even"><td>23</td>
261 <td>AM64X_DEV_MCU_DCC0</td>
262 </tr>
263 <tr class="row-odd"><td>24</td>
264 <td>AM64X_DEV_DEBUGSS_WRAP0</td>
265 </tr>
266 <tr class="row-even"><td>25</td>
267 <td>AM64X_DEV_DMASS0</td>
268 </tr>
269 <tr class="row-odd"><td>26</td>
270 <td>AM64X_DEV_DMASS0_BCDMA_0</td>
271 </tr>
272 <tr class="row-even"><td>27</td>
273 <td>AM64X_DEV_DMASS0_CBASS_0</td>
274 </tr>
275 <tr class="row-odd"><td>28</td>
276 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
277 </tr>
278 <tr class="row-even"><td>29</td>
279 <td>AM64X_DEV_DMASS0_IPCSS_0</td>
280 </tr>
281 <tr class="row-odd"><td>30</td>
282 <td>AM64X_DEV_DMASS0_PKTDMA_0</td>
283 </tr>
284 <tr class="row-even"><td>31</td>
285 <td>AM64X_DEV_DMASS0_PSILCFG_0</td>
286 </tr>
287 <tr class="row-odd"><td>32</td>
288 <td>AM64X_DEV_DMASS0_PSILSS_0</td>
289 </tr>
290 <tr class="row-even"><td>33</td>
291 <td>AM64X_DEV_DMASS0_RINGACC_0</td>
292 </tr>
293 <tr class="row-odd"><td>35</td>
294 <td>AM64X_DEV_MCU_TIMER0</td>
295 </tr>
296 <tr class="row-even"><td>36</td>
297 <td>AM64X_DEV_TIMER0</td>
298 </tr>
299 <tr class="row-odd"><td>37</td>
300 <td>AM64X_DEV_TIMER1</td>
301 </tr>
302 <tr class="row-even"><td>38</td>
303 <td>AM64X_DEV_TIMER2</td>
304 </tr>
305 <tr class="row-odd"><td>39</td>
306 <td>AM64X_DEV_TIMER3</td>
307 </tr>
308 <tr class="row-even"><td>40</td>
309 <td>AM64X_DEV_TIMER4</td>
310 </tr>
311 <tr class="row-odd"><td>41</td>
312 <td>AM64X_DEV_TIMER5</td>
313 </tr>
314 <tr class="row-even"><td>42</td>
315 <td>AM64X_DEV_TIMER6</td>
316 </tr>
317 <tr class="row-odd"><td>43</td>
318 <td>AM64X_DEV_TIMER7</td>
319 </tr>
320 <tr class="row-even"><td>44</td>
321 <td>AM64X_DEV_TIMER8</td>
322 </tr>
323 <tr class="row-odd"><td>45</td>
324 <td>AM64X_DEV_TIMER9</td>
325 </tr>
326 <tr class="row-even"><td>46</td>
327 <td>AM64X_DEV_TIMER10</td>
328 </tr>
329 <tr class="row-odd"><td>47</td>
330 <td>AM64X_DEV_TIMER11</td>
331 </tr>
332 <tr class="row-even"><td>48</td>
333 <td>AM64X_DEV_MCU_TIMER1</td>
334 </tr>
335 <tr class="row-odd"><td>49</td>
336 <td>AM64X_DEV_MCU_TIMER2</td>
337 </tr>
338 <tr class="row-even"><td>50</td>
339 <td>AM64X_DEV_MCU_TIMER3</td>
340 </tr>
341 <tr class="row-odd"><td>51</td>
342 <td>AM64X_DEV_ECAP0</td>
343 </tr>
344 <tr class="row-even"><td>52</td>
345 <td>AM64X_DEV_ECAP1</td>
346 </tr>
347 <tr class="row-odd"><td>53</td>
348 <td>AM64X_DEV_ECAP2</td>
349 </tr>
350 <tr class="row-even"><td>54</td>
351 <td>AM64X_DEV_ELM0</td>
352 </tr>
353 <tr class="row-odd"><td>55</td>
354 <td>AM64X_DEV_EMIF_DATA_0_VD</td>
355 </tr>
356 <tr class="row-even"><td>57</td>
357 <td>AM64X_DEV_MMCSD0</td>
358 </tr>
359 <tr class="row-odd"><td>58</td>
360 <td>AM64X_DEV_MMCSD1</td>
361 </tr>
362 <tr class="row-even"><td>59</td>
363 <td>AM64X_DEV_EQEP0</td>
364 </tr>
365 <tr class="row-odd"><td>60</td>
366 <td>AM64X_DEV_EQEP1</td>
367 </tr>
368 <tr class="row-even"><td>61</td>
369 <td>AM64X_DEV_GTC0</td>
370 </tr>
371 <tr class="row-odd"><td>62</td>
372 <td>AM64X_DEV_EQEP2</td>
373 </tr>
374 <tr class="row-even"><td>63</td>
375 <td>AM64X_DEV_ESM0</td>
376 </tr>
377 <tr class="row-odd"><td>64</td>
378 <td>AM64X_DEV_MCU_ESM0</td>
379 </tr>
380 <tr class="row-even"><td>65</td>
381 <td>AM64X_DEV_FSIRX0</td>
382 </tr>
383 <tr class="row-odd"><td>66</td>
384 <td>AM64X_DEV_FSIRX1</td>
385 </tr>
386 <tr class="row-even"><td>67</td>
387 <td>AM64X_DEV_FSIRX2</td>
388 </tr>
389 <tr class="row-odd"><td>68</td>
390 <td>AM64X_DEV_FSIRX3</td>
391 </tr>
392 <tr class="row-even"><td>69</td>
393 <td>AM64X_DEV_FSIRX4</td>
394 </tr>
395 <tr class="row-odd"><td>70</td>
396 <td>AM64X_DEV_FSIRX5</td>
397 </tr>
398 <tr class="row-even"><td>71</td>
399 <td>AM64X_DEV_FSITX0</td>
400 </tr>
401 <tr class="row-odd"><td>72</td>
402 <td>AM64X_DEV_FSITX1</td>
403 </tr>
404 <tr class="row-even"><td>73</td>
405 <td>AM64X_DEV_FSS0</td>
406 </tr>
407 <tr class="row-odd"><td>74</td>
408 <td>AM64X_DEV_FSS0_FSAS_0</td>
409 </tr>
410 <tr class="row-even"><td>75</td>
411 <td>AM64X_DEV_FSS0_OSPI_0</td>
412 </tr>
413 <tr class="row-odd"><td>76</td>
414 <td>AM64X_DEV_GICSS0</td>
415 </tr>
416 <tr class="row-even"><td>77</td>
417 <td>AM64X_DEV_GPIO0</td>
418 </tr>
419 <tr class="row-odd"><td>78</td>
420 <td>AM64X_DEV_GPIO1</td>
421 </tr>
422 <tr class="row-even"><td>79</td>
423 <td>AM64X_DEV_MCU_GPIO0</td>
424 </tr>
425 <tr class="row-odd"><td>80</td>
426 <td>AM64X_DEV_GPMC0</td>
427 </tr>
428 <tr class="row-even"><td>81</td>
429 <td>AM64X_DEV_PRU_ICSSG0</td>
430 </tr>
431 <tr class="row-odd"><td>82</td>
432 <td>AM64X_DEV_PRU_ICSSG1</td>
433 </tr>
434 <tr class="row-even"><td>83</td>
435 <td>AM64X_DEV_LED0</td>
436 </tr>
437 <tr class="row-odd"><td>84</td>
438 <td>AM64X_DEV_CPTS0</td>
439 </tr>
440 <tr class="row-even"><td>85</td>
441 <td>AM64X_DEV_DDPA0</td>
442 </tr>
443 <tr class="row-odd"><td>86</td>
444 <td>AM64X_DEV_EPWM0</td>
445 </tr>
446 <tr class="row-even"><td>87</td>
447 <td>AM64X_DEV_EPWM1</td>
448 </tr>
449 <tr class="row-odd"><td>88</td>
450 <td>AM64X_DEV_EPWM2</td>
451 </tr>
452 <tr class="row-even"><td>89</td>
453 <td>AM64X_DEV_EPWM3</td>
454 </tr>
455 <tr class="row-odd"><td>90</td>
456 <td>AM64X_DEV_EPWM4</td>
457 </tr>
458 <tr class="row-even"><td>91</td>
459 <td>AM64X_DEV_EPWM5</td>
460 </tr>
461 <tr class="row-odd"><td>92</td>
462 <td>AM64X_DEV_EPWM6</td>
463 </tr>
464 <tr class="row-even"><td>93</td>
465 <td>AM64X_DEV_EPWM7</td>
466 </tr>
467 <tr class="row-odd"><td>94</td>
468 <td>AM64X_DEV_EPWM8</td>
469 </tr>
470 <tr class="row-even"><td>95</td>
471 <td>AM64X_DEV_VTM0</td>
472 </tr>
473 <tr class="row-odd"><td>96</td>
474 <td>AM64X_DEV_MAILBOX0</td>
475 </tr>
476 <tr class="row-even"><td>97</td>
477 <td>AM64X_DEV_MAIN2MCU_VD</td>
478 </tr>
479 <tr class="row-odd"><td>98</td>
480 <td>AM64X_DEV_MCAN0</td>
481 </tr>
482 <tr class="row-even"><td>99</td>
483 <td>AM64X_DEV_MCAN1</td>
484 </tr>
485 <tr class="row-odd"><td>100</td>
486 <td>AM64X_DEV_MCU_MCRC64_0</td>
487 </tr>
488 <tr class="row-even"><td>101</td>
489 <td>AM64X_DEV_MCU2MAIN_VD</td>
490 </tr>
491 <tr class="row-odd"><td>102</td>
492 <td>AM64X_DEV_I2C0</td>
493 </tr>
494 <tr class="row-even"><td>103</td>
495 <td>AM64X_DEV_I2C1</td>
496 </tr>
497 <tr class="row-odd"><td>104</td>
498 <td>AM64X_DEV_I2C2</td>
499 </tr>
500 <tr class="row-even"><td>105</td>
501 <td>AM64X_DEV_I2C3</td>
502 </tr>
503 <tr class="row-odd"><td>106</td>
504 <td>AM64X_DEV_MCU_I2C0</td>
505 </tr>
506 <tr class="row-even"><td>107</td>
507 <td>AM64X_DEV_MCU_I2C1</td>
508 </tr>
509 <tr class="row-odd"><td>108</td>
510 <td>AM64X_DEV_MSRAM_256K0</td>
511 </tr>
512 <tr class="row-even"><td>109</td>
513 <td>AM64X_DEV_MSRAM_256K1</td>
514 </tr>
515 <tr class="row-odd"><td>110</td>
516 <td>AM64X_DEV_MSRAM_256K2</td>
517 </tr>
518 <tr class="row-even"><td>111</td>
519 <td>AM64X_DEV_MSRAM_256K3</td>
520 </tr>
521 <tr class="row-odd"><td>112</td>
522 <td>AM64X_DEV_MSRAM_256K4</td>
523 </tr>
524 <tr class="row-even"><td>113</td>
525 <td>AM64X_DEV_MSRAM_256K5</td>
526 </tr>
527 <tr class="row-odd"><td>114</td>
528 <td>AM64X_DEV_PCIE0</td>
529 </tr>
530 <tr class="row-even"><td>115</td>
531 <td>AM64X_DEV_POSTDIV1_16FFT1</td>
532 </tr>
533 <tr class="row-odd"><td>116</td>
534 <td>AM64X_DEV_POSTDIV4_16FF0</td>
535 </tr>
536 <tr class="row-even"><td>117</td>
537 <td>AM64X_DEV_POSTDIV4_16FF2</td>
538 </tr>
539 <tr class="row-odd"><td>118</td>
540 <td>AM64X_DEV_PSRAMECC0</td>
541 </tr>
542 <tr class="row-even"><td>119</td>
543 <td>AM64X_DEV_R5FSS0</td>
544 </tr>
545 <tr class="row-odd"><td>120</td>
546 <td>AM64X_DEV_R5FSS1</td>
547 </tr>
548 <tr class="row-even"><td>121</td>
549 <td>AM64X_DEV_R5FSS0_CORE0</td>
550 </tr>
551 <tr class="row-odd"><td>122</td>
552 <td>AM64X_DEV_R5FSS0_CORE1</td>
553 </tr>
554 <tr class="row-even"><td>123</td>
555 <td>AM64X_DEV_R5FSS1_CORE0</td>
556 </tr>
557 <tr class="row-odd"><td>124</td>
558 <td>AM64X_DEV_R5FSS1_CORE1</td>
559 </tr>
560 <tr class="row-even"><td>125</td>
561 <td>AM64X_DEV_RTI0</td>
562 </tr>
563 <tr class="row-odd"><td>126</td>
564 <td>AM64X_DEV_RTI1</td>
565 </tr>
566 <tr class="row-even"><td>127</td>
567 <td>AM64X_DEV_RTI8</td>
568 </tr>
569 <tr class="row-odd"><td>128</td>
570 <td>AM64X_DEV_RTI9</td>
571 </tr>
572 <tr class="row-even"><td>130</td>
573 <td>AM64X_DEV_RTI10</td>
574 </tr>
575 <tr class="row-odd"><td>131</td>
576 <td>AM64X_DEV_RTI11</td>
577 </tr>
578 <tr class="row-even"><td>132</td>
579 <td>AM64X_DEV_MCU_RTI0</td>
580 </tr>
581 <tr class="row-odd"><td>133</td>
582 <td>AM64X_DEV_SA2_UL0</td>
583 </tr>
584 <tr class="row-even"><td>134</td>
585 <td>AM64X_DEV_COMPUTE_CLUSTER0</td>
586 </tr>
587 <tr class="row-odd"><td>135</td>
588 <td>AM64X_DEV_A53SS0_CORE_0</td>
589 </tr>
590 <tr class="row-even"><td>136</td>
591 <td>AM64X_DEV_A53SS0_CORE_1</td>
592 </tr>
593 <tr class="row-odd"><td>137</td>
594 <td>AM64X_DEV_A53SS0</td>
595 </tr>
596 <tr class="row-even"><td>138</td>
597 <td>AM64X_DEV_DDR16SS0</td>
598 </tr>
599 <tr class="row-odd"><td>139</td>
600 <td>AM64X_DEV_PSC0</td>
601 </tr>
602 <tr class="row-even"><td>140</td>
603 <td>AM64X_DEV_MCU_PSC0</td>
604 </tr>
605 <tr class="row-odd"><td>141</td>
606 <td>AM64X_DEV_MCSPI0</td>
607 </tr>
608 <tr class="row-even"><td>142</td>
609 <td>AM64X_DEV_MCSPI1</td>
610 </tr>
611 <tr class="row-odd"><td>143</td>
612 <td>AM64X_DEV_MCSPI2</td>
613 </tr>
614 <tr class="row-even"><td>144</td>
615 <td>AM64X_DEV_MCSPI3</td>
616 </tr>
617 <tr class="row-odd"><td>145</td>
618 <td>AM64X_DEV_MCSPI4</td>
619 </tr>
620 <tr class="row-even"><td>146</td>
621 <td>AM64X_DEV_UART0</td>
622 </tr>
623 <tr class="row-odd"><td>147</td>
624 <td>AM64X_DEV_MCU_MCSPI0</td>
625 </tr>
626 <tr class="row-even"><td>148</td>
627 <td>AM64X_DEV_MCU_MCSPI1</td>
628 </tr>
629 <tr class="row-odd"><td>149</td>
630 <td>AM64X_DEV_MCU_UART0</td>
631 </tr>
632 <tr class="row-even"><td>150</td>
633 <td>AM64X_DEV_SPINLOCK0</td>
634 </tr>
635 <tr class="row-odd"><td>151</td>
636 <td>AM64X_DEV_TIMERMGR0</td>
637 </tr>
638 <tr class="row-even"><td>152</td>
639 <td>AM64X_DEV_UART1</td>
640 </tr>
641 <tr class="row-odd"><td>153</td>
642 <td>AM64X_DEV_UART2</td>
643 </tr>
644 <tr class="row-even"><td>154</td>
645 <td>AM64X_DEV_UART3</td>
646 </tr>
647 <tr class="row-odd"><td>155</td>
648 <td>AM64X_DEV_UART4</td>
649 </tr>
650 <tr class="row-even"><td>156</td>
651 <td>AM64X_DEV_UART5</td>
652 </tr>
653 <tr class="row-odd"><td>157</td>
654 <td>AM64X_DEV_BOARD0</td>
655 </tr>
656 <tr class="row-even"><td>158</td>
657 <td>AM64X_DEV_UART6</td>
658 </tr>
659 <tr class="row-odd"><td>160</td>
660 <td>AM64X_DEV_MCU_UART1</td>
661 </tr>
662 <tr class="row-even"><td>161</td>
663 <td>AM64X_DEV_USB0</td>
664 </tr>
665 <tr class="row-odd"><td>162</td>
666 <td>AM64X_DEV_SERDES_10G0</td>
667 </tr>
668 <tr class="row-even"><td>163</td>
669 <td>AM64X_DEV_PBIST0</td>
670 </tr>
671 <tr class="row-odd"><td>164</td>
672 <td>AM64X_DEV_PBIST1</td>
673 </tr>
674 <tr class="row-even"><td>165</td>
675 <td>AM64X_DEV_PBIST2</td>
676 </tr>
677 <tr class="row-odd"><td>166</td>
678 <td>AM64X_DEV_PBIST3</td>
679 </tr>
680 <tr class="row-even"><td>167</td>
681 <td>AM64X_DEV_COMPUTE_CLUSTER0_PBIST_0</td>
682 </tr>
683 </tbody>
684 </table>
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