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113 <li class="toctree-l3 current"><a class="current reference internal" href="#">AM64X Interrupt Management Device Descriptions</a><ul>
114 <li class="toctree-l4"><a class="reference internal" href="#introduction">Introduction</a></li>
115 <li class="toctree-l4"><a class="reference internal" href="#interrupt-router-device-ids">Interrupt Router Device IDs</a></li>
116 <li class="toctree-l4"><a class="reference internal" href="#cmp-event-introuter0-interrupt-router-input-sources">CMP_EVENT_INTROUTER0 Interrupt Router Input Sources</a></li>
117 <li class="toctree-l4"><a class="reference internal" href="#cmp-event-introuter0-interrupt-router-output-destinations">CMP_EVENT_INTROUTER0 Interrupt Router Output Destinations</a></li>
118 <li class="toctree-l4"><a class="reference internal" href="#main-gpiomux-introuter0-interrupt-router-input-sources">MAIN_GPIOMUX_INTROUTER0 Interrupt Router Input Sources</a></li>
119 <li class="toctree-l4"><a class="reference internal" href="#main-gpiomux-introuter0-interrupt-router-output-destinations">MAIN_GPIOMUX_INTROUTER0 Interrupt Router Output Destinations</a></li>
120 <li class="toctree-l4"><a class="reference internal" href="#mcu-mcu-gpiomux-introuter0-interrupt-router-input-sources">MCU_MCU_GPIOMUX_INTROUTER0 Interrupt Router Input Sources</a></li>
121 <li class="toctree-l4"><a class="reference internal" href="#mcu-mcu-gpiomux-introuter0-interrupt-router-output-destinations">MCU_MCU_GPIOMUX_INTROUTER0 Interrupt Router Output Destinations</a></li>
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124 <li class="toctree-l4"><a class="reference internal" href="#interrupt-aggregator-device-ids">Interrupt Aggregator Device IDs</a></li>
125 <li class="toctree-l4"><a class="reference internal" href="#interrupt-aggregator-virtual-interrupts">Interrupt Aggregator Virtual Interrupts</a></li>
126 <li class="toctree-l4"><a class="reference internal" href="#dmass0-intaggr-0-interrupt-aggregator-virtual-interrupt-destinations">DMASS0_INTAGGR_0 Interrupt Aggregator Virtual Interrupt Destinations</a></li>
127 <li class="toctree-l4"><a class="reference internal" href="#global-events">Global Events</a></li>
128 <li class="toctree-l4"><a class="reference internal" href="#event-based-interrupt-source-ids">Event-Based Interrupt Source IDs</a></li>
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192 <div class="section" id="am64x-interrupt-management-device-descriptions">
193 <h1>AM64X Interrupt Management Device Descriptions<a class="headerlink" href="#am64x-interrupt-management-device-descriptions" title="Permalink to this headline">¶</a></h1>
194 <div class="section" id="introduction">
195 <h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
196 <p>This chapter provides information on the Interrupt Management devices in the
197 AM64X SoC. Some System Firmware TISCI messages take device specific inputs.
198 This chapter provides information on the valid values for Interrupt Management
199 TISCI message parameters.</p>
200 </div>
201 <div class="section" id="interrupt-router-device-ids">
202 <span id="pub-soc-am64x-ir-device-ids"></span><h2>Interrupt Router Device IDs<a class="headerlink" href="#interrupt-router-device-ids" title="Permalink to this headline">¶</a></h2>
203 <p>Some System Firmware TISCI message APIs require the Interrupt Router device ID
204 be provided as part of the request. Based on <a class="reference internal" href="devices.html"><span class="doc">AM64X Device IDs</span></a>
205 these are the valid Interrupt Router device IDs.</p>
206 <table border="1" class="docutils">
207 <colgroup>
208 <col width="56%" />
209 <col width="44%" />
210 </colgroup>
211 <thead valign="bottom">
212 <tr class="row-odd"><th class="head">Interrupt Router Device Name</th>
213 <th class="head">Interrupt Router Device ID</th>
214 </tr>
215 </thead>
216 <tbody valign="top">
217 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
218 <td>1</td>
219 </tr>
220 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
221 <td>3</td>
222 </tr>
223 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
224 <td>5</td>
225 </tr>
226 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
227 <td>6</td>
228 </tr>
229 </tbody>
230 </table>
231 </div>
232 <div class="section" id="cmp-event-introuter0-interrupt-router-input-sources">
233 <span id="pub-soc-am64x-cmp-event-introuter0-input-src-list"></span><h2>CMP_EVENT_INTROUTER0 Interrupt Router Input Sources<a class="headerlink" href="#cmp-event-introuter0-interrupt-router-input-sources" title="Permalink to this headline">¶</a></h2>
234 <div class="admonition warning">
235 <p class="first admonition-title">Warning</p>
236 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
237 host within the RM Board Configuration resource assignment array. The RM
238 Board Configuration is rejected if an overlap with a reserved resource is
239 detected.</p>
240 </div>
241 <table border="1" class="docutils">
242 <colgroup>
243 <col width="25%" />
244 <col width="13%" />
245 <col width="14%" />
246 <col width="17%" />
247 <col width="18%" />
248 <col width="13%" />
249 </colgroup>
250 <thead valign="bottom">
251 <tr class="row-odd"><th class="head">IR Name</th>
252 <th class="head">IR Device ID</th>
253 <th class="head">IR Input Index</th>
254 <th class="head">Source Name</th>
255 <th class="head">Source Interface</th>
256 <th class="head">Source Index</th>
257 </tr>
258 </thead>
259 <tbody valign="top">
260 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
261 <td>1</td>
262 <td>0</td>
263 <td>AM64X_DEV_PRU_ICSSG0</td>
264 <td>pr1_host_intr_req</td>
265 <td>0</td>
266 </tr>
267 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
268 <td>1</td>
269 <td>1</td>
270 <td>AM64X_DEV_PRU_ICSSG0</td>
271 <td>pr1_host_intr_req</td>
272 <td>1</td>
273 </tr>
274 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
275 <td>1</td>
276 <td>2</td>
277 <td>AM64X_DEV_PRU_ICSSG0</td>
278 <td>pr1_host_intr_req</td>
279 <td>2</td>
280 </tr>
281 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
282 <td>1</td>
283 <td>3</td>
284 <td>AM64X_DEV_PRU_ICSSG0</td>
285 <td>pr1_host_intr_req</td>
286 <td>3</td>
287 </tr>
288 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
289 <td>1</td>
290 <td>4</td>
291 <td>AM64X_DEV_PRU_ICSSG0</td>
292 <td>pr1_host_intr_req</td>
293 <td>4</td>
294 </tr>
295 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
296 <td>1</td>
297 <td>5</td>
298 <td>AM64X_DEV_PRU_ICSSG0</td>
299 <td>pr1_host_intr_req</td>
300 <td>5</td>
301 </tr>
302 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
303 <td>1</td>
304 <td>6</td>
305 <td>AM64X_DEV_PRU_ICSSG0</td>
306 <td>pr1_host_intr_req</td>
307 <td>6</td>
308 </tr>
309 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
310 <td>1</td>
311 <td>7</td>
312 <td>AM64X_DEV_PRU_ICSSG0</td>
313 <td>pr1_host_intr_req</td>
314 <td>7</td>
315 </tr>
316 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
317 <td>1</td>
318 <td>8</td>
319 <td>AM64X_DEV_PRU_ICSSG1</td>
320 <td>pr1_host_intr_req</td>
321 <td>0</td>
322 </tr>
323 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
324 <td>1</td>
325 <td>9</td>
326 <td>AM64X_DEV_PRU_ICSSG1</td>
327 <td>pr1_host_intr_req</td>
328 <td>1</td>
329 </tr>
330 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
331 <td>1</td>
332 <td>10</td>
333 <td>AM64X_DEV_PRU_ICSSG1</td>
334 <td>pr1_host_intr_req</td>
335 <td>2</td>
336 </tr>
337 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
338 <td>1</td>
339 <td>11</td>
340 <td>AM64X_DEV_PRU_ICSSG1</td>
341 <td>pr1_host_intr_req</td>
342 <td>3</td>
343 </tr>
344 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
345 <td>1</td>
346 <td>12</td>
347 <td>AM64X_DEV_PRU_ICSSG1</td>
348 <td>pr1_host_intr_req</td>
349 <td>4</td>
350 </tr>
351 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
352 <td>1</td>
353 <td>13</td>
354 <td>AM64X_DEV_PRU_ICSSG1</td>
355 <td>pr1_host_intr_req</td>
356 <td>5</td>
357 </tr>
358 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
359 <td>1</td>
360 <td>14</td>
361 <td>AM64X_DEV_PRU_ICSSG1</td>
362 <td>pr1_host_intr_req</td>
363 <td>6</td>
364 </tr>
365 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
366 <td>1</td>
367 <td>15</td>
368 <td>AM64X_DEV_PRU_ICSSG1</td>
369 <td>pr1_host_intr_req</td>
370 <td>7</td>
371 </tr>
372 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
373 <td>1</td>
374 <td>16</td>
375 <td>AM64X_DEV_PRU_ICSSG0</td>
376 <td>pr1_iep0_cmp_intr_req</td>
377 <td>0</td>
378 </tr>
379 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
380 <td>1</td>
381 <td>17</td>
382 <td>AM64X_DEV_PRU_ICSSG0</td>
383 <td>pr1_iep0_cmp_intr_req</td>
384 <td>1</td>
385 </tr>
386 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
387 <td>1</td>
388 <td>18</td>
389 <td>AM64X_DEV_PRU_ICSSG0</td>
390 <td>pr1_iep0_cmp_intr_req</td>
391 <td>2</td>
392 </tr>
393 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
394 <td>1</td>
395 <td>19</td>
396 <td>AM64X_DEV_PRU_ICSSG0</td>
397 <td>pr1_iep0_cmp_intr_req</td>
398 <td>3</td>
399 </tr>
400 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
401 <td>1</td>
402 <td>20</td>
403 <td>AM64X_DEV_PRU_ICSSG0</td>
404 <td>pr1_iep0_cmp_intr_req</td>
405 <td>4</td>
406 </tr>
407 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
408 <td>1</td>
409 <td>21</td>
410 <td>AM64X_DEV_PRU_ICSSG0</td>
411 <td>pr1_iep0_cmp_intr_req</td>
412 <td>5</td>
413 </tr>
414 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
415 <td>1</td>
416 <td>22</td>
417 <td>AM64X_DEV_PRU_ICSSG0</td>
418 <td>pr1_iep0_cmp_intr_req</td>
419 <td>6</td>
420 </tr>
421 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
422 <td>1</td>
423 <td>23</td>
424 <td>AM64X_DEV_PRU_ICSSG0</td>
425 <td>pr1_iep0_cmp_intr_req</td>
426 <td>7</td>
427 </tr>
428 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
429 <td>1</td>
430 <td>24</td>
431 <td>AM64X_DEV_PRU_ICSSG0</td>
432 <td>pr1_iep0_cmp_intr_req</td>
433 <td>8</td>
434 </tr>
435 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
436 <td>1</td>
437 <td>25</td>
438 <td>AM64X_DEV_PRU_ICSSG0</td>
439 <td>pr1_iep0_cmp_intr_req</td>
440 <td>9</td>
441 </tr>
442 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
443 <td>1</td>
444 <td>26</td>
445 <td>AM64X_DEV_PRU_ICSSG0</td>
446 <td>pr1_iep0_cmp_intr_req</td>
447 <td>10</td>
448 </tr>
449 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
450 <td>1</td>
451 <td>27</td>
452 <td>AM64X_DEV_PRU_ICSSG0</td>
453 <td>pr1_iep0_cmp_intr_req</td>
454 <td>11</td>
455 </tr>
456 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
457 <td>1</td>
458 <td>28</td>
459 <td>AM64X_DEV_PRU_ICSSG0</td>
460 <td>pr1_iep0_cmp_intr_req</td>
461 <td>12</td>
462 </tr>
463 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
464 <td>1</td>
465 <td>29</td>
466 <td>AM64X_DEV_PRU_ICSSG0</td>
467 <td>pr1_iep0_cmp_intr_req</td>
468 <td>13</td>
469 </tr>
470 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
471 <td>1</td>
472 <td>30</td>
473 <td>AM64X_DEV_PRU_ICSSG0</td>
474 <td>pr1_iep0_cmp_intr_req</td>
475 <td>14</td>
476 </tr>
477 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
478 <td>1</td>
479 <td>31</td>
480 <td>AM64X_DEV_PRU_ICSSG0</td>
481 <td>pr1_iep0_cmp_intr_req</td>
482 <td>15</td>
483 </tr>
484 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
485 <td>1</td>
486 <td>32</td>
487 <td>AM64X_DEV_PRU_ICSSG0</td>
488 <td>pr1_iep1_cmp_intr_req</td>
489 <td>0</td>
490 </tr>
491 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
492 <td>1</td>
493 <td>33</td>
494 <td>AM64X_DEV_PRU_ICSSG0</td>
495 <td>pr1_iep1_cmp_intr_req</td>
496 <td>1</td>
497 </tr>
498 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
499 <td>1</td>
500 <td>34</td>
501 <td>AM64X_DEV_PRU_ICSSG0</td>
502 <td>pr1_iep1_cmp_intr_req</td>
503 <td>2</td>
504 </tr>
505 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
506 <td>1</td>
507 <td>35</td>
508 <td>AM64X_DEV_PRU_ICSSG0</td>
509 <td>pr1_iep1_cmp_intr_req</td>
510 <td>3</td>
511 </tr>
512 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
513 <td>1</td>
514 <td>36</td>
515 <td>AM64X_DEV_PRU_ICSSG0</td>
516 <td>pr1_iep1_cmp_intr_req</td>
517 <td>4</td>
518 </tr>
519 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
520 <td>1</td>
521 <td>37</td>
522 <td>AM64X_DEV_PRU_ICSSG0</td>
523 <td>pr1_iep1_cmp_intr_req</td>
524 <td>5</td>
525 </tr>
526 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
527 <td>1</td>
528 <td>38</td>
529 <td>AM64X_DEV_PRU_ICSSG0</td>
530 <td>pr1_iep1_cmp_intr_req</td>
531 <td>6</td>
532 </tr>
533 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
534 <td>1</td>
535 <td>39</td>
536 <td>AM64X_DEV_PRU_ICSSG0</td>
537 <td>pr1_iep1_cmp_intr_req</td>
538 <td>7</td>
539 </tr>
540 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
541 <td>1</td>
542 <td>40</td>
543 <td>AM64X_DEV_PRU_ICSSG0</td>
544 <td>pr1_iep1_cmp_intr_req</td>
545 <td>8</td>
546 </tr>
547 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
548 <td>1</td>
549 <td>41</td>
550 <td>AM64X_DEV_PRU_ICSSG0</td>
551 <td>pr1_iep1_cmp_intr_req</td>
552 <td>9</td>
553 </tr>
554 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
555 <td>1</td>
556 <td>42</td>
557 <td>AM64X_DEV_PRU_ICSSG0</td>
558 <td>pr1_iep1_cmp_intr_req</td>
559 <td>10</td>
560 </tr>
561 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
562 <td>1</td>
563 <td>43</td>
564 <td>AM64X_DEV_PRU_ICSSG0</td>
565 <td>pr1_iep1_cmp_intr_req</td>
566 <td>11</td>
567 </tr>
568 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
569 <td>1</td>
570 <td>44</td>
571 <td>AM64X_DEV_PRU_ICSSG0</td>
572 <td>pr1_iep1_cmp_intr_req</td>
573 <td>12</td>
574 </tr>
575 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
576 <td>1</td>
577 <td>45</td>
578 <td>AM64X_DEV_PRU_ICSSG0</td>
579 <td>pr1_iep1_cmp_intr_req</td>
580 <td>13</td>
581 </tr>
582 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
583 <td>1</td>
584 <td>46</td>
585 <td>AM64X_DEV_PRU_ICSSG0</td>
586 <td>pr1_iep1_cmp_intr_req</td>
587 <td>14</td>
588 </tr>
589 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
590 <td>1</td>
591 <td>47</td>
592 <td>AM64X_DEV_PRU_ICSSG0</td>
593 <td>pr1_iep1_cmp_intr_req</td>
594 <td>15</td>
595 </tr>
596 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
597 <td>1</td>
598 <td>48</td>
599 <td>AM64X_DEV_PRU_ICSSG1</td>
600 <td>pr1_iep0_cmp_intr_req</td>
601 <td>0</td>
602 </tr>
603 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
604 <td>1</td>
605 <td>49</td>
606 <td>AM64X_DEV_PRU_ICSSG1</td>
607 <td>pr1_iep0_cmp_intr_req</td>
608 <td>1</td>
609 </tr>
610 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
611 <td>1</td>
612 <td>50</td>
613 <td>AM64X_DEV_PRU_ICSSG1</td>
614 <td>pr1_iep0_cmp_intr_req</td>
615 <td>2</td>
616 </tr>
617 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
618 <td>1</td>
619 <td>51</td>
620 <td>AM64X_DEV_PRU_ICSSG1</td>
621 <td>pr1_iep0_cmp_intr_req</td>
622 <td>3</td>
623 </tr>
624 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
625 <td>1</td>
626 <td>52</td>
627 <td>AM64X_DEV_PRU_ICSSG1</td>
628 <td>pr1_iep0_cmp_intr_req</td>
629 <td>4</td>
630 </tr>
631 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
632 <td>1</td>
633 <td>53</td>
634 <td>AM64X_DEV_PRU_ICSSG1</td>
635 <td>pr1_iep0_cmp_intr_req</td>
636 <td>5</td>
637 </tr>
638 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
639 <td>1</td>
640 <td>54</td>
641 <td>AM64X_DEV_PRU_ICSSG1</td>
642 <td>pr1_iep0_cmp_intr_req</td>
643 <td>6</td>
644 </tr>
645 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
646 <td>1</td>
647 <td>55</td>
648 <td>AM64X_DEV_PRU_ICSSG1</td>
649 <td>pr1_iep0_cmp_intr_req</td>
650 <td>7</td>
651 </tr>
652 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
653 <td>1</td>
654 <td>56</td>
655 <td>AM64X_DEV_PRU_ICSSG1</td>
656 <td>pr1_iep0_cmp_intr_req</td>
657 <td>8</td>
658 </tr>
659 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
660 <td>1</td>
661 <td>57</td>
662 <td>AM64X_DEV_PRU_ICSSG1</td>
663 <td>pr1_iep0_cmp_intr_req</td>
664 <td>9</td>
665 </tr>
666 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
667 <td>1</td>
668 <td>58</td>
669 <td>AM64X_DEV_PRU_ICSSG1</td>
670 <td>pr1_iep0_cmp_intr_req</td>
671 <td>10</td>
672 </tr>
673 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
674 <td>1</td>
675 <td>59</td>
676 <td>AM64X_DEV_PRU_ICSSG1</td>
677 <td>pr1_iep0_cmp_intr_req</td>
678 <td>11</td>
679 </tr>
680 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
681 <td>1</td>
682 <td>60</td>
683 <td>AM64X_DEV_PRU_ICSSG1</td>
684 <td>pr1_iep0_cmp_intr_req</td>
685 <td>12</td>
686 </tr>
687 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
688 <td>1</td>
689 <td>61</td>
690 <td>AM64X_DEV_PRU_ICSSG1</td>
691 <td>pr1_iep0_cmp_intr_req</td>
692 <td>13</td>
693 </tr>
694 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
695 <td>1</td>
696 <td>62</td>
697 <td>AM64X_DEV_PRU_ICSSG1</td>
698 <td>pr1_iep0_cmp_intr_req</td>
699 <td>14</td>
700 </tr>
701 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
702 <td>1</td>
703 <td>63</td>
704 <td>AM64X_DEV_PRU_ICSSG1</td>
705 <td>pr1_iep0_cmp_intr_req</td>
706 <td>15</td>
707 </tr>
708 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
709 <td>1</td>
710 <td>64</td>
711 <td>AM64X_DEV_PRU_ICSSG1</td>
712 <td>pr1_iep1_cmp_intr_req</td>
713 <td>0</td>
714 </tr>
715 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
716 <td>1</td>
717 <td>65</td>
718 <td>AM64X_DEV_PRU_ICSSG1</td>
719 <td>pr1_iep1_cmp_intr_req</td>
720 <td>1</td>
721 </tr>
722 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
723 <td>1</td>
724 <td>66</td>
725 <td>AM64X_DEV_PRU_ICSSG1</td>
726 <td>pr1_iep1_cmp_intr_req</td>
727 <td>2</td>
728 </tr>
729 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
730 <td>1</td>
731 <td>67</td>
732 <td>AM64X_DEV_PRU_ICSSG1</td>
733 <td>pr1_iep1_cmp_intr_req</td>
734 <td>3</td>
735 </tr>
736 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
737 <td>1</td>
738 <td>68</td>
739 <td>AM64X_DEV_PRU_ICSSG1</td>
740 <td>pr1_iep1_cmp_intr_req</td>
741 <td>4</td>
742 </tr>
743 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
744 <td>1</td>
745 <td>69</td>
746 <td>AM64X_DEV_PRU_ICSSG1</td>
747 <td>pr1_iep1_cmp_intr_req</td>
748 <td>5</td>
749 </tr>
750 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
751 <td>1</td>
752 <td>70</td>
753 <td>AM64X_DEV_PRU_ICSSG1</td>
754 <td>pr1_iep1_cmp_intr_req</td>
755 <td>6</td>
756 </tr>
757 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
758 <td>1</td>
759 <td>71</td>
760 <td>AM64X_DEV_PRU_ICSSG1</td>
761 <td>pr1_iep1_cmp_intr_req</td>
762 <td>7</td>
763 </tr>
764 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
765 <td>1</td>
766 <td>72</td>
767 <td>AM64X_DEV_PRU_ICSSG1</td>
768 <td>pr1_iep1_cmp_intr_req</td>
769 <td>8</td>
770 </tr>
771 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
772 <td>1</td>
773 <td>73</td>
774 <td>AM64X_DEV_PRU_ICSSG1</td>
775 <td>pr1_iep1_cmp_intr_req</td>
776 <td>9</td>
777 </tr>
778 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
779 <td>1</td>
780 <td>74</td>
781 <td>AM64X_DEV_PRU_ICSSG1</td>
782 <td>pr1_iep1_cmp_intr_req</td>
783 <td>10</td>
784 </tr>
785 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
786 <td>1</td>
787 <td>75</td>
788 <td>AM64X_DEV_PRU_ICSSG1</td>
789 <td>pr1_iep1_cmp_intr_req</td>
790 <td>11</td>
791 </tr>
792 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
793 <td>1</td>
794 <td>76</td>
795 <td>AM64X_DEV_PRU_ICSSG1</td>
796 <td>pr1_iep1_cmp_intr_req</td>
797 <td>12</td>
798 </tr>
799 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
800 <td>1</td>
801 <td>77</td>
802 <td>AM64X_DEV_PRU_ICSSG1</td>
803 <td>pr1_iep1_cmp_intr_req</td>
804 <td>13</td>
805 </tr>
806 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
807 <td>1</td>
808 <td>78</td>
809 <td>AM64X_DEV_PRU_ICSSG1</td>
810 <td>pr1_iep1_cmp_intr_req</td>
811 <td>14</td>
812 </tr>
813 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
814 <td>1</td>
815 <td>79</td>
816 <td>AM64X_DEV_PRU_ICSSG1</td>
817 <td>pr1_iep1_cmp_intr_req</td>
818 <td>15</td>
819 </tr>
820 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
821 <td>1</td>
822 <td>80</td>
823 <td>AM64X_DEV_CPSW0</td>
824 <td>cpts_comp</td>
825 <td>0</td>
826 </tr>
827 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
828 <td>1</td>
829 <td>81</td>
830 <td>AM64X_DEV_PCIE0</td>
831 <td>pcie_cpts_comp</td>
832 <td>0</td>
833 </tr>
834 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
835 <td>1</td>
836 <td>82</td>
837 <td>AM64X_DEV_CPTS0</td>
838 <td>cpts_comp</td>
839 <td>0</td>
840 </tr>
841 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
842 <td>1</td>
843 <td>83</td>
844 <td>Not Connected</td>
845 <td> </td>
846 <td> </td>
847 </tr>
848 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
849 <td>1</td>
850 <td>84</td>
851 <td>Not Connected</td>
852 <td> </td>
853 <td> </td>
854 </tr>
855 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
856 <td>1</td>
857 <td>85</td>
858 <td>Not Connected</td>
859 <td> </td>
860 <td> </td>
861 </tr>
862 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
863 <td>1</td>
864 <td>86</td>
865 <td>Not Connected</td>
866 <td> </td>
867 <td> </td>
868 </tr>
869 </tbody>
870 </table>
871 </div>
872 <div class="section" id="cmp-event-introuter0-interrupt-router-output-destinations">
873 <span id="pub-soc-am64x-cmp-event-introuter0-output-src-list"></span><h2>CMP_EVENT_INTROUTER0 Interrupt Router Output Destinations<a class="headerlink" href="#cmp-event-introuter0-interrupt-router-output-destinations" title="Permalink to this headline">¶</a></h2>
874 <div class="admonition warning">
875 <p class="first admonition-title">Warning</p>
876 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
877 host within the RM Board Configuration resource assignment array. The RM
878 Board Configuration is rejected if an overlap with a reserved resource is
879 detected.</p>
880 </div>
881 <table border="1" class="docutils">
882 <colgroup>
883 <col width="23%" />
884 <col width="11%" />
885 <col width="13%" />
886 <col width="20%" />
887 <col width="18%" />
888 <col width="15%" />
889 </colgroup>
890 <thead valign="bottom">
891 <tr class="row-odd"><th class="head">IR Name</th>
892 <th class="head">IR Device ID</th>
893 <th class="head">IR Output Index</th>
894 <th class="head">Destination Name</th>
895 <th class="head">Destination Interface</th>
896 <th class="head">Destination Index</th>
897 </tr>
898 </thead>
899 <tbody valign="top">
900 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
901 <td>1</td>
902 <td>0</td>
903 <td>AM64X_DEV_GICSS0</td>
904 <td>spi</td>
905 <td>48</td>
906 </tr>
907 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
908 <td>1</td>
909 <td>1</td>
910 <td>AM64X_DEV_GICSS0</td>
911 <td>spi</td>
912 <td>49</td>
913 </tr>
914 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
915 <td>1</td>
916 <td>2</td>
917 <td>AM64X_DEV_GICSS0</td>
918 <td>spi</td>
919 <td>50</td>
920 </tr>
921 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
922 <td>1</td>
923 <td>3</td>
924 <td>AM64X_DEV_GICSS0</td>
925 <td>spi</td>
926 <td>51</td>
927 </tr>
928 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
929 <td>1</td>
930 <td>4</td>
931 <td>AM64X_DEV_GICSS0</td>
932 <td>spi</td>
933 <td>52</td>
934 </tr>
935 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
936 <td>1</td>
937 <td>5</td>
938 <td>AM64X_DEV_GICSS0</td>
939 <td>spi</td>
940 <td>53</td>
941 </tr>
942 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
943 <td>1</td>
944 <td>6</td>
945 <td>AM64X_DEV_GICSS0</td>
946 <td>spi</td>
947 <td>54</td>
948 </tr>
949 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
950 <td>1</td>
951 <td>7</td>
952 <td>AM64X_DEV_GICSS0</td>
953 <td>spi</td>
954 <td>55</td>
955 </tr>
956 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
957 <td>1</td>
958 <td>8</td>
959 <td>AM64X_DEV_GICSS0</td>
960 <td>spi</td>
961 <td>56</td>
962 </tr>
963 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
964 <td>1</td>
965 <td>9</td>
966 <td>AM64X_DEV_GICSS0</td>
967 <td>spi</td>
968 <td>57</td>
969 </tr>
970 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
971 <td>1</td>
972 <td>10</td>
973 <td>AM64X_DEV_GICSS0</td>
974 <td>spi</td>
975 <td>58</td>
976 </tr>
977 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
978 <td>1</td>
979 <td>11</td>
980 <td>AM64X_DEV_GICSS0</td>
981 <td>spi</td>
982 <td>59</td>
983 </tr>
984 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
985 <td>1</td>
986 <td>12</td>
987 <td>AM64X_DEV_GICSS0</td>
988 <td>spi</td>
989 <td>60</td>
990 </tr>
991 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
992 <td>1</td>
993 <td>13</td>
994 <td>AM64X_DEV_GICSS0</td>
995 <td>spi</td>
996 <td>61</td>
997 </tr>
998 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
999 <td>1</td>
1000 <td>14</td>
1001 <td>AM64X_DEV_GICSS0</td>
1002 <td>spi</td>
1003 <td>62</td>
1004 </tr>
1005 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1006 <td>1</td>
1007 <td>15</td>
1008 <td>AM64X_DEV_GICSS0</td>
1009 <td>spi</td>
1010 <td>63</td>
1011 </tr>
1012 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1013 <td>1</td>
1014 <td>16</td>
1015 <td>AM64X_DEV_R5FSS0_CORE0</td>
1016 <td>intr</td>
1017 <td>48</td>
1018 </tr>
1019 <tr class="row-odd"><td> </td>
1020 <td> </td>
1021 <td> </td>
1022 <td>AM64X_DEV_R5FSS0_CORE1</td>
1023 <td>intr</td>
1024 <td>48</td>
1025 </tr>
1026 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1027 <td>1</td>
1028 <td>17</td>
1029 <td>AM64X_DEV_R5FSS0_CORE0</td>
1030 <td>intr</td>
1031 <td>49</td>
1032 </tr>
1033 <tr class="row-odd"><td> </td>
1034 <td> </td>
1035 <td> </td>
1036 <td>AM64X_DEV_R5FSS0_CORE1</td>
1037 <td>intr</td>
1038 <td>49</td>
1039 </tr>
1040 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1041 <td>1</td>
1042 <td>18</td>
1043 <td>AM64X_DEV_R5FSS0_CORE0</td>
1044 <td>intr</td>
1045 <td>50</td>
1046 </tr>
1047 <tr class="row-odd"><td> </td>
1048 <td> </td>
1049 <td> </td>
1050 <td>AM64X_DEV_R5FSS0_CORE1</td>
1051 <td>intr</td>
1052 <td>50</td>
1053 </tr>
1054 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1055 <td>1</td>
1056 <td>19</td>
1057 <td>AM64X_DEV_R5FSS0_CORE0</td>
1058 <td>intr</td>
1059 <td>51</td>
1060 </tr>
1061 <tr class="row-odd"><td> </td>
1062 <td> </td>
1063 <td> </td>
1064 <td>AM64X_DEV_R5FSS0_CORE1</td>
1065 <td>intr</td>
1066 <td>51</td>
1067 </tr>
1068 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1069 <td>1</td>
1070 <td>20</td>
1071 <td>AM64X_DEV_R5FSS0_CORE0</td>
1072 <td>intr</td>
1073 <td>52</td>
1074 </tr>
1075 <tr class="row-odd"><td> </td>
1076 <td> </td>
1077 <td> </td>
1078 <td>AM64X_DEV_R5FSS0_CORE1</td>
1079 <td>intr</td>
1080 <td>52</td>
1081 </tr>
1082 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1083 <td>1</td>
1084 <td>21</td>
1085 <td>AM64X_DEV_R5FSS0_CORE0</td>
1086 <td>intr</td>
1087 <td>53</td>
1088 </tr>
1089 <tr class="row-odd"><td> </td>
1090 <td> </td>
1091 <td> </td>
1092 <td>AM64X_DEV_R5FSS0_CORE1</td>
1093 <td>intr</td>
1094 <td>53</td>
1095 </tr>
1096 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1097 <td>1</td>
1098 <td>22</td>
1099 <td>AM64X_DEV_R5FSS0_CORE0</td>
1100 <td>intr</td>
1101 <td>54</td>
1102 </tr>
1103 <tr class="row-odd"><td> </td>
1104 <td> </td>
1105 <td> </td>
1106 <td>AM64X_DEV_R5FSS0_CORE1</td>
1107 <td>intr</td>
1108 <td>54</td>
1109 </tr>
1110 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1111 <td>1</td>
1112 <td>23</td>
1113 <td>AM64X_DEV_R5FSS0_CORE0</td>
1114 <td>intr</td>
1115 <td>55</td>
1116 </tr>
1117 <tr class="row-odd"><td> </td>
1118 <td> </td>
1119 <td> </td>
1120 <td>AM64X_DEV_R5FSS0_CORE1</td>
1121 <td>intr</td>
1122 <td>55</td>
1123 </tr>
1124 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1125 <td>1</td>
1126 <td>24</td>
1127 <td>AM64X_DEV_R5FSS1_CORE0</td>
1128 <td>intr</td>
1129 <td>48</td>
1130 </tr>
1131 <tr class="row-odd"><td> </td>
1132 <td> </td>
1133 <td> </td>
1134 <td>AM64X_DEV_R5FSS1_CORE1</td>
1135 <td>intr</td>
1136 <td>48</td>
1137 </tr>
1138 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1139 <td>1</td>
1140 <td>25</td>
1141 <td>AM64X_DEV_R5FSS1_CORE0</td>
1142 <td>intr</td>
1143 <td>49</td>
1144 </tr>
1145 <tr class="row-odd"><td> </td>
1146 <td> </td>
1147 <td> </td>
1148 <td>AM64X_DEV_R5FSS1_CORE1</td>
1149 <td>intr</td>
1150 <td>49</td>
1151 </tr>
1152 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1153 <td>1</td>
1154 <td>26</td>
1155 <td>AM64X_DEV_R5FSS1_CORE0</td>
1156 <td>intr</td>
1157 <td>50</td>
1158 </tr>
1159 <tr class="row-odd"><td> </td>
1160 <td> </td>
1161 <td> </td>
1162 <td>AM64X_DEV_R5FSS1_CORE1</td>
1163 <td>intr</td>
1164 <td>50</td>
1165 </tr>
1166 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1167 <td>1</td>
1168 <td>27</td>
1169 <td>AM64X_DEV_R5FSS1_CORE0</td>
1170 <td>intr</td>
1171 <td>51</td>
1172 </tr>
1173 <tr class="row-odd"><td> </td>
1174 <td> </td>
1175 <td> </td>
1176 <td>AM64X_DEV_R5FSS1_CORE1</td>
1177 <td>intr</td>
1178 <td>51</td>
1179 </tr>
1180 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1181 <td>1</td>
1182 <td>28</td>
1183 <td>AM64X_DEV_R5FSS1_CORE0</td>
1184 <td>intr</td>
1185 <td>52</td>
1186 </tr>
1187 <tr class="row-odd"><td> </td>
1188 <td> </td>
1189 <td> </td>
1190 <td>AM64X_DEV_R5FSS1_CORE1</td>
1191 <td>intr</td>
1192 <td>52</td>
1193 </tr>
1194 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1195 <td>1</td>
1196 <td>29</td>
1197 <td>AM64X_DEV_R5FSS1_CORE0</td>
1198 <td>intr</td>
1199 <td>53</td>
1200 </tr>
1201 <tr class="row-odd"><td> </td>
1202 <td> </td>
1203 <td> </td>
1204 <td>AM64X_DEV_R5FSS1_CORE1</td>
1205 <td>intr</td>
1206 <td>53</td>
1207 </tr>
1208 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1209 <td>1</td>
1210 <td>30</td>
1211 <td>AM64X_DEV_R5FSS1_CORE0</td>
1212 <td>intr</td>
1213 <td>54</td>
1214 </tr>
1215 <tr class="row-odd"><td> </td>
1216 <td> </td>
1217 <td> </td>
1218 <td>AM64X_DEV_R5FSS1_CORE1</td>
1219 <td>intr</td>
1220 <td>54</td>
1221 </tr>
1222 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1223 <td>1</td>
1224 <td>31</td>
1225 <td>AM64X_DEV_R5FSS1_CORE0</td>
1226 <td>intr</td>
1227 <td>55</td>
1228 </tr>
1229 <tr class="row-odd"><td> </td>
1230 <td> </td>
1231 <td> </td>
1232 <td>AM64X_DEV_R5FSS1_CORE1</td>
1233 <td>intr</td>
1234 <td>55</td>
1235 </tr>
1236 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1237 <td>1</td>
1238 <td>32</td>
1239 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
1240 <td>intaggr_levi_pend</td>
1241 <td>0</td>
1242 </tr>
1243 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1244 <td>1</td>
1245 <td>33</td>
1246 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
1247 <td>intaggr_levi_pend</td>
1248 <td>1</td>
1249 </tr>
1250 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1251 <td>1</td>
1252 <td>34</td>
1253 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
1254 <td>intaggr_levi_pend</td>
1255 <td>2</td>
1256 </tr>
1257 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1258 <td>1</td>
1259 <td>35</td>
1260 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
1261 <td>intaggr_levi_pend</td>
1262 <td>3</td>
1263 </tr>
1264 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1265 <td>1</td>
1266 <td>36</td>
1267 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
1268 <td>intaggr_levi_pend</td>
1269 <td>4</td>
1270 </tr>
1271 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1272 <td>1</td>
1273 <td>37</td>
1274 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
1275 <td>intaggr_levi_pend</td>
1276 <td>5</td>
1277 </tr>
1278 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1279 <td>1</td>
1280 <td>38</td>
1281 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
1282 <td>intaggr_levi_pend</td>
1283 <td>6</td>
1284 </tr>
1285 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1286 <td>1</td>
1287 <td>39</td>
1288 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
1289 <td>intaggr_levi_pend</td>
1290 <td>7</td>
1291 </tr>
1292 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1293 <td>1</td>
1294 <td>40</td>
1295 <td>Not Connected</td>
1296 <td> </td>
1297 <td> </td>
1298 </tr>
1299 <tr class="row-odd"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1300 <td>1</td>
1301 <td>41</td>
1302 <td>Not Connected</td>
1303 <td> </td>
1304 <td> </td>
1305 </tr>
1306 <tr class="row-even"><td>AM64X_DEV_CMP_EVENT_INTROUTER0</td>
1307 <td>1</td>
1308 <td>42</td>
1309 <td>Not Connected</td>
1310 <td> </td>
1311 <td> </td>
1312 </tr>
1313 </tbody>
1314 </table>
1315 </div>
1316 <div class="section" id="main-gpiomux-introuter0-interrupt-router-input-sources">
1317 <span id="pub-soc-am64x-main-gpiomux-introuter0-input-src-list"></span><h2>MAIN_GPIOMUX_INTROUTER0 Interrupt Router Input Sources<a class="headerlink" href="#main-gpiomux-introuter0-interrupt-router-input-sources" title="Permalink to this headline">¶</a></h2>
1318 <div class="admonition warning">
1319 <p class="first admonition-title">Warning</p>
1320 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
1321 host within the RM Board Configuration resource assignment array. The RM
1322 Board Configuration is rejected if an overlap with a reserved resource is
1323 detected.</p>
1324 </div>
1325 <table border="1" class="docutils">
1326 <colgroup>
1327 <col width="29%" />
1328 <col width="13%" />
1329 <col width="15%" />
1330 <col width="14%" />
1331 <col width="16%" />
1332 <col width="13%" />
1333 </colgroup>
1334 <thead valign="bottom">
1335 <tr class="row-odd"><th class="head">IR Name</th>
1336 <th class="head">IR Device ID</th>
1337 <th class="head">IR Input Index</th>
1338 <th class="head">Source Name</th>
1339 <th class="head">Source Interface</th>
1340 <th class="head">Source Index</th>
1341 </tr>
1342 </thead>
1343 <tbody valign="top">
1344 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1345 <td>3</td>
1346 <td>0</td>
1347 <td>AM64X_DEV_GPIO0</td>
1348 <td>gpio</td>
1349 <td>0</td>
1350 </tr>
1351 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1352 <td>3</td>
1353 <td>1</td>
1354 <td>AM64X_DEV_GPIO0</td>
1355 <td>gpio</td>
1356 <td>1</td>
1357 </tr>
1358 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1359 <td>3</td>
1360 <td>2</td>
1361 <td>AM64X_DEV_GPIO0</td>
1362 <td>gpio</td>
1363 <td>2</td>
1364 </tr>
1365 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1366 <td>3</td>
1367 <td>3</td>
1368 <td>AM64X_DEV_GPIO0</td>
1369 <td>gpio</td>
1370 <td>3</td>
1371 </tr>
1372 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1373 <td>3</td>
1374 <td>4</td>
1375 <td>AM64X_DEV_GPIO0</td>
1376 <td>gpio</td>
1377 <td>4</td>
1378 </tr>
1379 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1380 <td>3</td>
1381 <td>5</td>
1382 <td>AM64X_DEV_GPIO0</td>
1383 <td>gpio</td>
1384 <td>5</td>
1385 </tr>
1386 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1387 <td>3</td>
1388 <td>6</td>
1389 <td>AM64X_DEV_GPIO0</td>
1390 <td>gpio</td>
1391 <td>6</td>
1392 </tr>
1393 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1394 <td>3</td>
1395 <td>7</td>
1396 <td>AM64X_DEV_GPIO0</td>
1397 <td>gpio</td>
1398 <td>7</td>
1399 </tr>
1400 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1401 <td>3</td>
1402 <td>8</td>
1403 <td>AM64X_DEV_GPIO0</td>
1404 <td>gpio</td>
1405 <td>8</td>
1406 </tr>
1407 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1408 <td>3</td>
1409 <td>9</td>
1410 <td>AM64X_DEV_GPIO0</td>
1411 <td>gpio</td>
1412 <td>9</td>
1413 </tr>
1414 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1415 <td>3</td>
1416 <td>10</td>
1417 <td>AM64X_DEV_GPIO0</td>
1418 <td>gpio</td>
1419 <td>10</td>
1420 </tr>
1421 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1422 <td>3</td>
1423 <td>11</td>
1424 <td>AM64X_DEV_GPIO0</td>
1425 <td>gpio</td>
1426 <td>11</td>
1427 </tr>
1428 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1429 <td>3</td>
1430 <td>12</td>
1431 <td>AM64X_DEV_GPIO0</td>
1432 <td>gpio</td>
1433 <td>12</td>
1434 </tr>
1435 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1436 <td>3</td>
1437 <td>13</td>
1438 <td>AM64X_DEV_GPIO0</td>
1439 <td>gpio</td>
1440 <td>13</td>
1441 </tr>
1442 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1443 <td>3</td>
1444 <td>14</td>
1445 <td>AM64X_DEV_GPIO0</td>
1446 <td>gpio</td>
1447 <td>14</td>
1448 </tr>
1449 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1450 <td>3</td>
1451 <td>15</td>
1452 <td>AM64X_DEV_GPIO0</td>
1453 <td>gpio</td>
1454 <td>15</td>
1455 </tr>
1456 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1457 <td>3</td>
1458 <td>16</td>
1459 <td>AM64X_DEV_GPIO0</td>
1460 <td>gpio</td>
1461 <td>16</td>
1462 </tr>
1463 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1464 <td>3</td>
1465 <td>17</td>
1466 <td>AM64X_DEV_GPIO0</td>
1467 <td>gpio</td>
1468 <td>17</td>
1469 </tr>
1470 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1471 <td>3</td>
1472 <td>18</td>
1473 <td>AM64X_DEV_GPIO0</td>
1474 <td>gpio</td>
1475 <td>18</td>
1476 </tr>
1477 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1478 <td>3</td>
1479 <td>19</td>
1480 <td>AM64X_DEV_GPIO0</td>
1481 <td>gpio</td>
1482 <td>19</td>
1483 </tr>
1484 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1485 <td>3</td>
1486 <td>20</td>
1487 <td>AM64X_DEV_GPIO0</td>
1488 <td>gpio</td>
1489 <td>20</td>
1490 </tr>
1491 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1492 <td>3</td>
1493 <td>21</td>
1494 <td>AM64X_DEV_GPIO0</td>
1495 <td>gpio</td>
1496 <td>21</td>
1497 </tr>
1498 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1499 <td>3</td>
1500 <td>22</td>
1501 <td>AM64X_DEV_GPIO0</td>
1502 <td>gpio</td>
1503 <td>22</td>
1504 </tr>
1505 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1506 <td>3</td>
1507 <td>23</td>
1508 <td>AM64X_DEV_GPIO0</td>
1509 <td>gpio</td>
1510 <td>23</td>
1511 </tr>
1512 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1513 <td>3</td>
1514 <td>24</td>
1515 <td>AM64X_DEV_GPIO0</td>
1516 <td>gpio</td>
1517 <td>24</td>
1518 </tr>
1519 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1520 <td>3</td>
1521 <td>25</td>
1522 <td>AM64X_DEV_GPIO0</td>
1523 <td>gpio</td>
1524 <td>25</td>
1525 </tr>
1526 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1527 <td>3</td>
1528 <td>26</td>
1529 <td>AM64X_DEV_GPIO0</td>
1530 <td>gpio</td>
1531 <td>26</td>
1532 </tr>
1533 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1534 <td>3</td>
1535 <td>27</td>
1536 <td>AM64X_DEV_GPIO0</td>
1537 <td>gpio</td>
1538 <td>27</td>
1539 </tr>
1540 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1541 <td>3</td>
1542 <td>28</td>
1543 <td>AM64X_DEV_GPIO0</td>
1544 <td>gpio</td>
1545 <td>28</td>
1546 </tr>
1547 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1548 <td>3</td>
1549 <td>29</td>
1550 <td>AM64X_DEV_GPIO0</td>
1551 <td>gpio</td>
1552 <td>29</td>
1553 </tr>
1554 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1555 <td>3</td>
1556 <td>30</td>
1557 <td>AM64X_DEV_GPIO0</td>
1558 <td>gpio</td>
1559 <td>30</td>
1560 </tr>
1561 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1562 <td>3</td>
1563 <td>31</td>
1564 <td>AM64X_DEV_GPIO0</td>
1565 <td>gpio</td>
1566 <td>31</td>
1567 </tr>
1568 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1569 <td>3</td>
1570 <td>32</td>
1571 <td>AM64X_DEV_GPIO0</td>
1572 <td>gpio</td>
1573 <td>32</td>
1574 </tr>
1575 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1576 <td>3</td>
1577 <td>33</td>
1578 <td>AM64X_DEV_GPIO0</td>
1579 <td>gpio</td>
1580 <td>33</td>
1581 </tr>
1582 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1583 <td>3</td>
1584 <td>34</td>
1585 <td>AM64X_DEV_GPIO0</td>
1586 <td>gpio</td>
1587 <td>34</td>
1588 </tr>
1589 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1590 <td>3</td>
1591 <td>35</td>
1592 <td>AM64X_DEV_GPIO0</td>
1593 <td>gpio</td>
1594 <td>35</td>
1595 </tr>
1596 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1597 <td>3</td>
1598 <td>36</td>
1599 <td>AM64X_DEV_GPIO0</td>
1600 <td>gpio</td>
1601 <td>36</td>
1602 </tr>
1603 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1604 <td>3</td>
1605 <td>37</td>
1606 <td>AM64X_DEV_GPIO0</td>
1607 <td>gpio</td>
1608 <td>37</td>
1609 </tr>
1610 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1611 <td>3</td>
1612 <td>38</td>
1613 <td>AM64X_DEV_GPIO0</td>
1614 <td>gpio</td>
1615 <td>38</td>
1616 </tr>
1617 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1618 <td>3</td>
1619 <td>39</td>
1620 <td>AM64X_DEV_GPIO0</td>
1621 <td>gpio</td>
1622 <td>39</td>
1623 </tr>
1624 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1625 <td>3</td>
1626 <td>40</td>
1627 <td>AM64X_DEV_GPIO0</td>
1628 <td>gpio</td>
1629 <td>40</td>
1630 </tr>
1631 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1632 <td>3</td>
1633 <td>41</td>
1634 <td>AM64X_DEV_GPIO0</td>
1635 <td>gpio</td>
1636 <td>41</td>
1637 </tr>
1638 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1639 <td>3</td>
1640 <td>42</td>
1641 <td>AM64X_DEV_GPIO0</td>
1642 <td>gpio</td>
1643 <td>42</td>
1644 </tr>
1645 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1646 <td>3</td>
1647 <td>43</td>
1648 <td>AM64X_DEV_GPIO0</td>
1649 <td>gpio</td>
1650 <td>43</td>
1651 </tr>
1652 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1653 <td>3</td>
1654 <td>44</td>
1655 <td>AM64X_DEV_GPIO0</td>
1656 <td>gpio</td>
1657 <td>44</td>
1658 </tr>
1659 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1660 <td>3</td>
1661 <td>45</td>
1662 <td>AM64X_DEV_GPIO0</td>
1663 <td>gpio</td>
1664 <td>45</td>
1665 </tr>
1666 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1667 <td>3</td>
1668 <td>46</td>
1669 <td>AM64X_DEV_GPIO0</td>
1670 <td>gpio</td>
1671 <td>46</td>
1672 </tr>
1673 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1674 <td>3</td>
1675 <td>47</td>
1676 <td>AM64X_DEV_GPIO0</td>
1677 <td>gpio</td>
1678 <td>47</td>
1679 </tr>
1680 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1681 <td>3</td>
1682 <td>48</td>
1683 <td>AM64X_DEV_GPIO0</td>
1684 <td>gpio</td>
1685 <td>48</td>
1686 </tr>
1687 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1688 <td>3</td>
1689 <td>49</td>
1690 <td>AM64X_DEV_GPIO0</td>
1691 <td>gpio</td>
1692 <td>49</td>
1693 </tr>
1694 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1695 <td>3</td>
1696 <td>50</td>
1697 <td>AM64X_DEV_GPIO0</td>
1698 <td>gpio</td>
1699 <td>50</td>
1700 </tr>
1701 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1702 <td>3</td>
1703 <td>51</td>
1704 <td>AM64X_DEV_GPIO0</td>
1705 <td>gpio</td>
1706 <td>51</td>
1707 </tr>
1708 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1709 <td>3</td>
1710 <td>52</td>
1711 <td>AM64X_DEV_GPIO0</td>
1712 <td>gpio</td>
1713 <td>52</td>
1714 </tr>
1715 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1716 <td>3</td>
1717 <td>53</td>
1718 <td>AM64X_DEV_GPIO0</td>
1719 <td>gpio</td>
1720 <td>53</td>
1721 </tr>
1722 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1723 <td>3</td>
1724 <td>54</td>
1725 <td>AM64X_DEV_GPIO0</td>
1726 <td>gpio</td>
1727 <td>54</td>
1728 </tr>
1729 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1730 <td>3</td>
1731 <td>55</td>
1732 <td>AM64X_DEV_GPIO0</td>
1733 <td>gpio</td>
1734 <td>55</td>
1735 </tr>
1736 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1737 <td>3</td>
1738 <td>56</td>
1739 <td>AM64X_DEV_GPIO0</td>
1740 <td>gpio</td>
1741 <td>56</td>
1742 </tr>
1743 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1744 <td>3</td>
1745 <td>57</td>
1746 <td>AM64X_DEV_GPIO0</td>
1747 <td>gpio</td>
1748 <td>57</td>
1749 </tr>
1750 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1751 <td>3</td>
1752 <td>58</td>
1753 <td>AM64X_DEV_GPIO0</td>
1754 <td>gpio</td>
1755 <td>58</td>
1756 </tr>
1757 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1758 <td>3</td>
1759 <td>59</td>
1760 <td>AM64X_DEV_GPIO0</td>
1761 <td>gpio</td>
1762 <td>59</td>
1763 </tr>
1764 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1765 <td>3</td>
1766 <td>60</td>
1767 <td>AM64X_DEV_GPIO0</td>
1768 <td>gpio</td>
1769 <td>60</td>
1770 </tr>
1771 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1772 <td>3</td>
1773 <td>61</td>
1774 <td>AM64X_DEV_GPIO0</td>
1775 <td>gpio</td>
1776 <td>61</td>
1777 </tr>
1778 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1779 <td>3</td>
1780 <td>62</td>
1781 <td>AM64X_DEV_GPIO0</td>
1782 <td>gpio</td>
1783 <td>62</td>
1784 </tr>
1785 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1786 <td>3</td>
1787 <td>63</td>
1788 <td>AM64X_DEV_GPIO0</td>
1789 <td>gpio</td>
1790 <td>63</td>
1791 </tr>
1792 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1793 <td>3</td>
1794 <td>64</td>
1795 <td>AM64X_DEV_GPIO0</td>
1796 <td>gpio</td>
1797 <td>64</td>
1798 </tr>
1799 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1800 <td>3</td>
1801 <td>65</td>
1802 <td>AM64X_DEV_GPIO0</td>
1803 <td>gpio</td>
1804 <td>65</td>
1805 </tr>
1806 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1807 <td>3</td>
1808 <td>66</td>
1809 <td>AM64X_DEV_GPIO0</td>
1810 <td>gpio</td>
1811 <td>66</td>
1812 </tr>
1813 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1814 <td>3</td>
1815 <td>67</td>
1816 <td>AM64X_DEV_GPIO0</td>
1817 <td>gpio</td>
1818 <td>67</td>
1819 </tr>
1820 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1821 <td>3</td>
1822 <td>68</td>
1823 <td>AM64X_DEV_GPIO0</td>
1824 <td>gpio</td>
1825 <td>68</td>
1826 </tr>
1827 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1828 <td>3</td>
1829 <td>69</td>
1830 <td>AM64X_DEV_GPIO0</td>
1831 <td>gpio</td>
1832 <td>69</td>
1833 </tr>
1834 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1835 <td>3</td>
1836 <td>70</td>
1837 <td>AM64X_DEV_GPIO0</td>
1838 <td>gpio</td>
1839 <td>70</td>
1840 </tr>
1841 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1842 <td>3</td>
1843 <td>71</td>
1844 <td>AM64X_DEV_GPIO0</td>
1845 <td>gpio</td>
1846 <td>71</td>
1847 </tr>
1848 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1849 <td>3</td>
1850 <td>72</td>
1851 <td>AM64X_DEV_GPIO0</td>
1852 <td>gpio</td>
1853 <td>72</td>
1854 </tr>
1855 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1856 <td>3</td>
1857 <td>73</td>
1858 <td>AM64X_DEV_GPIO0</td>
1859 <td>gpio</td>
1860 <td>73</td>
1861 </tr>
1862 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1863 <td>3</td>
1864 <td>74</td>
1865 <td>AM64X_DEV_GPIO0</td>
1866 <td>gpio</td>
1867 <td>74</td>
1868 </tr>
1869 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1870 <td>3</td>
1871 <td>75</td>
1872 <td>AM64X_DEV_GPIO0</td>
1873 <td>gpio</td>
1874 <td>75</td>
1875 </tr>
1876 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1877 <td>3</td>
1878 <td>76</td>
1879 <td>AM64X_DEV_GPIO0</td>
1880 <td>gpio</td>
1881 <td>76</td>
1882 </tr>
1883 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1884 <td>3</td>
1885 <td>77</td>
1886 <td>AM64X_DEV_GPIO0</td>
1887 <td>gpio</td>
1888 <td>77</td>
1889 </tr>
1890 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1891 <td>3</td>
1892 <td>78</td>
1893 <td>AM64X_DEV_GPIO0</td>
1894 <td>gpio</td>
1895 <td>78</td>
1896 </tr>
1897 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1898 <td>3</td>
1899 <td>79</td>
1900 <td>AM64X_DEV_GPIO0</td>
1901 <td>gpio</td>
1902 <td>79</td>
1903 </tr>
1904 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1905 <td>3</td>
1906 <td>80</td>
1907 <td>AM64X_DEV_GPIO0</td>
1908 <td>gpio</td>
1909 <td>80</td>
1910 </tr>
1911 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1912 <td>3</td>
1913 <td>81</td>
1914 <td>AM64X_DEV_GPIO0</td>
1915 <td>gpio</td>
1916 <td>81</td>
1917 </tr>
1918 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1919 <td>3</td>
1920 <td>82</td>
1921 <td>AM64X_DEV_GPIO0</td>
1922 <td>gpio</td>
1923 <td>82</td>
1924 </tr>
1925 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1926 <td>3</td>
1927 <td>83</td>
1928 <td>AM64X_DEV_GPIO0</td>
1929 <td>gpio</td>
1930 <td>83</td>
1931 </tr>
1932 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1933 <td>3</td>
1934 <td>84</td>
1935 <td>AM64X_DEV_GPIO0</td>
1936 <td>gpio</td>
1937 <td>84</td>
1938 </tr>
1939 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1940 <td>3</td>
1941 <td>85</td>
1942 <td>AM64X_DEV_GPIO0</td>
1943 <td>gpio</td>
1944 <td>85</td>
1945 </tr>
1946 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1947 <td>3</td>
1948 <td>86</td>
1949 <td>AM64X_DEV_GPIO0</td>
1950 <td>gpio</td>
1951 <td>86</td>
1952 </tr>
1953 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1954 <td>3</td>
1955 <td>87</td>
1956 <td>AM64X_DEV_GPIO0</td>
1957 <td>gpio</td>
1958 <td>87</td>
1959 </tr>
1960 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1961 <td>3</td>
1962 <td>88</td>
1963 <td>AM64X_DEV_GPIO0</td>
1964 <td>gpio</td>
1965 <td>88</td>
1966 </tr>
1967 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1968 <td>3</td>
1969 <td>89</td>
1970 <td>AM64X_DEV_GPIO0</td>
1971 <td>gpio</td>
1972 <td>89</td>
1973 </tr>
1974 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1975 <td>3</td>
1976 <td>90</td>
1977 <td>AM64X_DEV_GPIO1</td>
1978 <td>gpio</td>
1979 <td>0</td>
1980 </tr>
1981 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1982 <td>3</td>
1983 <td>91</td>
1984 <td>AM64X_DEV_GPIO1</td>
1985 <td>gpio</td>
1986 <td>1</td>
1987 </tr>
1988 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1989 <td>3</td>
1990 <td>92</td>
1991 <td>AM64X_DEV_GPIO1</td>
1992 <td>gpio</td>
1993 <td>2</td>
1994 </tr>
1995 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
1996 <td>3</td>
1997 <td>93</td>
1998 <td>AM64X_DEV_GPIO1</td>
1999 <td>gpio</td>
2000 <td>3</td>
2001 </tr>
2002 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2003 <td>3</td>
2004 <td>94</td>
2005 <td>AM64X_DEV_GPIO1</td>
2006 <td>gpio</td>
2007 <td>4</td>
2008 </tr>
2009 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2010 <td>3</td>
2011 <td>95</td>
2012 <td>AM64X_DEV_GPIO1</td>
2013 <td>gpio</td>
2014 <td>5</td>
2015 </tr>
2016 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2017 <td>3</td>
2018 <td>96</td>
2019 <td>AM64X_DEV_GPIO1</td>
2020 <td>gpio</td>
2021 <td>6</td>
2022 </tr>
2023 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2024 <td>3</td>
2025 <td>97</td>
2026 <td>AM64X_DEV_GPIO1</td>
2027 <td>gpio</td>
2028 <td>7</td>
2029 </tr>
2030 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2031 <td>3</td>
2032 <td>98</td>
2033 <td>AM64X_DEV_GPIO1</td>
2034 <td>gpio</td>
2035 <td>8</td>
2036 </tr>
2037 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2038 <td>3</td>
2039 <td>99</td>
2040 <td>AM64X_DEV_GPIO1</td>
2041 <td>gpio</td>
2042 <td>9</td>
2043 </tr>
2044 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2045 <td>3</td>
2046 <td>100</td>
2047 <td>AM64X_DEV_GPIO1</td>
2048 <td>gpio</td>
2049 <td>10</td>
2050 </tr>
2051 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2052 <td>3</td>
2053 <td>101</td>
2054 <td>AM64X_DEV_GPIO1</td>
2055 <td>gpio</td>
2056 <td>11</td>
2057 </tr>
2058 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2059 <td>3</td>
2060 <td>102</td>
2061 <td>AM64X_DEV_GPIO1</td>
2062 <td>gpio</td>
2063 <td>12</td>
2064 </tr>
2065 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2066 <td>3</td>
2067 <td>103</td>
2068 <td>AM64X_DEV_GPIO1</td>
2069 <td>gpio</td>
2070 <td>13</td>
2071 </tr>
2072 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2073 <td>3</td>
2074 <td>104</td>
2075 <td>AM64X_DEV_GPIO1</td>
2076 <td>gpio</td>
2077 <td>14</td>
2078 </tr>
2079 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2080 <td>3</td>
2081 <td>105</td>
2082 <td>AM64X_DEV_GPIO1</td>
2083 <td>gpio</td>
2084 <td>15</td>
2085 </tr>
2086 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2087 <td>3</td>
2088 <td>106</td>
2089 <td>AM64X_DEV_GPIO1</td>
2090 <td>gpio</td>
2091 <td>16</td>
2092 </tr>
2093 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2094 <td>3</td>
2095 <td>107</td>
2096 <td>AM64X_DEV_GPIO1</td>
2097 <td>gpio</td>
2098 <td>17</td>
2099 </tr>
2100 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2101 <td>3</td>
2102 <td>108</td>
2103 <td>AM64X_DEV_GPIO1</td>
2104 <td>gpio</td>
2105 <td>18</td>
2106 </tr>
2107 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2108 <td>3</td>
2109 <td>109</td>
2110 <td>AM64X_DEV_GPIO1</td>
2111 <td>gpio</td>
2112 <td>19</td>
2113 </tr>
2114 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2115 <td>3</td>
2116 <td>110</td>
2117 <td>AM64X_DEV_GPIO1</td>
2118 <td>gpio</td>
2119 <td>20</td>
2120 </tr>
2121 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2122 <td>3</td>
2123 <td>111</td>
2124 <td>AM64X_DEV_GPIO1</td>
2125 <td>gpio</td>
2126 <td>21</td>
2127 </tr>
2128 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2129 <td>3</td>
2130 <td>112</td>
2131 <td>AM64X_DEV_GPIO1</td>
2132 <td>gpio</td>
2133 <td>22</td>
2134 </tr>
2135 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2136 <td>3</td>
2137 <td>113</td>
2138 <td>AM64X_DEV_GPIO1</td>
2139 <td>gpio</td>
2140 <td>23</td>
2141 </tr>
2142 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2143 <td>3</td>
2144 <td>114</td>
2145 <td>AM64X_DEV_GPIO1</td>
2146 <td>gpio</td>
2147 <td>24</td>
2148 </tr>
2149 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2150 <td>3</td>
2151 <td>115</td>
2152 <td>AM64X_DEV_GPIO1</td>
2153 <td>gpio</td>
2154 <td>25</td>
2155 </tr>
2156 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2157 <td>3</td>
2158 <td>116</td>
2159 <td>AM64X_DEV_GPIO1</td>
2160 <td>gpio</td>
2161 <td>26</td>
2162 </tr>
2163 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2164 <td>3</td>
2165 <td>117</td>
2166 <td>AM64X_DEV_GPIO1</td>
2167 <td>gpio</td>
2168 <td>27</td>
2169 </tr>
2170 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2171 <td>3</td>
2172 <td>118</td>
2173 <td>AM64X_DEV_GPIO1</td>
2174 <td>gpio</td>
2175 <td>28</td>
2176 </tr>
2177 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2178 <td>3</td>
2179 <td>119</td>
2180 <td>AM64X_DEV_GPIO1</td>
2181 <td>gpio</td>
2182 <td>29</td>
2183 </tr>
2184 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2185 <td>3</td>
2186 <td>120</td>
2187 <td>AM64X_DEV_GPIO1</td>
2188 <td>gpio</td>
2189 <td>30</td>
2190 </tr>
2191 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2192 <td>3</td>
2193 <td>121</td>
2194 <td>AM64X_DEV_GPIO1</td>
2195 <td>gpio</td>
2196 <td>31</td>
2197 </tr>
2198 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2199 <td>3</td>
2200 <td>122</td>
2201 <td>AM64X_DEV_GPIO1</td>
2202 <td>gpio</td>
2203 <td>32</td>
2204 </tr>
2205 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2206 <td>3</td>
2207 <td>123</td>
2208 <td>AM64X_DEV_GPIO1</td>
2209 <td>gpio</td>
2210 <td>33</td>
2211 </tr>
2212 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2213 <td>3</td>
2214 <td>124</td>
2215 <td>AM64X_DEV_GPIO1</td>
2216 <td>gpio</td>
2217 <td>34</td>
2218 </tr>
2219 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2220 <td>3</td>
2221 <td>125</td>
2222 <td>AM64X_DEV_GPIO1</td>
2223 <td>gpio</td>
2224 <td>35</td>
2225 </tr>
2226 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2227 <td>3</td>
2228 <td>126</td>
2229 <td>AM64X_DEV_GPIO1</td>
2230 <td>gpio</td>
2231 <td>36</td>
2232 </tr>
2233 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2234 <td>3</td>
2235 <td>127</td>
2236 <td>AM64X_DEV_GPIO1</td>
2237 <td>gpio</td>
2238 <td>37</td>
2239 </tr>
2240 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2241 <td>3</td>
2242 <td>128</td>
2243 <td>AM64X_DEV_GPIO1</td>
2244 <td>gpio</td>
2245 <td>38</td>
2246 </tr>
2247 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2248 <td>3</td>
2249 <td>129</td>
2250 <td>AM64X_DEV_GPIO1</td>
2251 <td>gpio</td>
2252 <td>39</td>
2253 </tr>
2254 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2255 <td>3</td>
2256 <td>130</td>
2257 <td>AM64X_DEV_GPIO1</td>
2258 <td>gpio</td>
2259 <td>40</td>
2260 </tr>
2261 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2262 <td>3</td>
2263 <td>131</td>
2264 <td>AM64X_DEV_GPIO1</td>
2265 <td>gpio</td>
2266 <td>41</td>
2267 </tr>
2268 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2269 <td>3</td>
2270 <td>132</td>
2271 <td>AM64X_DEV_GPIO1</td>
2272 <td>gpio</td>
2273 <td>42</td>
2274 </tr>
2275 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2276 <td>3</td>
2277 <td>133</td>
2278 <td>AM64X_DEV_GPIO1</td>
2279 <td>gpio</td>
2280 <td>43</td>
2281 </tr>
2282 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2283 <td>3</td>
2284 <td>134</td>
2285 <td>AM64X_DEV_GPIO1</td>
2286 <td>gpio</td>
2287 <td>44</td>
2288 </tr>
2289 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2290 <td>3</td>
2291 <td>135</td>
2292 <td>AM64X_DEV_GPIO1</td>
2293 <td>gpio</td>
2294 <td>45</td>
2295 </tr>
2296 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2297 <td>3</td>
2298 <td>136</td>
2299 <td>AM64X_DEV_GPIO1</td>
2300 <td>gpio</td>
2301 <td>46</td>
2302 </tr>
2303 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2304 <td>3</td>
2305 <td>137</td>
2306 <td>AM64X_DEV_GPIO1</td>
2307 <td>gpio</td>
2308 <td>47</td>
2309 </tr>
2310 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2311 <td>3</td>
2312 <td>138</td>
2313 <td>AM64X_DEV_GPIO1</td>
2314 <td>gpio</td>
2315 <td>48</td>
2316 </tr>
2317 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2318 <td>3</td>
2319 <td>139</td>
2320 <td>AM64X_DEV_GPIO1</td>
2321 <td>gpio</td>
2322 <td>49</td>
2323 </tr>
2324 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2325 <td>3</td>
2326 <td>140</td>
2327 <td>AM64X_DEV_GPIO1</td>
2328 <td>gpio</td>
2329 <td>50</td>
2330 </tr>
2331 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2332 <td>3</td>
2333 <td>141</td>
2334 <td>AM64X_DEV_GPIO1</td>
2335 <td>gpio</td>
2336 <td>51</td>
2337 </tr>
2338 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2339 <td>3</td>
2340 <td>142</td>
2341 <td>AM64X_DEV_GPIO1</td>
2342 <td>gpio</td>
2343 <td>52</td>
2344 </tr>
2345 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2346 <td>3</td>
2347 <td>143</td>
2348 <td>AM64X_DEV_GPIO1</td>
2349 <td>gpio</td>
2350 <td>53</td>
2351 </tr>
2352 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2353 <td>3</td>
2354 <td>144</td>
2355 <td>AM64X_DEV_GPIO1</td>
2356 <td>gpio</td>
2357 <td>54</td>
2358 </tr>
2359 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2360 <td>3</td>
2361 <td>145</td>
2362 <td>AM64X_DEV_GPIO1</td>
2363 <td>gpio</td>
2364 <td>55</td>
2365 </tr>
2366 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2367 <td>3</td>
2368 <td>146</td>
2369 <td>AM64X_DEV_GPIO1</td>
2370 <td>gpio</td>
2371 <td>56</td>
2372 </tr>
2373 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2374 <td>3</td>
2375 <td>147</td>
2376 <td>AM64X_DEV_GPIO1</td>
2377 <td>gpio</td>
2378 <td>57</td>
2379 </tr>
2380 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2381 <td>3</td>
2382 <td>148</td>
2383 <td>AM64X_DEV_GPIO1</td>
2384 <td>gpio</td>
2385 <td>58</td>
2386 </tr>
2387 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2388 <td>3</td>
2389 <td>149</td>
2390 <td>AM64X_DEV_GPIO1</td>
2391 <td>gpio</td>
2392 <td>59</td>
2393 </tr>
2394 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2395 <td>3</td>
2396 <td>150</td>
2397 <td>AM64X_DEV_GPIO1</td>
2398 <td>gpio</td>
2399 <td>60</td>
2400 </tr>
2401 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2402 <td>3</td>
2403 <td>151</td>
2404 <td>AM64X_DEV_GPIO1</td>
2405 <td>gpio</td>
2406 <td>61</td>
2407 </tr>
2408 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2409 <td>3</td>
2410 <td>152</td>
2411 <td>AM64X_DEV_GPIO1</td>
2412 <td>gpio</td>
2413 <td>62</td>
2414 </tr>
2415 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2416 <td>3</td>
2417 <td>153</td>
2418 <td>AM64X_DEV_GPIO1</td>
2419 <td>gpio</td>
2420 <td>63</td>
2421 </tr>
2422 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2423 <td>3</td>
2424 <td>154</td>
2425 <td>AM64X_DEV_GPIO1</td>
2426 <td>gpio</td>
2427 <td>64</td>
2428 </tr>
2429 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2430 <td>3</td>
2431 <td>155</td>
2432 <td>AM64X_DEV_GPIO1</td>
2433 <td>gpio</td>
2434 <td>65</td>
2435 </tr>
2436 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2437 <td>3</td>
2438 <td>156</td>
2439 <td>AM64X_DEV_GPIO1</td>
2440 <td>gpio</td>
2441 <td>66</td>
2442 </tr>
2443 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2444 <td>3</td>
2445 <td>157</td>
2446 <td>AM64X_DEV_GPIO1</td>
2447 <td>gpio</td>
2448 <td>67</td>
2449 </tr>
2450 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2451 <td>3</td>
2452 <td>158</td>
2453 <td>AM64X_DEV_GPIO1</td>
2454 <td>gpio</td>
2455 <td>68</td>
2456 </tr>
2457 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2458 <td>3</td>
2459 <td>159</td>
2460 <td>AM64X_DEV_GPIO1</td>
2461 <td>gpio</td>
2462 <td>69</td>
2463 </tr>
2464 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2465 <td>3</td>
2466 <td>160</td>
2467 <td>AM64X_DEV_GPIO1</td>
2468 <td>gpio</td>
2469 <td>70</td>
2470 </tr>
2471 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2472 <td>3</td>
2473 <td>161</td>
2474 <td>AM64X_DEV_GPIO1</td>
2475 <td>gpio</td>
2476 <td>71</td>
2477 </tr>
2478 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2479 <td>3</td>
2480 <td>162</td>
2481 <td>AM64X_DEV_GPIO1</td>
2482 <td>gpio</td>
2483 <td>72</td>
2484 </tr>
2485 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2486 <td>3</td>
2487 <td>163</td>
2488 <td>AM64X_DEV_GPIO1</td>
2489 <td>gpio</td>
2490 <td>73</td>
2491 </tr>
2492 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2493 <td>3</td>
2494 <td>164</td>
2495 <td>AM64X_DEV_GPIO1</td>
2496 <td>gpio</td>
2497 <td>74</td>
2498 </tr>
2499 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2500 <td>3</td>
2501 <td>165</td>
2502 <td>AM64X_DEV_GPIO1</td>
2503 <td>gpio</td>
2504 <td>75</td>
2505 </tr>
2506 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2507 <td>3</td>
2508 <td>166</td>
2509 <td>AM64X_DEV_GPIO1</td>
2510 <td>gpio</td>
2511 <td>76</td>
2512 </tr>
2513 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2514 <td>3</td>
2515 <td>167</td>
2516 <td>AM64X_DEV_GPIO1</td>
2517 <td>gpio</td>
2518 <td>77</td>
2519 </tr>
2520 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2521 <td>3</td>
2522 <td>168</td>
2523 <td>AM64X_DEV_GPIO1</td>
2524 <td>gpio</td>
2525 <td>78</td>
2526 </tr>
2527 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2528 <td>3</td>
2529 <td>169</td>
2530 <td>AM64X_DEV_GPIO1</td>
2531 <td>gpio</td>
2532 <td>79</td>
2533 </tr>
2534 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2535 <td>3</td>
2536 <td>170</td>
2537 <td>AM64X_DEV_GPIO1</td>
2538 <td>gpio</td>
2539 <td>80</td>
2540 </tr>
2541 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2542 <td>3</td>
2543 <td>171</td>
2544 <td>AM64X_DEV_GPIO1</td>
2545 <td>gpio</td>
2546 <td>81</td>
2547 </tr>
2548 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2549 <td>3</td>
2550 <td>172</td>
2551 <td>AM64X_DEV_GPIO1</td>
2552 <td>gpio</td>
2553 <td>82</td>
2554 </tr>
2555 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2556 <td>3</td>
2557 <td>173</td>
2558 <td>AM64X_DEV_GPIO1</td>
2559 <td>gpio</td>
2560 <td>83</td>
2561 </tr>
2562 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2563 <td>3</td>
2564 <td>174</td>
2565 <td>AM64X_DEV_GPIO1</td>
2566 <td>gpio</td>
2567 <td>84</td>
2568 </tr>
2569 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2570 <td>3</td>
2571 <td>175</td>
2572 <td>AM64X_DEV_GPIO1</td>
2573 <td>gpio</td>
2574 <td>85</td>
2575 </tr>
2576 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2577 <td>3</td>
2578 <td>176</td>
2579 <td>AM64X_DEV_GPIO1</td>
2580 <td>gpio</td>
2581 <td>86</td>
2582 </tr>
2583 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2584 <td>3</td>
2585 <td>177</td>
2586 <td>AM64X_DEV_GPIO1</td>
2587 <td>gpio</td>
2588 <td>87</td>
2589 </tr>
2590 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2591 <td>3</td>
2592 <td>178</td>
2593 <td>AM64X_DEV_GPIO1</td>
2594 <td>gpio</td>
2595 <td>88</td>
2596 </tr>
2597 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2598 <td>3</td>
2599 <td>179</td>
2600 <td>AM64X_DEV_GPIO1</td>
2601 <td>gpio</td>
2602 <td>89</td>
2603 </tr>
2604 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2605 <td>3</td>
2606 <td>180</td>
2607 <td>AM64X_DEV_GPIO1</td>
2608 <td>gpio_bank</td>
2609 <td>0</td>
2610 </tr>
2611 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2612 <td>3</td>
2613 <td>181</td>
2614 <td>AM64X_DEV_GPIO1</td>
2615 <td>gpio_bank</td>
2616 <td>1</td>
2617 </tr>
2618 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2619 <td>3</td>
2620 <td>182</td>
2621 <td>AM64X_DEV_GPIO1</td>
2622 <td>gpio_bank</td>
2623 <td>2</td>
2624 </tr>
2625 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2626 <td>3</td>
2627 <td>183</td>
2628 <td>AM64X_DEV_GPIO1</td>
2629 <td>gpio_bank</td>
2630 <td>3</td>
2631 </tr>
2632 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2633 <td>3</td>
2634 <td>184</td>
2635 <td>AM64X_DEV_GPIO1</td>
2636 <td>gpio_bank</td>
2637 <td>4</td>
2638 </tr>
2639 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2640 <td>3</td>
2641 <td>185</td>
2642 <td>AM64X_DEV_GPIO1</td>
2643 <td>gpio_bank</td>
2644 <td>5</td>
2645 </tr>
2646 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2647 <td>3</td>
2648 <td>186</td>
2649 <td>AM64X_DEV_GPIO1</td>
2650 <td>gpio_bank</td>
2651 <td>6</td>
2652 </tr>
2653 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2654 <td>3</td>
2655 <td>187</td>
2656 <td>AM64X_DEV_GPIO1</td>
2657 <td>gpio_bank</td>
2658 <td>7</td>
2659 </tr>
2660 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2661 <td>3</td>
2662 <td>188</td>
2663 <td>AM64X_DEV_GPIO1</td>
2664 <td>gpio_bank</td>
2665 <td>8</td>
2666 </tr>
2667 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2668 <td>3</td>
2669 <td>189</td>
2670 <td>Not Connected</td>
2671 <td> </td>
2672 <td> </td>
2673 </tr>
2674 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2675 <td>3</td>
2676 <td>190</td>
2677 <td>AM64X_DEV_GPIO0</td>
2678 <td>gpio_bank</td>
2679 <td>0</td>
2680 </tr>
2681 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2682 <td>3</td>
2683 <td>191</td>
2684 <td>AM64X_DEV_GPIO0</td>
2685 <td>gpio_bank</td>
2686 <td>1</td>
2687 </tr>
2688 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2689 <td>3</td>
2690 <td>192</td>
2691 <td>AM64X_DEV_GPIO0</td>
2692 <td>gpio_bank</td>
2693 <td>2</td>
2694 </tr>
2695 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2696 <td>3</td>
2697 <td>193</td>
2698 <td>AM64X_DEV_GPIO0</td>
2699 <td>gpio_bank</td>
2700 <td>3</td>
2701 </tr>
2702 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2703 <td>3</td>
2704 <td>194</td>
2705 <td>AM64X_DEV_GPIO0</td>
2706 <td>gpio_bank</td>
2707 <td>4</td>
2708 </tr>
2709 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2710 <td>3</td>
2711 <td>195</td>
2712 <td>AM64X_DEV_GPIO0</td>
2713 <td>gpio_bank</td>
2714 <td>5</td>
2715 </tr>
2716 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2717 <td>3</td>
2718 <td>196</td>
2719 <td>AM64X_DEV_GPIO0</td>
2720 <td>gpio_bank</td>
2721 <td>6</td>
2722 </tr>
2723 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2724 <td>3</td>
2725 <td>197</td>
2726 <td>AM64X_DEV_GPIO0</td>
2727 <td>gpio_bank</td>
2728 <td>7</td>
2729 </tr>
2730 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2731 <td>3</td>
2732 <td>198</td>
2733 <td>AM64X_DEV_GPIO0</td>
2734 <td>gpio_bank</td>
2735 <td>8</td>
2736 </tr>
2737 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2738 <td>3</td>
2739 <td>199</td>
2740 <td>Not Connected</td>
2741 <td> </td>
2742 <td> </td>
2743 </tr>
2744 </tbody>
2745 </table>
2746 </div>
2747 <div class="section" id="main-gpiomux-introuter0-interrupt-router-output-destinations">
2748 <span id="pub-soc-am64x-main-gpiomux-introuter0-output-src-list"></span><h2>MAIN_GPIOMUX_INTROUTER0 Interrupt Router Output Destinations<a class="headerlink" href="#main-gpiomux-introuter0-interrupt-router-output-destinations" title="Permalink to this headline">¶</a></h2>
2749 <div class="admonition warning">
2750 <p class="first admonition-title">Warning</p>
2751 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
2752 host within the RM Board Configuration resource assignment array. The RM
2753 Board Configuration is rejected if an overlap with a reserved resource is
2754 detected.</p>
2755 </div>
2756 <table border="1" class="docutils">
2757 <colgroup>
2758 <col width="24%" />
2759 <col width="11%" />
2760 <col width="13%" />
2761 <col width="19%" />
2762 <col width="17%" />
2763 <col width="15%" />
2764 </colgroup>
2765 <thead valign="bottom">
2766 <tr class="row-odd"><th class="head">IR Name</th>
2767 <th class="head">IR Device ID</th>
2768 <th class="head">IR Output Index</th>
2769 <th class="head">Destination Name</th>
2770 <th class="head">Destination Interface</th>
2771 <th class="head">Destination Index</th>
2772 </tr>
2773 </thead>
2774 <tbody valign="top">
2775 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2776 <td>3</td>
2777 <td>0</td>
2778 <td>AM64X_DEV_GICSS0</td>
2779 <td>spi</td>
2780 <td>32</td>
2781 </tr>
2782 <tr class="row-odd"><td> </td>
2783 <td> </td>
2784 <td> </td>
2785 <td>AM64X_DEV_R5FSS0_CORE0</td>
2786 <td>intr</td>
2787 <td>32</td>
2788 </tr>
2789 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2790 <td>3</td>
2791 <td>0</td>
2792 <td>AM64X_DEV_R5FSS0_CORE1</td>
2793 <td>intr</td>
2794 <td>32</td>
2795 </tr>
2796 <tr class="row-odd"><td> </td>
2797 <td> </td>
2798 <td> </td>
2799 <td>AM64X_DEV_R5FSS1_CORE0</td>
2800 <td>intr</td>
2801 <td>32</td>
2802 </tr>
2803 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2804 <td>3</td>
2805 <td>0</td>
2806 <td>AM64X_DEV_R5FSS1_CORE1</td>
2807 <td>intr</td>
2808 <td>32</td>
2809 </tr>
2810 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2811 <td>3</td>
2812 <td>1</td>
2813 <td>AM64X_DEV_GICSS0</td>
2814 <td>spi</td>
2815 <td>33</td>
2816 </tr>
2817 <tr class="row-even"><td> </td>
2818 <td> </td>
2819 <td> </td>
2820 <td>AM64X_DEV_R5FSS0_CORE0</td>
2821 <td>intr</td>
2822 <td>33</td>
2823 </tr>
2824 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2825 <td>3</td>
2826 <td>1</td>
2827 <td>AM64X_DEV_R5FSS0_CORE1</td>
2828 <td>intr</td>
2829 <td>33</td>
2830 </tr>
2831 <tr class="row-even"><td> </td>
2832 <td> </td>
2833 <td> </td>
2834 <td>AM64X_DEV_R5FSS1_CORE0</td>
2835 <td>intr</td>
2836 <td>33</td>
2837 </tr>
2838 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2839 <td>3</td>
2840 <td>1</td>
2841 <td>AM64X_DEV_R5FSS1_CORE1</td>
2842 <td>intr</td>
2843 <td>33</td>
2844 </tr>
2845 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2846 <td>3</td>
2847 <td>2</td>
2848 <td>AM64X_DEV_GICSS0</td>
2849 <td>spi</td>
2850 <td>34</td>
2851 </tr>
2852 <tr class="row-odd"><td> </td>
2853 <td> </td>
2854 <td> </td>
2855 <td>AM64X_DEV_R5FSS0_CORE0</td>
2856 <td>intr</td>
2857 <td>34</td>
2858 </tr>
2859 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2860 <td>3</td>
2861 <td>2</td>
2862 <td>AM64X_DEV_R5FSS0_CORE1</td>
2863 <td>intr</td>
2864 <td>34</td>
2865 </tr>
2866 <tr class="row-odd"><td> </td>
2867 <td> </td>
2868 <td> </td>
2869 <td>AM64X_DEV_R5FSS1_CORE0</td>
2870 <td>intr</td>
2871 <td>34</td>
2872 </tr>
2873 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2874 <td>3</td>
2875 <td>2</td>
2876 <td>AM64X_DEV_R5FSS1_CORE1</td>
2877 <td>intr</td>
2878 <td>34</td>
2879 </tr>
2880 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2881 <td>3</td>
2882 <td>3</td>
2883 <td>AM64X_DEV_GICSS0</td>
2884 <td>spi</td>
2885 <td>35</td>
2886 </tr>
2887 <tr class="row-even"><td> </td>
2888 <td> </td>
2889 <td> </td>
2890 <td>AM64X_DEV_R5FSS0_CORE0</td>
2891 <td>intr</td>
2892 <td>35</td>
2893 </tr>
2894 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2895 <td>3</td>
2896 <td>3</td>
2897 <td>AM64X_DEV_R5FSS0_CORE1</td>
2898 <td>intr</td>
2899 <td>35</td>
2900 </tr>
2901 <tr class="row-even"><td> </td>
2902 <td> </td>
2903 <td> </td>
2904 <td>AM64X_DEV_R5FSS1_CORE0</td>
2905 <td>intr</td>
2906 <td>35</td>
2907 </tr>
2908 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2909 <td>3</td>
2910 <td>3</td>
2911 <td>AM64X_DEV_R5FSS1_CORE1</td>
2912 <td>intr</td>
2913 <td>35</td>
2914 </tr>
2915 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2916 <td>3</td>
2917 <td>4</td>
2918 <td>AM64X_DEV_GICSS0</td>
2919 <td>spi</td>
2920 <td>36</td>
2921 </tr>
2922 <tr class="row-odd"><td> </td>
2923 <td> </td>
2924 <td> </td>
2925 <td>AM64X_DEV_R5FSS0_CORE0</td>
2926 <td>intr</td>
2927 <td>36</td>
2928 </tr>
2929 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2930 <td>3</td>
2931 <td>4</td>
2932 <td>AM64X_DEV_R5FSS0_CORE1</td>
2933 <td>intr</td>
2934 <td>36</td>
2935 </tr>
2936 <tr class="row-odd"><td> </td>
2937 <td> </td>
2938 <td> </td>
2939 <td>AM64X_DEV_R5FSS1_CORE0</td>
2940 <td>intr</td>
2941 <td>36</td>
2942 </tr>
2943 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2944 <td>3</td>
2945 <td>4</td>
2946 <td>AM64X_DEV_R5FSS1_CORE1</td>
2947 <td>intr</td>
2948 <td>36</td>
2949 </tr>
2950 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2951 <td>3</td>
2952 <td>5</td>
2953 <td>AM64X_DEV_GICSS0</td>
2954 <td>spi</td>
2955 <td>37</td>
2956 </tr>
2957 <tr class="row-even"><td> </td>
2958 <td> </td>
2959 <td> </td>
2960 <td>AM64X_DEV_R5FSS0_CORE0</td>
2961 <td>intr</td>
2962 <td>37</td>
2963 </tr>
2964 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2965 <td>3</td>
2966 <td>5</td>
2967 <td>AM64X_DEV_R5FSS0_CORE1</td>
2968 <td>intr</td>
2969 <td>37</td>
2970 </tr>
2971 <tr class="row-even"><td> </td>
2972 <td> </td>
2973 <td> </td>
2974 <td>AM64X_DEV_R5FSS1_CORE0</td>
2975 <td>intr</td>
2976 <td>37</td>
2977 </tr>
2978 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2979 <td>3</td>
2980 <td>5</td>
2981 <td>AM64X_DEV_R5FSS1_CORE1</td>
2982 <td>intr</td>
2983 <td>37</td>
2984 </tr>
2985 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
2986 <td>3</td>
2987 <td>6</td>
2988 <td>AM64X_DEV_GICSS0</td>
2989 <td>spi</td>
2990 <td>38</td>
2991 </tr>
2992 <tr class="row-odd"><td> </td>
2993 <td> </td>
2994 <td> </td>
2995 <td>AM64X_DEV_R5FSS0_CORE0</td>
2996 <td>intr</td>
2997 <td>38</td>
2998 </tr>
2999 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3000 <td>3</td>
3001 <td>6</td>
3002 <td>AM64X_DEV_R5FSS0_CORE1</td>
3003 <td>intr</td>
3004 <td>38</td>
3005 </tr>
3006 <tr class="row-odd"><td> </td>
3007 <td> </td>
3008 <td> </td>
3009 <td>AM64X_DEV_R5FSS1_CORE0</td>
3010 <td>intr</td>
3011 <td>38</td>
3012 </tr>
3013 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3014 <td>3</td>
3015 <td>6</td>
3016 <td>AM64X_DEV_R5FSS1_CORE1</td>
3017 <td>intr</td>
3018 <td>38</td>
3019 </tr>
3020 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3021 <td>3</td>
3022 <td>7</td>
3023 <td>AM64X_DEV_GICSS0</td>
3024 <td>spi</td>
3025 <td>39</td>
3026 </tr>
3027 <tr class="row-even"><td> </td>
3028 <td> </td>
3029 <td> </td>
3030 <td>AM64X_DEV_R5FSS0_CORE0</td>
3031 <td>intr</td>
3032 <td>39</td>
3033 </tr>
3034 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3035 <td>3</td>
3036 <td>7</td>
3037 <td>AM64X_DEV_R5FSS0_CORE1</td>
3038 <td>intr</td>
3039 <td>39</td>
3040 </tr>
3041 <tr class="row-even"><td> </td>
3042 <td> </td>
3043 <td> </td>
3044 <td>AM64X_DEV_R5FSS1_CORE0</td>
3045 <td>intr</td>
3046 <td>39</td>
3047 </tr>
3048 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3049 <td>3</td>
3050 <td>7</td>
3051 <td>AM64X_DEV_R5FSS1_CORE1</td>
3052 <td>intr</td>
3053 <td>39</td>
3054 </tr>
3055 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3056 <td>3</td>
3057 <td>8</td>
3058 <td>AM64X_DEV_GICSS0</td>
3059 <td>spi</td>
3060 <td>40</td>
3061 </tr>
3062 <tr class="row-odd"><td> </td>
3063 <td> </td>
3064 <td> </td>
3065 <td>AM64X_DEV_R5FSS0_CORE0</td>
3066 <td>intr</td>
3067 <td>40</td>
3068 </tr>
3069 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3070 <td>3</td>
3071 <td>8</td>
3072 <td>AM64X_DEV_R5FSS0_CORE1</td>
3073 <td>intr</td>
3074 <td>40</td>
3075 </tr>
3076 <tr class="row-odd"><td> </td>
3077 <td> </td>
3078 <td> </td>
3079 <td>AM64X_DEV_R5FSS1_CORE0</td>
3080 <td>intr</td>
3081 <td>40</td>
3082 </tr>
3083 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3084 <td>3</td>
3085 <td>8</td>
3086 <td>AM64X_DEV_R5FSS1_CORE1</td>
3087 <td>intr</td>
3088 <td>40</td>
3089 </tr>
3090 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3091 <td>3</td>
3092 <td>9</td>
3093 <td>AM64X_DEV_GICSS0</td>
3094 <td>spi</td>
3095 <td>41</td>
3096 </tr>
3097 <tr class="row-even"><td> </td>
3098 <td> </td>
3099 <td> </td>
3100 <td>AM64X_DEV_R5FSS0_CORE0</td>
3101 <td>intr</td>
3102 <td>41</td>
3103 </tr>
3104 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3105 <td>3</td>
3106 <td>9</td>
3107 <td>AM64X_DEV_R5FSS0_CORE1</td>
3108 <td>intr</td>
3109 <td>41</td>
3110 </tr>
3111 <tr class="row-even"><td> </td>
3112 <td> </td>
3113 <td> </td>
3114 <td>AM64X_DEV_R5FSS1_CORE0</td>
3115 <td>intr</td>
3116 <td>41</td>
3117 </tr>
3118 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3119 <td>3</td>
3120 <td>9</td>
3121 <td>AM64X_DEV_R5FSS1_CORE1</td>
3122 <td>intr</td>
3123 <td>41</td>
3124 </tr>
3125 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3126 <td>3</td>
3127 <td>10</td>
3128 <td>AM64X_DEV_GICSS0</td>
3129 <td>spi</td>
3130 <td>42</td>
3131 </tr>
3132 <tr class="row-odd"><td> </td>
3133 <td> </td>
3134 <td> </td>
3135 <td>AM64X_DEV_R5FSS0_CORE0</td>
3136 <td>intr</td>
3137 <td>42</td>
3138 </tr>
3139 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3140 <td>3</td>
3141 <td>10</td>
3142 <td>AM64X_DEV_R5FSS0_CORE1</td>
3143 <td>intr</td>
3144 <td>42</td>
3145 </tr>
3146 <tr class="row-odd"><td> </td>
3147 <td> </td>
3148 <td> </td>
3149 <td>AM64X_DEV_R5FSS1_CORE0</td>
3150 <td>intr</td>
3151 <td>42</td>
3152 </tr>
3153 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3154 <td>3</td>
3155 <td>10</td>
3156 <td>AM64X_DEV_R5FSS1_CORE1</td>
3157 <td>intr</td>
3158 <td>42</td>
3159 </tr>
3160 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3161 <td>3</td>
3162 <td>11</td>
3163 <td>AM64X_DEV_GICSS0</td>
3164 <td>spi</td>
3165 <td>43</td>
3166 </tr>
3167 <tr class="row-even"><td> </td>
3168 <td> </td>
3169 <td> </td>
3170 <td>AM64X_DEV_R5FSS0_CORE0</td>
3171 <td>intr</td>
3172 <td>43</td>
3173 </tr>
3174 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3175 <td>3</td>
3176 <td>11</td>
3177 <td>AM64X_DEV_R5FSS0_CORE1</td>
3178 <td>intr</td>
3179 <td>43</td>
3180 </tr>
3181 <tr class="row-even"><td> </td>
3182 <td> </td>
3183 <td> </td>
3184 <td>AM64X_DEV_R5FSS1_CORE0</td>
3185 <td>intr</td>
3186 <td>43</td>
3187 </tr>
3188 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3189 <td>3</td>
3190 <td>11</td>
3191 <td>AM64X_DEV_R5FSS1_CORE1</td>
3192 <td>intr</td>
3193 <td>43</td>
3194 </tr>
3195 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3196 <td>3</td>
3197 <td>12</td>
3198 <td>AM64X_DEV_GICSS0</td>
3199 <td>spi</td>
3200 <td>44</td>
3201 </tr>
3202 <tr class="row-odd"><td> </td>
3203 <td> </td>
3204 <td> </td>
3205 <td>AM64X_DEV_R5FSS0_CORE0</td>
3206 <td>intr</td>
3207 <td>44</td>
3208 </tr>
3209 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3210 <td>3</td>
3211 <td>12</td>
3212 <td>AM64X_DEV_R5FSS0_CORE1</td>
3213 <td>intr</td>
3214 <td>44</td>
3215 </tr>
3216 <tr class="row-odd"><td> </td>
3217 <td> </td>
3218 <td> </td>
3219 <td>AM64X_DEV_R5FSS1_CORE0</td>
3220 <td>intr</td>
3221 <td>44</td>
3222 </tr>
3223 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3224 <td>3</td>
3225 <td>12</td>
3226 <td>AM64X_DEV_R5FSS1_CORE1</td>
3227 <td>intr</td>
3228 <td>44</td>
3229 </tr>
3230 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3231 <td>3</td>
3232 <td>13</td>
3233 <td>AM64X_DEV_GICSS0</td>
3234 <td>spi</td>
3235 <td>45</td>
3236 </tr>
3237 <tr class="row-even"><td> </td>
3238 <td> </td>
3239 <td> </td>
3240 <td>AM64X_DEV_R5FSS0_CORE0</td>
3241 <td>intr</td>
3242 <td>45</td>
3243 </tr>
3244 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3245 <td>3</td>
3246 <td>13</td>
3247 <td>AM64X_DEV_R5FSS0_CORE1</td>
3248 <td>intr</td>
3249 <td>45</td>
3250 </tr>
3251 <tr class="row-even"><td> </td>
3252 <td> </td>
3253 <td> </td>
3254 <td>AM64X_DEV_R5FSS1_CORE0</td>
3255 <td>intr</td>
3256 <td>45</td>
3257 </tr>
3258 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3259 <td>3</td>
3260 <td>13</td>
3261 <td>AM64X_DEV_R5FSS1_CORE1</td>
3262 <td>intr</td>
3263 <td>45</td>
3264 </tr>
3265 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3266 <td>3</td>
3267 <td>14</td>
3268 <td>AM64X_DEV_GICSS0</td>
3269 <td>spi</td>
3270 <td>46</td>
3271 </tr>
3272 <tr class="row-odd"><td> </td>
3273 <td> </td>
3274 <td> </td>
3275 <td>AM64X_DEV_R5FSS0_CORE0</td>
3276 <td>intr</td>
3277 <td>46</td>
3278 </tr>
3279 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3280 <td>3</td>
3281 <td>14</td>
3282 <td>AM64X_DEV_R5FSS0_CORE1</td>
3283 <td>intr</td>
3284 <td>46</td>
3285 </tr>
3286 <tr class="row-odd"><td> </td>
3287 <td> </td>
3288 <td> </td>
3289 <td>AM64X_DEV_R5FSS1_CORE0</td>
3290 <td>intr</td>
3291 <td>46</td>
3292 </tr>
3293 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3294 <td>3</td>
3295 <td>14</td>
3296 <td>AM64X_DEV_R5FSS1_CORE1</td>
3297 <td>intr</td>
3298 <td>46</td>
3299 </tr>
3300 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3301 <td>3</td>
3302 <td>15</td>
3303 <td>AM64X_DEV_GICSS0</td>
3304 <td>spi</td>
3305 <td>47</td>
3306 </tr>
3307 <tr class="row-even"><td> </td>
3308 <td> </td>
3309 <td> </td>
3310 <td>AM64X_DEV_R5FSS0_CORE0</td>
3311 <td>intr</td>
3312 <td>47</td>
3313 </tr>
3314 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3315 <td>3</td>
3316 <td>15</td>
3317 <td>AM64X_DEV_R5FSS0_CORE1</td>
3318 <td>intr</td>
3319 <td>47</td>
3320 </tr>
3321 <tr class="row-even"><td> </td>
3322 <td> </td>
3323 <td> </td>
3324 <td>AM64X_DEV_R5FSS1_CORE0</td>
3325 <td>intr</td>
3326 <td>47</td>
3327 </tr>
3328 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3329 <td>3</td>
3330 <td>15</td>
3331 <td>AM64X_DEV_R5FSS1_CORE1</td>
3332 <td>intr</td>
3333 <td>47</td>
3334 </tr>
3335 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3336 <td>3</td>
3337 <td>16</td>
3338 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
3339 <td>intaggr_levi_pend</td>
3340 <td>24</td>
3341 </tr>
3342 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3343 <td>3</td>
3344 <td>17</td>
3345 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
3346 <td>intaggr_levi_pend</td>
3347 <td>25</td>
3348 </tr>
3349 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3350 <td>3</td>
3351 <td>18</td>
3352 <td>AM64X_DEV_PRU_ICSSG0</td>
3353 <td>pr1_iep0_cap_intr_req</td>
3354 <td>0</td>
3355 </tr>
3356 <tr class="row-odd"><td> </td>
3357 <td> </td>
3358 <td> </td>
3359 <td>AM64X_DEV_PRU_ICSSG1</td>
3360 <td>pr1_iep0_cap_intr_req</td>
3361 <td>0</td>
3362 </tr>
3363 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3364 <td>3</td>
3365 <td>19</td>
3366 <td>AM64X_DEV_PRU_ICSSG0</td>
3367 <td>pr1_iep0_cap_intr_req</td>
3368 <td>1</td>
3369 </tr>
3370 <tr class="row-odd"><td> </td>
3371 <td> </td>
3372 <td> </td>
3373 <td>AM64X_DEV_PRU_ICSSG1</td>
3374 <td>pr1_iep0_cap_intr_req</td>
3375 <td>1</td>
3376 </tr>
3377 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3378 <td>3</td>
3379 <td>20</td>
3380 <td>AM64X_DEV_PRU_ICSSG0</td>
3381 <td>pr1_iep0_cap_intr_req</td>
3382 <td>2</td>
3383 </tr>
3384 <tr class="row-odd"><td> </td>
3385 <td> </td>
3386 <td> </td>
3387 <td>AM64X_DEV_PRU_ICSSG1</td>
3388 <td>pr1_iep0_cap_intr_req</td>
3389 <td>2</td>
3390 </tr>
3391 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3392 <td>3</td>
3393 <td>21</td>
3394 <td>AM64X_DEV_PRU_ICSSG0</td>
3395 <td>pr1_iep0_cap_intr_req</td>
3396 <td>3</td>
3397 </tr>
3398 <tr class="row-odd"><td> </td>
3399 <td> </td>
3400 <td> </td>
3401 <td>AM64X_DEV_PRU_ICSSG1</td>
3402 <td>pr1_iep0_cap_intr_req</td>
3403 <td>3</td>
3404 </tr>
3405 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3406 <td>3</td>
3407 <td>22</td>
3408 <td>AM64X_DEV_PRU_ICSSG0</td>
3409 <td>pr1_iep0_cap_intr_req</td>
3410 <td>4</td>
3411 </tr>
3412 <tr class="row-odd"><td> </td>
3413 <td> </td>
3414 <td> </td>
3415 <td>AM64X_DEV_PRU_ICSSG1</td>
3416 <td>pr1_iep0_cap_intr_req</td>
3417 <td>4</td>
3418 </tr>
3419 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3420 <td>3</td>
3421 <td>23</td>
3422 <td>AM64X_DEV_PRU_ICSSG0</td>
3423 <td>pr1_iep0_cap_intr_req</td>
3424 <td>5</td>
3425 </tr>
3426 <tr class="row-odd"><td> </td>
3427 <td> </td>
3428 <td> </td>
3429 <td>AM64X_DEV_PRU_ICSSG1</td>
3430 <td>pr1_iep0_cap_intr_req</td>
3431 <td>5</td>
3432 </tr>
3433 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3434 <td>3</td>
3435 <td>24</td>
3436 <td>AM64X_DEV_PRU_ICSSG0</td>
3437 <td>pr1_iep1_cap_intr_req</td>
3438 <td>0</td>
3439 </tr>
3440 <tr class="row-odd"><td> </td>
3441 <td> </td>
3442 <td> </td>
3443 <td>AM64X_DEV_PRU_ICSSG1</td>
3444 <td>pr1_iep1_cap_intr_req</td>
3445 <td>0</td>
3446 </tr>
3447 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3448 <td>3</td>
3449 <td>25</td>
3450 <td>AM64X_DEV_PRU_ICSSG0</td>
3451 <td>pr1_iep1_cap_intr_req</td>
3452 <td>1</td>
3453 </tr>
3454 <tr class="row-odd"><td> </td>
3455 <td> </td>
3456 <td> </td>
3457 <td>AM64X_DEV_PRU_ICSSG1</td>
3458 <td>pr1_iep1_cap_intr_req</td>
3459 <td>1</td>
3460 </tr>
3461 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3462 <td>3</td>
3463 <td>26</td>
3464 <td>AM64X_DEV_PRU_ICSSG0</td>
3465 <td>pr1_iep1_cap_intr_req</td>
3466 <td>2</td>
3467 </tr>
3468 <tr class="row-odd"><td> </td>
3469 <td> </td>
3470 <td> </td>
3471 <td>AM64X_DEV_PRU_ICSSG1</td>
3472 <td>pr1_iep1_cap_intr_req</td>
3473 <td>2</td>
3474 </tr>
3475 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3476 <td>3</td>
3477 <td>27</td>
3478 <td>AM64X_DEV_PRU_ICSSG0</td>
3479 <td>pr1_iep1_cap_intr_req</td>
3480 <td>3</td>
3481 </tr>
3482 <tr class="row-odd"><td> </td>
3483 <td> </td>
3484 <td> </td>
3485 <td>AM64X_DEV_PRU_ICSSG1</td>
3486 <td>pr1_iep1_cap_intr_req</td>
3487 <td>3</td>
3488 </tr>
3489 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3490 <td>3</td>
3491 <td>28</td>
3492 <td>AM64X_DEV_PRU_ICSSG0</td>
3493 <td>pr1_iep1_cap_intr_req</td>
3494 <td>4</td>
3495 </tr>
3496 <tr class="row-odd"><td> </td>
3497 <td> </td>
3498 <td> </td>
3499 <td>AM64X_DEV_PRU_ICSSG1</td>
3500 <td>pr1_iep1_cap_intr_req</td>
3501 <td>4</td>
3502 </tr>
3503 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3504 <td>3</td>
3505 <td>29</td>
3506 <td>AM64X_DEV_PRU_ICSSG0</td>
3507 <td>pr1_iep1_cap_intr_req</td>
3508 <td>5</td>
3509 </tr>
3510 <tr class="row-odd"><td> </td>
3511 <td> </td>
3512 <td> </td>
3513 <td>AM64X_DEV_PRU_ICSSG1</td>
3514 <td>pr1_iep1_cap_intr_req</td>
3515 <td>5</td>
3516 </tr>
3517 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3518 <td>3</td>
3519 <td>30</td>
3520 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
3521 <td>intaggr_levi_pend</td>
3522 <td>16</td>
3523 </tr>
3524 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3525 <td>3</td>
3526 <td>31</td>
3527 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
3528 <td>intaggr_levi_pend</td>
3529 <td>17</td>
3530 </tr>
3531 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3532 <td>3</td>
3533 <td>32</td>
3534 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
3535 <td>intaggr_levi_pend</td>
3536 <td>18</td>
3537 </tr>
3538 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3539 <td>3</td>
3540 <td>33</td>
3541 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
3542 <td>intaggr_levi_pend</td>
3543 <td>19</td>
3544 </tr>
3545 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3546 <td>3</td>
3547 <td>34</td>
3548 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
3549 <td>intaggr_levi_pend</td>
3550 <td>20</td>
3551 </tr>
3552 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3553 <td>3</td>
3554 <td>35</td>
3555 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
3556 <td>intaggr_levi_pend</td>
3557 <td>21</td>
3558 </tr>
3559 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3560 <td>3</td>
3561 <td>36</td>
3562 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
3563 <td>intaggr_levi_pend</td>
3564 <td>22</td>
3565 </tr>
3566 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3567 <td>3</td>
3568 <td>37</td>
3569 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
3570 <td>intaggr_levi_pend</td>
3571 <td>23</td>
3572 </tr>
3573 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3574 <td>3</td>
3575 <td>38</td>
3576 <td>AM64X_DEV_PRU_ICSSG0</td>
3577 <td>pr1_slv_intr</td>
3578 <td>46</td>
3579 </tr>
3580 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3581 <td>3</td>
3582 <td>39</td>
3583 <td>AM64X_DEV_PRU_ICSSG0</td>
3584 <td>pr1_slv_intr</td>
3585 <td>47</td>
3586 </tr>
3587 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3588 <td>3</td>
3589 <td>40</td>
3590 <td>AM64X_DEV_PRU_ICSSG0</td>
3591 <td>pr1_slv_intr</td>
3592 <td>48</td>
3593 </tr>
3594 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3595 <td>3</td>
3596 <td>41</td>
3597 <td>AM64X_DEV_PRU_ICSSG0</td>
3598 <td>pr1_slv_intr</td>
3599 <td>49</td>
3600 </tr>
3601 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3602 <td>3</td>
3603 <td>42</td>
3604 <td>AM64X_DEV_PRU_ICSSG0</td>
3605 <td>pr1_slv_intr</td>
3606 <td>50</td>
3607 </tr>
3608 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3609 <td>3</td>
3610 <td>43</td>
3611 <td>AM64X_DEV_PRU_ICSSG0</td>
3612 <td>pr1_slv_intr</td>
3613 <td>51</td>
3614 </tr>
3615 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3616 <td>3</td>
3617 <td>44</td>
3618 <td>AM64X_DEV_PRU_ICSSG0</td>
3619 <td>pr1_slv_intr</td>
3620 <td>52</td>
3621 </tr>
3622 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3623 <td>3</td>
3624 <td>45</td>
3625 <td>AM64X_DEV_PRU_ICSSG0</td>
3626 <td>pr1_slv_intr</td>
3627 <td>53</td>
3628 </tr>
3629 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3630 <td>3</td>
3631 <td>46</td>
3632 <td>AM64X_DEV_PRU_ICSSG1</td>
3633 <td>pr1_slv_intr</td>
3634 <td>46</td>
3635 </tr>
3636 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3637 <td>3</td>
3638 <td>47</td>
3639 <td>AM64X_DEV_PRU_ICSSG1</td>
3640 <td>pr1_slv_intr</td>
3641 <td>47</td>
3642 </tr>
3643 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3644 <td>3</td>
3645 <td>48</td>
3646 <td>AM64X_DEV_PRU_ICSSG1</td>
3647 <td>pr1_slv_intr</td>
3648 <td>48</td>
3649 </tr>
3650 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3651 <td>3</td>
3652 <td>49</td>
3653 <td>AM64X_DEV_PRU_ICSSG1</td>
3654 <td>pr1_slv_intr</td>
3655 <td>49</td>
3656 </tr>
3657 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3658 <td>3</td>
3659 <td>50</td>
3660 <td>AM64X_DEV_PRU_ICSSG1</td>
3661 <td>pr1_slv_intr</td>
3662 <td>50</td>
3663 </tr>
3664 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3665 <td>3</td>
3666 <td>51</td>
3667 <td>AM64X_DEV_PRU_ICSSG1</td>
3668 <td>pr1_slv_intr</td>
3669 <td>51</td>
3670 </tr>
3671 <tr class="row-even"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3672 <td>3</td>
3673 <td>52</td>
3674 <td>AM64X_DEV_PRU_ICSSG1</td>
3675 <td>pr1_slv_intr</td>
3676 <td>52</td>
3677 </tr>
3678 <tr class="row-odd"><td>AM64X_DEV_MAIN_GPIOMUX_INTROUTER0</td>
3679 <td>3</td>
3680 <td>53</td>
3681 <td>AM64X_DEV_PRU_ICSSG1</td>
3682 <td>pr1_slv_intr</td>
3683 <td>53</td>
3684 </tr>
3685 </tbody>
3686 </table>
3687 </div>
3688 <div class="section" id="mcu-mcu-gpiomux-introuter0-interrupt-router-input-sources">
3689 <span id="pub-soc-am64x-mcu-mcu-gpiomux-introuter0-input-src-list"></span><h2>MCU_MCU_GPIOMUX_INTROUTER0 Interrupt Router Input Sources<a class="headerlink" href="#mcu-mcu-gpiomux-introuter0-interrupt-router-input-sources" title="Permalink to this headline">¶</a></h2>
3690 <div class="admonition warning">
3691 <p class="first admonition-title">Warning</p>
3692 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
3693 host within the RM Board Configuration resource assignment array. The RM
3694 Board Configuration is rejected if an overlap with a reserved resource is
3695 detected.</p>
3696 </div>
3697 <table border="1" class="docutils">
3698 <colgroup>
3699 <col width="29%" />
3700 <col width="12%" />
3701 <col width="14%" />
3702 <col width="16%" />
3703 <col width="16%" />
3704 <col width="12%" />
3705 </colgroup>
3706 <thead valign="bottom">
3707 <tr class="row-odd"><th class="head">IR Name</th>
3708 <th class="head">IR Device ID</th>
3709 <th class="head">IR Input Index</th>
3710 <th class="head">Source Name</th>
3711 <th class="head">Source Interface</th>
3712 <th class="head">Source Index</th>
3713 </tr>
3714 </thead>
3715 <tbody valign="top">
3716 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3717 <td>5</td>
3718 <td>0</td>
3719 <td>AM64X_DEV_MCU_GPIO0</td>
3720 <td>gpio</td>
3721 <td>0</td>
3722 </tr>
3723 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3724 <td>5</td>
3725 <td>1</td>
3726 <td>AM64X_DEV_MCU_GPIO0</td>
3727 <td>gpio</td>
3728 <td>1</td>
3729 </tr>
3730 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3731 <td>5</td>
3732 <td>2</td>
3733 <td>AM64X_DEV_MCU_GPIO0</td>
3734 <td>gpio</td>
3735 <td>2</td>
3736 </tr>
3737 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3738 <td>5</td>
3739 <td>3</td>
3740 <td>AM64X_DEV_MCU_GPIO0</td>
3741 <td>gpio</td>
3742 <td>3</td>
3743 </tr>
3744 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3745 <td>5</td>
3746 <td>4</td>
3747 <td>AM64X_DEV_MCU_GPIO0</td>
3748 <td>gpio</td>
3749 <td>4</td>
3750 </tr>
3751 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3752 <td>5</td>
3753 <td>5</td>
3754 <td>AM64X_DEV_MCU_GPIO0</td>
3755 <td>gpio</td>
3756 <td>5</td>
3757 </tr>
3758 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3759 <td>5</td>
3760 <td>6</td>
3761 <td>AM64X_DEV_MCU_GPIO0</td>
3762 <td>gpio</td>
3763 <td>6</td>
3764 </tr>
3765 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3766 <td>5</td>
3767 <td>7</td>
3768 <td>AM64X_DEV_MCU_GPIO0</td>
3769 <td>gpio</td>
3770 <td>7</td>
3771 </tr>
3772 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3773 <td>5</td>
3774 <td>8</td>
3775 <td>AM64X_DEV_MCU_GPIO0</td>
3776 <td>gpio</td>
3777 <td>8</td>
3778 </tr>
3779 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3780 <td>5</td>
3781 <td>9</td>
3782 <td>AM64X_DEV_MCU_GPIO0</td>
3783 <td>gpio</td>
3784 <td>9</td>
3785 </tr>
3786 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3787 <td>5</td>
3788 <td>10</td>
3789 <td>AM64X_DEV_MCU_GPIO0</td>
3790 <td>gpio</td>
3791 <td>10</td>
3792 </tr>
3793 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3794 <td>5</td>
3795 <td>11</td>
3796 <td>AM64X_DEV_MCU_GPIO0</td>
3797 <td>gpio</td>
3798 <td>11</td>
3799 </tr>
3800 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3801 <td>5</td>
3802 <td>12</td>
3803 <td>AM64X_DEV_MCU_GPIO0</td>
3804 <td>gpio</td>
3805 <td>12</td>
3806 </tr>
3807 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3808 <td>5</td>
3809 <td>13</td>
3810 <td>AM64X_DEV_MCU_GPIO0</td>
3811 <td>gpio</td>
3812 <td>13</td>
3813 </tr>
3814 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3815 <td>5</td>
3816 <td>14</td>
3817 <td>AM64X_DEV_MCU_GPIO0</td>
3818 <td>gpio</td>
3819 <td>14</td>
3820 </tr>
3821 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3822 <td>5</td>
3823 <td>15</td>
3824 <td>AM64X_DEV_MCU_GPIO0</td>
3825 <td>gpio</td>
3826 <td>15</td>
3827 </tr>
3828 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3829 <td>5</td>
3830 <td>16</td>
3831 <td>AM64X_DEV_MCU_GPIO0</td>
3832 <td>gpio</td>
3833 <td>16</td>
3834 </tr>
3835 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3836 <td>5</td>
3837 <td>17</td>
3838 <td>AM64X_DEV_MCU_GPIO0</td>
3839 <td>gpio</td>
3840 <td>17</td>
3841 </tr>
3842 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3843 <td>5</td>
3844 <td>18</td>
3845 <td>AM64X_DEV_MCU_GPIO0</td>
3846 <td>gpio</td>
3847 <td>18</td>
3848 </tr>
3849 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3850 <td>5</td>
3851 <td>19</td>
3852 <td>AM64X_DEV_MCU_GPIO0</td>
3853 <td>gpio</td>
3854 <td>19</td>
3855 </tr>
3856 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3857 <td>5</td>
3858 <td>20</td>
3859 <td>AM64X_DEV_MCU_GPIO0</td>
3860 <td>gpio</td>
3861 <td>20</td>
3862 </tr>
3863 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3864 <td>5</td>
3865 <td>21</td>
3866 <td>AM64X_DEV_MCU_GPIO0</td>
3867 <td>gpio</td>
3868 <td>21</td>
3869 </tr>
3870 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3871 <td>5</td>
3872 <td>22</td>
3873 <td>AM64X_DEV_MCU_GPIO0</td>
3874 <td>gpio</td>
3875 <td>22</td>
3876 </tr>
3877 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3878 <td>5</td>
3879 <td>23</td>
3880 <td>AM64X_DEV_MCU_GPIO0</td>
3881 <td>gpio</td>
3882 <td>23</td>
3883 </tr>
3884 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3885 <td>5</td>
3886 <td>24</td>
3887 <td>AM64X_DEV_MCU_GPIO0</td>
3888 <td>gpio</td>
3889 <td>24</td>
3890 </tr>
3891 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3892 <td>5</td>
3893 <td>25</td>
3894 <td>AM64X_DEV_MCU_GPIO0</td>
3895 <td>gpio</td>
3896 <td>25</td>
3897 </tr>
3898 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3899 <td>5</td>
3900 <td>26</td>
3901 <td>AM64X_DEV_MCU_GPIO0</td>
3902 <td>gpio</td>
3903 <td>26</td>
3904 </tr>
3905 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3906 <td>5</td>
3907 <td>27</td>
3908 <td>AM64X_DEV_MCU_GPIO0</td>
3909 <td>gpio</td>
3910 <td>27</td>
3911 </tr>
3912 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3913 <td>5</td>
3914 <td>28</td>
3915 <td>AM64X_DEV_MCU_GPIO0</td>
3916 <td>gpio</td>
3917 <td>28</td>
3918 </tr>
3919 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3920 <td>5</td>
3921 <td>29</td>
3922 <td>AM64X_DEV_MCU_GPIO0</td>
3923 <td>gpio</td>
3924 <td>29</td>
3925 </tr>
3926 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3927 <td>5</td>
3928 <td>30</td>
3929 <td>AM64X_DEV_MCU_GPIO0</td>
3930 <td>gpio_bank</td>
3931 <td>0</td>
3932 </tr>
3933 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3934 <td>5</td>
3935 <td>31</td>
3936 <td>AM64X_DEV_MCU_GPIO0</td>
3937 <td>gpio_bank</td>
3938 <td>1</td>
3939 </tr>
3940 </tbody>
3941 </table>
3942 </div>
3943 <div class="section" id="mcu-mcu-gpiomux-introuter0-interrupt-router-output-destinations">
3944 <span id="pub-soc-am64x-mcu-mcu-gpiomux-introuter0-output-src-list"></span><h2>MCU_MCU_GPIOMUX_INTROUTER0 Interrupt Router Output Destinations<a class="headerlink" href="#mcu-mcu-gpiomux-introuter0-interrupt-router-output-destinations" title="Permalink to this headline">¶</a></h2>
3945 <div class="admonition warning">
3946 <p class="first admonition-title">Warning</p>
3947 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
3948 host within the RM Board Configuration resource assignment array. The RM
3949 Board Configuration is rejected if an overlap with a reserved resource is
3950 detected.</p>
3951 </div>
3952 <table border="1" class="docutils">
3953 <colgroup>
3954 <col width="26%" />
3955 <col width="11%" />
3956 <col width="13%" />
3957 <col width="19%" />
3958 <col width="17%" />
3959 <col width="14%" />
3960 </colgroup>
3961 <thead valign="bottom">
3962 <tr class="row-odd"><th class="head">IR Name</th>
3963 <th class="head">IR Device ID</th>
3964 <th class="head">IR Output Index</th>
3965 <th class="head">Destination Name</th>
3966 <th class="head">Destination Interface</th>
3967 <th class="head">Destination Index</th>
3968 </tr>
3969 </thead>
3970 <tbody valign="top">
3971 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3972 <td>5</td>
3973 <td>0</td>
3974 <td>AM64X_DEV_GICSS0</td>
3975 <td>spi</td>
3976 <td>104</td>
3977 </tr>
3978 <tr class="row-odd"><td> </td>
3979 <td> </td>
3980 <td> </td>
3981 <td>AM64X_DEV_R5FSS0_CORE0</td>
3982 <td>intr</td>
3983 <td>104</td>
3984 </tr>
3985 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
3986 <td>5</td>
3987 <td>0</td>
3988 <td>AM64X_DEV_R5FSS0_CORE1</td>
3989 <td>intr</td>
3990 <td>104</td>
3991 </tr>
3992 <tr class="row-odd"><td> </td>
3993 <td> </td>
3994 <td> </td>
3995 <td>AM64X_DEV_R5FSS1_CORE0</td>
3996 <td>intr</td>
3997 <td>104</td>
3998 </tr>
3999 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4000 <td>5</td>
4001 <td>0</td>
4002 <td>AM64X_DEV_R5FSS1_CORE1</td>
4003 <td>intr</td>
4004 <td>104</td>
4005 </tr>
4006 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4007 <td>5</td>
4008 <td>1</td>
4009 <td>AM64X_DEV_GICSS0</td>
4010 <td>spi</td>
4011 <td>105</td>
4012 </tr>
4013 <tr class="row-even"><td> </td>
4014 <td> </td>
4015 <td> </td>
4016 <td>AM64X_DEV_R5FSS0_CORE0</td>
4017 <td>intr</td>
4018 <td>105</td>
4019 </tr>
4020 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4021 <td>5</td>
4022 <td>1</td>
4023 <td>AM64X_DEV_R5FSS0_CORE1</td>
4024 <td>intr</td>
4025 <td>105</td>
4026 </tr>
4027 <tr class="row-even"><td> </td>
4028 <td> </td>
4029 <td> </td>
4030 <td>AM64X_DEV_R5FSS1_CORE0</td>
4031 <td>intr</td>
4032 <td>105</td>
4033 </tr>
4034 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4035 <td>5</td>
4036 <td>1</td>
4037 <td>AM64X_DEV_R5FSS1_CORE1</td>
4038 <td>intr</td>
4039 <td>105</td>
4040 </tr>
4041 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4042 <td>5</td>
4043 <td>2</td>
4044 <td>AM64X_DEV_GICSS0</td>
4045 <td>spi</td>
4046 <td>106</td>
4047 </tr>
4048 <tr class="row-odd"><td> </td>
4049 <td> </td>
4050 <td> </td>
4051 <td>AM64X_DEV_R5FSS0_CORE0</td>
4052 <td>intr</td>
4053 <td>106</td>
4054 </tr>
4055 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4056 <td>5</td>
4057 <td>2</td>
4058 <td>AM64X_DEV_R5FSS0_CORE1</td>
4059 <td>intr</td>
4060 <td>106</td>
4061 </tr>
4062 <tr class="row-odd"><td> </td>
4063 <td> </td>
4064 <td> </td>
4065 <td>AM64X_DEV_R5FSS1_CORE0</td>
4066 <td>intr</td>
4067 <td>106</td>
4068 </tr>
4069 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4070 <td>5</td>
4071 <td>2</td>
4072 <td>AM64X_DEV_R5FSS1_CORE1</td>
4073 <td>intr</td>
4074 <td>106</td>
4075 </tr>
4076 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4077 <td>5</td>
4078 <td>3</td>
4079 <td>AM64X_DEV_GICSS0</td>
4080 <td>spi</td>
4081 <td>107</td>
4082 </tr>
4083 <tr class="row-even"><td> </td>
4084 <td> </td>
4085 <td> </td>
4086 <td>AM64X_DEV_R5FSS0_CORE0</td>
4087 <td>intr</td>
4088 <td>107</td>
4089 </tr>
4090 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4091 <td>5</td>
4092 <td>3</td>
4093 <td>AM64X_DEV_R5FSS0_CORE1</td>
4094 <td>intr</td>
4095 <td>107</td>
4096 </tr>
4097 <tr class="row-even"><td> </td>
4098 <td> </td>
4099 <td> </td>
4100 <td>AM64X_DEV_R5FSS1_CORE0</td>
4101 <td>intr</td>
4102 <td>107</td>
4103 </tr>
4104 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4105 <td>5</td>
4106 <td>3</td>
4107 <td>AM64X_DEV_R5FSS1_CORE1</td>
4108 <td>intr</td>
4109 <td>107</td>
4110 </tr>
4111 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4112 <td>5</td>
4113 <td>4</td>
4114 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
4115 <td>nvic</td>
4116 <td>0</td>
4117 </tr>
4118 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4119 <td>5</td>
4120 <td>5</td>
4121 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
4122 <td>nvic</td>
4123 <td>1</td>
4124 </tr>
4125 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4126 <td>5</td>
4127 <td>6</td>
4128 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
4129 <td>nvic</td>
4130 <td>2</td>
4131 </tr>
4132 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4133 <td>5</td>
4134 <td>7</td>
4135 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
4136 <td>nvic</td>
4137 <td>3</td>
4138 </tr>
4139 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4140 <td>5</td>
4141 <td>8</td>
4142 <td>AM64X_DEV_MCU_ESM0</td>
4143 <td>esm_pls_event0</td>
4144 <td>88</td>
4145 </tr>
4146 <tr class="row-odd"><td> </td>
4147 <td> </td>
4148 <td> </td>
4149 <td>AM64X_DEV_MCU_ESM0</td>
4150 <td>esm_pls_event1</td>
4151 <td>88</td>
4152 </tr>
4153 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4154 <td>5</td>
4155 <td>8</td>
4156 <td>AM64X_DEV_MCU_ESM0</td>
4157 <td>esm_pls_event2</td>
4158 <td>88</td>
4159 </tr>
4160 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4161 <td>5</td>
4162 <td>9</td>
4163 <td>AM64X_DEV_MCU_ESM0</td>
4164 <td>esm_pls_event0</td>
4165 <td>89</td>
4166 </tr>
4167 <tr class="row-even"><td> </td>
4168 <td> </td>
4169 <td> </td>
4170 <td>AM64X_DEV_MCU_ESM0</td>
4171 <td>esm_pls_event1</td>
4172 <td>89</td>
4173 </tr>
4174 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4175 <td>5</td>
4176 <td>9</td>
4177 <td>AM64X_DEV_MCU_ESM0</td>
4178 <td>esm_pls_event2</td>
4179 <td>89</td>
4180 </tr>
4181 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4182 <td>5</td>
4183 <td>10</td>
4184 <td>AM64X_DEV_MCU_ESM0</td>
4185 <td>esm_pls_event0</td>
4186 <td>90</td>
4187 </tr>
4188 <tr class="row-odd"><td> </td>
4189 <td> </td>
4190 <td> </td>
4191 <td>AM64X_DEV_MCU_ESM0</td>
4192 <td>esm_pls_event1</td>
4193 <td>90</td>
4194 </tr>
4195 <tr class="row-even"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4196 <td>5</td>
4197 <td>10</td>
4198 <td>AM64X_DEV_MCU_ESM0</td>
4199 <td>esm_pls_event2</td>
4200 <td>90</td>
4201 </tr>
4202 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4203 <td>5</td>
4204 <td>11</td>
4205 <td>AM64X_DEV_MCU_ESM0</td>
4206 <td>esm_pls_event0</td>
4207 <td>91</td>
4208 </tr>
4209 <tr class="row-even"><td> </td>
4210 <td> </td>
4211 <td> </td>
4212 <td>AM64X_DEV_MCU_ESM0</td>
4213 <td>esm_pls_event1</td>
4214 <td>91</td>
4215 </tr>
4216 <tr class="row-odd"><td>AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0</td>
4217 <td>5</td>
4218 <td>11</td>
4219 <td>AM64X_DEV_MCU_ESM0</td>
4220 <td>esm_pls_event2</td>
4221 <td>91</td>
4222 </tr>
4223 </tbody>
4224 </table>
4225 </div>
4226 <div class="section" id="timesync-event-introuter0-interrupt-router-input-sources">
4227 <span id="pub-soc-am64x-timesync-event-introuter0-input-src-list"></span><h2>TIMESYNC_EVENT_INTROUTER0 Interrupt Router Input Sources<a class="headerlink" href="#timesync-event-introuter0-interrupt-router-input-sources" title="Permalink to this headline">¶</a></h2>
4228 <div class="admonition warning">
4229 <p class="first admonition-title">Warning</p>
4230 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
4231 host within the RM Board Configuration resource assignment array. The RM
4232 Board Configuration is rejected if an overlap with a reserved resource is
4233 detected.</p>
4234 </div>
4235 <table border="1" class="docutils">
4236 <colgroup>
4237 <col width="28%" />
4238 <col width="12%" />
4239 <col width="14%" />
4240 <col width="17%" />
4241 <col width="17%" />
4242 <col width="12%" />
4243 </colgroup>
4244 <thead valign="bottom">
4245 <tr class="row-odd"><th class="head">IR Name</th>
4246 <th class="head">IR Device ID</th>
4247 <th class="head">IR Input Index</th>
4248 <th class="head">Source Name</th>
4249 <th class="head">Source Interface</th>
4250 <th class="head">Source Index</th>
4251 </tr>
4252 </thead>
4253 <tbody valign="top">
4254 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4255 <td>6</td>
4256 <td>0</td>
4257 <td>AM64X_DEV_TIMER0</td>
4258 <td>timer_pwm</td>
4259 <td>0</td>
4260 </tr>
4261 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4262 <td>6</td>
4263 <td>1</td>
4264 <td>AM64X_DEV_TIMER1</td>
4265 <td>timer_pwm</td>
4266 <td>0</td>
4267 </tr>
4268 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4269 <td>6</td>
4270 <td>2</td>
4271 <td>AM64X_DEV_TIMER2</td>
4272 <td>timer_pwm</td>
4273 <td>0</td>
4274 </tr>
4275 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4276 <td>6</td>
4277 <td>3</td>
4278 <td>AM64X_DEV_TIMER3</td>
4279 <td>timer_pwm</td>
4280 <td>0</td>
4281 </tr>
4282 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4283 <td>6</td>
4284 <td>4</td>
4285 <td>Not Connected</td>
4286 <td> </td>
4287 <td> </td>
4288 </tr>
4289 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4290 <td>6</td>
4291 <td>5</td>
4292 <td>Not Connected</td>
4293 <td> </td>
4294 <td> </td>
4295 </tr>
4296 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4297 <td>6</td>
4298 <td>6</td>
4299 <td>Not Connected</td>
4300 <td> </td>
4301 <td> </td>
4302 </tr>
4303 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4304 <td>6</td>
4305 <td>7</td>
4306 <td>Not Connected</td>
4307 <td> </td>
4308 <td> </td>
4309 </tr>
4310 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4311 <td>6</td>
4312 <td>8</td>
4313 <td>Not Connected</td>
4314 <td> </td>
4315 <td> </td>
4316 </tr>
4317 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4318 <td>6</td>
4319 <td>9</td>
4320 <td>Not Connected</td>
4321 <td> </td>
4322 <td> </td>
4323 </tr>
4324 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4325 <td>6</td>
4326 <td>10</td>
4327 <td>Not Connected</td>
4328 <td> </td>
4329 <td> </td>
4330 </tr>
4331 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4332 <td>6</td>
4333 <td>11</td>
4334 <td>Not Connected</td>
4335 <td> </td>
4336 <td> </td>
4337 </tr>
4338 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4339 <td>6</td>
4340 <td>12</td>
4341 <td>Not Connected</td>
4342 <td> </td>
4343 <td> </td>
4344 </tr>
4345 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4346 <td>6</td>
4347 <td>13</td>
4348 <td>Not Connected</td>
4349 <td> </td>
4350 <td> </td>
4351 </tr>
4352 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4353 <td>6</td>
4354 <td>14</td>
4355 <td>Not Connected</td>
4356 <td> </td>
4357 <td> </td>
4358 </tr>
4359 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4360 <td>6</td>
4361 <td>15</td>
4362 <td>Not Connected</td>
4363 <td> </td>
4364 <td> </td>
4365 </tr>
4366 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4367 <td>6</td>
4368 <td>16</td>
4369 <td>AM64X_DEV_CPTS0</td>
4370 <td>cpts_genf0</td>
4371 <td>0</td>
4372 </tr>
4373 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4374 <td>6</td>
4375 <td>17</td>
4376 <td>AM64X_DEV_CPTS0</td>
4377 <td>cpts_genf1</td>
4378 <td>0</td>
4379 </tr>
4380 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4381 <td>6</td>
4382 <td>18</td>
4383 <td>AM64X_DEV_CPTS0</td>
4384 <td>cpts_genf2</td>
4385 <td>0</td>
4386 </tr>
4387 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4388 <td>6</td>
4389 <td>19</td>
4390 <td>AM64X_DEV_CPTS0</td>
4391 <td>cpts_genf3</td>
4392 <td>0</td>
4393 </tr>
4394 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4395 <td>6</td>
4396 <td>20</td>
4397 <td>AM64X_DEV_CPTS0</td>
4398 <td>cpts_genf4</td>
4399 <td>0</td>
4400 </tr>
4401 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4402 <td>6</td>
4403 <td>21</td>
4404 <td>AM64X_DEV_CPSW0</td>
4405 <td>cpts_genf0</td>
4406 <td>0</td>
4407 </tr>
4408 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4409 <td>6</td>
4410 <td>22</td>
4411 <td>AM64X_DEV_CPSW0</td>
4412 <td>cpts_genf1</td>
4413 <td>0</td>
4414 </tr>
4415 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4416 <td>6</td>
4417 <td>23</td>
4418 <td>AM64X_DEV_PCIE0</td>
4419 <td>pcie_cpts_genf0</td>
4420 <td>0</td>
4421 </tr>
4422 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4423 <td>6</td>
4424 <td>24</td>
4425 <td>AM64X_DEV_CPTS0</td>
4426 <td>cpts_genf5</td>
4427 <td>0</td>
4428 </tr>
4429 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4430 <td>6</td>
4431 <td>25</td>
4432 <td>AM64X_DEV_PRU_ICSSG0</td>
4433 <td>pr1_edc0_sync0_out</td>
4434 <td>0</td>
4435 </tr>
4436 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4437 <td>6</td>
4438 <td>26</td>
4439 <td>AM64X_DEV_PRU_ICSSG0</td>
4440 <td>pr1_edc0_sync1_out</td>
4441 <td>0</td>
4442 </tr>
4443 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4444 <td>6</td>
4445 <td>27</td>
4446 <td>AM64X_DEV_PRU_ICSSG0</td>
4447 <td>pr1_edc1_sync0_out</td>
4448 <td>0</td>
4449 </tr>
4450 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4451 <td>6</td>
4452 <td>28</td>
4453 <td>AM64X_DEV_PRU_ICSSG0</td>
4454 <td>pr1_edc1_sync1_out</td>
4455 <td>0</td>
4456 </tr>
4457 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4458 <td>6</td>
4459 <td>29</td>
4460 <td>AM64X_DEV_PRU_ICSSG1</td>
4461 <td>pr1_edc0_sync0_out</td>
4462 <td>0</td>
4463 </tr>
4464 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4465 <td>6</td>
4466 <td>30</td>
4467 <td>AM64X_DEV_PRU_ICSSG1</td>
4468 <td>pr1_edc0_sync1_out</td>
4469 <td>0</td>
4470 </tr>
4471 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4472 <td>6</td>
4473 <td>31</td>
4474 <td>AM64X_DEV_PRU_ICSSG1</td>
4475 <td>pr1_edc1_sync0_out</td>
4476 <td>0</td>
4477 </tr>
4478 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4479 <td>6</td>
4480 <td>32</td>
4481 <td>AM64X_DEV_PRU_ICSSG1</td>
4482 <td>pr1_edc1_sync1_out</td>
4483 <td>0</td>
4484 </tr>
4485 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4486 <td>6</td>
4487 <td>33</td>
4488 <td>AM64X_DEV_PCIE0</td>
4489 <td>pcie_cpts_sync</td>
4490 <td>0</td>
4491 </tr>
4492 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4493 <td>6</td>
4494 <td>34</td>
4495 <td>AM64X_DEV_CPSW0</td>
4496 <td>cpts_sync</td>
4497 <td>0</td>
4498 </tr>
4499 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4500 <td>6</td>
4501 <td>35</td>
4502 <td>AM64X_DEV_CPTS0</td>
4503 <td>cpts_sync</td>
4504 <td>0</td>
4505 </tr>
4506 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4507 <td>6</td>
4508 <td>36</td>
4509 <td>AM64X_DEV_GTC0</td>
4510 <td>gtc_push_event</td>
4511 <td>0</td>
4512 </tr>
4513 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4514 <td>6</td>
4515 <td>37</td>
4516 <td>AM64X_DEV_PCIE0</td>
4517 <td>pcie_cpts_hw1_push</td>
4518 <td>0</td>
4519 </tr>
4520 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4521 <td>6</td>
4522 <td>38</td>
4523 <td>AM64X_DEV_PCIE0</td>
4524 <td>pcie_ptm_valid_pulse</td>
4525 <td>0</td>
4526 </tr>
4527 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4528 <td>6</td>
4529 <td>39</td>
4530 <td>AM64X_DEV_EPWM0</td>
4531 <td>epwm_synco_o</td>
4532 <td>0</td>
4533 </tr>
4534 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4535 <td>6</td>
4536 <td>40</td>
4537 <td>AM64X_DEV_EPWM3</td>
4538 <td>epwm_synco_o</td>
4539 <td>0</td>
4540 </tr>
4541 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4542 <td>6</td>
4543 <td>41</td>
4544 <td>AM64X_DEV_EPWM6</td>
4545 <td>epwm_synco_o</td>
4546 <td>0</td>
4547 </tr>
4548 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4549 <td>6</td>
4550 <td>42</td>
4551 <td>Not Connected</td>
4552 <td> </td>
4553 <td> </td>
4554 </tr>
4555 </tbody>
4556 </table>
4557 </div>
4558 <div class="section" id="timesync-event-introuter0-interrupt-router-output-destinations">
4559 <span id="pub-soc-am64x-timesync-event-introuter0-output-src-list"></span><h2>TIMESYNC_EVENT_INTROUTER0 Interrupt Router Output Destinations<a class="headerlink" href="#timesync-event-introuter0-interrupt-router-output-destinations" title="Permalink to this headline">¶</a></h2>
4560 <div class="admonition warning">
4561 <p class="first admonition-title">Warning</p>
4562 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
4563 host within the RM Board Configuration resource assignment array. The RM
4564 Board Configuration is rejected if an overlap with a reserved resource is
4565 detected.</p>
4566 </div>
4567 <table border="1" class="docutils">
4568 <colgroup>
4569 <col width="25%" />
4570 <col width="11%" />
4571 <col width="13%" />
4572 <col width="19%" />
4573 <col width="17%" />
4574 <col width="14%" />
4575 </colgroup>
4576 <thead valign="bottom">
4577 <tr class="row-odd"><th class="head">IR Name</th>
4578 <th class="head">IR Device ID</th>
4579 <th class="head">IR Output Index</th>
4580 <th class="head">Destination Name</th>
4581 <th class="head">Destination Interface</th>
4582 <th class="head">Destination Index</th>
4583 </tr>
4584 </thead>
4585 <tbody valign="top">
4586 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4587 <td>6</td>
4588 <td>0</td>
4589 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4590 <td>intaggr_levi_pend</td>
4591 <td>8</td>
4592 </tr>
4593 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4594 <td>6</td>
4595 <td>1</td>
4596 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4597 <td>intaggr_levi_pend</td>
4598 <td>9</td>
4599 </tr>
4600 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4601 <td>6</td>
4602 <td>2</td>
4603 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4604 <td>intaggr_levi_pend</td>
4605 <td>10</td>
4606 </tr>
4607 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4608 <td>6</td>
4609 <td>3</td>
4610 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4611 <td>intaggr_levi_pend</td>
4612 <td>11</td>
4613 </tr>
4614 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4615 <td>6</td>
4616 <td>4</td>
4617 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4618 <td>intaggr_levi_pend</td>
4619 <td>12</td>
4620 </tr>
4621 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4622 <td>6</td>
4623 <td>5</td>
4624 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4625 <td>intaggr_levi_pend</td>
4626 <td>13</td>
4627 </tr>
4628 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4629 <td>6</td>
4630 <td>6</td>
4631 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4632 <td>intaggr_levi_pend</td>
4633 <td>14</td>
4634 </tr>
4635 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4636 <td>6</td>
4637 <td>7</td>
4638 <td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4639 <td>intaggr_levi_pend</td>
4640 <td>15</td>
4641 </tr>
4642 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4643 <td>6</td>
4644 <td>8</td>
4645 <td>AM64X_DEV_PRU_ICSSG0</td>
4646 <td>pr1_edc0_latch0_in</td>
4647 <td>0</td>
4648 </tr>
4649 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4650 <td>6</td>
4651 <td>9</td>
4652 <td>AM64X_DEV_PRU_ICSSG0</td>
4653 <td>pr1_edc0_latch1_in</td>
4654 <td>0</td>
4655 </tr>
4656 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4657 <td>6</td>
4658 <td>10</td>
4659 <td>AM64X_DEV_PRU_ICSSG0</td>
4660 <td>pr1_edc1_latch0_in</td>
4661 <td>0</td>
4662 </tr>
4663 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4664 <td>6</td>
4665 <td>11</td>
4666 <td>AM64X_DEV_PRU_ICSSG0</td>
4667 <td>pr1_edc1_latch1_in</td>
4668 <td>0</td>
4669 </tr>
4670 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4671 <td>6</td>
4672 <td>12</td>
4673 <td>AM64X_DEV_PRU_ICSSG1</td>
4674 <td>pr1_edc0_latch0_in</td>
4675 <td>0</td>
4676 </tr>
4677 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4678 <td>6</td>
4679 <td>13</td>
4680 <td>AM64X_DEV_PRU_ICSSG1</td>
4681 <td>pr1_edc0_latch1_in</td>
4682 <td>0</td>
4683 </tr>
4684 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4685 <td>6</td>
4686 <td>14</td>
4687 <td>AM64X_DEV_PRU_ICSSG1</td>
4688 <td>pr1_edc1_latch0_in</td>
4689 <td>0</td>
4690 </tr>
4691 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4692 <td>6</td>
4693 <td>15</td>
4694 <td>AM64X_DEV_PRU_ICSSG1</td>
4695 <td>pr1_edc1_latch1_in</td>
4696 <td>0</td>
4697 </tr>
4698 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4699 <td>6</td>
4700 <td>16</td>
4701 <td>AM64X_DEV_CPTS0</td>
4702 <td>cpts_hw1_push</td>
4703 <td>0</td>
4704 </tr>
4705 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4706 <td>6</td>
4707 <td>17</td>
4708 <td>AM64X_DEV_CPTS0</td>
4709 <td>cpts_hw2_push</td>
4710 <td>0</td>
4711 </tr>
4712 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4713 <td>6</td>
4714 <td>18</td>
4715 <td>AM64X_DEV_CPTS0</td>
4716 <td>cpts_hw3_push</td>
4717 <td>0</td>
4718 </tr>
4719 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4720 <td>6</td>
4721 <td>19</td>
4722 <td>AM64X_DEV_CPTS0</td>
4723 <td>cpts_hw4_push</td>
4724 <td>0</td>
4725 </tr>
4726 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4727 <td>6</td>
4728 <td>20</td>
4729 <td>AM64X_DEV_CPTS0</td>
4730 <td>cpts_hw5_push</td>
4731 <td>0</td>
4732 </tr>
4733 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4734 <td>6</td>
4735 <td>21</td>
4736 <td>AM64X_DEV_CPTS0</td>
4737 <td>cpts_hw6_push</td>
4738 <td>0</td>
4739 </tr>
4740 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4741 <td>6</td>
4742 <td>22</td>
4743 <td>AM64X_DEV_CPTS0</td>
4744 <td>cpts_hw7_push</td>
4745 <td>0</td>
4746 </tr>
4747 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4748 <td>6</td>
4749 <td>23</td>
4750 <td>AM64X_DEV_CPTS0</td>
4751 <td>cpts_hw8_push</td>
4752 <td>0</td>
4753 </tr>
4754 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4755 <td>6</td>
4756 <td>24</td>
4757 <td>Not Connected</td>
4758 <td> </td>
4759 <td> </td>
4760 </tr>
4761 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4762 <td>6</td>
4763 <td>25</td>
4764 <td>Not Connected</td>
4765 <td> </td>
4766 <td> </td>
4767 </tr>
4768 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4769 <td>6</td>
4770 <td>26</td>
4771 <td>Not Connected</td>
4772 <td> </td>
4773 <td> </td>
4774 </tr>
4775 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4776 <td>6</td>
4777 <td>27</td>
4778 <td>Not Connected</td>
4779 <td> </td>
4780 <td> </td>
4781 </tr>
4782 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4783 <td>6</td>
4784 <td>28</td>
4785 <td>Not Connected</td>
4786 <td> </td>
4787 <td> </td>
4788 </tr>
4789 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4790 <td>6</td>
4791 <td>29</td>
4792 <td>AM64X_DEV_PCIE0</td>
4793 <td>pcie_cpts_hw2_push</td>
4794 <td>0</td>
4795 </tr>
4796 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4797 <td>6</td>
4798 <td>30</td>
4799 <td>AM64X_DEV_CPSW0</td>
4800 <td>cpts_hw1_push</td>
4801 <td>0</td>
4802 </tr>
4803 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4804 <td>6</td>
4805 <td>31</td>
4806 <td>AM64X_DEV_CPSW0</td>
4807 <td>cpts_hw2_push</td>
4808 <td>0</td>
4809 </tr>
4810 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4811 <td>6</td>
4812 <td>32</td>
4813 <td>AM64X_DEV_CPSW0</td>
4814 <td>cpts_hw3_push</td>
4815 <td>0</td>
4816 </tr>
4817 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4818 <td>6</td>
4819 <td>33</td>
4820 <td>AM64X_DEV_CPSW0</td>
4821 <td>cpts_hw4_push</td>
4822 <td>0</td>
4823 </tr>
4824 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4825 <td>6</td>
4826 <td>34</td>
4827 <td>AM64X_DEV_CPSW0</td>
4828 <td>cpts_hw5_push</td>
4829 <td>0</td>
4830 </tr>
4831 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4832 <td>6</td>
4833 <td>35</td>
4834 <td>AM64X_DEV_CPSW0</td>
4835 <td>cpts_hw6_push</td>
4836 <td>0</td>
4837 </tr>
4838 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4839 <td>6</td>
4840 <td>36</td>
4841 <td>AM64X_DEV_CPSW0</td>
4842 <td>cpts_hw7_push</td>
4843 <td>0</td>
4844 </tr>
4845 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4846 <td>6</td>
4847 <td>37</td>
4848 <td>AM64X_DEV_CPSW0</td>
4849 <td>cpts_hw8_push</td>
4850 <td>0</td>
4851 </tr>
4852 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4853 <td>6</td>
4854 <td>38</td>
4855 <td>Not Connected</td>
4856 <td> </td>
4857 <td> </td>
4858 </tr>
4859 <tr class="row-odd"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4860 <td>6</td>
4861 <td>39</td>
4862 <td>Not Connected</td>
4863 <td> </td>
4864 <td> </td>
4865 </tr>
4866 <tr class="row-even"><td>AM64X_DEV_TIMESYNC_EVENT_INTROUTER0</td>
4867 <td>6</td>
4868 <td>40</td>
4869 <td>Not Connected</td>
4870 <td> </td>
4871 <td> </td>
4872 </tr>
4873 </tbody>
4874 </table>
4875 </div>
4876 <div class="section" id="interrupt-aggregator-device-ids">
4877 <span id="pub-soc-am64x-ia-device-ids"></span><h2>Interrupt Aggregator Device IDs<a class="headerlink" href="#interrupt-aggregator-device-ids" title="Permalink to this headline">¶</a></h2>
4878 <p>Some System Firmware TISCI message APIs require the Interrupt Aggregator device
4879 ID be provided as part of the request. Based on <a class="reference internal" href="devices.html"><span class="doc">AM64X Device IDs</span></a> these are the valid Interrupt Aggregator device IDs.</p>
4880 <table border="1" class="docutils">
4881 <colgroup>
4882 <col width="51%" />
4883 <col width="49%" />
4884 </colgroup>
4885 <thead valign="bottom">
4886 <tr class="row-odd"><th class="head">Interrupt Aggregator Device Name</th>
4887 <th class="head">Interrupt Aggregator Device ID</th>
4888 </tr>
4889 </thead>
4890 <tbody valign="top">
4891 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4892 <td>28</td>
4893 </tr>
4894 </tbody>
4895 </table>
4896 </div>
4897 <div class="section" id="interrupt-aggregator-virtual-interrupts">
4898 <span id="pub-soc-am64x-ia-vints"></span><h2>Interrupt Aggregator Virtual Interrupts<a class="headerlink" href="#interrupt-aggregator-virtual-interrupts" title="Permalink to this headline">¶</a></h2>
4899 <p>This section describes Interrupt Aggregator virtual interrupts. The virtual
4900 interrupts are used in interrupt management based TISCI messages.</p>
4901 <div class="admonition warning">
4902 <p class="first admonition-title">Warning</p>
4903 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
4904 host within the RM Board Configuration resource assignment array. The RM
4905 Board Configuration is rejected if an overlap with a reserved resource is
4906 detected.</p>
4907 </div>
4908 <table border="1" class="docutils">
4909 <colgroup>
4910 <col width="56%" />
4911 <col width="44%" />
4912 </colgroup>
4913 <thead valign="bottom">
4914 <tr class="row-odd"><th class="head">Interrupt Aggregator Name</th>
4915 <th class="head">Virtual Interrupt Range</th>
4916 </tr>
4917 </thead>
4918 <tbody valign="top">
4919 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
4920 (<strong>RESERVED BY SYSTEM FIRMWARE</strong>)</td>
4921 <td>0 to 3</td>
4922 </tr>
4923 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4924 <td>4 to 39</td>
4925 </tr>
4926 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
4927 (<strong>RESERVED BY SYSTEM FIRMWARE</strong>)</td>
4928 <td>40 to 43</td>
4929 </tr>
4930 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4931 <td>44 to 87</td>
4932 </tr>
4933 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
4934 (<strong>RESERVED BY SYSTEM FIRMWARE</strong>)</td>
4935 <td>88 to 91</td>
4936 </tr>
4937 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4938 <td>92 to 135</td>
4939 </tr>
4940 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
4941 (<strong>RESERVED BY SYSTEM FIRMWARE</strong>)</td>
4942 <td>136 to 138</td>
4943 </tr>
4944 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
4945 <td>139 to 183</td>
4946 </tr>
4947 </tbody>
4948 </table>
4949 </div>
4950 <div class="section" id="dmass0-intaggr-0-interrupt-aggregator-virtual-interrupt-destinations">
4951 <span id="pub-soc-am64x-dmass0-intaggr-0-vint-output-dst-list"></span><h2>DMASS0_INTAGGR_0 Interrupt Aggregator Virtual Interrupt Destinations<a class="headerlink" href="#dmass0-intaggr-0-interrupt-aggregator-virtual-interrupt-destinations" title="Permalink to this headline">¶</a></h2>
4952 <div class="admonition warning">
4953 <p class="first admonition-title">Warning</p>
4954 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
4955 host within the RM Board Configuration resource assignment array. The RM
4956 Board Configuration is rejected if an overlap with a reserved resource is
4957 detected.</p>
4958 </div>
4959 <table border="1" class="docutils">
4960 <colgroup>
4961 <col width="25%" />
4962 <col width="11%" />
4963 <col width="12%" />
4964 <col width="20%" />
4965 <col width="18%" />
4966 <col width="15%" />
4967 </colgroup>
4968 <thead valign="bottom">
4969 <tr class="row-odd"><th class="head">IA Name</th>
4970 <th class="head">IA Device ID</th>
4971 <th class="head">IA VINT Index</th>
4972 <th class="head">Destination Name</th>
4973 <th class="head">Destination Interface</th>
4974 <th class="head">Destination Index</th>
4975 </tr>
4976 </thead>
4977 <tbody valign="top">
4978 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
4979 (<strong>Reserved by System Firmware</strong>)</td>
4980 <td>28</td>
4981 <td>0</td>
4982 <td>AM64X_DEV_GICSS0</td>
4983 <td>spi</td>
4984 <td>64</td>
4985 </tr>
4986 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0
4987 (<strong>Reserved by System Firmware</strong>)</td>
4988 <td>28</td>
4989 <td>1</td>
4990 <td>AM64X_DEV_GICSS0</td>
4991 <td>spi</td>
4992 <td>65</td>
4993 </tr>
4994 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
4995 (<strong>Reserved by System Firmware</strong>)</td>
4996 <td>28</td>
4997 <td>2</td>
4998 <td>AM64X_DEV_GICSS0</td>
4999 <td>spi</td>
5000 <td>66</td>
5001 </tr>
5002 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0
5003 (<strong>Reserved by System Firmware</strong>)</td>
5004 <td>28</td>
5005 <td>3</td>
5006 <td>AM64X_DEV_GICSS0</td>
5007 <td>spi</td>
5008 <td>67</td>
5009 </tr>
5010 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5011 <td>28</td>
5012 <td>4</td>
5013 <td>AM64X_DEV_GICSS0</td>
5014 <td>spi</td>
5015 <td>68</td>
5016 </tr>
5017 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5018 <td>28</td>
5019 <td>5</td>
5020 <td>AM64X_DEV_GICSS0</td>
5021 <td>spi</td>
5022 <td>69</td>
5023 </tr>
5024 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5025 <td>28</td>
5026 <td>6</td>
5027 <td>AM64X_DEV_GICSS0</td>
5028 <td>spi</td>
5029 <td>70</td>
5030 </tr>
5031 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5032 <td>28</td>
5033 <td>7</td>
5034 <td>AM64X_DEV_GICSS0</td>
5035 <td>spi</td>
5036 <td>71</td>
5037 </tr>
5038 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5039 <td>28</td>
5040 <td>8</td>
5041 <td>AM64X_DEV_GICSS0</td>
5042 <td>spi</td>
5043 <td>72</td>
5044 </tr>
5045 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5046 <td>28</td>
5047 <td>9</td>
5048 <td>AM64X_DEV_GICSS0</td>
5049 <td>spi</td>
5050 <td>73</td>
5051 </tr>
5052 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5053 <td>28</td>
5054 <td>10</td>
5055 <td>AM64X_DEV_GICSS0</td>
5056 <td>spi</td>
5057 <td>74</td>
5058 </tr>
5059 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5060 <td>28</td>
5061 <td>11</td>
5062 <td>AM64X_DEV_GICSS0</td>
5063 <td>spi</td>
5064 <td>75</td>
5065 </tr>
5066 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5067 <td>28</td>
5068 <td>12</td>
5069 <td>AM64X_DEV_GICSS0</td>
5070 <td>spi</td>
5071 <td>76</td>
5072 </tr>
5073 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5074 <td>28</td>
5075 <td>13</td>
5076 <td>AM64X_DEV_GICSS0</td>
5077 <td>spi</td>
5078 <td>77</td>
5079 </tr>
5080 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5081 <td>28</td>
5082 <td>14</td>
5083 <td>AM64X_DEV_GICSS0</td>
5084 <td>spi</td>
5085 <td>78</td>
5086 </tr>
5087 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5088 <td>28</td>
5089 <td>15</td>
5090 <td>AM64X_DEV_GICSS0</td>
5091 <td>spi</td>
5092 <td>79</td>
5093 </tr>
5094 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5095 <td>28</td>
5096 <td>16</td>
5097 <td>AM64X_DEV_GICSS0</td>
5098 <td>spi</td>
5099 <td>80</td>
5100 </tr>
5101 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5102 <td>28</td>
5103 <td>17</td>
5104 <td>AM64X_DEV_GICSS0</td>
5105 <td>spi</td>
5106 <td>81</td>
5107 </tr>
5108 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5109 <td>28</td>
5110 <td>18</td>
5111 <td>AM64X_DEV_GICSS0</td>
5112 <td>spi</td>
5113 <td>82</td>
5114 </tr>
5115 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5116 <td>28</td>
5117 <td>19</td>
5118 <td>AM64X_DEV_GICSS0</td>
5119 <td>spi</td>
5120 <td>83</td>
5121 </tr>
5122 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5123 <td>28</td>
5124 <td>20</td>
5125 <td>AM64X_DEV_GICSS0</td>
5126 <td>spi</td>
5127 <td>84</td>
5128 </tr>
5129 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5130 <td>28</td>
5131 <td>21</td>
5132 <td>AM64X_DEV_GICSS0</td>
5133 <td>spi</td>
5134 <td>85</td>
5135 </tr>
5136 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5137 <td>28</td>
5138 <td>22</td>
5139 <td>AM64X_DEV_GICSS0</td>
5140 <td>spi</td>
5141 <td>86</td>
5142 </tr>
5143 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5144 <td>28</td>
5145 <td>23</td>
5146 <td>AM64X_DEV_GICSS0</td>
5147 <td>spi</td>
5148 <td>87</td>
5149 </tr>
5150 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5151 <td>28</td>
5152 <td>24</td>
5153 <td>AM64X_DEV_GICSS0</td>
5154 <td>spi</td>
5155 <td>88</td>
5156 </tr>
5157 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5158 <td>28</td>
5159 <td>25</td>
5160 <td>AM64X_DEV_GICSS0</td>
5161 <td>spi</td>
5162 <td>89</td>
5163 </tr>
5164 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5165 <td>28</td>
5166 <td>26</td>
5167 <td>AM64X_DEV_GICSS0</td>
5168 <td>spi</td>
5169 <td>90</td>
5170 </tr>
5171 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5172 <td>28</td>
5173 <td>27</td>
5174 <td>AM64X_DEV_GICSS0</td>
5175 <td>spi</td>
5176 <td>91</td>
5177 </tr>
5178 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5179 <td>28</td>
5180 <td>28</td>
5181 <td>AM64X_DEV_GICSS0</td>
5182 <td>spi</td>
5183 <td>92</td>
5184 </tr>
5185 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5186 <td>28</td>
5187 <td>29</td>
5188 <td>AM64X_DEV_GICSS0</td>
5189 <td>spi</td>
5190 <td>93</td>
5191 </tr>
5192 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5193 <td>28</td>
5194 <td>30</td>
5195 <td>AM64X_DEV_GICSS0</td>
5196 <td>spi</td>
5197 <td>94</td>
5198 </tr>
5199 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5200 <td>28</td>
5201 <td>31</td>
5202 <td>AM64X_DEV_GICSS0</td>
5203 <td>spi</td>
5204 <td>95</td>
5205 </tr>
5206 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5207 <td>28</td>
5208 <td>32</td>
5209 <td>AM64X_DEV_GICSS0</td>
5210 <td>spi</td>
5211 <td>96</td>
5212 </tr>
5213 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5214 <td>28</td>
5215 <td>33</td>
5216 <td>AM64X_DEV_GICSS0</td>
5217 <td>spi</td>
5218 <td>97</td>
5219 </tr>
5220 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5221 <td>28</td>
5222 <td>34</td>
5223 <td>AM64X_DEV_GICSS0</td>
5224 <td>spi</td>
5225 <td>98</td>
5226 </tr>
5227 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5228 <td>28</td>
5229 <td>35</td>
5230 <td>AM64X_DEV_GICSS0</td>
5231 <td>spi</td>
5232 <td>99</td>
5233 </tr>
5234 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5235 <td>28</td>
5236 <td>36</td>
5237 <td>AM64X_DEV_GICSS0</td>
5238 <td>spi</td>
5239 <td>100</td>
5240 </tr>
5241 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5242 <td>28</td>
5243 <td>37</td>
5244 <td>AM64X_DEV_GICSS0</td>
5245 <td>spi</td>
5246 <td>101</td>
5247 </tr>
5248 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5249 <td>28</td>
5250 <td>38</td>
5251 <td>AM64X_DEV_GICSS0</td>
5252 <td>spi</td>
5253 <td>102</td>
5254 </tr>
5255 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5256 <td>28</td>
5257 <td>39</td>
5258 <td>AM64X_DEV_GICSS0</td>
5259 <td>spi</td>
5260 <td>103</td>
5261 </tr>
5262 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
5263 (<strong>Reserved by System Firmware</strong>)</td>
5264 <td>28</td>
5265 <td>40</td>
5266 <td>AM64X_DEV_R5FSS0_CORE0</td>
5267 <td>intr</td>
5268 <td>64</td>
5269 </tr>
5270 <tr class="row-odd"><td> </td>
5271 <td> </td>
5272 <td> </td>
5273 <td>AM64X_DEV_R5FSS0_CORE1</td>
5274 <td>intr</td>
5275 <td>64</td>
5276 </tr>
5277 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
5278 (<strong>Reserved by System Firmware</strong>)</td>
5279 <td>28</td>
5280 <td>41</td>
5281 <td>AM64X_DEV_R5FSS0_CORE0</td>
5282 <td>intr</td>
5283 <td>65</td>
5284 </tr>
5285 <tr class="row-odd"><td> </td>
5286 <td> </td>
5287 <td> </td>
5288 <td>AM64X_DEV_R5FSS0_CORE1</td>
5289 <td>intr</td>
5290 <td>65</td>
5291 </tr>
5292 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
5293 (<strong>Reserved by System Firmware</strong>)</td>
5294 <td>28</td>
5295 <td>42</td>
5296 <td>AM64X_DEV_R5FSS0_CORE0</td>
5297 <td>intr</td>
5298 <td>66</td>
5299 </tr>
5300 <tr class="row-odd"><td> </td>
5301 <td> </td>
5302 <td> </td>
5303 <td>AM64X_DEV_R5FSS0_CORE1</td>
5304 <td>intr</td>
5305 <td>66</td>
5306 </tr>
5307 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
5308 (<strong>Reserved by System Firmware</strong>)</td>
5309 <td>28</td>
5310 <td>43</td>
5311 <td>AM64X_DEV_R5FSS0_CORE0</td>
5312 <td>intr</td>
5313 <td>67</td>
5314 </tr>
5315 <tr class="row-odd"><td> </td>
5316 <td> </td>
5317 <td> </td>
5318 <td>AM64X_DEV_R5FSS0_CORE1</td>
5319 <td>intr</td>
5320 <td>67</td>
5321 </tr>
5322 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5323 <td>28</td>
5324 <td>44</td>
5325 <td>AM64X_DEV_R5FSS0_CORE0</td>
5326 <td>intr</td>
5327 <td>68</td>
5328 </tr>
5329 <tr class="row-odd"><td> </td>
5330 <td> </td>
5331 <td> </td>
5332 <td>AM64X_DEV_R5FSS0_CORE1</td>
5333 <td>intr</td>
5334 <td>68</td>
5335 </tr>
5336 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5337 <td>28</td>
5338 <td>45</td>
5339 <td>AM64X_DEV_R5FSS0_CORE0</td>
5340 <td>intr</td>
5341 <td>69</td>
5342 </tr>
5343 <tr class="row-odd"><td> </td>
5344 <td> </td>
5345 <td> </td>
5346 <td>AM64X_DEV_R5FSS0_CORE1</td>
5347 <td>intr</td>
5348 <td>69</td>
5349 </tr>
5350 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5351 <td>28</td>
5352 <td>46</td>
5353 <td>AM64X_DEV_R5FSS0_CORE0</td>
5354 <td>intr</td>
5355 <td>70</td>
5356 </tr>
5357 <tr class="row-odd"><td> </td>
5358 <td> </td>
5359 <td> </td>
5360 <td>AM64X_DEV_R5FSS0_CORE1</td>
5361 <td>intr</td>
5362 <td>70</td>
5363 </tr>
5364 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5365 <td>28</td>
5366 <td>47</td>
5367 <td>AM64X_DEV_R5FSS0_CORE0</td>
5368 <td>intr</td>
5369 <td>71</td>
5370 </tr>
5371 <tr class="row-odd"><td> </td>
5372 <td> </td>
5373 <td> </td>
5374 <td>AM64X_DEV_R5FSS0_CORE1</td>
5375 <td>intr</td>
5376 <td>71</td>
5377 </tr>
5378 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5379 <td>28</td>
5380 <td>48</td>
5381 <td>AM64X_DEV_R5FSS0_CORE0</td>
5382 <td>intr</td>
5383 <td>72</td>
5384 </tr>
5385 <tr class="row-odd"><td> </td>
5386 <td> </td>
5387 <td> </td>
5388 <td>AM64X_DEV_R5FSS0_CORE1</td>
5389 <td>intr</td>
5390 <td>72</td>
5391 </tr>
5392 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5393 <td>28</td>
5394 <td>49</td>
5395 <td>AM64X_DEV_R5FSS0_CORE0</td>
5396 <td>intr</td>
5397 <td>73</td>
5398 </tr>
5399 <tr class="row-odd"><td> </td>
5400 <td> </td>
5401 <td> </td>
5402 <td>AM64X_DEV_R5FSS0_CORE1</td>
5403 <td>intr</td>
5404 <td>73</td>
5405 </tr>
5406 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5407 <td>28</td>
5408 <td>50</td>
5409 <td>AM64X_DEV_R5FSS0_CORE0</td>
5410 <td>intr</td>
5411 <td>74</td>
5412 </tr>
5413 <tr class="row-odd"><td> </td>
5414 <td> </td>
5415 <td> </td>
5416 <td>AM64X_DEV_R5FSS0_CORE1</td>
5417 <td>intr</td>
5418 <td>74</td>
5419 </tr>
5420 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5421 <td>28</td>
5422 <td>51</td>
5423 <td>AM64X_DEV_R5FSS0_CORE0</td>
5424 <td>intr</td>
5425 <td>75</td>
5426 </tr>
5427 <tr class="row-odd"><td> </td>
5428 <td> </td>
5429 <td> </td>
5430 <td>AM64X_DEV_R5FSS0_CORE1</td>
5431 <td>intr</td>
5432 <td>75</td>
5433 </tr>
5434 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5435 <td>28</td>
5436 <td>52</td>
5437 <td>AM64X_DEV_R5FSS0_CORE0</td>
5438 <td>intr</td>
5439 <td>76</td>
5440 </tr>
5441 <tr class="row-odd"><td> </td>
5442 <td> </td>
5443 <td> </td>
5444 <td>AM64X_DEV_R5FSS0_CORE1</td>
5445 <td>intr</td>
5446 <td>76</td>
5447 </tr>
5448 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5449 <td>28</td>
5450 <td>53</td>
5451 <td>AM64X_DEV_R5FSS0_CORE0</td>
5452 <td>intr</td>
5453 <td>77</td>
5454 </tr>
5455 <tr class="row-odd"><td> </td>
5456 <td> </td>
5457 <td> </td>
5458 <td>AM64X_DEV_R5FSS0_CORE1</td>
5459 <td>intr</td>
5460 <td>77</td>
5461 </tr>
5462 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5463 <td>28</td>
5464 <td>54</td>
5465 <td>AM64X_DEV_R5FSS0_CORE0</td>
5466 <td>intr</td>
5467 <td>78</td>
5468 </tr>
5469 <tr class="row-odd"><td> </td>
5470 <td> </td>
5471 <td> </td>
5472 <td>AM64X_DEV_R5FSS0_CORE1</td>
5473 <td>intr</td>
5474 <td>78</td>
5475 </tr>
5476 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5477 <td>28</td>
5478 <td>55</td>
5479 <td>AM64X_DEV_R5FSS0_CORE0</td>
5480 <td>intr</td>
5481 <td>79</td>
5482 </tr>
5483 <tr class="row-odd"><td> </td>
5484 <td> </td>
5485 <td> </td>
5486 <td>AM64X_DEV_R5FSS0_CORE1</td>
5487 <td>intr</td>
5488 <td>79</td>
5489 </tr>
5490 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5491 <td>28</td>
5492 <td>56</td>
5493 <td>AM64X_DEV_R5FSS0_CORE0</td>
5494 <td>intr</td>
5495 <td>80</td>
5496 </tr>
5497 <tr class="row-odd"><td> </td>
5498 <td> </td>
5499 <td> </td>
5500 <td>AM64X_DEV_R5FSS0_CORE1</td>
5501 <td>intr</td>
5502 <td>80</td>
5503 </tr>
5504 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5505 <td>28</td>
5506 <td>57</td>
5507 <td>AM64X_DEV_R5FSS0_CORE0</td>
5508 <td>intr</td>
5509 <td>81</td>
5510 </tr>
5511 <tr class="row-odd"><td> </td>
5512 <td> </td>
5513 <td> </td>
5514 <td>AM64X_DEV_R5FSS0_CORE1</td>
5515 <td>intr</td>
5516 <td>81</td>
5517 </tr>
5518 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5519 <td>28</td>
5520 <td>58</td>
5521 <td>AM64X_DEV_R5FSS0_CORE0</td>
5522 <td>intr</td>
5523 <td>82</td>
5524 </tr>
5525 <tr class="row-odd"><td> </td>
5526 <td> </td>
5527 <td> </td>
5528 <td>AM64X_DEV_R5FSS0_CORE1</td>
5529 <td>intr</td>
5530 <td>82</td>
5531 </tr>
5532 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5533 <td>28</td>
5534 <td>59</td>
5535 <td>AM64X_DEV_R5FSS0_CORE0</td>
5536 <td>intr</td>
5537 <td>83</td>
5538 </tr>
5539 <tr class="row-odd"><td> </td>
5540 <td> </td>
5541 <td> </td>
5542 <td>AM64X_DEV_R5FSS0_CORE1</td>
5543 <td>intr</td>
5544 <td>83</td>
5545 </tr>
5546 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5547 <td>28</td>
5548 <td>60</td>
5549 <td>AM64X_DEV_R5FSS0_CORE0</td>
5550 <td>intr</td>
5551 <td>84</td>
5552 </tr>
5553 <tr class="row-odd"><td> </td>
5554 <td> </td>
5555 <td> </td>
5556 <td>AM64X_DEV_R5FSS0_CORE1</td>
5557 <td>intr</td>
5558 <td>84</td>
5559 </tr>
5560 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5561 <td>28</td>
5562 <td>61</td>
5563 <td>AM64X_DEV_R5FSS0_CORE0</td>
5564 <td>intr</td>
5565 <td>85</td>
5566 </tr>
5567 <tr class="row-odd"><td> </td>
5568 <td> </td>
5569 <td> </td>
5570 <td>AM64X_DEV_R5FSS0_CORE1</td>
5571 <td>intr</td>
5572 <td>85</td>
5573 </tr>
5574 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5575 <td>28</td>
5576 <td>62</td>
5577 <td>AM64X_DEV_R5FSS0_CORE0</td>
5578 <td>intr</td>
5579 <td>86</td>
5580 </tr>
5581 <tr class="row-odd"><td> </td>
5582 <td> </td>
5583 <td> </td>
5584 <td>AM64X_DEV_R5FSS0_CORE1</td>
5585 <td>intr</td>
5586 <td>86</td>
5587 </tr>
5588 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5589 <td>28</td>
5590 <td>63</td>
5591 <td>AM64X_DEV_R5FSS0_CORE0</td>
5592 <td>intr</td>
5593 <td>87</td>
5594 </tr>
5595 <tr class="row-odd"><td> </td>
5596 <td> </td>
5597 <td> </td>
5598 <td>AM64X_DEV_R5FSS0_CORE1</td>
5599 <td>intr</td>
5600 <td>87</td>
5601 </tr>
5602 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5603 <td>28</td>
5604 <td>64</td>
5605 <td>AM64X_DEV_R5FSS0_CORE0</td>
5606 <td>intr</td>
5607 <td>88</td>
5608 </tr>
5609 <tr class="row-odd"><td> </td>
5610 <td> </td>
5611 <td> </td>
5612 <td>AM64X_DEV_R5FSS0_CORE1</td>
5613 <td>intr</td>
5614 <td>88</td>
5615 </tr>
5616 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5617 <td>28</td>
5618 <td>65</td>
5619 <td>AM64X_DEV_R5FSS0_CORE0</td>
5620 <td>intr</td>
5621 <td>89</td>
5622 </tr>
5623 <tr class="row-odd"><td> </td>
5624 <td> </td>
5625 <td> </td>
5626 <td>AM64X_DEV_R5FSS0_CORE1</td>
5627 <td>intr</td>
5628 <td>89</td>
5629 </tr>
5630 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5631 <td>28</td>
5632 <td>66</td>
5633 <td>AM64X_DEV_R5FSS0_CORE0</td>
5634 <td>intr</td>
5635 <td>90</td>
5636 </tr>
5637 <tr class="row-odd"><td> </td>
5638 <td> </td>
5639 <td> </td>
5640 <td>AM64X_DEV_R5FSS0_CORE1</td>
5641 <td>intr</td>
5642 <td>90</td>
5643 </tr>
5644 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5645 <td>28</td>
5646 <td>67</td>
5647 <td>AM64X_DEV_R5FSS0_CORE0</td>
5648 <td>intr</td>
5649 <td>91</td>
5650 </tr>
5651 <tr class="row-odd"><td> </td>
5652 <td> </td>
5653 <td> </td>
5654 <td>AM64X_DEV_R5FSS0_CORE1</td>
5655 <td>intr</td>
5656 <td>91</td>
5657 </tr>
5658 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5659 <td>28</td>
5660 <td>68</td>
5661 <td>AM64X_DEV_R5FSS0_CORE0</td>
5662 <td>intr</td>
5663 <td>92</td>
5664 </tr>
5665 <tr class="row-odd"><td> </td>
5666 <td> </td>
5667 <td> </td>
5668 <td>AM64X_DEV_R5FSS0_CORE1</td>
5669 <td>intr</td>
5670 <td>92</td>
5671 </tr>
5672 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5673 <td>28</td>
5674 <td>69</td>
5675 <td>AM64X_DEV_R5FSS0_CORE0</td>
5676 <td>intr</td>
5677 <td>93</td>
5678 </tr>
5679 <tr class="row-odd"><td> </td>
5680 <td> </td>
5681 <td> </td>
5682 <td>AM64X_DEV_R5FSS0_CORE1</td>
5683 <td>intr</td>
5684 <td>93</td>
5685 </tr>
5686 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5687 <td>28</td>
5688 <td>70</td>
5689 <td>AM64X_DEV_R5FSS0_CORE0</td>
5690 <td>intr</td>
5691 <td>94</td>
5692 </tr>
5693 <tr class="row-odd"><td> </td>
5694 <td> </td>
5695 <td> </td>
5696 <td>AM64X_DEV_R5FSS0_CORE1</td>
5697 <td>intr</td>
5698 <td>94</td>
5699 </tr>
5700 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5701 <td>28</td>
5702 <td>71</td>
5703 <td>AM64X_DEV_R5FSS0_CORE0</td>
5704 <td>intr</td>
5705 <td>95</td>
5706 </tr>
5707 <tr class="row-odd"><td> </td>
5708 <td> </td>
5709 <td> </td>
5710 <td>AM64X_DEV_R5FSS0_CORE1</td>
5711 <td>intr</td>
5712 <td>95</td>
5713 </tr>
5714 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5715 <td>28</td>
5716 <td>72</td>
5717 <td>AM64X_DEV_R5FSS0_CORE0</td>
5718 <td>intr</td>
5719 <td>8</td>
5720 </tr>
5721 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5722 <td>28</td>
5723 <td>73</td>
5724 <td>AM64X_DEV_R5FSS0_CORE0</td>
5725 <td>intr</td>
5726 <td>9</td>
5727 </tr>
5728 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5729 <td>28</td>
5730 <td>74</td>
5731 <td>AM64X_DEV_R5FSS0_CORE0</td>
5732 <td>intr</td>
5733 <td>10</td>
5734 </tr>
5735 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5736 <td>28</td>
5737 <td>75</td>
5738 <td>AM64X_DEV_R5FSS0_CORE0</td>
5739 <td>intr</td>
5740 <td>11</td>
5741 </tr>
5742 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5743 <td>28</td>
5744 <td>76</td>
5745 <td>AM64X_DEV_R5FSS0_CORE0</td>
5746 <td>intr</td>
5747 <td>12</td>
5748 </tr>
5749 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5750 <td>28</td>
5751 <td>77</td>
5752 <td>AM64X_DEV_R5FSS0_CORE0</td>
5753 <td>intr</td>
5754 <td>13</td>
5755 </tr>
5756 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5757 <td>28</td>
5758 <td>78</td>
5759 <td>AM64X_DEV_R5FSS0_CORE0</td>
5760 <td>intr</td>
5761 <td>14</td>
5762 </tr>
5763 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5764 <td>28</td>
5765 <td>79</td>
5766 <td>AM64X_DEV_R5FSS0_CORE0</td>
5767 <td>intr</td>
5768 <td>15</td>
5769 </tr>
5770 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5771 <td>28</td>
5772 <td>80</td>
5773 <td>AM64X_DEV_R5FSS0_CORE1</td>
5774 <td>intr</td>
5775 <td>8</td>
5776 </tr>
5777 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5778 <td>28</td>
5779 <td>81</td>
5780 <td>AM64X_DEV_R5FSS0_CORE1</td>
5781 <td>intr</td>
5782 <td>9</td>
5783 </tr>
5784 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5785 <td>28</td>
5786 <td>82</td>
5787 <td>AM64X_DEV_R5FSS0_CORE1</td>
5788 <td>intr</td>
5789 <td>10</td>
5790 </tr>
5791 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5792 <td>28</td>
5793 <td>83</td>
5794 <td>AM64X_DEV_R5FSS0_CORE1</td>
5795 <td>intr</td>
5796 <td>11</td>
5797 </tr>
5798 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5799 <td>28</td>
5800 <td>84</td>
5801 <td>AM64X_DEV_R5FSS0_CORE1</td>
5802 <td>intr</td>
5803 <td>12</td>
5804 </tr>
5805 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5806 <td>28</td>
5807 <td>85</td>
5808 <td>AM64X_DEV_R5FSS0_CORE1</td>
5809 <td>intr</td>
5810 <td>13</td>
5811 </tr>
5812 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5813 <td>28</td>
5814 <td>86</td>
5815 <td>AM64X_DEV_R5FSS0_CORE1</td>
5816 <td>intr</td>
5817 <td>14</td>
5818 </tr>
5819 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5820 <td>28</td>
5821 <td>87</td>
5822 <td>AM64X_DEV_R5FSS0_CORE1</td>
5823 <td>intr</td>
5824 <td>15</td>
5825 </tr>
5826 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
5827 (<strong>Reserved by System Firmware</strong>)</td>
5828 <td>28</td>
5829 <td>88</td>
5830 <td>AM64X_DEV_R5FSS1_CORE0</td>
5831 <td>intr</td>
5832 <td>64</td>
5833 </tr>
5834 <tr class="row-odd"><td> </td>
5835 <td> </td>
5836 <td> </td>
5837 <td>AM64X_DEV_R5FSS1_CORE1</td>
5838 <td>intr</td>
5839 <td>64</td>
5840 </tr>
5841 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
5842 (<strong>Reserved by System Firmware</strong>)</td>
5843 <td>28</td>
5844 <td>89</td>
5845 <td>AM64X_DEV_R5FSS1_CORE0</td>
5846 <td>intr</td>
5847 <td>65</td>
5848 </tr>
5849 <tr class="row-odd"><td> </td>
5850 <td> </td>
5851 <td> </td>
5852 <td>AM64X_DEV_R5FSS1_CORE1</td>
5853 <td>intr</td>
5854 <td>65</td>
5855 </tr>
5856 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
5857 (<strong>Reserved by System Firmware</strong>)</td>
5858 <td>28</td>
5859 <td>90</td>
5860 <td>AM64X_DEV_R5FSS1_CORE0</td>
5861 <td>intr</td>
5862 <td>66</td>
5863 </tr>
5864 <tr class="row-odd"><td> </td>
5865 <td> </td>
5866 <td> </td>
5867 <td>AM64X_DEV_R5FSS1_CORE1</td>
5868 <td>intr</td>
5869 <td>66</td>
5870 </tr>
5871 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
5872 (<strong>Reserved by System Firmware</strong>)</td>
5873 <td>28</td>
5874 <td>91</td>
5875 <td>AM64X_DEV_R5FSS1_CORE0</td>
5876 <td>intr</td>
5877 <td>67</td>
5878 </tr>
5879 <tr class="row-odd"><td> </td>
5880 <td> </td>
5881 <td> </td>
5882 <td>AM64X_DEV_R5FSS1_CORE1</td>
5883 <td>intr</td>
5884 <td>67</td>
5885 </tr>
5886 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5887 <td>28</td>
5888 <td>92</td>
5889 <td>AM64X_DEV_R5FSS1_CORE0</td>
5890 <td>intr</td>
5891 <td>68</td>
5892 </tr>
5893 <tr class="row-odd"><td> </td>
5894 <td> </td>
5895 <td> </td>
5896 <td>AM64X_DEV_R5FSS1_CORE1</td>
5897 <td>intr</td>
5898 <td>68</td>
5899 </tr>
5900 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5901 <td>28</td>
5902 <td>93</td>
5903 <td>AM64X_DEV_R5FSS1_CORE0</td>
5904 <td>intr</td>
5905 <td>69</td>
5906 </tr>
5907 <tr class="row-odd"><td> </td>
5908 <td> </td>
5909 <td> </td>
5910 <td>AM64X_DEV_R5FSS1_CORE1</td>
5911 <td>intr</td>
5912 <td>69</td>
5913 </tr>
5914 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5915 <td>28</td>
5916 <td>94</td>
5917 <td>AM64X_DEV_R5FSS1_CORE0</td>
5918 <td>intr</td>
5919 <td>70</td>
5920 </tr>
5921 <tr class="row-odd"><td> </td>
5922 <td> </td>
5923 <td> </td>
5924 <td>AM64X_DEV_R5FSS1_CORE1</td>
5925 <td>intr</td>
5926 <td>70</td>
5927 </tr>
5928 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5929 <td>28</td>
5930 <td>95</td>
5931 <td>AM64X_DEV_R5FSS1_CORE0</td>
5932 <td>intr</td>
5933 <td>71</td>
5934 </tr>
5935 <tr class="row-odd"><td> </td>
5936 <td> </td>
5937 <td> </td>
5938 <td>AM64X_DEV_R5FSS1_CORE1</td>
5939 <td>intr</td>
5940 <td>71</td>
5941 </tr>
5942 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5943 <td>28</td>
5944 <td>96</td>
5945 <td>AM64X_DEV_R5FSS1_CORE0</td>
5946 <td>intr</td>
5947 <td>72</td>
5948 </tr>
5949 <tr class="row-odd"><td> </td>
5950 <td> </td>
5951 <td> </td>
5952 <td>AM64X_DEV_R5FSS1_CORE1</td>
5953 <td>intr</td>
5954 <td>72</td>
5955 </tr>
5956 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5957 <td>28</td>
5958 <td>97</td>
5959 <td>AM64X_DEV_R5FSS1_CORE0</td>
5960 <td>intr</td>
5961 <td>73</td>
5962 </tr>
5963 <tr class="row-odd"><td> </td>
5964 <td> </td>
5965 <td> </td>
5966 <td>AM64X_DEV_R5FSS1_CORE1</td>
5967 <td>intr</td>
5968 <td>73</td>
5969 </tr>
5970 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5971 <td>28</td>
5972 <td>98</td>
5973 <td>AM64X_DEV_R5FSS1_CORE0</td>
5974 <td>intr</td>
5975 <td>74</td>
5976 </tr>
5977 <tr class="row-odd"><td> </td>
5978 <td> </td>
5979 <td> </td>
5980 <td>AM64X_DEV_R5FSS1_CORE1</td>
5981 <td>intr</td>
5982 <td>74</td>
5983 </tr>
5984 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5985 <td>28</td>
5986 <td>99</td>
5987 <td>AM64X_DEV_R5FSS1_CORE0</td>
5988 <td>intr</td>
5989 <td>75</td>
5990 </tr>
5991 <tr class="row-odd"><td> </td>
5992 <td> </td>
5993 <td> </td>
5994 <td>AM64X_DEV_R5FSS1_CORE1</td>
5995 <td>intr</td>
5996 <td>75</td>
5997 </tr>
5998 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
5999 <td>28</td>
6000 <td>100</td>
6001 <td>AM64X_DEV_R5FSS1_CORE0</td>
6002 <td>intr</td>
6003 <td>76</td>
6004 </tr>
6005 <tr class="row-odd"><td> </td>
6006 <td> </td>
6007 <td> </td>
6008 <td>AM64X_DEV_R5FSS1_CORE1</td>
6009 <td>intr</td>
6010 <td>76</td>
6011 </tr>
6012 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6013 <td>28</td>
6014 <td>101</td>
6015 <td>AM64X_DEV_R5FSS1_CORE0</td>
6016 <td>intr</td>
6017 <td>77</td>
6018 </tr>
6019 <tr class="row-odd"><td> </td>
6020 <td> </td>
6021 <td> </td>
6022 <td>AM64X_DEV_R5FSS1_CORE1</td>
6023 <td>intr</td>
6024 <td>77</td>
6025 </tr>
6026 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6027 <td>28</td>
6028 <td>102</td>
6029 <td>AM64X_DEV_R5FSS1_CORE0</td>
6030 <td>intr</td>
6031 <td>78</td>
6032 </tr>
6033 <tr class="row-odd"><td> </td>
6034 <td> </td>
6035 <td> </td>
6036 <td>AM64X_DEV_R5FSS1_CORE1</td>
6037 <td>intr</td>
6038 <td>78</td>
6039 </tr>
6040 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6041 <td>28</td>
6042 <td>103</td>
6043 <td>AM64X_DEV_R5FSS1_CORE0</td>
6044 <td>intr</td>
6045 <td>79</td>
6046 </tr>
6047 <tr class="row-odd"><td> </td>
6048 <td> </td>
6049 <td> </td>
6050 <td>AM64X_DEV_R5FSS1_CORE1</td>
6051 <td>intr</td>
6052 <td>79</td>
6053 </tr>
6054 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6055 <td>28</td>
6056 <td>104</td>
6057 <td>AM64X_DEV_R5FSS1_CORE0</td>
6058 <td>intr</td>
6059 <td>80</td>
6060 </tr>
6061 <tr class="row-odd"><td> </td>
6062 <td> </td>
6063 <td> </td>
6064 <td>AM64X_DEV_R5FSS1_CORE1</td>
6065 <td>intr</td>
6066 <td>80</td>
6067 </tr>
6068 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6069 <td>28</td>
6070 <td>105</td>
6071 <td>AM64X_DEV_R5FSS1_CORE0</td>
6072 <td>intr</td>
6073 <td>81</td>
6074 </tr>
6075 <tr class="row-odd"><td> </td>
6076 <td> </td>
6077 <td> </td>
6078 <td>AM64X_DEV_R5FSS1_CORE1</td>
6079 <td>intr</td>
6080 <td>81</td>
6081 </tr>
6082 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6083 <td>28</td>
6084 <td>106</td>
6085 <td>AM64X_DEV_R5FSS1_CORE0</td>
6086 <td>intr</td>
6087 <td>82</td>
6088 </tr>
6089 <tr class="row-odd"><td> </td>
6090 <td> </td>
6091 <td> </td>
6092 <td>AM64X_DEV_R5FSS1_CORE1</td>
6093 <td>intr</td>
6094 <td>82</td>
6095 </tr>
6096 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6097 <td>28</td>
6098 <td>107</td>
6099 <td>AM64X_DEV_R5FSS1_CORE0</td>
6100 <td>intr</td>
6101 <td>83</td>
6102 </tr>
6103 <tr class="row-odd"><td> </td>
6104 <td> </td>
6105 <td> </td>
6106 <td>AM64X_DEV_R5FSS1_CORE1</td>
6107 <td>intr</td>
6108 <td>83</td>
6109 </tr>
6110 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6111 <td>28</td>
6112 <td>108</td>
6113 <td>AM64X_DEV_R5FSS1_CORE0</td>
6114 <td>intr</td>
6115 <td>84</td>
6116 </tr>
6117 <tr class="row-odd"><td> </td>
6118 <td> </td>
6119 <td> </td>
6120 <td>AM64X_DEV_R5FSS1_CORE1</td>
6121 <td>intr</td>
6122 <td>84</td>
6123 </tr>
6124 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6125 <td>28</td>
6126 <td>109</td>
6127 <td>AM64X_DEV_R5FSS1_CORE0</td>
6128 <td>intr</td>
6129 <td>85</td>
6130 </tr>
6131 <tr class="row-odd"><td> </td>
6132 <td> </td>
6133 <td> </td>
6134 <td>AM64X_DEV_R5FSS1_CORE1</td>
6135 <td>intr</td>
6136 <td>85</td>
6137 </tr>
6138 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6139 <td>28</td>
6140 <td>110</td>
6141 <td>AM64X_DEV_R5FSS1_CORE0</td>
6142 <td>intr</td>
6143 <td>86</td>
6144 </tr>
6145 <tr class="row-odd"><td> </td>
6146 <td> </td>
6147 <td> </td>
6148 <td>AM64X_DEV_R5FSS1_CORE1</td>
6149 <td>intr</td>
6150 <td>86</td>
6151 </tr>
6152 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6153 <td>28</td>
6154 <td>111</td>
6155 <td>AM64X_DEV_R5FSS1_CORE0</td>
6156 <td>intr</td>
6157 <td>87</td>
6158 </tr>
6159 <tr class="row-odd"><td> </td>
6160 <td> </td>
6161 <td> </td>
6162 <td>AM64X_DEV_R5FSS1_CORE1</td>
6163 <td>intr</td>
6164 <td>87</td>
6165 </tr>
6166 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6167 <td>28</td>
6168 <td>112</td>
6169 <td>AM64X_DEV_R5FSS1_CORE0</td>
6170 <td>intr</td>
6171 <td>88</td>
6172 </tr>
6173 <tr class="row-odd"><td> </td>
6174 <td> </td>
6175 <td> </td>
6176 <td>AM64X_DEV_R5FSS1_CORE1</td>
6177 <td>intr</td>
6178 <td>88</td>
6179 </tr>
6180 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6181 <td>28</td>
6182 <td>113</td>
6183 <td>AM64X_DEV_R5FSS1_CORE0</td>
6184 <td>intr</td>
6185 <td>89</td>
6186 </tr>
6187 <tr class="row-odd"><td> </td>
6188 <td> </td>
6189 <td> </td>
6190 <td>AM64X_DEV_R5FSS1_CORE1</td>
6191 <td>intr</td>
6192 <td>89</td>
6193 </tr>
6194 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6195 <td>28</td>
6196 <td>114</td>
6197 <td>AM64X_DEV_R5FSS1_CORE0</td>
6198 <td>intr</td>
6199 <td>90</td>
6200 </tr>
6201 <tr class="row-odd"><td> </td>
6202 <td> </td>
6203 <td> </td>
6204 <td>AM64X_DEV_R5FSS1_CORE1</td>
6205 <td>intr</td>
6206 <td>90</td>
6207 </tr>
6208 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6209 <td>28</td>
6210 <td>115</td>
6211 <td>AM64X_DEV_R5FSS1_CORE0</td>
6212 <td>intr</td>
6213 <td>91</td>
6214 </tr>
6215 <tr class="row-odd"><td> </td>
6216 <td> </td>
6217 <td> </td>
6218 <td>AM64X_DEV_R5FSS1_CORE1</td>
6219 <td>intr</td>
6220 <td>91</td>
6221 </tr>
6222 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6223 <td>28</td>
6224 <td>116</td>
6225 <td>AM64X_DEV_R5FSS1_CORE0</td>
6226 <td>intr</td>
6227 <td>92</td>
6228 </tr>
6229 <tr class="row-odd"><td> </td>
6230 <td> </td>
6231 <td> </td>
6232 <td>AM64X_DEV_R5FSS1_CORE1</td>
6233 <td>intr</td>
6234 <td>92</td>
6235 </tr>
6236 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6237 <td>28</td>
6238 <td>117</td>
6239 <td>AM64X_DEV_R5FSS1_CORE0</td>
6240 <td>intr</td>
6241 <td>93</td>
6242 </tr>
6243 <tr class="row-odd"><td> </td>
6244 <td> </td>
6245 <td> </td>
6246 <td>AM64X_DEV_R5FSS1_CORE1</td>
6247 <td>intr</td>
6248 <td>93</td>
6249 </tr>
6250 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6251 <td>28</td>
6252 <td>118</td>
6253 <td>AM64X_DEV_R5FSS1_CORE0</td>
6254 <td>intr</td>
6255 <td>94</td>
6256 </tr>
6257 <tr class="row-odd"><td> </td>
6258 <td> </td>
6259 <td> </td>
6260 <td>AM64X_DEV_R5FSS1_CORE1</td>
6261 <td>intr</td>
6262 <td>94</td>
6263 </tr>
6264 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6265 <td>28</td>
6266 <td>119</td>
6267 <td>AM64X_DEV_R5FSS1_CORE0</td>
6268 <td>intr</td>
6269 <td>95</td>
6270 </tr>
6271 <tr class="row-odd"><td> </td>
6272 <td> </td>
6273 <td> </td>
6274 <td>AM64X_DEV_R5FSS1_CORE1</td>
6275 <td>intr</td>
6276 <td>95</td>
6277 </tr>
6278 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6279 <td>28</td>
6280 <td>120</td>
6281 <td>AM64X_DEV_R5FSS1_CORE0</td>
6282 <td>intr</td>
6283 <td>8</td>
6284 </tr>
6285 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6286 <td>28</td>
6287 <td>121</td>
6288 <td>AM64X_DEV_R5FSS1_CORE0</td>
6289 <td>intr</td>
6290 <td>9</td>
6291 </tr>
6292 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6293 <td>28</td>
6294 <td>122</td>
6295 <td>AM64X_DEV_R5FSS1_CORE0</td>
6296 <td>intr</td>
6297 <td>10</td>
6298 </tr>
6299 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6300 <td>28</td>
6301 <td>123</td>
6302 <td>AM64X_DEV_R5FSS1_CORE0</td>
6303 <td>intr</td>
6304 <td>11</td>
6305 </tr>
6306 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6307 <td>28</td>
6308 <td>124</td>
6309 <td>AM64X_DEV_R5FSS1_CORE0</td>
6310 <td>intr</td>
6311 <td>12</td>
6312 </tr>
6313 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6314 <td>28</td>
6315 <td>125</td>
6316 <td>AM64X_DEV_R5FSS1_CORE0</td>
6317 <td>intr</td>
6318 <td>13</td>
6319 </tr>
6320 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6321 <td>28</td>
6322 <td>126</td>
6323 <td>AM64X_DEV_R5FSS1_CORE0</td>
6324 <td>intr</td>
6325 <td>14</td>
6326 </tr>
6327 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6328 <td>28</td>
6329 <td>127</td>
6330 <td>AM64X_DEV_R5FSS1_CORE0</td>
6331 <td>intr</td>
6332 <td>15</td>
6333 </tr>
6334 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6335 <td>28</td>
6336 <td>128</td>
6337 <td>AM64X_DEV_R5FSS1_CORE1</td>
6338 <td>intr</td>
6339 <td>8</td>
6340 </tr>
6341 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6342 <td>28</td>
6343 <td>129</td>
6344 <td>AM64X_DEV_R5FSS1_CORE1</td>
6345 <td>intr</td>
6346 <td>9</td>
6347 </tr>
6348 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6349 <td>28</td>
6350 <td>130</td>
6351 <td>AM64X_DEV_R5FSS1_CORE1</td>
6352 <td>intr</td>
6353 <td>10</td>
6354 </tr>
6355 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6356 <td>28</td>
6357 <td>131</td>
6358 <td>AM64X_DEV_R5FSS1_CORE1</td>
6359 <td>intr</td>
6360 <td>11</td>
6361 </tr>
6362 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6363 <td>28</td>
6364 <td>132</td>
6365 <td>AM64X_DEV_R5FSS1_CORE1</td>
6366 <td>intr</td>
6367 <td>12</td>
6368 </tr>
6369 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6370 <td>28</td>
6371 <td>133</td>
6372 <td>AM64X_DEV_R5FSS1_CORE1</td>
6373 <td>intr</td>
6374 <td>13</td>
6375 </tr>
6376 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6377 <td>28</td>
6378 <td>134</td>
6379 <td>AM64X_DEV_R5FSS1_CORE1</td>
6380 <td>intr</td>
6381 <td>14</td>
6382 </tr>
6383 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6384 <td>28</td>
6385 <td>135</td>
6386 <td>AM64X_DEV_R5FSS1_CORE1</td>
6387 <td>intr</td>
6388 <td>15</td>
6389 </tr>
6390 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
6391 (<strong>Reserved by System Firmware</strong>)</td>
6392 <td>28</td>
6393 <td>136</td>
6394 <td>Not Connected</td>
6395 <td> </td>
6396 <td> </td>
6397 </tr>
6398 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0
6399 (<strong>Reserved by System Firmware</strong>)</td>
6400 <td>28</td>
6401 <td>137</td>
6402 <td>Not Connected</td>
6403 <td> </td>
6404 <td> </td>
6405 </tr>
6406 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0
6407 (<strong>Reserved by System Firmware</strong>)</td>
6408 <td>28</td>
6409 <td>138</td>
6410 <td>Not Connected</td>
6411 <td> </td>
6412 <td> </td>
6413 </tr>
6414 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6415 <td>28</td>
6416 <td>139</td>
6417 <td>Not Connected</td>
6418 <td> </td>
6419 <td> </td>
6420 </tr>
6421 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6422 <td>28</td>
6423 <td>140</td>
6424 <td>Not Connected</td>
6425 <td> </td>
6426 <td> </td>
6427 </tr>
6428 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6429 <td>28</td>
6430 <td>141</td>
6431 <td>Not Connected</td>
6432 <td> </td>
6433 <td> </td>
6434 </tr>
6435 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6436 <td>28</td>
6437 <td>142</td>
6438 <td>Not Connected</td>
6439 <td> </td>
6440 <td> </td>
6441 </tr>
6442 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6443 <td>28</td>
6444 <td>143</td>
6445 <td>Not Connected</td>
6446 <td> </td>
6447 <td> </td>
6448 </tr>
6449 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6450 <td>28</td>
6451 <td>144</td>
6452 <td>Not Connected</td>
6453 <td> </td>
6454 <td> </td>
6455 </tr>
6456 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6457 <td>28</td>
6458 <td>145</td>
6459 <td>Not Connected</td>
6460 <td> </td>
6461 <td> </td>
6462 </tr>
6463 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6464 <td>28</td>
6465 <td>146</td>
6466 <td>Not Connected</td>
6467 <td> </td>
6468 <td> </td>
6469 </tr>
6470 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6471 <td>28</td>
6472 <td>147</td>
6473 <td>Not Connected</td>
6474 <td> </td>
6475 <td> </td>
6476 </tr>
6477 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6478 <td>28</td>
6479 <td>148</td>
6480 <td>Not Connected</td>
6481 <td> </td>
6482 <td> </td>
6483 </tr>
6484 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6485 <td>28</td>
6486 <td>149</td>
6487 <td>Not Connected</td>
6488 <td> </td>
6489 <td> </td>
6490 </tr>
6491 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6492 <td>28</td>
6493 <td>150</td>
6494 <td>Not Connected</td>
6495 <td> </td>
6496 <td> </td>
6497 </tr>
6498 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6499 <td>28</td>
6500 <td>151</td>
6501 <td>Not Connected</td>
6502 <td> </td>
6503 <td> </td>
6504 </tr>
6505 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6506 <td>28</td>
6507 <td>152</td>
6508 <td>AM64X_DEV_PRU_ICSSG0</td>
6509 <td>pr1_slv_intr</td>
6510 <td>0</td>
6511 </tr>
6512 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6513 <td>28</td>
6514 <td>153</td>
6515 <td>AM64X_DEV_PRU_ICSSG0</td>
6516 <td>pr1_slv_intr</td>
6517 <td>1</td>
6518 </tr>
6519 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6520 <td>28</td>
6521 <td>154</td>
6522 <td>AM64X_DEV_PRU_ICSSG0</td>
6523 <td>pr1_slv_intr</td>
6524 <td>2</td>
6525 </tr>
6526 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6527 <td>28</td>
6528 <td>155</td>
6529 <td>AM64X_DEV_PRU_ICSSG0</td>
6530 <td>pr1_slv_intr</td>
6531 <td>3</td>
6532 </tr>
6533 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6534 <td>28</td>
6535 <td>156</td>
6536 <td>AM64X_DEV_PRU_ICSSG0</td>
6537 <td>pr1_slv_intr</td>
6538 <td>4</td>
6539 </tr>
6540 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6541 <td>28</td>
6542 <td>157</td>
6543 <td>AM64X_DEV_PRU_ICSSG0</td>
6544 <td>pr1_slv_intr</td>
6545 <td>5</td>
6546 </tr>
6547 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6548 <td>28</td>
6549 <td>158</td>
6550 <td>AM64X_DEV_PRU_ICSSG0</td>
6551 <td>pr1_slv_intr</td>
6552 <td>6</td>
6553 </tr>
6554 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6555 <td>28</td>
6556 <td>159</td>
6557 <td>AM64X_DEV_PRU_ICSSG0</td>
6558 <td>pr1_slv_intr</td>
6559 <td>7</td>
6560 </tr>
6561 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6562 <td>28</td>
6563 <td>160</td>
6564 <td>AM64X_DEV_PRU_ICSSG1</td>
6565 <td>pr1_slv_intr</td>
6566 <td>0</td>
6567 </tr>
6568 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6569 <td>28</td>
6570 <td>161</td>
6571 <td>AM64X_DEV_PRU_ICSSG1</td>
6572 <td>pr1_slv_intr</td>
6573 <td>1</td>
6574 </tr>
6575 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6576 <td>28</td>
6577 <td>162</td>
6578 <td>AM64X_DEV_PRU_ICSSG1</td>
6579 <td>pr1_slv_intr</td>
6580 <td>2</td>
6581 </tr>
6582 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6583 <td>28</td>
6584 <td>163</td>
6585 <td>AM64X_DEV_PRU_ICSSG1</td>
6586 <td>pr1_slv_intr</td>
6587 <td>3</td>
6588 </tr>
6589 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6590 <td>28</td>
6591 <td>164</td>
6592 <td>AM64X_DEV_PRU_ICSSG1</td>
6593 <td>pr1_slv_intr</td>
6594 <td>4</td>
6595 </tr>
6596 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6597 <td>28</td>
6598 <td>165</td>
6599 <td>AM64X_DEV_PRU_ICSSG1</td>
6600 <td>pr1_slv_intr</td>
6601 <td>5</td>
6602 </tr>
6603 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6604 <td>28</td>
6605 <td>166</td>
6606 <td>AM64X_DEV_PRU_ICSSG1</td>
6607 <td>pr1_slv_intr</td>
6608 <td>6</td>
6609 </tr>
6610 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6611 <td>28</td>
6612 <td>167</td>
6613 <td>AM64X_DEV_PRU_ICSSG1</td>
6614 <td>pr1_slv_intr</td>
6615 <td>7</td>
6616 </tr>
6617 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6618 <td>28</td>
6619 <td>168</td>
6620 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6621 <td>nvic</td>
6622 <td>32</td>
6623 </tr>
6624 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6625 <td>28</td>
6626 <td>169</td>
6627 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6628 <td>nvic</td>
6629 <td>33</td>
6630 </tr>
6631 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6632 <td>28</td>
6633 <td>170</td>
6634 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6635 <td>nvic</td>
6636 <td>34</td>
6637 </tr>
6638 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6639 <td>28</td>
6640 <td>171</td>
6641 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6642 <td>nvic</td>
6643 <td>35</td>
6644 </tr>
6645 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6646 <td>28</td>
6647 <td>172</td>
6648 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6649 <td>nvic</td>
6650 <td>36</td>
6651 </tr>
6652 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6653 <td>28</td>
6654 <td>173</td>
6655 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6656 <td>nvic</td>
6657 <td>37</td>
6658 </tr>
6659 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6660 <td>28</td>
6661 <td>174</td>
6662 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6663 <td>nvic</td>
6664 <td>38</td>
6665 </tr>
6666 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6667 <td>28</td>
6668 <td>175</td>
6669 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6670 <td>nvic</td>
6671 <td>39</td>
6672 </tr>
6673 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6674 <td>28</td>
6675 <td>176</td>
6676 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6677 <td>nvic</td>
6678 <td>40</td>
6679 </tr>
6680 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6681 <td>28</td>
6682 <td>177</td>
6683 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6684 <td>nvic</td>
6685 <td>41</td>
6686 </tr>
6687 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6688 <td>28</td>
6689 <td>178</td>
6690 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6691 <td>nvic</td>
6692 <td>42</td>
6693 </tr>
6694 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6695 <td>28</td>
6696 <td>179</td>
6697 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6698 <td>nvic</td>
6699 <td>43</td>
6700 </tr>
6701 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6702 <td>28</td>
6703 <td>180</td>
6704 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6705 <td>nvic</td>
6706 <td>44</td>
6707 </tr>
6708 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6709 <td>28</td>
6710 <td>181</td>
6711 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6712 <td>nvic</td>
6713 <td>45</td>
6714 </tr>
6715 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6716 <td>28</td>
6717 <td>182</td>
6718 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6719 <td>nvic</td>
6720 <td>46</td>
6721 </tr>
6722 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6723 <td>28</td>
6724 <td>183</td>
6725 <td>AM64X_DEV_MCU_M4FSS0_CORE0</td>
6726 <td>nvic</td>
6727 <td>47</td>
6728 </tr>
6729 </tbody>
6730 </table>
6731 </div>
6732 <div class="section" id="global-events">
6733 <span id="pub-soc-am64x-global-events"></span><h2>Global Events<a class="headerlink" href="#global-events" title="Permalink to this headline">¶</a></h2>
6734 <p>This section describes AM64X global events. The global events are used in
6735 interrupt management based TISCI messages.</p>
6736 <div class="admonition warning">
6737 <p class="first admonition-title">Warning</p>
6738 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
6739 host within the RM Board Configuration resource assignment array. The RM
6740 Board Configuration is rejected if an overlap with a reserved resource is
6741 detected.</p>
6742 </div>
6743 <table border="1" class="docutils">
6744 <colgroup>
6745 <col width="61%" />
6746 <col width="39%" />
6747 </colgroup>
6748 <thead valign="bottom">
6749 <tr class="row-odd"><th class="head">Global Event Name</th>
6750 <th class="head">Global Event Range</th>
6751 </tr>
6752 </thead>
6753 <tbody valign="top">
6754 <tr class="row-even"><td>DMASS0_INTAGGR_0 SEVT
6755 (<strong>RESERVED BY SYSTEM FIRMWARE</strong>)</td>
6756 <td>0 to 14</td>
6757 </tr>
6758 <tr class="row-odd"><td>DMASS0_INTAGGR_0 SEVT</td>
6759 <td>15 to 1535</td>
6760 </tr>
6761 <tr class="row-even"><td>DMASS0_INTAGGR_0 MEVT</td>
6762 <td>8192 to 8319</td>
6763 </tr>
6764 <tr class="row-odd"><td>DMASS0_INTAGGR_0 GEVT</td>
6765 <td>10240 to 10495</td>
6766 </tr>
6767 <tr class="row-even"><td>DMASS0_INTAGGR_0 LEVT</td>
6768 <td>32768 to 32799</td>
6769 </tr>
6770 <tr class="row-odd"><td>DMASS0_BCDMA_0 TRIGGER</td>
6771 <td>50176 to 50311</td>
6772 </tr>
6773 </tbody>
6774 </table>
6775 </div>
6776 <div class="section" id="event-based-interrupt-source-ids">
6777 <span id="pub-soc-am64x-event-int-src-list"></span><h2>Event-Based Interrupt Source IDs<a class="headerlink" href="#event-based-interrupt-source-ids" title="Permalink to this headline">¶</a></h2>
6778 <table border="1" class="docutils">
6779 <colgroup>
6780 <col width="22%" />
6781 <col width="10%" />
6782 <col width="48%" />
6783 <col width="20%" />
6784 </colgroup>
6785 <thead valign="bottom">
6786 <tr class="row-odd"><th class="head">Device Name</th>
6787 <th class="head">Device ID</th>
6788 <th class="head">Interrupt Source Name</th>
6789 <th class="head">Interrupt Source Index</th>
6790 </tr>
6791 </thead>
6792 <tbody valign="top">
6793 <tr class="row-even"><td>AM64X_DEV_DMASS0_RINGACC_0</td>
6794 <td>33</td>
6795 <td>Ring events</td>
6796 <td>20 to 31</td>
6797 </tr>
6798 <tr class="row-odd"><td>AM64X_DEV_DMASS0_RINGACC_0</td>
6799 <td>33</td>
6800 <td>Ring global error event</td>
6801 <td>32</td>
6802 </tr>
6803 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6804 <td>28</td>
6805 <td>DMASS0_INTAGGR_0 mapped timermgr_evt events</td>
6806 <td>0 to 1023</td>
6807 </tr>
6808 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6809 <td>28</td>
6810 <td>DMASS0_INTAGGR_0 mapped pktdma_tx_chan_error events</td>
6811 <td>4096 to 4137</td>
6812 </tr>
6813 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6814 <td>28</td>
6815 <td>DMASS0_INTAGGR_0 mapped pktdma_tx_flow_completion events</td>
6816 <td>4608 to 4719</td>
6817 </tr>
6818 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6819 <td>28</td>
6820 <td>DMASS0_INTAGGR_0 mapped pktdma_rx_chan_error events</td>
6821 <td>5120 to 5148</td>
6822 </tr>
6823 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6824 <td>28</td>
6825 <td>DMASS0_INTAGGR_0 mapped pktdma_rx_flow_completion events</td>
6826 <td>5632 to 5807</td>
6827 </tr>
6828 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6829 <td>28</td>
6830 <td>DMASS0_INTAGGR_0 mapped pktdma_rx_flow_starvation events</td>
6831 <td>6144 to 6319</td>
6832 </tr>
6833 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6834 <td>28</td>
6835 <td>DMASS0_INTAGGR_0 mapped pktdma_rx_flow_firewall events</td>
6836 <td>6656 to 6831</td>
6837 </tr>
6838 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6839 <td>28</td>
6840 <td>DMASS0_INTAGGR_0 mapped bcdma_chan_error events</td>
6841 <td>8192 to 8219</td>
6842 </tr>
6843 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6844 <td>28</td>
6845 <td>DMASS0_INTAGGR_0 mapped bcdma_chan_data_completion events</td>
6846 <td>8704 to 8731</td>
6847 </tr>
6848 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6849 <td>28</td>
6850 <td>DMASS0_INTAGGR_0 mapped bcdma_chan_ring_completion events</td>
6851 <td>9216 to 9243</td>
6852 </tr>
6853 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6854 <td>28</td>
6855 <td>DMASS0_INTAGGR_0 mapped bcdma_tx_chan_error events</td>
6856 <td>9728 to 9747</td>
6857 </tr>
6858 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6859 <td>28</td>
6860 <td>DMASS0_INTAGGR_0 mapped bcdma_tx_chan_data_completion events</td>
6861 <td>10240 to 10259</td>
6862 </tr>
6863 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6864 <td>28</td>
6865 <td>DMASS0_INTAGGR_0 mapped bcdma_tx_chan_ring_completion events</td>
6866 <td>10752 to 10771</td>
6867 </tr>
6868 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6869 <td>28</td>
6870 <td>DMASS0_INTAGGR_0 mapped bcdma_rx_chan_error events</td>
6871 <td>11264 to 11283</td>
6872 </tr>
6873 <tr class="row-even"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6874 <td>28</td>
6875 <td>DMASS0_INTAGGR_0 mapped bcdma_rx_chan_data_completion events</td>
6876 <td>11776 to 11795</td>
6877 </tr>
6878 <tr class="row-odd"><td>AM64X_DEV_DMASS0_INTAGGR_0</td>
6879 <td>28</td>
6880 <td>DMASS0_INTAGGR_0 mapped bcdma_rx_chan_ring_completion events</td>
6881 <td>12288 to 12307</td>
6882 </tr>
6883 </tbody>
6884 </table>
6885 </div>
6886 </div>
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6890 </div>
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