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 181 <h1>AM64X PLL Defaults<a class="headerlink" href="#am64x-pll-defaults" title="Permalink to this headline">¶</a></h1>
 182 <div class="section" id="pll-defaults-for-am64x-device">
 183 <span id="soc-doc-am64x-public-plls-desc-intro"></span><h2>PLL Defaults for AM64X Device<a class="headerlink" href="#pll-defaults-for-am64x-device" title="Permalink to this headline">¶</a></h2>
 184 <p>This chapter provides information on the PLL defaults which the System firmware programs
 185 for AM64X SoC.</p>
 186 <p>This is what the system firmware programs after the PM board configuration is provided.
 187 The exact M and N values programmed are based on the crystal connected on the board.
 188 The crystal frequency is understood by the ROM from the BOOTPINS. This value is read
 189 by the System Firmware from the DEVSTAT register to determine which HFOSC is connected to the device</p>
 190 <p>The System Firmware maintains a table of device clock frequency defaults at which the PLLs
 191 are programmed. This document is a reference that the users of System Firmware
 192 can look at to determine the default PLL configuration done during boot when PM board configuration
 193 message is sent.</p>
 194 <p>Once the PM Init during board configuration is complete the bootloader or application can
 195 program individual clocks of individual modules to tweak the clocks based on the usecase
 196 which differ from the default. The APIs to refer to setting individual module clocks are
 197 <a class="reference internal" href="../../2_tisci_msgs/pm/clocks.html#pm-clocks-msg-set-freq"><span class="std std-ref">TISCI_MSG_SET_FREQ</span></a>, <a class="reference internal" href="../../2_tisci_msgs/pm/clocks.html#pm-clocks-msg-query-freq"><span class="std std-ref">TISCI_MSG_QUERY_FREQ</span></a>.</p>
 198 <p>The following table gives the PLL configurations for the input crystal Frequency of 19.2 MHz.</p>
 199 <table border="1" class="docutils">
 200 <colgroup>
 201 <col width="20%" />
 202 <col width="11%" />
 203 <col width="4%" />
 204 <col width="3%" />
 205 <col width="9%" />
 206 <col width="3%" />
 207 <col width="6%" />
 208 <col width="6%" />
 209 <col width="6%" />
 210 <col width="6%" />
 211 <col width="6%" />
 212 <col width="6%" />
 213 <col width="6%" />
 214 <col width="6%" />
 215 <col width="6%" />
 216 </colgroup>
 217 <thead valign="bottom">
 218 <tr class="row-odd"><th class="head">PLL Name</th>
 219 <th class="head">CLKOUT Freq (Hz)</th>
 220 <th class="head">N+1</th>
 221 <th class="head">M</th>
 222 <th class="head">Fractional M</th>
 223 <th class="head">M2</th>
 224 <th class="head">HSDIV0</th>
 225 <th class="head">HSDIV1</th>
 226 <th class="head">HSDIV2</th>
 227 <th class="head">HSDIV3</th>
 228 <th class="head">HSDIV4</th>
 229 <th class="head">HSDIV5</th>
 230 <th class="head">HSDIV6</th>
 231 <th class="head">HSDIV7</th>
 232 <th class="head">HSDIV8</th>
 233 </tr>
 234 </thead>
 235 <tbody valign="top">
 236 <tr class="row-even"><td>MCU (PLLFRACF_SSMOD_16FFT_MCU_0)</td>
 237 <td>2400000000</td>
 238 <td>1</td>
 239 <td>125</td>
 240 <td>0</td>
 241 <td>1</td>
 242 <td>6</td>
 243 <td>25</td>
 244 <td>25</td>
 245 <td>12</td>
 246 <td>12</td>
 247 <td>NA</td>
 248 <td>NA</td>
 249 <td>NA</td>
 250 <td>NA</td>
 251 </tr>
 252 <tr class="row-odd"><td>MAIN (PLLFRACF_SSMOD_16FFT_MAIN_0)</td>
 253 <td>1000000000</td>
 254 <td>3</td>
 255 <td>312</td>
 256 <td>8388608</td>
 257 <td>2</td>
 258 <td>4</td>
 259 <td>10</td>
 260 <td>25</td>
 261 <td>15</td>
 262 <td>8</td>
 263 <td>5</td>
 264 <td>5</td>
 265 <td>5</td>
 266 <td>8</td>
 267 </tr>
 268 <tr class="row-even"><td>PER0 (PLLFRACF_SSMOD_16FFT_MAIN_1)</td>
 269 <td>960000000</td>
 270 <td>1</td>
 271 <td>100</td>
 272 <td>0</td>
 273 <td>2</td>
 274 <td>10</td>
 275 <td>12</td>
 276 <td>5</td>
 277 <td>10</td>
 278 <td>80</td>
 279 <td>6</td>
 280 <td>16</td>
 281 <td>NA</td>
 282 <td>NA</td>
 283 </tr>
 284 <tr class="row-odd"><td>PER1 (PLLFRACF_SSMOD_16FFT_MAIN_2)</td>
 285 <td>1800000000</td>
 286 <td>1</td>
 287 <td>93</td>
 288 <td>12582912</td>
 289 <td>1</td>
 290 <td>8</td>
 291 <td>NA</td>
 292 <td>9</td>
 293 <td>6</td>
 294 <td>18</td>
 295 <td>8</td>
 296 <td>8</td>
 297 <td>18</td>
 298 <td>30</td>
 299 </tr>
 300 <tr class="row-even"><td>ARM0 (PLLFRACF_SSMOD_16FFT_MAIN_8)</td>
 301 <td>2000000000</td>
 302 <td>3</td>
 303 <td>312</td>
 304 <td>8388608</td>
 305 <td>1</td>
 306 <td>2</td>
 307 <td>NA</td>
 308 <td>NA</td>
 309 <td>NA</td>
 310 <td>NA</td>
 311 <td>NA</td>
 312 <td>NA</td>
 313 <td>NA</td>
 314 <td>NA</td>
 315 </tr>
 316 <tr class="row-odd"><td>DDR (PLLFRACF_SSMOD_16FFT_MAIN_12)</td>
 317 <td>1600000000</td>
 318 <td>3</td>
 319 <td>250</td>
 320 <td>0</td>
 321 <td>1</td>
 322 <td>4</td>
 323 <td>NA</td>
 324 <td>NA</td>
 325 <td>NA</td>
 326 <td>NA</td>
 327 <td>NA</td>
 328 <td>NA</td>
 329 <td>NA</td>
 330 <td>NA</td>
 331 </tr>
 332 <tr class="row-even"><td>R5F (PLLFRACF_SSMOD_16FFT_MAIN_14)</td>
 333 <td>2400000000</td>
 334 <td>1</td>
 335 <td>125</td>
 336 <td>0</td>
 337 <td>1</td>
 338 <td>3</td>
 339 <td>3</td>
 340 <td>NA</td>
 341 <td>NA</td>
 342 <td>NA</td>
 343 <td>NA</td>
 344 <td>NA</td>
 345 <td>NA</td>
 346 <td>NA</td>
 347 </tr>
 348 </tbody>
 349 </table>
 350 <p>The following table gives the PLL configurations for the input crystal Frequency of 20.0 MHz.</p>
 351 <table border="1" class="docutils">
 352 <colgroup>
 353 <col width="20%" />
 354 <col width="11%" />
 355 <col width="4%" />
 356 <col width="3%" />
 357 <col width="9%" />
 358 <col width="3%" />
 359 <col width="6%" />
 360 <col width="6%" />
 361 <col width="6%" />
 362 <col width="6%" />
 363 <col width="6%" />
 364 <col width="6%" />
 365 <col width="6%" />
 366 <col width="6%" />
 367 <col width="6%" />
 368 </colgroup>
 369 <thead valign="bottom">
 370 <tr class="row-odd"><th class="head">PLL Name</th>
 371 <th class="head">CLKOUT Freq (Hz)</th>
 372 <th class="head">N+1</th>
 373 <th class="head">M</th>
 374 <th class="head">Fractional M</th>
 375 <th class="head">M2</th>
 376 <th class="head">HSDIV0</th>
 377 <th class="head">HSDIV1</th>
 378 <th class="head">HSDIV2</th>
 379 <th class="head">HSDIV3</th>
 380 <th class="head">HSDIV4</th>
 381 <th class="head">HSDIV5</th>
 382 <th class="head">HSDIV6</th>
 383 <th class="head">HSDIV7</th>
 384 <th class="head">HSDIV8</th>
 385 </tr>
 386 </thead>
 387 <tbody valign="top">
 388 <tr class="row-even"><td>MCU (PLLFRACF_SSMOD_16FFT_MCU_0)</td>
 389 <td>2400000000</td>
 390 <td>1</td>
 391 <td>120</td>
 392 <td>0</td>
 393 <td>1</td>
 394 <td>6</td>
 395 <td>25</td>
 396 <td>25</td>
 397 <td>12</td>
 398 <td>12</td>
 399 <td>NA</td>
 400 <td>NA</td>
 401 <td>NA</td>
 402 <td>NA</td>
 403 </tr>
 404 <tr class="row-odd"><td>MAIN (PLLFRACF_SSMOD_16FFT_MAIN_0)</td>
 405 <td>1000000000</td>
 406 <td>1</td>
 407 <td>100</td>
 408 <td>0</td>
 409 <td>2</td>
 410 <td>4</td>
 411 <td>10</td>
 412 <td>25</td>
 413 <td>15</td>
 414 <td>8</td>
 415 <td>5</td>
 416 <td>5</td>
 417 <td>5</td>
 418 <td>8</td>
 419 </tr>
 420 <tr class="row-even"><td>PER0 (PLLFRACF_SSMOD_16FFT_MAIN_1)</td>
 421 <td>960000000</td>
 422 <td>1</td>
 423 <td>96</td>
 424 <td>0</td>
 425 <td>2</td>
 426 <td>10</td>
 427 <td>12</td>
 428 <td>5</td>
 429 <td>10</td>
 430 <td>80</td>
 431 <td>6</td>
 432 <td>16</td>
 433 <td>NA</td>
 434 <td>NA</td>
 435 </tr>
 436 <tr class="row-odd"><td>PER1 (PLLFRACF_SSMOD_16FFT_MAIN_2)</td>
 437 <td>1800000000</td>
 438 <td>1</td>
 439 <td>90</td>
 440 <td>0</td>
 441 <td>1</td>
 442 <td>8</td>
 443 <td>NA</td>
 444 <td>9</td>
 445 <td>6</td>
 446 <td>18</td>
 447 <td>8</td>
 448 <td>8</td>
 449 <td>18</td>
 450 <td>30</td>
 451 </tr>
 452 <tr class="row-even"><td>ARM0 (PLLFRACF_SSMOD_16FFT_MAIN_8)</td>
 453 <td>2000000000</td>
 454 <td>1</td>
 455 <td>100</td>
 456 <td>0</td>
 457 <td>1</td>
 458 <td>2</td>
 459 <td>NA</td>
 460 <td>NA</td>
 461 <td>NA</td>
 462 <td>NA</td>
 463 <td>NA</td>
 464 <td>NA</td>
 465 <td>NA</td>
 466 <td>NA</td>
 467 </tr>
 468 <tr class="row-odd"><td>DDR (PLLFRACF_SSMOD_16FFT_MAIN_12)</td>
 469 <td>1600000000</td>
 470 <td>1</td>
 471 <td>80</td>
 472 <td>0</td>
 473 <td>1</td>
 474 <td>4</td>
 475 <td>NA</td>
 476 <td>NA</td>
 477 <td>NA</td>
 478 <td>NA</td>
 479 <td>NA</td>
 480 <td>NA</td>
 481 <td>NA</td>
 482 <td>NA</td>
 483 </tr>
 484 <tr class="row-even"><td>R5F (PLLFRACF_SSMOD_16FFT_MAIN_14)</td>
 485 <td>2400000000</td>
 486 <td>1</td>
 487 <td>120</td>
 488 <td>0</td>
 489 <td>1</td>
 490 <td>3</td>
 491 <td>3</td>
 492 <td>NA</td>
 493 <td>NA</td>
 494 <td>NA</td>
 495 <td>NA</td>
 496 <td>NA</td>
 497 <td>NA</td>
 498 <td>NA</td>
 499 </tr>
 500 </tbody>
 501 </table>
 502 <p>The following table gives the PLL configurations for the input crystal Frequency of 24.0 MHz.</p>
 503 <table border="1" class="docutils">
 504 <colgroup>
 505 <col width="20%" />
 506 <col width="11%" />
 507 <col width="4%" />
 508 <col width="3%" />
 509 <col width="9%" />
 510 <col width="3%" />
 511 <col width="6%" />
 512 <col width="6%" />
 513 <col width="6%" />
 514 <col width="6%" />
 515 <col width="6%" />
 516 <col width="6%" />
 517 <col width="6%" />
 518 <col width="6%" />
 519 <col width="6%" />
 520 </colgroup>
 521 <thead valign="bottom">
 522 <tr class="row-odd"><th class="head">PLL Name</th>
 523 <th class="head">CLKOUT Freq (Hz)</th>
 524 <th class="head">N+1</th>
 525 <th class="head">M</th>
 526 <th class="head">Fractional M</th>
 527 <th class="head">M2</th>
 528 <th class="head">HSDIV0</th>
 529 <th class="head">HSDIV1</th>
 530 <th class="head">HSDIV2</th>
 531 <th class="head">HSDIV3</th>
 532 <th class="head">HSDIV4</th>
 533 <th class="head">HSDIV5</th>
 534 <th class="head">HSDIV6</th>
 535 <th class="head">HSDIV7</th>
 536 <th class="head">HSDIV8</th>
 537 </tr>
 538 </thead>
 539 <tbody valign="top">
 540 <tr class="row-even"><td>PER0 (PLLFRACF_SSMOD_16FFT_MAIN_1)</td>
 541 <td>960000000</td>
 542 <td>1</td>
 543 <td>80</td>
 544 <td>0</td>
 545 <td>2</td>
 546 <td>10</td>
 547 <td>12</td>
 548 <td>5</td>
 549 <td>10</td>
 550 <td>80</td>
 551 <td>6</td>
 552 <td>16</td>
 553 <td>NA</td>
 554 <td>NA</td>
 555 </tr>
 556 </tbody>
 557 </table>
 558 <p>The following table gives the PLL configurations for the input crystal Frequency of 25.0 MHz.</p>
 559 <table border="1" class="docutils">
 560 <colgroup>
 561 <col width="20%" />
 562 <col width="11%" />
 563 <col width="4%" />
 564 <col width="3%" />
 565 <col width="9%" />
 566 <col width="3%" />
 567 <col width="6%" />
 568 <col width="6%" />
 569 <col width="6%" />
 570 <col width="6%" />
 571 <col width="6%" />
 572 <col width="6%" />
 573 <col width="6%" />
 574 <col width="6%" />
 575 <col width="6%" />
 576 </colgroup>
 577 <thead valign="bottom">
 578 <tr class="row-odd"><th class="head">PLL Name</th>
 579 <th class="head">CLKOUT Freq (Hz)</th>
 580 <th class="head">N+1</th>
 581 <th class="head">M</th>
 582 <th class="head">Fractional M</th>
 583 <th class="head">M2</th>
 584 <th class="head">HSDIV0</th>
 585 <th class="head">HSDIV1</th>
 586 <th class="head">HSDIV2</th>
 587 <th class="head">HSDIV3</th>
 588 <th class="head">HSDIV4</th>
 589 <th class="head">HSDIV5</th>
 590 <th class="head">HSDIV6</th>
 591 <th class="head">HSDIV7</th>
 592 <th class="head">HSDIV8</th>
 593 </tr>
 594 </thead>
 595 <tbody valign="top">
 596 <tr class="row-even"><td>MCU (PLLFRACF_SSMOD_16FFT_MCU_0)</td>
 597 <td>2400000000</td>
 598 <td>1</td>
 599 <td>96</td>
 600 <td>0</td>
 601 <td>1</td>
 602 <td>6</td>
 603 <td>25</td>
 604 <td>25</td>
 605 <td>12</td>
 606 <td>12</td>
 607 <td>NA</td>
 608 <td>NA</td>
 609 <td>NA</td>
 610 <td>NA</td>
 611 </tr>
 612 <tr class="row-odd"><td>MAIN (PLLFRACF_SSMOD_16FFT_MAIN_0)</td>
 613 <td>1000000000</td>
 614 <td>1</td>
 615 <td>80</td>
 616 <td>0</td>
 617 <td>2</td>
 618 <td>4</td>
 619 <td>10</td>
 620 <td>25</td>
 621 <td>15</td>
 622 <td>8</td>
 623 <td>5</td>
 624 <td>5</td>
 625 <td>5</td>
 626 <td>8</td>
 627 </tr>
 628 <tr class="row-even"><td>PER0 (PLLFRACF_SSMOD_16FFT_MAIN_1)</td>
 629 <td>960000000</td>
 630 <td>5</td>
 631 <td>384</td>
 632 <td>0</td>
 633 <td>2</td>
 634 <td>10</td>
 635 <td>12</td>
 636 <td>5</td>
 637 <td>10</td>
 638 <td>80</td>
 639 <td>6</td>
 640 <td>16</td>
 641 <td>NA</td>
 642 <td>NA</td>
 643 </tr>
 644 <tr class="row-odd"><td>PER1 (PLLFRACF_SSMOD_16FFT_MAIN_2)</td>
 645 <td>1800000000</td>
 646 <td>1</td>
 647 <td>72</td>
 648 <td>0</td>
 649 <td>1</td>
 650 <td>8</td>
 651 <td>NA</td>
 652 <td>9</td>
 653 <td>6</td>
 654 <td>18</td>
 655 <td>8</td>
 656 <td>8</td>
 657 <td>18</td>
 658 <td>30</td>
 659 </tr>
 660 <tr class="row-even"><td>ARM0 (PLLFRACF_SSMOD_16FFT_MAIN_8)</td>
 661 <td>2000000000</td>
 662 <td>1</td>
 663 <td>80</td>
 664 <td>0</td>
 665 <td>1</td>
 666 <td>2</td>
 667 <td>NA</td>
 668 <td>NA</td>
 669 <td>NA</td>
 670 <td>NA</td>
 671 <td>NA</td>
 672 <td>NA</td>
 673 <td>NA</td>
 674 <td>NA</td>
 675 </tr>
 676 <tr class="row-odd"><td>DDR (PLLFRACF_SSMOD_16FFT_MAIN_12)</td>
 677 <td>1600000000</td>
 678 <td>1</td>
 679 <td>64</td>
 680 <td>0</td>
 681 <td>1</td>
 682 <td>4</td>
 683 <td>NA</td>
 684 <td>NA</td>
 685 <td>NA</td>
 686 <td>NA</td>
 687 <td>NA</td>
 688 <td>NA</td>
 689 <td>NA</td>
 690 <td>NA</td>
 691 </tr>
 692 <tr class="row-even"><td>R5F (PLLFRACF_SSMOD_16FFT_MAIN_14)</td>
 693 <td>2400000000</td>
 694 <td>1</td>
 695 <td>96</td>
 696 <td>0</td>
 697 <td>1</td>
 698 <td>3</td>
 699 <td>3</td>
 700 <td>NA</td>
 701 <td>NA</td>
 702 <td>NA</td>
 703 <td>NA</td>
 704 <td>NA</td>
 705 <td>NA</td>
 706 <td>NA</td>
 707 </tr>
 708 </tbody>
 709 </table>
 710 <p>The following table gives the PLL configurations for the input crystal Frequency of 26.0 MHz.</p>
 711 <table border="1" class="docutils">
 712 <colgroup>
 713 <col width="20%" />
 714 <col width="11%" />
 715 <col width="4%" />
 716 <col width="3%" />
 717 <col width="9%" />
 718 <col width="3%" />
 719 <col width="6%" />
 720 <col width="6%" />
 721 <col width="6%" />
 722 <col width="6%" />
 723 <col width="6%" />
 724 <col width="6%" />
 725 <col width="6%" />
 726 <col width="6%" />
 727 <col width="6%" />
 728 </colgroup>
 729 <thead valign="bottom">
 730 <tr class="row-odd"><th class="head">PLL Name</th>
 731 <th class="head">CLKOUT Freq (Hz)</th>
 732 <th class="head">N+1</th>
 733 <th class="head">M</th>
 734 <th class="head">Fractional M</th>
 735 <th class="head">M2</th>
 736 <th class="head">HSDIV0</th>
 737 <th class="head">HSDIV1</th>
 738 <th class="head">HSDIV2</th>
 739 <th class="head">HSDIV3</th>
 740 <th class="head">HSDIV4</th>
 741 <th class="head">HSDIV5</th>
 742 <th class="head">HSDIV6</th>
 743 <th class="head">HSDIV7</th>
 744 <th class="head">HSDIV8</th>
 745 </tr>
 746 </thead>
 747 <tbody valign="top">
 748 <tr class="row-even"><td>PER0 (PLLFRACF_SSMOD_16FFT_MAIN_1)</td>
 749 <td>960000000</td>
 750 <td>1</td>
 751 <td>73</td>
 752 <td>14196106</td>
 753 <td>2</td>
 754 <td>10</td>
 755 <td>12</td>
 756 <td>5</td>
 757 <td>10</td>
 758 <td>80</td>
 759 <td>6</td>
 760 <td>16</td>
 761 <td>NA</td>
 762 <td>NA</td>
 763 </tr>
 764 </tbody>
 765 </table>
 766 <p>The following table gives the PLL configurations for the input crystal Frequency of 27.0 MHz.</p>
 767 <table border="1" class="docutils">
 768 <colgroup>
 769 <col width="20%" />
 770 <col width="11%" />
 771 <col width="4%" />
 772 <col width="3%" />
 773 <col width="9%" />
 774 <col width="3%" />
 775 <col width="6%" />
 776 <col width="6%" />
 777 <col width="6%" />
 778 <col width="6%" />
 779 <col width="6%" />
 780 <col width="6%" />
 781 <col width="6%" />
 782 <col width="6%" />
 783 <col width="6%" />
 784 </colgroup>
 785 <thead valign="bottom">
 786 <tr class="row-odd"><th class="head">PLL Name</th>
 787 <th class="head">CLKOUT Freq (Hz)</th>
 788 <th class="head">N+1</th>
 789 <th class="head">M</th>
 790 <th class="head">Fractional M</th>
 791 <th class="head">M2</th>
 792 <th class="head">HSDIV0</th>
 793 <th class="head">HSDIV1</th>
 794 <th class="head">HSDIV2</th>
 795 <th class="head">HSDIV3</th>
 796 <th class="head">HSDIV4</th>
 797 <th class="head">HSDIV5</th>
 798 <th class="head">HSDIV6</th>
 799 <th class="head">HSDIV7</th>
 800 <th class="head">HSDIV8</th>
 801 </tr>
 802 </thead>
 803 <tbody valign="top">
 804 <tr class="row-even"><td>PER0 (PLLFRACF_SSMOD_16FFT_MAIN_1)</td>
 805 <td>960000000</td>
 806 <td>5</td>
 807 <td>384</td>
 808 <td>0</td>
 809 <td>2</td>
 810 <td>10</td>
 811 <td>12</td>
 812 <td>5</td>
 813 <td>10</td>
 814 <td>80</td>
 815 <td>6</td>
 816 <td>16</td>
 817 <td>NA</td>
 818 <td>NA</td>
 819 </tr>
 820 </tbody>
 821 </table>
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