packages/ti/drv/sciclient/soc/sysfw/binaries/system-firmware-public-documentation/5_soc_doc/am65x_sr2/interrupt_cfg.html

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 117 <li class="toctree-l4"><a class="reference internal" href="#introduction">Introduction</a></li>
 118 <li class="toctree-l4"><a class="reference internal" href="#interrupt-router-device-ids">Interrupt Router Device IDs</a></li>
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 120 <li class="toctree-l4"><a class="reference internal" href="#cmpevent-intrtr0-interrupt-router-output-destinations">CMPEVENT_INTRTR0 Interrupt Router Output Destinations</a></li>
 121 <li class="toctree-l4"><a class="reference internal" href="#main2mcu-lvl-intrtr0-interrupt-router-input-sources">MAIN2MCU_LVL_INTRTR0 Interrupt Router Input Sources</a></li>
 122 <li class="toctree-l4"><a class="reference internal" href="#main2mcu-lvl-intrtr0-interrupt-router-output-destinations">MAIN2MCU_LVL_INTRTR0 Interrupt Router Output Destinations</a></li>
 123 <li class="toctree-l4"><a class="reference internal" href="#main2mcu-pls-intrtr0-interrupt-router-input-sources">MAIN2MCU_PLS_INTRTR0 Interrupt Router Input Sources</a></li>
 124 <li class="toctree-l4"><a class="reference internal" href="#main2mcu-pls-intrtr0-interrupt-router-output-destinations">MAIN2MCU_PLS_INTRTR0 Interrupt Router Output Destinations</a></li>
 125 <li class="toctree-l4"><a class="reference internal" href="#gpiomux-intrtr0-interrupt-router-input-sources">GPIOMUX_INTRTR0 Interrupt Router Input Sources</a></li>
 126 <li class="toctree-l4"><a class="reference internal" href="#gpiomux-intrtr0-interrupt-router-output-destinations">GPIOMUX_INTRTR0 Interrupt Router Output Destinations</a></li>
 127 <li class="toctree-l4"><a class="reference internal" href="#navss0-intr-router-0-interrupt-router-input-sources">navss0_intr_router_0 Interrupt Router Input Sources</a></li>
 128 <li class="toctree-l4"><a class="reference internal" href="#navss0-intr-router-0-interrupt-router-output-destinations">navss0_intr_router_0 Interrupt Router Output Destinations</a></li>
 129 <li class="toctree-l4"><a class="reference internal" href="#mcu-navss0-intr-router-0-interrupt-router-input-sources">mcu_navss0_intr_router_0 Interrupt Router Input Sources</a></li>
 130 <li class="toctree-l4"><a class="reference internal" href="#mcu-navss0-intr-router-0-interrupt-router-output-destinations">mcu_navss0_intr_router_0 Interrupt Router Output Destinations</a></li>
 131 <li class="toctree-l4"><a class="reference internal" href="#timesync-intrtr0-interrupt-router-input-sources">TIMESYNC_INTRTR0 Interrupt Router Input Sources</a></li>
 132 <li class="toctree-l4"><a class="reference internal" href="#timesync-intrtr0-interrupt-router-output-destinations">TIMESYNC_INTRTR0 Interrupt Router Output Destinations</a></li>
 133 <li class="toctree-l4"><a class="reference internal" href="#wkup-gpiomux-intrtr0-interrupt-router-input-sources">WKUP_GPIOMUX_INTRTR0 Interrupt Router Input Sources</a></li>
 134 <li class="toctree-l4"><a class="reference internal" href="#wkup-gpiomux-intrtr0-interrupt-router-output-destinations">WKUP_GPIOMUX_INTRTR0 Interrupt Router Output Destinations</a></li>
 135 <li class="toctree-l4"><a class="reference internal" href="#interrupt-aggregator-device-ids">Interrupt Aggregator Device IDs</a></li>
 136 <li class="toctree-l4"><a class="reference internal" href="#interrupt-aggregator-virtual-interrupts">Interrupt Aggregator Virtual Interrupts</a></li>
 137 <li class="toctree-l4"><a class="reference internal" href="#navss0-modss-inta0-interrupt-aggregator-virtual-interrupt-destinations">navss0_modss_inta0 Interrupt Aggregator Virtual Interrupt Destinations</a></li>
 138 <li class="toctree-l4"><a class="reference internal" href="#navss0-modss-inta1-interrupt-aggregator-virtual-interrupt-destinations">navss0_modss_inta1 Interrupt Aggregator Virtual Interrupt Destinations</a></li>
 139 <li class="toctree-l4"><a class="reference internal" href="#navss0-udmass-inta0-interrupt-aggregator-virtual-interrupt-destinations">navss0_udmass_inta0 Interrupt Aggregator Virtual Interrupt Destinations</a></li>
 140 <li class="toctree-l4"><a class="reference internal" href="#mcu-navss0-intr-aggr-0-interrupt-aggregator-virtual-interrupt-destinations">mcu_navss0_intr_aggr_0 Interrupt Aggregator Virtual Interrupt Destinations</a></li>
 141 <li class="toctree-l4"><a class="reference internal" href="#global-events">Global Events</a></li>
 142 <li class="toctree-l4"><a class="reference internal" href="#event-based-interrupt-source-ids">Event-Based Interrupt Source IDs</a></li>
 143 </ul>
 144 </li>
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 207   <div class="section" id="am65x-sr2-interrupt-management-device-descriptions">
 208 <h1>AM65X_SR2 Interrupt Management Device Descriptions<a class="headerlink" href="#am65x-sr2-interrupt-management-device-descriptions" title="Permalink to this headline">¶</a></h1>
 209 <div class="section" id="introduction">
 210 <h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
 211 <p>This chapter provides information on the Interrupt Management devices in the
 212 AM65X_SR2 SoC.  Some System Firmware TISCI messages take device specific inputs.
 213 This chapter provides information on the valid values for Interrupt Management
 214 TISCI message parameters.</p>
 215 </div>
 216 <div class="section" id="interrupt-router-device-ids">
 217 <span id="pub-soc-am65x-sr2-ir-device-ids"></span><h2>Interrupt Router Device IDs<a class="headerlink" href="#interrupt-router-device-ids" title="Permalink to this headline">¶</a></h2>
 218 <p>Some System Firmware TISCI message APIs require the Interrupt Router device ID
 219 be provided as part of the request. Based on <a class="reference internal" href="devices.html"><span class="doc">AM65X_SR2 Device IDs</span></a> these are the valid Interrupt Router device IDs.</p>
 220 <table border="1" class="docutils">
 221 <colgroup>
 222 <col width="53%" />
 223 <col width="47%" />
 224 </colgroup>
 225 <thead valign="bottom">
 226 <tr class="row-odd"><th class="head">Interrupt Router Device Name</th>
 227 <th class="head">Interrupt Router Device ID</th>
 228 </tr>
 229 </thead>
 230 <tbody valign="top">
 231 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 232 <td>3</td>
 233 </tr>
 234 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
 235 <td>97</td>
 236 </tr>
 237 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
 238 <td>98</td>
 239 </tr>
 240 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
 241 <td>100</td>
 242 </tr>
 243 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
 244 <td>182</td>
 245 </tr>
 246 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
 247 <td>190</td>
 248 </tr>
 249 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
 250 <td>145</td>
 251 </tr>
 252 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
 253 <td>156</td>
 254 </tr>
 255 </tbody>
 256 </table>
 257 </div>
 258 <div class="section" id="cmpevent-intrtr0-interrupt-router-input-sources">
 259 <span id="pub-soc-am65x-sr2-cmpevent-intrtr0-input-src-list"></span><h2>CMPEVENT_INTRTR0 Interrupt Router Input Sources<a class="headerlink" href="#cmpevent-intrtr0-interrupt-router-input-sources" title="Permalink to this headline">¶</a></h2>
 260 <div class="admonition warning">
 261 <p class="first admonition-title">Warning</p>
 262 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
 263 host within the RM Board Configuration resource assignment array.  The RM
 264 Board Configuration is rejected if an overlap with a reserved resource is
 265 detected.</p>
 266 </div>
 267 <table border="1" class="docutils">
 268 <colgroup>
 269 <col width="22%" />
 270 <col width="13%" />
 271 <col width="15%" />
 272 <col width="17%" />
 273 <col width="19%" />
 274 <col width="13%" />
 275 </colgroup>
 276 <thead valign="bottom">
 277 <tr class="row-odd"><th class="head">IR Name</th>
 278 <th class="head">IR Device ID</th>
 279 <th class="head">IR Input Index</th>
 280 <th class="head">Source Name</th>
 281 <th class="head">Source Interface</th>
 282 <th class="head">Source Index</th>
 283 </tr>
 284 </thead>
 285 <tbody valign="top">
 286 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 287 <td>3</td>
 288 <td>0</td>
 289 <td>Not Connected</td>
 290 <td>&#160;</td>
 291 <td>&#160;</td>
 292 </tr>
 293 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 294 <td>3</td>
 295 <td>1</td>
 296 <td>Not Connected</td>
 297 <td>&#160;</td>
 298 <td>&#160;</td>
 299 </tr>
 300 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 301 <td>3</td>
 302 <td>2</td>
 303 <td>Not Connected</td>
 304 <td>&#160;</td>
 305 <td>&#160;</td>
 306 </tr>
 307 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 308 <td>3</td>
 309 <td>3</td>
 310 <td>Not Connected</td>
 311 <td>&#160;</td>
 312 <td>&#160;</td>
 313 </tr>
 314 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 315 <td>3</td>
 316 <td>4</td>
 317 <td>AM6_DEV_NAVSS0</td>
 318 <td>cpts0_comp</td>
 319 <td>0</td>
 320 </tr>
 321 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 322 <td>3</td>
 323 <td>5</td>
 324 <td>AM6_DEV_PCIE0</td>
 325 <td>pcie_cpts_comp</td>
 326 <td>0</td>
 327 </tr>
 328 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 329 <td>3</td>
 330 <td>6</td>
 331 <td>AM6_DEV_PCIE1</td>
 332 <td>pcie_cpts_comp</td>
 333 <td>0</td>
 334 </tr>
 335 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 336 <td>3</td>
 337 <td>7</td>
 338 <td>AM6_DEV_MCU_CPSW0</td>
 339 <td>cpts_comp</td>
 340 <td>0</td>
 341 </tr>
 342 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 343 <td>3</td>
 344 <td>8</td>
 345 <td>AM6_DEV_PRU_ICSSG0</td>
 346 <td>pr1_host_intr_req</td>
 347 <td>0</td>
 348 </tr>
 349 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 350 <td>3</td>
 351 <td>9</td>
 352 <td>AM6_DEV_PRU_ICSSG0</td>
 353 <td>pr1_host_intr_req</td>
 354 <td>1</td>
 355 </tr>
 356 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 357 <td>3</td>
 358 <td>10</td>
 359 <td>AM6_DEV_PRU_ICSSG0</td>
 360 <td>pr1_host_intr_req</td>
 361 <td>2</td>
 362 </tr>
 363 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 364 <td>3</td>
 365 <td>11</td>
 366 <td>AM6_DEV_PRU_ICSSG0</td>
 367 <td>pr1_host_intr_req</td>
 368 <td>3</td>
 369 </tr>
 370 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 371 <td>3</td>
 372 <td>12</td>
 373 <td>AM6_DEV_PRU_ICSSG0</td>
 374 <td>pr1_host_intr_req</td>
 375 <td>4</td>
 376 </tr>
 377 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 378 <td>3</td>
 379 <td>13</td>
 380 <td>AM6_DEV_PRU_ICSSG0</td>
 381 <td>pr1_host_intr_req</td>
 382 <td>5</td>
 383 </tr>
 384 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 385 <td>3</td>
 386 <td>14</td>
 387 <td>AM6_DEV_PRU_ICSSG0</td>
 388 <td>pr1_host_intr_req</td>
 389 <td>6</td>
 390 </tr>
 391 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 392 <td>3</td>
 393 <td>15</td>
 394 <td>AM6_DEV_PRU_ICSSG0</td>
 395 <td>pr1_host_intr_req</td>
 396 <td>7</td>
 397 </tr>
 398 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 399 <td>3</td>
 400 <td>16</td>
 401 <td>AM6_DEV_PRU_ICSSG1</td>
 402 <td>pr1_host_intr_req</td>
 403 <td>0</td>
 404 </tr>
 405 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 406 <td>3</td>
 407 <td>17</td>
 408 <td>AM6_DEV_PRU_ICSSG1</td>
 409 <td>pr1_host_intr_req</td>
 410 <td>1</td>
 411 </tr>
 412 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 413 <td>3</td>
 414 <td>18</td>
 415 <td>AM6_DEV_PRU_ICSSG1</td>
 416 <td>pr1_host_intr_req</td>
 417 <td>2</td>
 418 </tr>
 419 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 420 <td>3</td>
 421 <td>19</td>
 422 <td>AM6_DEV_PRU_ICSSG1</td>
 423 <td>pr1_host_intr_req</td>
 424 <td>3</td>
 425 </tr>
 426 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 427 <td>3</td>
 428 <td>20</td>
 429 <td>AM6_DEV_PRU_ICSSG1</td>
 430 <td>pr1_host_intr_req</td>
 431 <td>4</td>
 432 </tr>
 433 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 434 <td>3</td>
 435 <td>21</td>
 436 <td>AM6_DEV_PRU_ICSSG1</td>
 437 <td>pr1_host_intr_req</td>
 438 <td>5</td>
 439 </tr>
 440 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 441 <td>3</td>
 442 <td>22</td>
 443 <td>AM6_DEV_PRU_ICSSG1</td>
 444 <td>pr1_host_intr_req</td>
 445 <td>6</td>
 446 </tr>
 447 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 448 <td>3</td>
 449 <td>23</td>
 450 <td>AM6_DEV_PRU_ICSSG1</td>
 451 <td>pr1_host_intr_req</td>
 452 <td>7</td>
 453 </tr>
 454 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 455 <td>3</td>
 456 <td>24</td>
 457 <td>AM6_DEV_PRU_ICSSG2</td>
 458 <td>pr1_host_intr_req</td>
 459 <td>0</td>
 460 </tr>
 461 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 462 <td>3</td>
 463 <td>25</td>
 464 <td>AM6_DEV_PRU_ICSSG2</td>
 465 <td>pr1_host_intr_req</td>
 466 <td>1</td>
 467 </tr>
 468 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 469 <td>3</td>
 470 <td>26</td>
 471 <td>AM6_DEV_PRU_ICSSG2</td>
 472 <td>pr1_host_intr_req</td>
 473 <td>2</td>
 474 </tr>
 475 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 476 <td>3</td>
 477 <td>27</td>
 478 <td>AM6_DEV_PRU_ICSSG2</td>
 479 <td>pr1_host_intr_req</td>
 480 <td>3</td>
 481 </tr>
 482 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 483 <td>3</td>
 484 <td>28</td>
 485 <td>AM6_DEV_PRU_ICSSG2</td>
 486 <td>pr1_host_intr_req</td>
 487 <td>4</td>
 488 </tr>
 489 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 490 <td>3</td>
 491 <td>29</td>
 492 <td>AM6_DEV_PRU_ICSSG2</td>
 493 <td>pr1_host_intr_req</td>
 494 <td>5</td>
 495 </tr>
 496 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 497 <td>3</td>
 498 <td>30</td>
 499 <td>AM6_DEV_PRU_ICSSG2</td>
 500 <td>pr1_host_intr_req</td>
 501 <td>6</td>
 502 </tr>
 503 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 504 <td>3</td>
 505 <td>31</td>
 506 <td>AM6_DEV_PRU_ICSSG2</td>
 507 <td>pr1_host_intr_req</td>
 508 <td>7</td>
 509 </tr>
 510 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 511 <td>3</td>
 512 <td>32</td>
 513 <td>AM6_DEV_PRU_ICSSG0</td>
 514 <td>pr1_iep0_cmp_intr_req</td>
 515 <td>0</td>
 516 </tr>
 517 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 518 <td>3</td>
 519 <td>33</td>
 520 <td>AM6_DEV_PRU_ICSSG0</td>
 521 <td>pr1_iep0_cmp_intr_req</td>
 522 <td>1</td>
 523 </tr>
 524 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 525 <td>3</td>
 526 <td>34</td>
 527 <td>AM6_DEV_PRU_ICSSG0</td>
 528 <td>pr1_iep0_cmp_intr_req</td>
 529 <td>2</td>
 530 </tr>
 531 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 532 <td>3</td>
 533 <td>35</td>
 534 <td>AM6_DEV_PRU_ICSSG0</td>
 535 <td>pr1_iep0_cmp_intr_req</td>
 536 <td>3</td>
 537 </tr>
 538 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 539 <td>3</td>
 540 <td>36</td>
 541 <td>AM6_DEV_PRU_ICSSG0</td>
 542 <td>pr1_iep0_cmp_intr_req</td>
 543 <td>4</td>
 544 </tr>
 545 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 546 <td>3</td>
 547 <td>37</td>
 548 <td>AM6_DEV_PRU_ICSSG0</td>
 549 <td>pr1_iep0_cmp_intr_req</td>
 550 <td>5</td>
 551 </tr>
 552 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 553 <td>3</td>
 554 <td>38</td>
 555 <td>AM6_DEV_PRU_ICSSG0</td>
 556 <td>pr1_iep0_cmp_intr_req</td>
 557 <td>6</td>
 558 </tr>
 559 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 560 <td>3</td>
 561 <td>39</td>
 562 <td>AM6_DEV_PRU_ICSSG0</td>
 563 <td>pr1_iep0_cmp_intr_req</td>
 564 <td>7</td>
 565 </tr>
 566 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 567 <td>3</td>
 568 <td>40</td>
 569 <td>AM6_DEV_PRU_ICSSG0</td>
 570 <td>pr1_iep0_cmp_intr_req</td>
 571 <td>8</td>
 572 </tr>
 573 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 574 <td>3</td>
 575 <td>41</td>
 576 <td>AM6_DEV_PRU_ICSSG0</td>
 577 <td>pr1_iep0_cmp_intr_req</td>
 578 <td>9</td>
 579 </tr>
 580 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 581 <td>3</td>
 582 <td>42</td>
 583 <td>AM6_DEV_PRU_ICSSG0</td>
 584 <td>pr1_iep0_cmp_intr_req</td>
 585 <td>10</td>
 586 </tr>
 587 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 588 <td>3</td>
 589 <td>43</td>
 590 <td>AM6_DEV_PRU_ICSSG0</td>
 591 <td>pr1_iep0_cmp_intr_req</td>
 592 <td>11</td>
 593 </tr>
 594 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 595 <td>3</td>
 596 <td>44</td>
 597 <td>AM6_DEV_PRU_ICSSG0</td>
 598 <td>pr1_iep0_cmp_intr_req</td>
 599 <td>12</td>
 600 </tr>
 601 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 602 <td>3</td>
 603 <td>45</td>
 604 <td>AM6_DEV_PRU_ICSSG0</td>
 605 <td>pr1_iep0_cmp_intr_req</td>
 606 <td>13</td>
 607 </tr>
 608 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 609 <td>3</td>
 610 <td>46</td>
 611 <td>AM6_DEV_PRU_ICSSG0</td>
 612 <td>pr1_iep0_cmp_intr_req</td>
 613 <td>14</td>
 614 </tr>
 615 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 616 <td>3</td>
 617 <td>47</td>
 618 <td>AM6_DEV_PRU_ICSSG0</td>
 619 <td>pr1_iep0_cmp_intr_req</td>
 620 <td>15</td>
 621 </tr>
 622 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 623 <td>3</td>
 624 <td>48</td>
 625 <td>AM6_DEV_PRU_ICSSG0</td>
 626 <td>pr1_iep1_cmp_intr_req</td>
 627 <td>0</td>
 628 </tr>
 629 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 630 <td>3</td>
 631 <td>49</td>
 632 <td>AM6_DEV_PRU_ICSSG0</td>
 633 <td>pr1_iep1_cmp_intr_req</td>
 634 <td>1</td>
 635 </tr>
 636 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 637 <td>3</td>
 638 <td>50</td>
 639 <td>AM6_DEV_PRU_ICSSG0</td>
 640 <td>pr1_iep1_cmp_intr_req</td>
 641 <td>2</td>
 642 </tr>
 643 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 644 <td>3</td>
 645 <td>51</td>
 646 <td>AM6_DEV_PRU_ICSSG0</td>
 647 <td>pr1_iep1_cmp_intr_req</td>
 648 <td>3</td>
 649 </tr>
 650 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 651 <td>3</td>
 652 <td>52</td>
 653 <td>AM6_DEV_PRU_ICSSG0</td>
 654 <td>pr1_iep1_cmp_intr_req</td>
 655 <td>4</td>
 656 </tr>
 657 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 658 <td>3</td>
 659 <td>53</td>
 660 <td>AM6_DEV_PRU_ICSSG0</td>
 661 <td>pr1_iep1_cmp_intr_req</td>
 662 <td>5</td>
 663 </tr>
 664 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 665 <td>3</td>
 666 <td>54</td>
 667 <td>AM6_DEV_PRU_ICSSG0</td>
 668 <td>pr1_iep1_cmp_intr_req</td>
 669 <td>6</td>
 670 </tr>
 671 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 672 <td>3</td>
 673 <td>55</td>
 674 <td>AM6_DEV_PRU_ICSSG0</td>
 675 <td>pr1_iep1_cmp_intr_req</td>
 676 <td>7</td>
 677 </tr>
 678 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 679 <td>3</td>
 680 <td>56</td>
 681 <td>AM6_DEV_PRU_ICSSG0</td>
 682 <td>pr1_iep1_cmp_intr_req</td>
 683 <td>8</td>
 684 </tr>
 685 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 686 <td>3</td>
 687 <td>57</td>
 688 <td>AM6_DEV_PRU_ICSSG0</td>
 689 <td>pr1_iep1_cmp_intr_req</td>
 690 <td>9</td>
 691 </tr>
 692 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 693 <td>3</td>
 694 <td>58</td>
 695 <td>AM6_DEV_PRU_ICSSG0</td>
 696 <td>pr1_iep1_cmp_intr_req</td>
 697 <td>10</td>
 698 </tr>
 699 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 700 <td>3</td>
 701 <td>59</td>
 702 <td>AM6_DEV_PRU_ICSSG0</td>
 703 <td>pr1_iep1_cmp_intr_req</td>
 704 <td>11</td>
 705 </tr>
 706 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 707 <td>3</td>
 708 <td>60</td>
 709 <td>AM6_DEV_PRU_ICSSG0</td>
 710 <td>pr1_iep1_cmp_intr_req</td>
 711 <td>12</td>
 712 </tr>
 713 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 714 <td>3</td>
 715 <td>61</td>
 716 <td>AM6_DEV_PRU_ICSSG0</td>
 717 <td>pr1_iep1_cmp_intr_req</td>
 718 <td>13</td>
 719 </tr>
 720 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 721 <td>3</td>
 722 <td>62</td>
 723 <td>AM6_DEV_PRU_ICSSG0</td>
 724 <td>pr1_iep1_cmp_intr_req</td>
 725 <td>14</td>
 726 </tr>
 727 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 728 <td>3</td>
 729 <td>63</td>
 730 <td>AM6_DEV_PRU_ICSSG0</td>
 731 <td>pr1_iep1_cmp_intr_req</td>
 732 <td>15</td>
 733 </tr>
 734 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 735 <td>3</td>
 736 <td>64</td>
 737 <td>AM6_DEV_PRU_ICSSG1</td>
 738 <td>pr1_iep0_cmp_intr_req</td>
 739 <td>0</td>
 740 </tr>
 741 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 742 <td>3</td>
 743 <td>65</td>
 744 <td>AM6_DEV_PRU_ICSSG1</td>
 745 <td>pr1_iep0_cmp_intr_req</td>
 746 <td>1</td>
 747 </tr>
 748 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 749 <td>3</td>
 750 <td>66</td>
 751 <td>AM6_DEV_PRU_ICSSG1</td>
 752 <td>pr1_iep0_cmp_intr_req</td>
 753 <td>2</td>
 754 </tr>
 755 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 756 <td>3</td>
 757 <td>67</td>
 758 <td>AM6_DEV_PRU_ICSSG1</td>
 759 <td>pr1_iep0_cmp_intr_req</td>
 760 <td>3</td>
 761 </tr>
 762 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 763 <td>3</td>
 764 <td>68</td>
 765 <td>AM6_DEV_PRU_ICSSG1</td>
 766 <td>pr1_iep0_cmp_intr_req</td>
 767 <td>4</td>
 768 </tr>
 769 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 770 <td>3</td>
 771 <td>69</td>
 772 <td>AM6_DEV_PRU_ICSSG1</td>
 773 <td>pr1_iep0_cmp_intr_req</td>
 774 <td>5</td>
 775 </tr>
 776 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 777 <td>3</td>
 778 <td>70</td>
 779 <td>AM6_DEV_PRU_ICSSG1</td>
 780 <td>pr1_iep0_cmp_intr_req</td>
 781 <td>6</td>
 782 </tr>
 783 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 784 <td>3</td>
 785 <td>71</td>
 786 <td>AM6_DEV_PRU_ICSSG1</td>
 787 <td>pr1_iep0_cmp_intr_req</td>
 788 <td>7</td>
 789 </tr>
 790 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 791 <td>3</td>
 792 <td>72</td>
 793 <td>AM6_DEV_PRU_ICSSG1</td>
 794 <td>pr1_iep0_cmp_intr_req</td>
 795 <td>8</td>
 796 </tr>
 797 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 798 <td>3</td>
 799 <td>73</td>
 800 <td>AM6_DEV_PRU_ICSSG1</td>
 801 <td>pr1_iep0_cmp_intr_req</td>
 802 <td>9</td>
 803 </tr>
 804 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 805 <td>3</td>
 806 <td>74</td>
 807 <td>AM6_DEV_PRU_ICSSG1</td>
 808 <td>pr1_iep0_cmp_intr_req</td>
 809 <td>10</td>
 810 </tr>
 811 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 812 <td>3</td>
 813 <td>75</td>
 814 <td>AM6_DEV_PRU_ICSSG1</td>
 815 <td>pr1_iep0_cmp_intr_req</td>
 816 <td>11</td>
 817 </tr>
 818 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 819 <td>3</td>
 820 <td>76</td>
 821 <td>AM6_DEV_PRU_ICSSG1</td>
 822 <td>pr1_iep0_cmp_intr_req</td>
 823 <td>12</td>
 824 </tr>
 825 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 826 <td>3</td>
 827 <td>77</td>
 828 <td>AM6_DEV_PRU_ICSSG1</td>
 829 <td>pr1_iep0_cmp_intr_req</td>
 830 <td>13</td>
 831 </tr>
 832 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 833 <td>3</td>
 834 <td>78</td>
 835 <td>AM6_DEV_PRU_ICSSG1</td>
 836 <td>pr1_iep0_cmp_intr_req</td>
 837 <td>14</td>
 838 </tr>
 839 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 840 <td>3</td>
 841 <td>79</td>
 842 <td>AM6_DEV_PRU_ICSSG1</td>
 843 <td>pr1_iep0_cmp_intr_req</td>
 844 <td>15</td>
 845 </tr>
 846 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 847 <td>3</td>
 848 <td>80</td>
 849 <td>AM6_DEV_PRU_ICSSG1</td>
 850 <td>pr1_iep1_cmp_intr_req</td>
 851 <td>0</td>
 852 </tr>
 853 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 854 <td>3</td>
 855 <td>81</td>
 856 <td>AM6_DEV_PRU_ICSSG1</td>
 857 <td>pr1_iep1_cmp_intr_req</td>
 858 <td>1</td>
 859 </tr>
 860 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 861 <td>3</td>
 862 <td>82</td>
 863 <td>AM6_DEV_PRU_ICSSG1</td>
 864 <td>pr1_iep1_cmp_intr_req</td>
 865 <td>2</td>
 866 </tr>
 867 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 868 <td>3</td>
 869 <td>83</td>
 870 <td>AM6_DEV_PRU_ICSSG1</td>
 871 <td>pr1_iep1_cmp_intr_req</td>
 872 <td>3</td>
 873 </tr>
 874 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 875 <td>3</td>
 876 <td>84</td>
 877 <td>AM6_DEV_PRU_ICSSG1</td>
 878 <td>pr1_iep1_cmp_intr_req</td>
 879 <td>4</td>
 880 </tr>
 881 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 882 <td>3</td>
 883 <td>85</td>
 884 <td>AM6_DEV_PRU_ICSSG1</td>
 885 <td>pr1_iep1_cmp_intr_req</td>
 886 <td>5</td>
 887 </tr>
 888 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 889 <td>3</td>
 890 <td>86</td>
 891 <td>AM6_DEV_PRU_ICSSG1</td>
 892 <td>pr1_iep1_cmp_intr_req</td>
 893 <td>6</td>
 894 </tr>
 895 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 896 <td>3</td>
 897 <td>87</td>
 898 <td>AM6_DEV_PRU_ICSSG1</td>
 899 <td>pr1_iep1_cmp_intr_req</td>
 900 <td>7</td>
 901 </tr>
 902 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 903 <td>3</td>
 904 <td>88</td>
 905 <td>AM6_DEV_PRU_ICSSG1</td>
 906 <td>pr1_iep1_cmp_intr_req</td>
 907 <td>8</td>
 908 </tr>
 909 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 910 <td>3</td>
 911 <td>89</td>
 912 <td>AM6_DEV_PRU_ICSSG1</td>
 913 <td>pr1_iep1_cmp_intr_req</td>
 914 <td>9</td>
 915 </tr>
 916 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 917 <td>3</td>
 918 <td>90</td>
 919 <td>AM6_DEV_PRU_ICSSG1</td>
 920 <td>pr1_iep1_cmp_intr_req</td>
 921 <td>10</td>
 922 </tr>
 923 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 924 <td>3</td>
 925 <td>91</td>
 926 <td>AM6_DEV_PRU_ICSSG1</td>
 927 <td>pr1_iep1_cmp_intr_req</td>
 928 <td>11</td>
 929 </tr>
 930 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 931 <td>3</td>
 932 <td>92</td>
 933 <td>AM6_DEV_PRU_ICSSG1</td>
 934 <td>pr1_iep1_cmp_intr_req</td>
 935 <td>12</td>
 936 </tr>
 937 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 938 <td>3</td>
 939 <td>93</td>
 940 <td>AM6_DEV_PRU_ICSSG1</td>
 941 <td>pr1_iep1_cmp_intr_req</td>
 942 <td>13</td>
 943 </tr>
 944 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 945 <td>3</td>
 946 <td>94</td>
 947 <td>AM6_DEV_PRU_ICSSG1</td>
 948 <td>pr1_iep1_cmp_intr_req</td>
 949 <td>14</td>
 950 </tr>
 951 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 952 <td>3</td>
 953 <td>95</td>
 954 <td>AM6_DEV_PRU_ICSSG1</td>
 955 <td>pr1_iep1_cmp_intr_req</td>
 956 <td>15</td>
 957 </tr>
 958 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 959 <td>3</td>
 960 <td>96</td>
 961 <td>AM6_DEV_PRU_ICSSG2</td>
 962 <td>pr1_iep0_cmp_intr_req</td>
 963 <td>0</td>
 964 </tr>
 965 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 966 <td>3</td>
 967 <td>97</td>
 968 <td>AM6_DEV_PRU_ICSSG2</td>
 969 <td>pr1_iep0_cmp_intr_req</td>
 970 <td>1</td>
 971 </tr>
 972 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 973 <td>3</td>
 974 <td>98</td>
 975 <td>AM6_DEV_PRU_ICSSG2</td>
 976 <td>pr1_iep0_cmp_intr_req</td>
 977 <td>2</td>
 978 </tr>
 979 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 980 <td>3</td>
 981 <td>99</td>
 982 <td>AM6_DEV_PRU_ICSSG2</td>
 983 <td>pr1_iep0_cmp_intr_req</td>
 984 <td>3</td>
 985 </tr>
 986 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 987 <td>3</td>
 988 <td>100</td>
 989 <td>AM6_DEV_PRU_ICSSG2</td>
 990 <td>pr1_iep0_cmp_intr_req</td>
 991 <td>4</td>
 992 </tr>
 993 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 994 <td>3</td>
 995 <td>101</td>
 996 <td>AM6_DEV_PRU_ICSSG2</td>
 997 <td>pr1_iep0_cmp_intr_req</td>
 998 <td>5</td>
 999 </tr>
1000 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1001 <td>3</td>
1002 <td>102</td>
1003 <td>AM6_DEV_PRU_ICSSG2</td>
1004 <td>pr1_iep0_cmp_intr_req</td>
1005 <td>6</td>
1006 </tr>
1007 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1008 <td>3</td>
1009 <td>103</td>
1010 <td>AM6_DEV_PRU_ICSSG2</td>
1011 <td>pr1_iep0_cmp_intr_req</td>
1012 <td>7</td>
1013 </tr>
1014 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1015 <td>3</td>
1016 <td>104</td>
1017 <td>AM6_DEV_PRU_ICSSG2</td>
1018 <td>pr1_iep0_cmp_intr_req</td>
1019 <td>8</td>
1020 </tr>
1021 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1022 <td>3</td>
1023 <td>105</td>
1024 <td>AM6_DEV_PRU_ICSSG2</td>
1025 <td>pr1_iep0_cmp_intr_req</td>
1026 <td>9</td>
1027 </tr>
1028 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1029 <td>3</td>
1030 <td>106</td>
1031 <td>AM6_DEV_PRU_ICSSG2</td>
1032 <td>pr1_iep0_cmp_intr_req</td>
1033 <td>10</td>
1034 </tr>
1035 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1036 <td>3</td>
1037 <td>107</td>
1038 <td>AM6_DEV_PRU_ICSSG2</td>
1039 <td>pr1_iep0_cmp_intr_req</td>
1040 <td>11</td>
1041 </tr>
1042 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1043 <td>3</td>
1044 <td>108</td>
1045 <td>AM6_DEV_PRU_ICSSG2</td>
1046 <td>pr1_iep0_cmp_intr_req</td>
1047 <td>12</td>
1048 </tr>
1049 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1050 <td>3</td>
1051 <td>109</td>
1052 <td>AM6_DEV_PRU_ICSSG2</td>
1053 <td>pr1_iep0_cmp_intr_req</td>
1054 <td>13</td>
1055 </tr>
1056 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1057 <td>3</td>
1058 <td>110</td>
1059 <td>AM6_DEV_PRU_ICSSG2</td>
1060 <td>pr1_iep0_cmp_intr_req</td>
1061 <td>14</td>
1062 </tr>
1063 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1064 <td>3</td>
1065 <td>111</td>
1066 <td>AM6_DEV_PRU_ICSSG2</td>
1067 <td>pr1_iep0_cmp_intr_req</td>
1068 <td>15</td>
1069 </tr>
1070 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1071 <td>3</td>
1072 <td>112</td>
1073 <td>AM6_DEV_PRU_ICSSG2</td>
1074 <td>pr1_iep1_cmp_intr_req</td>
1075 <td>0</td>
1076 </tr>
1077 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1078 <td>3</td>
1079 <td>113</td>
1080 <td>AM6_DEV_PRU_ICSSG2</td>
1081 <td>pr1_iep1_cmp_intr_req</td>
1082 <td>1</td>
1083 </tr>
1084 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1085 <td>3</td>
1086 <td>114</td>
1087 <td>AM6_DEV_PRU_ICSSG2</td>
1088 <td>pr1_iep1_cmp_intr_req</td>
1089 <td>2</td>
1090 </tr>
1091 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1092 <td>3</td>
1093 <td>115</td>
1094 <td>AM6_DEV_PRU_ICSSG2</td>
1095 <td>pr1_iep1_cmp_intr_req</td>
1096 <td>3</td>
1097 </tr>
1098 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1099 <td>3</td>
1100 <td>116</td>
1101 <td>AM6_DEV_PRU_ICSSG2</td>
1102 <td>pr1_iep1_cmp_intr_req</td>
1103 <td>4</td>
1104 </tr>
1105 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1106 <td>3</td>
1107 <td>117</td>
1108 <td>AM6_DEV_PRU_ICSSG2</td>
1109 <td>pr1_iep1_cmp_intr_req</td>
1110 <td>5</td>
1111 </tr>
1112 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1113 <td>3</td>
1114 <td>118</td>
1115 <td>AM6_DEV_PRU_ICSSG2</td>
1116 <td>pr1_iep1_cmp_intr_req</td>
1117 <td>6</td>
1118 </tr>
1119 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1120 <td>3</td>
1121 <td>119</td>
1122 <td>AM6_DEV_PRU_ICSSG2</td>
1123 <td>pr1_iep1_cmp_intr_req</td>
1124 <td>7</td>
1125 </tr>
1126 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1127 <td>3</td>
1128 <td>120</td>
1129 <td>AM6_DEV_PRU_ICSSG2</td>
1130 <td>pr1_iep1_cmp_intr_req</td>
1131 <td>8</td>
1132 </tr>
1133 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1134 <td>3</td>
1135 <td>121</td>
1136 <td>AM6_DEV_PRU_ICSSG2</td>
1137 <td>pr1_iep1_cmp_intr_req</td>
1138 <td>9</td>
1139 </tr>
1140 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1141 <td>3</td>
1142 <td>122</td>
1143 <td>AM6_DEV_PRU_ICSSG2</td>
1144 <td>pr1_iep1_cmp_intr_req</td>
1145 <td>10</td>
1146 </tr>
1147 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1148 <td>3</td>
1149 <td>123</td>
1150 <td>AM6_DEV_PRU_ICSSG2</td>
1151 <td>pr1_iep1_cmp_intr_req</td>
1152 <td>11</td>
1153 </tr>
1154 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1155 <td>3</td>
1156 <td>124</td>
1157 <td>AM6_DEV_PRU_ICSSG2</td>
1158 <td>pr1_iep1_cmp_intr_req</td>
1159 <td>12</td>
1160 </tr>
1161 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1162 <td>3</td>
1163 <td>125</td>
1164 <td>AM6_DEV_PRU_ICSSG2</td>
1165 <td>pr1_iep1_cmp_intr_req</td>
1166 <td>13</td>
1167 </tr>
1168 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1169 <td>3</td>
1170 <td>126</td>
1171 <td>AM6_DEV_PRU_ICSSG2</td>
1172 <td>pr1_iep1_cmp_intr_req</td>
1173 <td>14</td>
1174 </tr>
1175 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1176 <td>3</td>
1177 <td>127</td>
1178 <td>AM6_DEV_PRU_ICSSG2</td>
1179 <td>pr1_iep1_cmp_intr_req</td>
1180 <td>15</td>
1181 </tr>
1182 </tbody>
1183 </table>
1184 </div>
1185 <div class="section" id="cmpevent-intrtr0-interrupt-router-output-destinations">
1186 <span id="pub-soc-am65x-sr2-cmpevent-intrtr0-output-src-list"></span><h2>CMPEVENT_INTRTR0 Interrupt Router Output Destinations<a class="headerlink" href="#cmpevent-intrtr0-interrupt-router-output-destinations" title="Permalink to this headline">¶</a></h2>
1187 <div class="admonition warning">
1188 <p class="first admonition-title">Warning</p>
1189 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
1190 host within the RM Board Configuration resource assignment array.  The RM
1191 Board Configuration is rejected if an overlap with a reserved resource is
1192 detected.</p>
1193 </div>
1194 <table border="1" class="docutils">
1195 <colgroup>
1196 <col width="20%" />
1197 <col width="13%" />
1198 <col width="15%" />
1199 <col width="16%" />
1200 <col width="20%" />
1201 <col width="17%" />
1202 </colgroup>
1203 <thead valign="bottom">
1204 <tr class="row-odd"><th class="head">IR Name</th>
1205 <th class="head">IR Device ID</th>
1206 <th class="head">IR Output Index</th>
1207 <th class="head">Destination Name</th>
1208 <th class="head">Destination Interface</th>
1209 <th class="head">Destination Index</th>
1210 </tr>
1211 </thead>
1212 <tbody valign="top">
1213 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1214 <td>3</td>
1215 <td>0</td>
1216 <td>AM6_DEV_GIC0</td>
1217 <td>spi</td>
1218 <td>544</td>
1219 </tr>
1220 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1221 <td>3</td>
1222 <td>1</td>
1223 <td>AM6_DEV_GIC0</td>
1224 <td>spi</td>
1225 <td>545</td>
1226 </tr>
1227 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1228 <td>3</td>
1229 <td>2</td>
1230 <td>AM6_DEV_GIC0</td>
1231 <td>spi</td>
1232 <td>546</td>
1233 </tr>
1234 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1235 <td>3</td>
1236 <td>3</td>
1237 <td>AM6_DEV_GIC0</td>
1238 <td>spi</td>
1239 <td>547</td>
1240 </tr>
1241 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1242 <td>3</td>
1243 <td>4</td>
1244 <td>AM6_DEV_GIC0</td>
1245 <td>spi</td>
1246 <td>548</td>
1247 </tr>
1248 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1249 <td>3</td>
1250 <td>5</td>
1251 <td>AM6_DEV_GIC0</td>
1252 <td>spi</td>
1253 <td>549</td>
1254 </tr>
1255 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1256 <td>3</td>
1257 <td>6</td>
1258 <td>AM6_DEV_GIC0</td>
1259 <td>spi</td>
1260 <td>550</td>
1261 </tr>
1262 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1263 <td>3</td>
1264 <td>7</td>
1265 <td>AM6_DEV_GIC0</td>
1266 <td>spi</td>
1267 <td>551</td>
1268 </tr>
1269 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1270 <td>3</td>
1271 <td>8</td>
1272 <td>AM6_DEV_GIC0</td>
1273 <td>spi</td>
1274 <td>552</td>
1275 </tr>
1276 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1277 <td>3</td>
1278 <td>9</td>
1279 <td>AM6_DEV_GIC0</td>
1280 <td>spi</td>
1281 <td>553</td>
1282 </tr>
1283 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1284 <td>3</td>
1285 <td>10</td>
1286 <td>AM6_DEV_GIC0</td>
1287 <td>spi</td>
1288 <td>554</td>
1289 </tr>
1290 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1291 <td>3</td>
1292 <td>11</td>
1293 <td>AM6_DEV_GIC0</td>
1294 <td>spi</td>
1295 <td>555</td>
1296 </tr>
1297 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1298 <td>3</td>
1299 <td>12</td>
1300 <td>AM6_DEV_GIC0</td>
1301 <td>spi</td>
1302 <td>556</td>
1303 </tr>
1304 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1305 <td>3</td>
1306 <td>13</td>
1307 <td>AM6_DEV_GIC0</td>
1308 <td>spi</td>
1309 <td>557</td>
1310 </tr>
1311 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1312 <td>3</td>
1313 <td>14</td>
1314 <td>AM6_DEV_GIC0</td>
1315 <td>spi</td>
1316 <td>558</td>
1317 </tr>
1318 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1319 <td>3</td>
1320 <td>15</td>
1321 <td>AM6_DEV_GIC0</td>
1322 <td>spi</td>
1323 <td>559</td>
1324 </tr>
1325 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1326 <td>3</td>
1327 <td>16</td>
1328 <td>Not Connected</td>
1329 <td>&#160;</td>
1330 <td>&#160;</td>
1331 </tr>
1332 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1333 <td>3</td>
1334 <td>17</td>
1335 <td>Not Connected</td>
1336 <td>&#160;</td>
1337 <td>&#160;</td>
1338 </tr>
1339 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1340 <td>3</td>
1341 <td>18</td>
1342 <td>Not Connected</td>
1343 <td>&#160;</td>
1344 <td>&#160;</td>
1345 </tr>
1346 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1347 <td>3</td>
1348 <td>19</td>
1349 <td>Not Connected</td>
1350 <td>&#160;</td>
1351 <td>&#160;</td>
1352 </tr>
1353 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1354 <td>3</td>
1355 <td>20</td>
1356 <td>Not Connected</td>
1357 <td>&#160;</td>
1358 <td>&#160;</td>
1359 </tr>
1360 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1361 <td>3</td>
1362 <td>21</td>
1363 <td>Not Connected</td>
1364 <td>&#160;</td>
1365 <td>&#160;</td>
1366 </tr>
1367 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1368 <td>3</td>
1369 <td>22</td>
1370 <td>Not Connected</td>
1371 <td>&#160;</td>
1372 <td>&#160;</td>
1373 </tr>
1374 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1375 <td>3</td>
1376 <td>23</td>
1377 <td>Not Connected</td>
1378 <td>&#160;</td>
1379 <td>&#160;</td>
1380 </tr>
1381 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1382 <td>3</td>
1383 <td>24</td>
1384 <td>AM6_DEV_PDMA1</td>
1385 <td>levent_in</td>
1386 <td>8</td>
1387 </tr>
1388 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1389 <td>3</td>
1390 <td>25</td>
1391 <td>AM6_DEV_PDMA1</td>
1392 <td>levent_in</td>
1393 <td>9</td>
1394 </tr>
1395 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1396 <td>3</td>
1397 <td>26</td>
1398 <td>AM6_DEV_PDMA1</td>
1399 <td>levent_in</td>
1400 <td>10</td>
1401 </tr>
1402 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1403 <td>3</td>
1404 <td>27</td>
1405 <td>AM6_DEV_PDMA1</td>
1406 <td>levent_in</td>
1407 <td>11</td>
1408 </tr>
1409 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1410 <td>3</td>
1411 <td>28</td>
1412 <td>AM6_DEV_PDMA1</td>
1413 <td>levent_in</td>
1414 <td>12</td>
1415 </tr>
1416 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1417 <td>3</td>
1418 <td>29</td>
1419 <td>AM6_DEV_PDMA1</td>
1420 <td>levent_in</td>
1421 <td>13</td>
1422 </tr>
1423 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1424 <td>3</td>
1425 <td>30</td>
1426 <td>AM6_DEV_PDMA1</td>
1427 <td>levent_in</td>
1428 <td>14</td>
1429 </tr>
1430 <tr class="row-odd"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
1431 <td>3</td>
1432 <td>31</td>
1433 <td>AM6_DEV_PDMA1</td>
1434 <td>levent_in</td>
1435 <td>15</td>
1436 </tr>
1437 </tbody>
1438 </table>
1439 </div>
1440 <div class="section" id="main2mcu-lvl-intrtr0-interrupt-router-input-sources">
1441 <span id="pub-soc-am65x-sr2-main2mcu-lvl-intrtr0-input-src-list"></span><h2>MAIN2MCU_LVL_INTRTR0 Interrupt Router Input Sources<a class="headerlink" href="#main2mcu-lvl-intrtr0-interrupt-router-input-sources" title="Permalink to this headline">¶</a></h2>
1442 <div class="admonition warning">
1443 <p class="first admonition-title">Warning</p>
1444 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
1445 host within the RM Board Configuration resource assignment array.  The RM
1446 Board Configuration is rejected if an overlap with a reserved resource is
1447 detected.</p>
1448 </div>
1449 <table border="1" class="docutils">
1450 <colgroup>
1451 <col width="22%" />
1452 <col width="12%" />
1453 <col width="13%" />
1454 <col width="22%" />
1455 <col width="19%" />
1456 <col width="12%" />
1457 </colgroup>
1458 <thead valign="bottom">
1459 <tr class="row-odd"><th class="head">IR Name</th>
1460 <th class="head">IR Device ID</th>
1461 <th class="head">IR Input Index</th>
1462 <th class="head">Source Name</th>
1463 <th class="head">Source Interface</th>
1464 <th class="head">Source Index</th>
1465 </tr>
1466 </thead>
1467 <tbody valign="top">
1468 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1469 <td>97</td>
1470 <td>0</td>
1471 <td>Not Connected</td>
1472 <td>&#160;</td>
1473 <td>&#160;</td>
1474 </tr>
1475 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1476 <td>97</td>
1477 <td>1</td>
1478 <td>Not Connected</td>
1479 <td>&#160;</td>
1480 <td>&#160;</td>
1481 </tr>
1482 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1483 <td>97</td>
1484 <td>2</td>
1485 <td>AM6_DEV_DSS0</td>
1486 <td>dispc_intr_req_0</td>
1487 <td>0</td>
1488 </tr>
1489 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1490 <td>97</td>
1491 <td>3</td>
1492 <td>AM6_DEV_DSS0</td>
1493 <td>dispc_intr_req_1</td>
1494 <td>0</td>
1495 </tr>
1496 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1497 <td>97</td>
1498 <td>4</td>
1499 <td>AM6_DEV_SA2_UL0</td>
1500 <td>sa_ul_trng</td>
1501 <td>0</td>
1502 </tr>
1503 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1504 <td>97</td>
1505 <td>5</td>
1506 <td>AM6_DEV_SA2_UL0</td>
1507 <td>sa_ul_pka</td>
1508 <td>0</td>
1509 </tr>
1510 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1511 <td>97</td>
1512 <td>6</td>
1513 <td>AM6_DEV_CTRL_MMR0</td>
1514 <td>access_err</td>
1515 <td>0</td>
1516 </tr>
1517 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1518 <td>97</td>
1519 <td>7</td>
1520 <td>AM6_DEV_ELM0</td>
1521 <td>elm_porocpsinterrupt_lvl</td>
1522 <td>0</td>
1523 </tr>
1524 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1525 <td>97</td>
1526 <td>8</td>
1527 <td>AM6_DEV_GPMC0</td>
1528 <td>gpmc_sinterrupt</td>
1529 <td>0</td>
1530 </tr>
1531 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1532 <td>97</td>
1533 <td>9</td>
1534 <td>Not Connected</td>
1535 <td>&#160;</td>
1536 <td>&#160;</td>
1537 </tr>
1538 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1539 <td>97</td>
1540 <td>10</td>
1541 <td>AM6_DEV_DDRSS0</td>
1542 <td>ddrss_v2h_other_err_lvl</td>
1543 <td>0</td>
1544 </tr>
1545 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1546 <td>97</td>
1547 <td>11</td>
1548 <td>AM6_DEV_CAL0</td>
1549 <td>int_cal_l</td>
1550 <td>0</td>
1551 </tr>
1552 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1553 <td>97</td>
1554 <td>12</td>
1555 <td>Not Connected</td>
1556 <td>&#160;</td>
1557 <td>&#160;</td>
1558 </tr>
1559 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1560 <td>97</td>
1561 <td>13</td>
1562 <td>AM6_DEV_CCDEBUGSS0</td>
1563 <td>aqcmpintr_level</td>
1564 <td>0</td>
1565 </tr>
1566 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1567 <td>97</td>
1568 <td>14</td>
1569 <td>AM6_DEV_DEBUGSS0</td>
1570 <td>aqcmpintr_level</td>
1571 <td>0</td>
1572 </tr>
1573 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1574 <td>97</td>
1575 <td>15</td>
1576 <td>AM6_DEV_DEBUGSS0</td>
1577 <td>ctm_level</td>
1578 <td>0</td>
1579 </tr>
1580 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1581 <td>97</td>
1582 <td>16</td>
1583 <td>AM6_DEV_MCASP0</td>
1584 <td>xmit_intr_pend</td>
1585 <td>0</td>
1586 </tr>
1587 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1588 <td>97</td>
1589 <td>17</td>
1590 <td>AM6_DEV_MCASP0</td>
1591 <td>rec_intr_pend</td>
1592 <td>0</td>
1593 </tr>
1594 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1595 <td>97</td>
1596 <td>18</td>
1597 <td>AM6_DEV_MCASP1</td>
1598 <td>xmit_intr_pend</td>
1599 <td>0</td>
1600 </tr>
1601 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1602 <td>97</td>
1603 <td>19</td>
1604 <td>AM6_DEV_MCASP1</td>
1605 <td>rec_intr_pend</td>
1606 <td>0</td>
1607 </tr>
1608 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1609 <td>97</td>
1610 <td>20</td>
1611 <td>AM6_DEV_MCASP2</td>
1612 <td>xmit_intr_pend</td>
1613 <td>0</td>
1614 </tr>
1615 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1616 <td>97</td>
1617 <td>21</td>
1618 <td>AM6_DEV_MCASP2</td>
1619 <td>rec_intr_pend</td>
1620 <td>0</td>
1621 </tr>
1622 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1623 <td>97</td>
1624 <td>22</td>
1625 <td>Not Connected</td>
1626 <td>&#160;</td>
1627 <td>&#160;</td>
1628 </tr>
1629 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1630 <td>97</td>
1631 <td>23</td>
1632 <td>Not Connected</td>
1633 <td>&#160;</td>
1634 <td>&#160;</td>
1635 </tr>
1636 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1637 <td>97</td>
1638 <td>24</td>
1639 <td>Not Connected</td>
1640 <td>&#160;</td>
1641 <td>&#160;</td>
1642 </tr>
1643 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1644 <td>97</td>
1645 <td>25</td>
1646 <td>Not Connected</td>
1647 <td>&#160;</td>
1648 <td>&#160;</td>
1649 </tr>
1650 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1651 <td>97</td>
1652 <td>26</td>
1653 <td>Not Connected</td>
1654 <td>&#160;</td>
1655 <td>&#160;</td>
1656 </tr>
1657 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1658 <td>97</td>
1659 <td>27</td>
1660 <td>Not Connected</td>
1661 <td>&#160;</td>
1662 <td>&#160;</td>
1663 </tr>
1664 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1665 <td>97</td>
1666 <td>28</td>
1667 <td>AM6_DEV_MMCSD1</td>
1668 <td>emmcsdss_intr</td>
1669 <td>0</td>
1670 </tr>
1671 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1672 <td>97</td>
1673 <td>29</td>
1674 <td>AM6_DEV_MMCSD0</td>
1675 <td>emmcsdss_intr</td>
1676 <td>0</td>
1677 </tr>
1678 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1679 <td>97</td>
1680 <td>30</td>
1681 <td>Not Connected</td>
1682 <td>&#160;</td>
1683 <td>&#160;</td>
1684 </tr>
1685 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1686 <td>97</td>
1687 <td>31</td>
1688 <td>Not Connected</td>
1689 <td>&#160;</td>
1690 <td>&#160;</td>
1691 </tr>
1692 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1693 <td>97</td>
1694 <td>32</td>
1695 <td>AM6_DEV_PRU_ICSSG0</td>
1696 <td>pr1_host_intr_pend</td>
1697 <td>0</td>
1698 </tr>
1699 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1700 <td>97</td>
1701 <td>33</td>
1702 <td>AM6_DEV_PRU_ICSSG0</td>
1703 <td>pr1_host_intr_pend</td>
1704 <td>1</td>
1705 </tr>
1706 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1707 <td>97</td>
1708 <td>34</td>
1709 <td>AM6_DEV_PRU_ICSSG0</td>
1710 <td>pr1_host_intr_pend</td>
1711 <td>2</td>
1712 </tr>
1713 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1714 <td>97</td>
1715 <td>35</td>
1716 <td>AM6_DEV_PRU_ICSSG0</td>
1717 <td>pr1_host_intr_pend</td>
1718 <td>3</td>
1719 </tr>
1720 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1721 <td>97</td>
1722 <td>36</td>
1723 <td>AM6_DEV_PRU_ICSSG0</td>
1724 <td>pr1_host_intr_pend</td>
1725 <td>4</td>
1726 </tr>
1727 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1728 <td>97</td>
1729 <td>37</td>
1730 <td>AM6_DEV_PRU_ICSSG0</td>
1731 <td>pr1_host_intr_pend</td>
1732 <td>5</td>
1733 </tr>
1734 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1735 <td>97</td>
1736 <td>38</td>
1737 <td>AM6_DEV_PRU_ICSSG0</td>
1738 <td>pr1_host_intr_pend</td>
1739 <td>6</td>
1740 </tr>
1741 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1742 <td>97</td>
1743 <td>39</td>
1744 <td>AM6_DEV_PRU_ICSSG0</td>
1745 <td>pr1_host_intr_pend</td>
1746 <td>7</td>
1747 </tr>
1748 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1749 <td>97</td>
1750 <td>40</td>
1751 <td>AM6_DEV_PRU_ICSSG1</td>
1752 <td>pr1_host_intr_pend</td>
1753 <td>0</td>
1754 </tr>
1755 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1756 <td>97</td>
1757 <td>41</td>
1758 <td>AM6_DEV_PRU_ICSSG1</td>
1759 <td>pr1_host_intr_pend</td>
1760 <td>1</td>
1761 </tr>
1762 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1763 <td>97</td>
1764 <td>42</td>
1765 <td>AM6_DEV_PRU_ICSSG1</td>
1766 <td>pr1_host_intr_pend</td>
1767 <td>2</td>
1768 </tr>
1769 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1770 <td>97</td>
1771 <td>43</td>
1772 <td>AM6_DEV_PRU_ICSSG1</td>
1773 <td>pr1_host_intr_pend</td>
1774 <td>3</td>
1775 </tr>
1776 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1777 <td>97</td>
1778 <td>44</td>
1779 <td>AM6_DEV_PRU_ICSSG1</td>
1780 <td>pr1_host_intr_pend</td>
1781 <td>4</td>
1782 </tr>
1783 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1784 <td>97</td>
1785 <td>45</td>
1786 <td>AM6_DEV_PRU_ICSSG1</td>
1787 <td>pr1_host_intr_pend</td>
1788 <td>5</td>
1789 </tr>
1790 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1791 <td>97</td>
1792 <td>46</td>
1793 <td>AM6_DEV_PRU_ICSSG1</td>
1794 <td>pr1_host_intr_pend</td>
1795 <td>6</td>
1796 </tr>
1797 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1798 <td>97</td>
1799 <td>47</td>
1800 <td>AM6_DEV_PRU_ICSSG1</td>
1801 <td>pr1_host_intr_pend</td>
1802 <td>7</td>
1803 </tr>
1804 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1805 <td>97</td>
1806 <td>48</td>
1807 <td>AM6_DEV_PRU_ICSSG2</td>
1808 <td>pr1_host_intr_pend</td>
1809 <td>0</td>
1810 </tr>
1811 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1812 <td>97</td>
1813 <td>49</td>
1814 <td>AM6_DEV_PRU_ICSSG2</td>
1815 <td>pr1_host_intr_pend</td>
1816 <td>1</td>
1817 </tr>
1818 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1819 <td>97</td>
1820 <td>50</td>
1821 <td>AM6_DEV_PRU_ICSSG2</td>
1822 <td>pr1_host_intr_pend</td>
1823 <td>2</td>
1824 </tr>
1825 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1826 <td>97</td>
1827 <td>51</td>
1828 <td>AM6_DEV_PRU_ICSSG2</td>
1829 <td>pr1_host_intr_pend</td>
1830 <td>3</td>
1831 </tr>
1832 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1833 <td>97</td>
1834 <td>52</td>
1835 <td>AM6_DEV_PRU_ICSSG2</td>
1836 <td>pr1_host_intr_pend</td>
1837 <td>4</td>
1838 </tr>
1839 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1840 <td>97</td>
1841 <td>53</td>
1842 <td>AM6_DEV_PRU_ICSSG2</td>
1843 <td>pr1_host_intr_pend</td>
1844 <td>5</td>
1845 </tr>
1846 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1847 <td>97</td>
1848 <td>54</td>
1849 <td>AM6_DEV_PRU_ICSSG2</td>
1850 <td>pr1_host_intr_pend</td>
1851 <td>6</td>
1852 </tr>
1853 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1854 <td>97</td>
1855 <td>55</td>
1856 <td>AM6_DEV_PRU_ICSSG2</td>
1857 <td>pr1_host_intr_pend</td>
1858 <td>7</td>
1859 </tr>
1860 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1861 <td>97</td>
1862 <td>56</td>
1863 <td>AM6_DEV_GPU0</td>
1864 <td>gpu_irq</td>
1865 <td>0</td>
1866 </tr>
1867 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1868 <td>97</td>
1869 <td>57</td>
1870 <td>AM6_DEV_GPU0</td>
1871 <td>exp_intr</td>
1872 <td>0</td>
1873 </tr>
1874 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1875 <td>97</td>
1876 <td>58</td>
1877 <td>AM6_DEV_GPU0</td>
1878 <td>init_err</td>
1879 <td>0</td>
1880 </tr>
1881 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1882 <td>97</td>
1883 <td>59</td>
1884 <td>AM6_DEV_GPU0</td>
1885 <td>target_err</td>
1886 <td>0</td>
1887 </tr>
1888 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1889 <td>97</td>
1890 <td>60</td>
1891 <td>Not Connected</td>
1892 <td>&#160;</td>
1893 <td>&#160;</td>
1894 </tr>
1895 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1896 <td>97</td>
1897 <td>61</td>
1898 <td>Not Connected</td>
1899 <td>&#160;</td>
1900 <td>&#160;</td>
1901 </tr>
1902 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1903 <td>97</td>
1904 <td>62</td>
1905 <td>Not Connected</td>
1906 <td>&#160;</td>
1907 <td>&#160;</td>
1908 </tr>
1909 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1910 <td>97</td>
1911 <td>63</td>
1912 <td>Not Connected</td>
1913 <td>&#160;</td>
1914 <td>&#160;</td>
1915 </tr>
1916 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1917 <td>97</td>
1918 <td>64</td>
1919 <td>AM6_DEV_PCIE0</td>
1920 <td>pcie0_pend</td>
1921 <td>0</td>
1922 </tr>
1923 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1924 <td>97</td>
1925 <td>65</td>
1926 <td>AM6_DEV_PCIE0</td>
1927 <td>pcie1_pend</td>
1928 <td>0</td>
1929 </tr>
1930 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1931 <td>97</td>
1932 <td>66</td>
1933 <td>AM6_DEV_PCIE0</td>
1934 <td>pcie2_pend</td>
1935 <td>0</td>
1936 </tr>
1937 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1938 <td>97</td>
1939 <td>67</td>
1940 <td>AM6_DEV_PCIE0</td>
1941 <td>pcie3_pend</td>
1942 <td>0</td>
1943 </tr>
1944 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1945 <td>97</td>
1946 <td>68</td>
1947 <td>AM6_DEV_PCIE0</td>
1948 <td>pcie4_pend</td>
1949 <td>0</td>
1950 </tr>
1951 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1952 <td>97</td>
1953 <td>69</td>
1954 <td>AM6_DEV_PCIE0</td>
1955 <td>pcie5_pend</td>
1956 <td>0</td>
1957 </tr>
1958 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1959 <td>97</td>
1960 <td>70</td>
1961 <td>AM6_DEV_PCIE0</td>
1962 <td>pcie6_pend</td>
1963 <td>0</td>
1964 </tr>
1965 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1966 <td>97</td>
1967 <td>71</td>
1968 <td>AM6_DEV_PCIE0</td>
1969 <td>pcie7_pend</td>
1970 <td>0</td>
1971 </tr>
1972 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1973 <td>97</td>
1974 <td>72</td>
1975 <td>AM6_DEV_PCIE0</td>
1976 <td>pcie8_pend</td>
1977 <td>0</td>
1978 </tr>
1979 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1980 <td>97</td>
1981 <td>73</td>
1982 <td>AM6_DEV_PCIE0</td>
1983 <td>pcie9_pend</td>
1984 <td>0</td>
1985 </tr>
1986 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1987 <td>97</td>
1988 <td>74</td>
1989 <td>AM6_DEV_PCIE0</td>
1990 <td>pcie10_pend</td>
1991 <td>0</td>
1992 </tr>
1993 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
1994 <td>97</td>
1995 <td>75</td>
1996 <td>AM6_DEV_PCIE0</td>
1997 <td>pcie11_pend</td>
1998 <td>0</td>
1999 </tr>
2000 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2001 <td>97</td>
2002 <td>76</td>
2003 <td>AM6_DEV_PCIE0</td>
2004 <td>pcie12_pend</td>
2005 <td>0</td>
2006 </tr>
2007 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2008 <td>97</td>
2009 <td>77</td>
2010 <td>AM6_DEV_PCIE0</td>
2011 <td>pcie13_pend</td>
2012 <td>0</td>
2013 </tr>
2014 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2015 <td>97</td>
2016 <td>78</td>
2017 <td>AM6_DEV_PCIE0</td>
2018 <td>pcie14_pend</td>
2019 <td>0</td>
2020 </tr>
2021 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2022 <td>97</td>
2023 <td>79</td>
2024 <td>AM6_DEV_PCIE0</td>
2025 <td>pcie_cpts_pend</td>
2026 <td>0</td>
2027 </tr>
2028 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2029 <td>97</td>
2030 <td>80</td>
2031 <td>AM6_DEV_PCIE1</td>
2032 <td>pcie0_pend</td>
2033 <td>0</td>
2034 </tr>
2035 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2036 <td>97</td>
2037 <td>81</td>
2038 <td>AM6_DEV_PCIE1</td>
2039 <td>pcie1_pend</td>
2040 <td>0</td>
2041 </tr>
2042 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2043 <td>97</td>
2044 <td>82</td>
2045 <td>AM6_DEV_PCIE1</td>
2046 <td>pcie2_pend</td>
2047 <td>0</td>
2048 </tr>
2049 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2050 <td>97</td>
2051 <td>83</td>
2052 <td>AM6_DEV_PCIE1</td>
2053 <td>pcie3_pend</td>
2054 <td>0</td>
2055 </tr>
2056 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2057 <td>97</td>
2058 <td>84</td>
2059 <td>AM6_DEV_PCIE1</td>
2060 <td>pcie4_pend</td>
2061 <td>0</td>
2062 </tr>
2063 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2064 <td>97</td>
2065 <td>85</td>
2066 <td>AM6_DEV_PCIE1</td>
2067 <td>pcie5_pend</td>
2068 <td>0</td>
2069 </tr>
2070 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2071 <td>97</td>
2072 <td>86</td>
2073 <td>AM6_DEV_PCIE1</td>
2074 <td>pcie6_pend</td>
2075 <td>0</td>
2076 </tr>
2077 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2078 <td>97</td>
2079 <td>87</td>
2080 <td>AM6_DEV_PCIE1</td>
2081 <td>pcie7_pend</td>
2082 <td>0</td>
2083 </tr>
2084 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2085 <td>97</td>
2086 <td>88</td>
2087 <td>AM6_DEV_PCIE1</td>
2088 <td>pcie8_pend</td>
2089 <td>0</td>
2090 </tr>
2091 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2092 <td>97</td>
2093 <td>89</td>
2094 <td>AM6_DEV_PCIE1</td>
2095 <td>pcie9_pend</td>
2096 <td>0</td>
2097 </tr>
2098 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2099 <td>97</td>
2100 <td>90</td>
2101 <td>AM6_DEV_PCIE1</td>
2102 <td>pcie10_pend</td>
2103 <td>0</td>
2104 </tr>
2105 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2106 <td>97</td>
2107 <td>91</td>
2108 <td>AM6_DEV_PCIE1</td>
2109 <td>pcie11_pend</td>
2110 <td>0</td>
2111 </tr>
2112 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2113 <td>97</td>
2114 <td>92</td>
2115 <td>AM6_DEV_PCIE1</td>
2116 <td>pcie12_pend</td>
2117 <td>0</td>
2118 </tr>
2119 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2120 <td>97</td>
2121 <td>93</td>
2122 <td>AM6_DEV_PCIE1</td>
2123 <td>pcie13_pend</td>
2124 <td>0</td>
2125 </tr>
2126 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2127 <td>97</td>
2128 <td>94</td>
2129 <td>AM6_DEV_PCIE1</td>
2130 <td>pcie14_pend</td>
2131 <td>0</td>
2132 </tr>
2133 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2134 <td>97</td>
2135 <td>95</td>
2136 <td>AM6_DEV_PCIE1</td>
2137 <td>pcie_cpts_pend</td>
2138 <td>0</td>
2139 </tr>
2140 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2141 <td>97</td>
2142 <td>96</td>
2143 <td>AM6_DEV_MCSPI0</td>
2144 <td>intr_spi</td>
2145 <td>0</td>
2146 </tr>
2147 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2148 <td>97</td>
2149 <td>97</td>
2150 <td>AM6_DEV_MCSPI1</td>
2151 <td>intr_spi</td>
2152 <td>0</td>
2153 </tr>
2154 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2155 <td>97</td>
2156 <td>98</td>
2157 <td>AM6_DEV_MCSPI2</td>
2158 <td>intr_spi</td>
2159 <td>0</td>
2160 </tr>
2161 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2162 <td>97</td>
2163 <td>99</td>
2164 <td>AM6_DEV_MCSPI3</td>
2165 <td>intr_spi</td>
2166 <td>0</td>
2167 </tr>
2168 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2169 <td>97</td>
2170 <td>100</td>
2171 <td>AM6_DEV_I2C0</td>
2172 <td>pointrpend</td>
2173 <td>0</td>
2174 </tr>
2175 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2176 <td>97</td>
2177 <td>101</td>
2178 <td>AM6_DEV_I2C1</td>
2179 <td>pointrpend</td>
2180 <td>0</td>
2181 </tr>
2182 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2183 <td>97</td>
2184 <td>102</td>
2185 <td>AM6_DEV_I2C2</td>
2186 <td>pointrpend</td>
2187 <td>0</td>
2188 </tr>
2189 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2190 <td>97</td>
2191 <td>103</td>
2192 <td>AM6_DEV_I2C3</td>
2193 <td>pointrpend</td>
2194 <td>0</td>
2195 </tr>
2196 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2197 <td>97</td>
2198 <td>104</td>
2199 <td>AM6_DEV_UART0</td>
2200 <td>usart_irq</td>
2201 <td>0</td>
2202 </tr>
2203 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2204 <td>97</td>
2205 <td>105</td>
2206 <td>AM6_DEV_UART1</td>
2207 <td>usart_irq</td>
2208 <td>0</td>
2209 </tr>
2210 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2211 <td>97</td>
2212 <td>106</td>
2213 <td>AM6_DEV_UART2</td>
2214 <td>usart_irq</td>
2215 <td>0</td>
2216 </tr>
2217 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2218 <td>97</td>
2219 <td>107</td>
2220 <td>Not Connected</td>
2221 <td>&#160;</td>
2222 <td>&#160;</td>
2223 </tr>
2224 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2225 <td>97</td>
2226 <td>108</td>
2227 <td>AM6_DEV_TIMER0</td>
2228 <td>intr_pend</td>
2229 <td>0</td>
2230 </tr>
2231 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2232 <td>97</td>
2233 <td>109</td>
2234 <td>AM6_DEV_TIMER1</td>
2235 <td>intr_pend</td>
2236 <td>0</td>
2237 </tr>
2238 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2239 <td>97</td>
2240 <td>110</td>
2241 <td>AM6_DEV_TIMER2</td>
2242 <td>intr_pend</td>
2243 <td>0</td>
2244 </tr>
2245 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2246 <td>97</td>
2247 <td>111</td>
2248 <td>AM6_DEV_TIMER3</td>
2249 <td>intr_pend</td>
2250 <td>0</td>
2251 </tr>
2252 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2253 <td>97</td>
2254 <td>112</td>
2255 <td>AM6_DEV_TIMER4</td>
2256 <td>intr_pend</td>
2257 <td>0</td>
2258 </tr>
2259 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2260 <td>97</td>
2261 <td>113</td>
2262 <td>AM6_DEV_TIMER5</td>
2263 <td>intr_pend</td>
2264 <td>0</td>
2265 </tr>
2266 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2267 <td>97</td>
2268 <td>114</td>
2269 <td>AM6_DEV_TIMER6</td>
2270 <td>intr_pend</td>
2271 <td>0</td>
2272 </tr>
2273 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2274 <td>97</td>
2275 <td>115</td>
2276 <td>AM6_DEV_TIMER7</td>
2277 <td>intr_pend</td>
2278 <td>0</td>
2279 </tr>
2280 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2281 <td>97</td>
2282 <td>116</td>
2283 <td>AM6_DEV_TIMER8</td>
2284 <td>intr_pend</td>
2285 <td>0</td>
2286 </tr>
2287 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2288 <td>97</td>
2289 <td>117</td>
2290 <td>AM6_DEV_TIMER9</td>
2291 <td>intr_pend</td>
2292 <td>0</td>
2293 </tr>
2294 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2295 <td>97</td>
2296 <td>118</td>
2297 <td>AM6_DEV_TIMER10</td>
2298 <td>intr_pend</td>
2299 <td>0</td>
2300 </tr>
2301 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2302 <td>97</td>
2303 <td>119</td>
2304 <td>AM6_DEV_TIMER11</td>
2305 <td>intr_pend</td>
2306 <td>0</td>
2307 </tr>
2308 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2309 <td>97</td>
2310 <td>120</td>
2311 <td>AM6_DEV_DCC0</td>
2312 <td>intr_done_level</td>
2313 <td>0</td>
2314 </tr>
2315 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2316 <td>97</td>
2317 <td>121</td>
2318 <td>AM6_DEV_DCC1</td>
2319 <td>intr_done_level</td>
2320 <td>0</td>
2321 </tr>
2322 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2323 <td>97</td>
2324 <td>122</td>
2325 <td>AM6_DEV_DCC2</td>
2326 <td>intr_done_level</td>
2327 <td>0</td>
2328 </tr>
2329 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2330 <td>97</td>
2331 <td>123</td>
2332 <td>AM6_DEV_DCC3</td>
2333 <td>intr_done_level</td>
2334 <td>0</td>
2335 </tr>
2336 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2337 <td>97</td>
2338 <td>124</td>
2339 <td>AM6_DEV_DCC4</td>
2340 <td>intr_done_level</td>
2341 <td>0</td>
2342 </tr>
2343 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2344 <td>97</td>
2345 <td>125</td>
2346 <td>AM6_DEV_DCC5</td>
2347 <td>intr_done_level</td>
2348 <td>0</td>
2349 </tr>
2350 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2351 <td>97</td>
2352 <td>126</td>
2353 <td>AM6_DEV_DCC6</td>
2354 <td>intr_done_level</td>
2355 <td>0</td>
2356 </tr>
2357 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2358 <td>97</td>
2359 <td>127</td>
2360 <td>AM6_DEV_DCC7</td>
2361 <td>intr_done_level</td>
2362 <td>0</td>
2363 </tr>
2364 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2365 <td>97</td>
2366 <td>128</td>
2367 <td>AM6_DEV_USB3SS0</td>
2368 <td>otg_lvl</td>
2369 <td>0</td>
2370 </tr>
2371 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2372 <td>97</td>
2373 <td>129</td>
2374 <td>AM6_DEV_USB3SS0</td>
2375 <td>misc_lvl</td>
2376 <td>0</td>
2377 </tr>
2378 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2379 <td>97</td>
2380 <td>130</td>
2381 <td>AM6_DEV_USB3SS0</td>
2382 <td>bc_lvl</td>
2383 <td>0</td>
2384 </tr>
2385 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2386 <td>97</td>
2387 <td>131</td>
2388 <td>AM6_DEV_USB3SS0</td>
2389 <td>pme_gen_lvl</td>
2390 <td>0</td>
2391 </tr>
2392 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2393 <td>97</td>
2394 <td>132</td>
2395 <td>AM6_DEV_USB3SS0</td>
2396 <td>i00_lvl</td>
2397 <td>0</td>
2398 </tr>
2399 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2400 <td>97</td>
2401 <td>133</td>
2402 <td>AM6_DEV_USB3SS0</td>
2403 <td>i01_lvl</td>
2404 <td>0</td>
2405 </tr>
2406 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2407 <td>97</td>
2408 <td>134</td>
2409 <td>AM6_DEV_USB3SS0</td>
2410 <td>i02_lvl</td>
2411 <td>0</td>
2412 </tr>
2413 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2414 <td>97</td>
2415 <td>135</td>
2416 <td>AM6_DEV_USB3SS0</td>
2417 <td>i03_lvl</td>
2418 <td>0</td>
2419 </tr>
2420 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2421 <td>97</td>
2422 <td>136</td>
2423 <td>AM6_DEV_USB3SS0</td>
2424 <td>i04_lvl</td>
2425 <td>0</td>
2426 </tr>
2427 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2428 <td>97</td>
2429 <td>137</td>
2430 <td>AM6_DEV_USB3SS0</td>
2431 <td>i05_lvl</td>
2432 <td>0</td>
2433 </tr>
2434 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2435 <td>97</td>
2436 <td>138</td>
2437 <td>AM6_DEV_USB3SS0</td>
2438 <td>i06_lvl</td>
2439 <td>0</td>
2440 </tr>
2441 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2442 <td>97</td>
2443 <td>139</td>
2444 <td>AM6_DEV_USB3SS0</td>
2445 <td>i07_lvl</td>
2446 <td>0</td>
2447 </tr>
2448 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2449 <td>97</td>
2450 <td>140</td>
2451 <td>AM6_DEV_USB3SS0</td>
2452 <td>i08_lvl</td>
2453 <td>0</td>
2454 </tr>
2455 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2456 <td>97</td>
2457 <td>141</td>
2458 <td>AM6_DEV_USB3SS0</td>
2459 <td>i09_lvl</td>
2460 <td>0</td>
2461 </tr>
2462 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2463 <td>97</td>
2464 <td>142</td>
2465 <td>AM6_DEV_USB3SS0</td>
2466 <td>i10_lvl</td>
2467 <td>0</td>
2468 </tr>
2469 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2470 <td>97</td>
2471 <td>143</td>
2472 <td>AM6_DEV_USB3SS0</td>
2473 <td>i11_lvl</td>
2474 <td>0</td>
2475 </tr>
2476 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2477 <td>97</td>
2478 <td>144</td>
2479 <td>AM6_DEV_USB3SS0</td>
2480 <td>i12_lvl</td>
2481 <td>0</td>
2482 </tr>
2483 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2484 <td>97</td>
2485 <td>145</td>
2486 <td>AM6_DEV_USB3SS0</td>
2487 <td>i13_lvl</td>
2488 <td>0</td>
2489 </tr>
2490 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2491 <td>97</td>
2492 <td>146</td>
2493 <td>AM6_DEV_USB3SS0</td>
2494 <td>i14_lvl</td>
2495 <td>0</td>
2496 </tr>
2497 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2498 <td>97</td>
2499 <td>147</td>
2500 <td>AM6_DEV_USB3SS0</td>
2501 <td>i15_lvl</td>
2502 <td>0</td>
2503 </tr>
2504 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2505 <td>97</td>
2506 <td>148</td>
2507 <td>AM6_DEV_USB3SS1</td>
2508 <td>otg_lvl</td>
2509 <td>0</td>
2510 </tr>
2511 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2512 <td>97</td>
2513 <td>149</td>
2514 <td>AM6_DEV_USB3SS1</td>
2515 <td>misc_lvl</td>
2516 <td>0</td>
2517 </tr>
2518 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2519 <td>97</td>
2520 <td>150</td>
2521 <td>AM6_DEV_USB3SS1</td>
2522 <td>bc_lvl</td>
2523 <td>0</td>
2524 </tr>
2525 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2526 <td>97</td>
2527 <td>151</td>
2528 <td>AM6_DEV_USB3SS1</td>
2529 <td>pme_gen_lvl</td>
2530 <td>0</td>
2531 </tr>
2532 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2533 <td>97</td>
2534 <td>152</td>
2535 <td>AM6_DEV_USB3SS1</td>
2536 <td>i00_lvl</td>
2537 <td>0</td>
2538 </tr>
2539 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2540 <td>97</td>
2541 <td>153</td>
2542 <td>AM6_DEV_USB3SS1</td>
2543 <td>i01_lvl</td>
2544 <td>0</td>
2545 </tr>
2546 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2547 <td>97</td>
2548 <td>154</td>
2549 <td>AM6_DEV_USB3SS1</td>
2550 <td>i02_lvl</td>
2551 <td>0</td>
2552 </tr>
2553 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2554 <td>97</td>
2555 <td>155</td>
2556 <td>AM6_DEV_USB3SS1</td>
2557 <td>i03_lvl</td>
2558 <td>0</td>
2559 </tr>
2560 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2561 <td>97</td>
2562 <td>156</td>
2563 <td>AM6_DEV_USB3SS1</td>
2564 <td>i04_lvl</td>
2565 <td>0</td>
2566 </tr>
2567 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2568 <td>97</td>
2569 <td>157</td>
2570 <td>AM6_DEV_USB3SS1</td>
2571 <td>i05_lvl</td>
2572 <td>0</td>
2573 </tr>
2574 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2575 <td>97</td>
2576 <td>158</td>
2577 <td>AM6_DEV_USB3SS1</td>
2578 <td>i06_lvl</td>
2579 <td>0</td>
2580 </tr>
2581 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2582 <td>97</td>
2583 <td>159</td>
2584 <td>AM6_DEV_USB3SS1</td>
2585 <td>i07_lvl</td>
2586 <td>0</td>
2587 </tr>
2588 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2589 <td>97</td>
2590 <td>160</td>
2591 <td>AM6_DEV_USB3SS1</td>
2592 <td>i08_lvl</td>
2593 <td>0</td>
2594 </tr>
2595 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2596 <td>97</td>
2597 <td>161</td>
2598 <td>AM6_DEV_USB3SS1</td>
2599 <td>i09_lvl</td>
2600 <td>0</td>
2601 </tr>
2602 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2603 <td>97</td>
2604 <td>162</td>
2605 <td>AM6_DEV_USB3SS1</td>
2606 <td>i10_lvl</td>
2607 <td>0</td>
2608 </tr>
2609 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2610 <td>97</td>
2611 <td>163</td>
2612 <td>AM6_DEV_USB3SS1</td>
2613 <td>i11_lvl</td>
2614 <td>0</td>
2615 </tr>
2616 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2617 <td>97</td>
2618 <td>164</td>
2619 <td>AM6_DEV_USB3SS1</td>
2620 <td>i12_lvl</td>
2621 <td>0</td>
2622 </tr>
2623 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2624 <td>97</td>
2625 <td>165</td>
2626 <td>AM6_DEV_USB3SS1</td>
2627 <td>i13_lvl</td>
2628 <td>0</td>
2629 </tr>
2630 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2631 <td>97</td>
2632 <td>166</td>
2633 <td>AM6_DEV_USB3SS1</td>
2634 <td>i14_lvl</td>
2635 <td>0</td>
2636 </tr>
2637 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2638 <td>97</td>
2639 <td>167</td>
2640 <td>AM6_DEV_USB3SS1</td>
2641 <td>i15_lvl</td>
2642 <td>0</td>
2643 </tr>
2644 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2645 <td>97</td>
2646 <td>168</td>
2647 <td>Not Connected</td>
2648 <td>&#160;</td>
2649 <td>&#160;</td>
2650 </tr>
2651 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2652 <td>97</td>
2653 <td>169</td>
2654 <td>Not Connected</td>
2655 <td>&#160;</td>
2656 <td>&#160;</td>
2657 </tr>
2658 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2659 <td>97</td>
2660 <td>170</td>
2661 <td>Not Connected</td>
2662 <td>&#160;</td>
2663 <td>&#160;</td>
2664 </tr>
2665 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2666 <td>97</td>
2667 <td>171</td>
2668 <td>Not Connected</td>
2669 <td>&#160;</td>
2670 <td>&#160;</td>
2671 </tr>
2672 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2673 <td>97</td>
2674 <td>172</td>
2675 <td>AM6_DEV_CBASS0</td>
2676 <td>LPSC_per_common_err_intr</td>
2677 <td>0</td>
2678 </tr>
2679 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2680 <td>97</td>
2681 <td>173</td>
2682 <td>AM6_DEV_CBASS_DEBUG0</td>
2683 <td>LPSC_main_debug_err_intr</td>
2684 <td>0</td>
2685 </tr>
2686 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2687 <td>97</td>
2688 <td>174</td>
2689 <td>AM6_DEV_CBASS_FW0</td>
2690 <td>LPSC_main_infra_err_intr</td>
2691 <td>0</td>
2692 </tr>
2693 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2694 <td>97</td>
2695 <td>175</td>
2696 <td>AM6_DEV_CBASS_INFRA0</td>
2697 <td>LPSC_main_infra_err_intr</td>
2698 <td>0</td>
2699 </tr>
2700 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2701 <td>97</td>
2702 <td>176</td>
2703 <td>Not Connected</td>
2704 <td>&#160;</td>
2705 <td>&#160;</td>
2706 </tr>
2707 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2708 <td>97</td>
2709 <td>177</td>
2710 <td>Not Connected</td>
2711 <td>&#160;</td>
2712 <td>&#160;</td>
2713 </tr>
2714 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2715 <td>97</td>
2716 <td>178</td>
2717 <td>Not Connected</td>
2718 <td>&#160;</td>
2719 <td>&#160;</td>
2720 </tr>
2721 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2722 <td>97</td>
2723 <td>179</td>
2724 <td>Not Connected</td>
2725 <td>&#160;</td>
2726 <td>&#160;</td>
2727 </tr>
2728 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2729 <td>97</td>
2730 <td>180</td>
2731 <td>Not Connected</td>
2732 <td>&#160;</td>
2733 <td>&#160;</td>
2734 </tr>
2735 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2736 <td>97</td>
2737 <td>181</td>
2738 <td>Not Connected</td>
2739 <td>&#160;</td>
2740 <td>&#160;</td>
2741 </tr>
2742 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2743 <td>97</td>
2744 <td>182</td>
2745 <td>Not Connected</td>
2746 <td>&#160;</td>
2747 <td>&#160;</td>
2748 </tr>
2749 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2750 <td>97</td>
2751 <td>183</td>
2752 <td>Not Connected</td>
2753 <td>&#160;</td>
2754 <td>&#160;</td>
2755 </tr>
2756 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2757 <td>97</td>
2758 <td>184</td>
2759 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
2760 <td>outl_intr</td>
2761 <td>120</td>
2762 </tr>
2763 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2764 <td>97</td>
2765 <td>185</td>
2766 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
2767 <td>outl_intr</td>
2768 <td>121</td>
2769 </tr>
2770 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2771 <td>97</td>
2772 <td>186</td>
2773 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
2774 <td>outl_intr</td>
2775 <td>122</td>
2776 </tr>
2777 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2778 <td>97</td>
2779 <td>187</td>
2780 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
2781 <td>outl_intr</td>
2782 <td>123</td>
2783 </tr>
2784 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2785 <td>97</td>
2786 <td>188</td>
2787 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
2788 <td>outl_intr</td>
2789 <td>124</td>
2790 </tr>
2791 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2792 <td>97</td>
2793 <td>189</td>
2794 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
2795 <td>outl_intr</td>
2796 <td>125</td>
2797 </tr>
2798 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2799 <td>97</td>
2800 <td>190</td>
2801 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
2802 <td>outl_intr</td>
2803 <td>126</td>
2804 </tr>
2805 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2806 <td>97</td>
2807 <td>191</td>
2808 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
2809 <td>outl_intr</td>
2810 <td>127</td>
2811 </tr>
2812 </tbody>
2813 </table>
2814 </div>
2815 <div class="section" id="main2mcu-lvl-intrtr0-interrupt-router-output-destinations">
2816 <span id="pub-soc-am65x-sr2-main2mcu-lvl-intrtr0-output-src-list"></span><h2>MAIN2MCU_LVL_INTRTR0 Interrupt Router Output Destinations<a class="headerlink" href="#main2mcu-lvl-intrtr0-interrupt-router-output-destinations" title="Permalink to this headline">¶</a></h2>
2817 <div class="admonition warning">
2818 <p class="first admonition-title">Warning</p>
2819 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
2820 host within the RM Board Configuration resource assignment array.  The RM
2821 Board Configuration is rejected if an overlap with a reserved resource is
2822 detected.</p>
2823 </div>
2824 <table border="1" class="docutils">
2825 <colgroup>
2826 <col width="22%" />
2827 <col width="12%" />
2828 <col width="14%" />
2829 <col width="18%" />
2830 <col width="18%" />
2831 <col width="15%" />
2832 </colgroup>
2833 <thead valign="bottom">
2834 <tr class="row-odd"><th class="head">IR Name</th>
2835 <th class="head">IR Device ID</th>
2836 <th class="head">IR Output Index</th>
2837 <th class="head">Destination Name</th>
2838 <th class="head">Destination Interface</th>
2839 <th class="head">Destination Index</th>
2840 </tr>
2841 </thead>
2842 <tbody valign="top">
2843 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2844 <td>97</td>
2845 <td>0</td>
2846 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
2847 <td>intr</td>
2848 <td>160</td>
2849 </tr>
2850 <tr class="row-odd"><td>&#160;</td>
2851 <td>&#160;</td>
2852 <td>&#160;</td>
2853 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
2854 <td>intr</td>
2855 <td>160</td>
2856 </tr>
2857 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2858 <td>97</td>
2859 <td>1</td>
2860 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
2861 <td>intr</td>
2862 <td>161</td>
2863 </tr>
2864 <tr class="row-odd"><td>&#160;</td>
2865 <td>&#160;</td>
2866 <td>&#160;</td>
2867 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
2868 <td>intr</td>
2869 <td>161</td>
2870 </tr>
2871 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2872 <td>97</td>
2873 <td>2</td>
2874 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
2875 <td>intr</td>
2876 <td>162</td>
2877 </tr>
2878 <tr class="row-odd"><td>&#160;</td>
2879 <td>&#160;</td>
2880 <td>&#160;</td>
2881 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
2882 <td>intr</td>
2883 <td>162</td>
2884 </tr>
2885 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2886 <td>97</td>
2887 <td>3</td>
2888 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
2889 <td>intr</td>
2890 <td>163</td>
2891 </tr>
2892 <tr class="row-odd"><td>&#160;</td>
2893 <td>&#160;</td>
2894 <td>&#160;</td>
2895 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
2896 <td>intr</td>
2897 <td>163</td>
2898 </tr>
2899 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2900 <td>97</td>
2901 <td>4</td>
2902 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
2903 <td>intr</td>
2904 <td>164</td>
2905 </tr>
2906 <tr class="row-odd"><td>&#160;</td>
2907 <td>&#160;</td>
2908 <td>&#160;</td>
2909 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
2910 <td>intr</td>
2911 <td>164</td>
2912 </tr>
2913 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2914 <td>97</td>
2915 <td>5</td>
2916 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
2917 <td>intr</td>
2918 <td>165</td>
2919 </tr>
2920 <tr class="row-odd"><td>&#160;</td>
2921 <td>&#160;</td>
2922 <td>&#160;</td>
2923 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
2924 <td>intr</td>
2925 <td>165</td>
2926 </tr>
2927 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2928 <td>97</td>
2929 <td>6</td>
2930 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
2931 <td>intr</td>
2932 <td>166</td>
2933 </tr>
2934 <tr class="row-odd"><td>&#160;</td>
2935 <td>&#160;</td>
2936 <td>&#160;</td>
2937 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
2938 <td>intr</td>
2939 <td>166</td>
2940 </tr>
2941 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2942 <td>97</td>
2943 <td>7</td>
2944 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
2945 <td>intr</td>
2946 <td>167</td>
2947 </tr>
2948 <tr class="row-odd"><td>&#160;</td>
2949 <td>&#160;</td>
2950 <td>&#160;</td>
2951 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
2952 <td>intr</td>
2953 <td>167</td>
2954 </tr>
2955 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2956 <td>97</td>
2957 <td>8</td>
2958 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
2959 <td>intr</td>
2960 <td>168</td>
2961 </tr>
2962 <tr class="row-odd"><td>&#160;</td>
2963 <td>&#160;</td>
2964 <td>&#160;</td>
2965 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
2966 <td>intr</td>
2967 <td>168</td>
2968 </tr>
2969 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2970 <td>97</td>
2971 <td>9</td>
2972 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
2973 <td>intr</td>
2974 <td>169</td>
2975 </tr>
2976 <tr class="row-odd"><td>&#160;</td>
2977 <td>&#160;</td>
2978 <td>&#160;</td>
2979 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
2980 <td>intr</td>
2981 <td>169</td>
2982 </tr>
2983 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2984 <td>97</td>
2985 <td>10</td>
2986 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
2987 <td>intr</td>
2988 <td>170</td>
2989 </tr>
2990 <tr class="row-odd"><td>&#160;</td>
2991 <td>&#160;</td>
2992 <td>&#160;</td>
2993 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
2994 <td>intr</td>
2995 <td>170</td>
2996 </tr>
2997 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
2998 <td>97</td>
2999 <td>11</td>
3000 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3001 <td>intr</td>
3002 <td>171</td>
3003 </tr>
3004 <tr class="row-odd"><td>&#160;</td>
3005 <td>&#160;</td>
3006 <td>&#160;</td>
3007 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3008 <td>intr</td>
3009 <td>171</td>
3010 </tr>
3011 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3012 <td>97</td>
3013 <td>12</td>
3014 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3015 <td>intr</td>
3016 <td>172</td>
3017 </tr>
3018 <tr class="row-odd"><td>&#160;</td>
3019 <td>&#160;</td>
3020 <td>&#160;</td>
3021 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3022 <td>intr</td>
3023 <td>172</td>
3024 </tr>
3025 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3026 <td>97</td>
3027 <td>13</td>
3028 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3029 <td>intr</td>
3030 <td>173</td>
3031 </tr>
3032 <tr class="row-odd"><td>&#160;</td>
3033 <td>&#160;</td>
3034 <td>&#160;</td>
3035 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3036 <td>intr</td>
3037 <td>173</td>
3038 </tr>
3039 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3040 <td>97</td>
3041 <td>14</td>
3042 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3043 <td>intr</td>
3044 <td>174</td>
3045 </tr>
3046 <tr class="row-odd"><td>&#160;</td>
3047 <td>&#160;</td>
3048 <td>&#160;</td>
3049 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3050 <td>intr</td>
3051 <td>174</td>
3052 </tr>
3053 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3054 <td>97</td>
3055 <td>15</td>
3056 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3057 <td>intr</td>
3058 <td>175</td>
3059 </tr>
3060 <tr class="row-odd"><td>&#160;</td>
3061 <td>&#160;</td>
3062 <td>&#160;</td>
3063 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3064 <td>intr</td>
3065 <td>175</td>
3066 </tr>
3067 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3068 <td>97</td>
3069 <td>16</td>
3070 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3071 <td>intr</td>
3072 <td>176</td>
3073 </tr>
3074 <tr class="row-odd"><td>&#160;</td>
3075 <td>&#160;</td>
3076 <td>&#160;</td>
3077 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3078 <td>intr</td>
3079 <td>176</td>
3080 </tr>
3081 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3082 <td>97</td>
3083 <td>17</td>
3084 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3085 <td>intr</td>
3086 <td>177</td>
3087 </tr>
3088 <tr class="row-odd"><td>&#160;</td>
3089 <td>&#160;</td>
3090 <td>&#160;</td>
3091 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3092 <td>intr</td>
3093 <td>177</td>
3094 </tr>
3095 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3096 <td>97</td>
3097 <td>18</td>
3098 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3099 <td>intr</td>
3100 <td>178</td>
3101 </tr>
3102 <tr class="row-odd"><td>&#160;</td>
3103 <td>&#160;</td>
3104 <td>&#160;</td>
3105 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3106 <td>intr</td>
3107 <td>178</td>
3108 </tr>
3109 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3110 <td>97</td>
3111 <td>19</td>
3112 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3113 <td>intr</td>
3114 <td>179</td>
3115 </tr>
3116 <tr class="row-odd"><td>&#160;</td>
3117 <td>&#160;</td>
3118 <td>&#160;</td>
3119 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3120 <td>intr</td>
3121 <td>179</td>
3122 </tr>
3123 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3124 <td>97</td>
3125 <td>20</td>
3126 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3127 <td>intr</td>
3128 <td>180</td>
3129 </tr>
3130 <tr class="row-odd"><td>&#160;</td>
3131 <td>&#160;</td>
3132 <td>&#160;</td>
3133 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3134 <td>intr</td>
3135 <td>180</td>
3136 </tr>
3137 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3138 <td>97</td>
3139 <td>21</td>
3140 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3141 <td>intr</td>
3142 <td>181</td>
3143 </tr>
3144 <tr class="row-odd"><td>&#160;</td>
3145 <td>&#160;</td>
3146 <td>&#160;</td>
3147 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3148 <td>intr</td>
3149 <td>181</td>
3150 </tr>
3151 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3152 <td>97</td>
3153 <td>22</td>
3154 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3155 <td>intr</td>
3156 <td>182</td>
3157 </tr>
3158 <tr class="row-odd"><td>&#160;</td>
3159 <td>&#160;</td>
3160 <td>&#160;</td>
3161 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3162 <td>intr</td>
3163 <td>182</td>
3164 </tr>
3165 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3166 <td>97</td>
3167 <td>23</td>
3168 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3169 <td>intr</td>
3170 <td>183</td>
3171 </tr>
3172 <tr class="row-odd"><td>&#160;</td>
3173 <td>&#160;</td>
3174 <td>&#160;</td>
3175 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3176 <td>intr</td>
3177 <td>183</td>
3178 </tr>
3179 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3180 <td>97</td>
3181 <td>24</td>
3182 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3183 <td>intr</td>
3184 <td>184</td>
3185 </tr>
3186 <tr class="row-odd"><td>&#160;</td>
3187 <td>&#160;</td>
3188 <td>&#160;</td>
3189 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3190 <td>intr</td>
3191 <td>184</td>
3192 </tr>
3193 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3194 <td>97</td>
3195 <td>25</td>
3196 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3197 <td>intr</td>
3198 <td>185</td>
3199 </tr>
3200 <tr class="row-odd"><td>&#160;</td>
3201 <td>&#160;</td>
3202 <td>&#160;</td>
3203 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3204 <td>intr</td>
3205 <td>185</td>
3206 </tr>
3207 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3208 <td>97</td>
3209 <td>26</td>
3210 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3211 <td>intr</td>
3212 <td>186</td>
3213 </tr>
3214 <tr class="row-odd"><td>&#160;</td>
3215 <td>&#160;</td>
3216 <td>&#160;</td>
3217 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3218 <td>intr</td>
3219 <td>186</td>
3220 </tr>
3221 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3222 <td>97</td>
3223 <td>27</td>
3224 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3225 <td>intr</td>
3226 <td>187</td>
3227 </tr>
3228 <tr class="row-odd"><td>&#160;</td>
3229 <td>&#160;</td>
3230 <td>&#160;</td>
3231 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3232 <td>intr</td>
3233 <td>187</td>
3234 </tr>
3235 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3236 <td>97</td>
3237 <td>28</td>
3238 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3239 <td>intr</td>
3240 <td>188</td>
3241 </tr>
3242 <tr class="row-odd"><td>&#160;</td>
3243 <td>&#160;</td>
3244 <td>&#160;</td>
3245 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3246 <td>intr</td>
3247 <td>188</td>
3248 </tr>
3249 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3250 <td>97</td>
3251 <td>29</td>
3252 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3253 <td>intr</td>
3254 <td>189</td>
3255 </tr>
3256 <tr class="row-odd"><td>&#160;</td>
3257 <td>&#160;</td>
3258 <td>&#160;</td>
3259 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3260 <td>intr</td>
3261 <td>189</td>
3262 </tr>
3263 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3264 <td>97</td>
3265 <td>30</td>
3266 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3267 <td>intr</td>
3268 <td>190</td>
3269 </tr>
3270 <tr class="row-odd"><td>&#160;</td>
3271 <td>&#160;</td>
3272 <td>&#160;</td>
3273 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3274 <td>intr</td>
3275 <td>190</td>
3276 </tr>
3277 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3278 <td>97</td>
3279 <td>31</td>
3280 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3281 <td>intr</td>
3282 <td>191</td>
3283 </tr>
3284 <tr class="row-odd"><td>&#160;</td>
3285 <td>&#160;</td>
3286 <td>&#160;</td>
3287 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3288 <td>intr</td>
3289 <td>191</td>
3290 </tr>
3291 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3292 <td>97</td>
3293 <td>32</td>
3294 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3295 <td>intr</td>
3296 <td>192</td>
3297 </tr>
3298 <tr class="row-odd"><td>&#160;</td>
3299 <td>&#160;</td>
3300 <td>&#160;</td>
3301 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3302 <td>intr</td>
3303 <td>192</td>
3304 </tr>
3305 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3306 <td>97</td>
3307 <td>33</td>
3308 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3309 <td>intr</td>
3310 <td>193</td>
3311 </tr>
3312 <tr class="row-odd"><td>&#160;</td>
3313 <td>&#160;</td>
3314 <td>&#160;</td>
3315 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3316 <td>intr</td>
3317 <td>193</td>
3318 </tr>
3319 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3320 <td>97</td>
3321 <td>34</td>
3322 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3323 <td>intr</td>
3324 <td>194</td>
3325 </tr>
3326 <tr class="row-odd"><td>&#160;</td>
3327 <td>&#160;</td>
3328 <td>&#160;</td>
3329 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3330 <td>intr</td>
3331 <td>194</td>
3332 </tr>
3333 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3334 <td>97</td>
3335 <td>35</td>
3336 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3337 <td>intr</td>
3338 <td>195</td>
3339 </tr>
3340 <tr class="row-odd"><td>&#160;</td>
3341 <td>&#160;</td>
3342 <td>&#160;</td>
3343 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3344 <td>intr</td>
3345 <td>195</td>
3346 </tr>
3347 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3348 <td>97</td>
3349 <td>36</td>
3350 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3351 <td>intr</td>
3352 <td>196</td>
3353 </tr>
3354 <tr class="row-odd"><td>&#160;</td>
3355 <td>&#160;</td>
3356 <td>&#160;</td>
3357 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3358 <td>intr</td>
3359 <td>196</td>
3360 </tr>
3361 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3362 <td>97</td>
3363 <td>37</td>
3364 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3365 <td>intr</td>
3366 <td>197</td>
3367 </tr>
3368 <tr class="row-odd"><td>&#160;</td>
3369 <td>&#160;</td>
3370 <td>&#160;</td>
3371 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3372 <td>intr</td>
3373 <td>197</td>
3374 </tr>
3375 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3376 <td>97</td>
3377 <td>38</td>
3378 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3379 <td>intr</td>
3380 <td>198</td>
3381 </tr>
3382 <tr class="row-odd"><td>&#160;</td>
3383 <td>&#160;</td>
3384 <td>&#160;</td>
3385 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3386 <td>intr</td>
3387 <td>198</td>
3388 </tr>
3389 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3390 <td>97</td>
3391 <td>39</td>
3392 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3393 <td>intr</td>
3394 <td>199</td>
3395 </tr>
3396 <tr class="row-odd"><td>&#160;</td>
3397 <td>&#160;</td>
3398 <td>&#160;</td>
3399 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3400 <td>intr</td>
3401 <td>199</td>
3402 </tr>
3403 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3404 <td>97</td>
3405 <td>40</td>
3406 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3407 <td>intr</td>
3408 <td>200</td>
3409 </tr>
3410 <tr class="row-odd"><td>&#160;</td>
3411 <td>&#160;</td>
3412 <td>&#160;</td>
3413 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3414 <td>intr</td>
3415 <td>200</td>
3416 </tr>
3417 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3418 <td>97</td>
3419 <td>41</td>
3420 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3421 <td>intr</td>
3422 <td>201</td>
3423 </tr>
3424 <tr class="row-odd"><td>&#160;</td>
3425 <td>&#160;</td>
3426 <td>&#160;</td>
3427 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3428 <td>intr</td>
3429 <td>201</td>
3430 </tr>
3431 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3432 <td>97</td>
3433 <td>42</td>
3434 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3435 <td>intr</td>
3436 <td>202</td>
3437 </tr>
3438 <tr class="row-odd"><td>&#160;</td>
3439 <td>&#160;</td>
3440 <td>&#160;</td>
3441 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3442 <td>intr</td>
3443 <td>202</td>
3444 </tr>
3445 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3446 <td>97</td>
3447 <td>43</td>
3448 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3449 <td>intr</td>
3450 <td>203</td>
3451 </tr>
3452 <tr class="row-odd"><td>&#160;</td>
3453 <td>&#160;</td>
3454 <td>&#160;</td>
3455 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3456 <td>intr</td>
3457 <td>203</td>
3458 </tr>
3459 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3460 <td>97</td>
3461 <td>44</td>
3462 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3463 <td>intr</td>
3464 <td>204</td>
3465 </tr>
3466 <tr class="row-odd"><td>&#160;</td>
3467 <td>&#160;</td>
3468 <td>&#160;</td>
3469 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3470 <td>intr</td>
3471 <td>204</td>
3472 </tr>
3473 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3474 <td>97</td>
3475 <td>45</td>
3476 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3477 <td>intr</td>
3478 <td>205</td>
3479 </tr>
3480 <tr class="row-odd"><td>&#160;</td>
3481 <td>&#160;</td>
3482 <td>&#160;</td>
3483 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3484 <td>intr</td>
3485 <td>205</td>
3486 </tr>
3487 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3488 <td>97</td>
3489 <td>46</td>
3490 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3491 <td>intr</td>
3492 <td>206</td>
3493 </tr>
3494 <tr class="row-odd"><td>&#160;</td>
3495 <td>&#160;</td>
3496 <td>&#160;</td>
3497 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3498 <td>intr</td>
3499 <td>206</td>
3500 </tr>
3501 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3502 <td>97</td>
3503 <td>47</td>
3504 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3505 <td>intr</td>
3506 <td>207</td>
3507 </tr>
3508 <tr class="row-odd"><td>&#160;</td>
3509 <td>&#160;</td>
3510 <td>&#160;</td>
3511 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3512 <td>intr</td>
3513 <td>207</td>
3514 </tr>
3515 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3516 <td>97</td>
3517 <td>48</td>
3518 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3519 <td>intr</td>
3520 <td>208</td>
3521 </tr>
3522 <tr class="row-odd"><td>&#160;</td>
3523 <td>&#160;</td>
3524 <td>&#160;</td>
3525 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3526 <td>intr</td>
3527 <td>208</td>
3528 </tr>
3529 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3530 <td>97</td>
3531 <td>49</td>
3532 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3533 <td>intr</td>
3534 <td>209</td>
3535 </tr>
3536 <tr class="row-odd"><td>&#160;</td>
3537 <td>&#160;</td>
3538 <td>&#160;</td>
3539 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3540 <td>intr</td>
3541 <td>209</td>
3542 </tr>
3543 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3544 <td>97</td>
3545 <td>50</td>
3546 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3547 <td>intr</td>
3548 <td>210</td>
3549 </tr>
3550 <tr class="row-odd"><td>&#160;</td>
3551 <td>&#160;</td>
3552 <td>&#160;</td>
3553 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3554 <td>intr</td>
3555 <td>210</td>
3556 </tr>
3557 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3558 <td>97</td>
3559 <td>51</td>
3560 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3561 <td>intr</td>
3562 <td>211</td>
3563 </tr>
3564 <tr class="row-odd"><td>&#160;</td>
3565 <td>&#160;</td>
3566 <td>&#160;</td>
3567 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3568 <td>intr</td>
3569 <td>211</td>
3570 </tr>
3571 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3572 <td>97</td>
3573 <td>52</td>
3574 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3575 <td>intr</td>
3576 <td>212</td>
3577 </tr>
3578 <tr class="row-odd"><td>&#160;</td>
3579 <td>&#160;</td>
3580 <td>&#160;</td>
3581 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3582 <td>intr</td>
3583 <td>212</td>
3584 </tr>
3585 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3586 <td>97</td>
3587 <td>53</td>
3588 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3589 <td>intr</td>
3590 <td>213</td>
3591 </tr>
3592 <tr class="row-odd"><td>&#160;</td>
3593 <td>&#160;</td>
3594 <td>&#160;</td>
3595 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3596 <td>intr</td>
3597 <td>213</td>
3598 </tr>
3599 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3600 <td>97</td>
3601 <td>54</td>
3602 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3603 <td>intr</td>
3604 <td>214</td>
3605 </tr>
3606 <tr class="row-odd"><td>&#160;</td>
3607 <td>&#160;</td>
3608 <td>&#160;</td>
3609 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3610 <td>intr</td>
3611 <td>214</td>
3612 </tr>
3613 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3614 <td>97</td>
3615 <td>55</td>
3616 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3617 <td>intr</td>
3618 <td>215</td>
3619 </tr>
3620 <tr class="row-odd"><td>&#160;</td>
3621 <td>&#160;</td>
3622 <td>&#160;</td>
3623 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3624 <td>intr</td>
3625 <td>215</td>
3626 </tr>
3627 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3628 <td>97</td>
3629 <td>56</td>
3630 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3631 <td>intr</td>
3632 <td>216</td>
3633 </tr>
3634 <tr class="row-odd"><td>&#160;</td>
3635 <td>&#160;</td>
3636 <td>&#160;</td>
3637 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3638 <td>intr</td>
3639 <td>216</td>
3640 </tr>
3641 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3642 <td>97</td>
3643 <td>57</td>
3644 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3645 <td>intr</td>
3646 <td>217</td>
3647 </tr>
3648 <tr class="row-odd"><td>&#160;</td>
3649 <td>&#160;</td>
3650 <td>&#160;</td>
3651 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3652 <td>intr</td>
3653 <td>217</td>
3654 </tr>
3655 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3656 <td>97</td>
3657 <td>58</td>
3658 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3659 <td>intr</td>
3660 <td>218</td>
3661 </tr>
3662 <tr class="row-odd"><td>&#160;</td>
3663 <td>&#160;</td>
3664 <td>&#160;</td>
3665 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3666 <td>intr</td>
3667 <td>218</td>
3668 </tr>
3669 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3670 <td>97</td>
3671 <td>59</td>
3672 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3673 <td>intr</td>
3674 <td>219</td>
3675 </tr>
3676 <tr class="row-odd"><td>&#160;</td>
3677 <td>&#160;</td>
3678 <td>&#160;</td>
3679 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3680 <td>intr</td>
3681 <td>219</td>
3682 </tr>
3683 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3684 <td>97</td>
3685 <td>60</td>
3686 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3687 <td>intr</td>
3688 <td>220</td>
3689 </tr>
3690 <tr class="row-odd"><td>&#160;</td>
3691 <td>&#160;</td>
3692 <td>&#160;</td>
3693 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3694 <td>intr</td>
3695 <td>220</td>
3696 </tr>
3697 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3698 <td>97</td>
3699 <td>61</td>
3700 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3701 <td>intr</td>
3702 <td>221</td>
3703 </tr>
3704 <tr class="row-odd"><td>&#160;</td>
3705 <td>&#160;</td>
3706 <td>&#160;</td>
3707 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3708 <td>intr</td>
3709 <td>221</td>
3710 </tr>
3711 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3712 <td>97</td>
3713 <td>62</td>
3714 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3715 <td>intr</td>
3716 <td>222</td>
3717 </tr>
3718 <tr class="row-odd"><td>&#160;</td>
3719 <td>&#160;</td>
3720 <td>&#160;</td>
3721 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3722 <td>intr</td>
3723 <td>222</td>
3724 </tr>
3725 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
3726 <td>97</td>
3727 <td>63</td>
3728 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
3729 <td>intr</td>
3730 <td>223</td>
3731 </tr>
3732 <tr class="row-odd"><td>&#160;</td>
3733 <td>&#160;</td>
3734 <td>&#160;</td>
3735 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
3736 <td>intr</td>
3737 <td>223</td>
3738 </tr>
3739 </tbody>
3740 </table>
3741 </div>
3742 <div class="section" id="main2mcu-pls-intrtr0-interrupt-router-input-sources">
3743 <span id="pub-soc-am65x-sr2-main2mcu-pls-intrtr0-input-src-list"></span><h2>MAIN2MCU_PLS_INTRTR0 Interrupt Router Input Sources<a class="headerlink" href="#main2mcu-pls-intrtr0-interrupt-router-input-sources" title="Permalink to this headline">¶</a></h2>
3744 <div class="admonition warning">
3745 <p class="first admonition-title">Warning</p>
3746 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
3747 host within the RM Board Configuration resource assignment array.  The RM
3748 Board Configuration is rejected if an overlap with a reserved resource is
3749 detected.</p>
3750 </div>
3751 <table border="1" class="docutils">
3752 <colgroup>
3753 <col width="25%" />
3754 <col width="13%" />
3755 <col width="15%" />
3756 <col width="17%" />
3757 <col width="17%" />
3758 <col width="13%" />
3759 </colgroup>
3760 <thead valign="bottom">
3761 <tr class="row-odd"><th class="head">IR Name</th>
3762 <th class="head">IR Device ID</th>
3763 <th class="head">IR Input Index</th>
3764 <th class="head">Source Name</th>
3765 <th class="head">Source Interface</th>
3766 <th class="head">Source Index</th>
3767 </tr>
3768 </thead>
3769 <tbody valign="top">
3770 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3771 <td>98</td>
3772 <td>0</td>
3773 <td>Not Connected</td>
3774 <td>&#160;</td>
3775 <td>&#160;</td>
3776 </tr>
3777 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3778 <td>98</td>
3779 <td>1</td>
3780 <td>Not Connected</td>
3781 <td>&#160;</td>
3782 <td>&#160;</td>
3783 </tr>
3784 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3785 <td>98</td>
3786 <td>2</td>
3787 <td>AM6_DEV_EHRPWM0</td>
3788 <td>epwm_etint</td>
3789 <td>0</td>
3790 </tr>
3791 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3792 <td>98</td>
3793 <td>3</td>
3794 <td>AM6_DEV_EHRPWM1</td>
3795 <td>epwm_etint</td>
3796 <td>0</td>
3797 </tr>
3798 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3799 <td>98</td>
3800 <td>4</td>
3801 <td>AM6_DEV_EHRPWM2</td>
3802 <td>epwm_etint</td>
3803 <td>0</td>
3804 </tr>
3805 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3806 <td>98</td>
3807 <td>5</td>
3808 <td>AM6_DEV_EHRPWM3</td>
3809 <td>epwm_etint</td>
3810 <td>0</td>
3811 </tr>
3812 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3813 <td>98</td>
3814 <td>6</td>
3815 <td>AM6_DEV_EHRPWM4</td>
3816 <td>epwm_etint</td>
3817 <td>0</td>
3818 </tr>
3819 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3820 <td>98</td>
3821 <td>7</td>
3822 <td>AM6_DEV_EHRPWM5</td>
3823 <td>epwm_etint</td>
3824 <td>0</td>
3825 </tr>
3826 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3827 <td>98</td>
3828 <td>8</td>
3829 <td>AM6_DEV_EHRPWM0</td>
3830 <td>epwm_tripzint</td>
3831 <td>0</td>
3832 </tr>
3833 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3834 <td>98</td>
3835 <td>9</td>
3836 <td>AM6_DEV_EHRPWM1</td>
3837 <td>epwm_tripzint</td>
3838 <td>0</td>
3839 </tr>
3840 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3841 <td>98</td>
3842 <td>10</td>
3843 <td>AM6_DEV_EHRPWM2</td>
3844 <td>epwm_tripzint</td>
3845 <td>0</td>
3846 </tr>
3847 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3848 <td>98</td>
3849 <td>11</td>
3850 <td>AM6_DEV_EHRPWM3</td>
3851 <td>epwm_tripzint</td>
3852 <td>0</td>
3853 </tr>
3854 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3855 <td>98</td>
3856 <td>12</td>
3857 <td>AM6_DEV_EHRPWM4</td>
3858 <td>epwm_tripzint</td>
3859 <td>0</td>
3860 </tr>
3861 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3862 <td>98</td>
3863 <td>13</td>
3864 <td>AM6_DEV_EHRPWM5</td>
3865 <td>epwm_tripzint</td>
3866 <td>0</td>
3867 </tr>
3868 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3869 <td>98</td>
3870 <td>14</td>
3871 <td>AM6_DEV_EQEP0</td>
3872 <td>eqep_int</td>
3873 <td>0</td>
3874 </tr>
3875 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3876 <td>98</td>
3877 <td>15</td>
3878 <td>AM6_DEV_EQEP1</td>
3879 <td>eqep_int</td>
3880 <td>0</td>
3881 </tr>
3882 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3883 <td>98</td>
3884 <td>16</td>
3885 <td>AM6_DEV_EQEP2</td>
3886 <td>eqep_int</td>
3887 <td>0</td>
3888 </tr>
3889 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3890 <td>98</td>
3891 <td>17</td>
3892 <td>AM6_DEV_ECAP0</td>
3893 <td>ecap_int</td>
3894 <td>0</td>
3895 </tr>
3896 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3897 <td>98</td>
3898 <td>18</td>
3899 <td>Not Connected</td>
3900 <td>&#160;</td>
3901 <td>&#160;</td>
3902 </tr>
3903 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3904 <td>98</td>
3905 <td>19</td>
3906 <td>Not Connected</td>
3907 <td>&#160;</td>
3908 <td>&#160;</td>
3909 </tr>
3910 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3911 <td>98</td>
3912 <td>20</td>
3913 <td>AM6_DEV_PRU_ICSSG0</td>
3914 <td>pr1_rx_sof_intr_req</td>
3915 <td>0</td>
3916 </tr>
3917 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3918 <td>98</td>
3919 <td>21</td>
3920 <td>AM6_DEV_PRU_ICSSG0</td>
3921 <td>pr1_rx_sof_intr_req</td>
3922 <td>1</td>
3923 </tr>
3924 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3925 <td>98</td>
3926 <td>22</td>
3927 <td>AM6_DEV_PRU_ICSSG0</td>
3928 <td>pr1_tx_sof_intr_req</td>
3929 <td>0</td>
3930 </tr>
3931 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3932 <td>98</td>
3933 <td>23</td>
3934 <td>AM6_DEV_PRU_ICSSG0</td>
3935 <td>pr1_tx_sof_intr_req</td>
3936 <td>1</td>
3937 </tr>
3938 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3939 <td>98</td>
3940 <td>24</td>
3941 <td>AM6_DEV_PRU_ICSSG1</td>
3942 <td>pr1_rx_sof_intr_req</td>
3943 <td>0</td>
3944 </tr>
3945 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3946 <td>98</td>
3947 <td>25</td>
3948 <td>AM6_DEV_PRU_ICSSG1</td>
3949 <td>pr1_rx_sof_intr_req</td>
3950 <td>1</td>
3951 </tr>
3952 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3953 <td>98</td>
3954 <td>26</td>
3955 <td>AM6_DEV_PRU_ICSSG1</td>
3956 <td>pr1_tx_sof_intr_req</td>
3957 <td>0</td>
3958 </tr>
3959 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3960 <td>98</td>
3961 <td>27</td>
3962 <td>AM6_DEV_PRU_ICSSG1</td>
3963 <td>pr1_tx_sof_intr_req</td>
3964 <td>1</td>
3965 </tr>
3966 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3967 <td>98</td>
3968 <td>28</td>
3969 <td>AM6_DEV_PRU_ICSSG2</td>
3970 <td>pr1_rx_sof_intr_req</td>
3971 <td>0</td>
3972 </tr>
3973 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3974 <td>98</td>
3975 <td>29</td>
3976 <td>AM6_DEV_PRU_ICSSG2</td>
3977 <td>pr1_rx_sof_intr_req</td>
3978 <td>1</td>
3979 </tr>
3980 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3981 <td>98</td>
3982 <td>30</td>
3983 <td>AM6_DEV_PRU_ICSSG2</td>
3984 <td>pr1_tx_sof_intr_req</td>
3985 <td>0</td>
3986 </tr>
3987 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
3988 <td>98</td>
3989 <td>31</td>
3990 <td>AM6_DEV_PRU_ICSSG2</td>
3991 <td>pr1_tx_sof_intr_req</td>
3992 <td>1</td>
3993 </tr>
3994 </tbody>
3995 </table>
3996 </div>
3997 <div class="section" id="main2mcu-pls-intrtr0-interrupt-router-output-destinations">
3998 <span id="pub-soc-am65x-sr2-main2mcu-pls-intrtr0-output-src-list"></span><h2>MAIN2MCU_PLS_INTRTR0 Interrupt Router Output Destinations<a class="headerlink" href="#main2mcu-pls-intrtr0-interrupt-router-output-destinations" title="Permalink to this headline">¶</a></h2>
3999 <div class="admonition warning">
4000 <p class="first admonition-title">Warning</p>
4001 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
4002 host within the RM Board Configuration resource assignment array.  The RM
4003 Board Configuration is rejected if an overlap with a reserved resource is
4004 detected.</p>
4005 </div>
4006 <table border="1" class="docutils">
4007 <colgroup>
4008 <col width="22%" />
4009 <col width="12%" />
4010 <col width="14%" />
4011 <col width="18%" />
4012 <col width="18%" />
4013 <col width="15%" />
4014 </colgroup>
4015 <thead valign="bottom">
4016 <tr class="row-odd"><th class="head">IR Name</th>
4017 <th class="head">IR Device ID</th>
4018 <th class="head">IR Output Index</th>
4019 <th class="head">Destination Name</th>
4020 <th class="head">Destination Interface</th>
4021 <th class="head">Destination Index</th>
4022 </tr>
4023 </thead>
4024 <tbody valign="top">
4025 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4026 <td>98</td>
4027 <td>0</td>
4028 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4029 <td>intr</td>
4030 <td>224</td>
4031 </tr>
4032 <tr class="row-odd"><td>&#160;</td>
4033 <td>&#160;</td>
4034 <td>&#160;</td>
4035 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4036 <td>intr</td>
4037 <td>224</td>
4038 </tr>
4039 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4040 <td>98</td>
4041 <td>1</td>
4042 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4043 <td>intr</td>
4044 <td>225</td>
4045 </tr>
4046 <tr class="row-odd"><td>&#160;</td>
4047 <td>&#160;</td>
4048 <td>&#160;</td>
4049 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4050 <td>intr</td>
4051 <td>225</td>
4052 </tr>
4053 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4054 <td>98</td>
4055 <td>2</td>
4056 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4057 <td>intr</td>
4058 <td>226</td>
4059 </tr>
4060 <tr class="row-odd"><td>&#160;</td>
4061 <td>&#160;</td>
4062 <td>&#160;</td>
4063 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4064 <td>intr</td>
4065 <td>226</td>
4066 </tr>
4067 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4068 <td>98</td>
4069 <td>3</td>
4070 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4071 <td>intr</td>
4072 <td>227</td>
4073 </tr>
4074 <tr class="row-odd"><td>&#160;</td>
4075 <td>&#160;</td>
4076 <td>&#160;</td>
4077 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4078 <td>intr</td>
4079 <td>227</td>
4080 </tr>
4081 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4082 <td>98</td>
4083 <td>4</td>
4084 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4085 <td>intr</td>
4086 <td>228</td>
4087 </tr>
4088 <tr class="row-odd"><td>&#160;</td>
4089 <td>&#160;</td>
4090 <td>&#160;</td>
4091 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4092 <td>intr</td>
4093 <td>228</td>
4094 </tr>
4095 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4096 <td>98</td>
4097 <td>5</td>
4098 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4099 <td>intr</td>
4100 <td>229</td>
4101 </tr>
4102 <tr class="row-odd"><td>&#160;</td>
4103 <td>&#160;</td>
4104 <td>&#160;</td>
4105 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4106 <td>intr</td>
4107 <td>229</td>
4108 </tr>
4109 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4110 <td>98</td>
4111 <td>6</td>
4112 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4113 <td>intr</td>
4114 <td>230</td>
4115 </tr>
4116 <tr class="row-odd"><td>&#160;</td>
4117 <td>&#160;</td>
4118 <td>&#160;</td>
4119 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4120 <td>intr</td>
4121 <td>230</td>
4122 </tr>
4123 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4124 <td>98</td>
4125 <td>7</td>
4126 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4127 <td>intr</td>
4128 <td>231</td>
4129 </tr>
4130 <tr class="row-odd"><td>&#160;</td>
4131 <td>&#160;</td>
4132 <td>&#160;</td>
4133 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4134 <td>intr</td>
4135 <td>231</td>
4136 </tr>
4137 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4138 <td>98</td>
4139 <td>8</td>
4140 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4141 <td>intr</td>
4142 <td>232</td>
4143 </tr>
4144 <tr class="row-odd"><td>&#160;</td>
4145 <td>&#160;</td>
4146 <td>&#160;</td>
4147 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4148 <td>intr</td>
4149 <td>232</td>
4150 </tr>
4151 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4152 <td>98</td>
4153 <td>9</td>
4154 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4155 <td>intr</td>
4156 <td>233</td>
4157 </tr>
4158 <tr class="row-odd"><td>&#160;</td>
4159 <td>&#160;</td>
4160 <td>&#160;</td>
4161 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4162 <td>intr</td>
4163 <td>233</td>
4164 </tr>
4165 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4166 <td>98</td>
4167 <td>10</td>
4168 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4169 <td>intr</td>
4170 <td>234</td>
4171 </tr>
4172 <tr class="row-odd"><td>&#160;</td>
4173 <td>&#160;</td>
4174 <td>&#160;</td>
4175 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4176 <td>intr</td>
4177 <td>234</td>
4178 </tr>
4179 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4180 <td>98</td>
4181 <td>11</td>
4182 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4183 <td>intr</td>
4184 <td>235</td>
4185 </tr>
4186 <tr class="row-odd"><td>&#160;</td>
4187 <td>&#160;</td>
4188 <td>&#160;</td>
4189 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4190 <td>intr</td>
4191 <td>235</td>
4192 </tr>
4193 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4194 <td>98</td>
4195 <td>12</td>
4196 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4197 <td>intr</td>
4198 <td>236</td>
4199 </tr>
4200 <tr class="row-odd"><td>&#160;</td>
4201 <td>&#160;</td>
4202 <td>&#160;</td>
4203 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4204 <td>intr</td>
4205 <td>236</td>
4206 </tr>
4207 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4208 <td>98</td>
4209 <td>13</td>
4210 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4211 <td>intr</td>
4212 <td>237</td>
4213 </tr>
4214 <tr class="row-odd"><td>&#160;</td>
4215 <td>&#160;</td>
4216 <td>&#160;</td>
4217 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4218 <td>intr</td>
4219 <td>237</td>
4220 </tr>
4221 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4222 <td>98</td>
4223 <td>14</td>
4224 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4225 <td>intr</td>
4226 <td>238</td>
4227 </tr>
4228 <tr class="row-odd"><td>&#160;</td>
4229 <td>&#160;</td>
4230 <td>&#160;</td>
4231 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4232 <td>intr</td>
4233 <td>238</td>
4234 </tr>
4235 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4236 <td>98</td>
4237 <td>15</td>
4238 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4239 <td>intr</td>
4240 <td>239</td>
4241 </tr>
4242 <tr class="row-odd"><td>&#160;</td>
4243 <td>&#160;</td>
4244 <td>&#160;</td>
4245 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4246 <td>intr</td>
4247 <td>239</td>
4248 </tr>
4249 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4250 <td>98</td>
4251 <td>16</td>
4252 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4253 <td>intr</td>
4254 <td>240</td>
4255 </tr>
4256 <tr class="row-odd"><td>&#160;</td>
4257 <td>&#160;</td>
4258 <td>&#160;</td>
4259 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4260 <td>intr</td>
4261 <td>240</td>
4262 </tr>
4263 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4264 <td>98</td>
4265 <td>17</td>
4266 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4267 <td>intr</td>
4268 <td>241</td>
4269 </tr>
4270 <tr class="row-odd"><td>&#160;</td>
4271 <td>&#160;</td>
4272 <td>&#160;</td>
4273 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4274 <td>intr</td>
4275 <td>241</td>
4276 </tr>
4277 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4278 <td>98</td>
4279 <td>18</td>
4280 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4281 <td>intr</td>
4282 <td>242</td>
4283 </tr>
4284 <tr class="row-odd"><td>&#160;</td>
4285 <td>&#160;</td>
4286 <td>&#160;</td>
4287 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4288 <td>intr</td>
4289 <td>242</td>
4290 </tr>
4291 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4292 <td>98</td>
4293 <td>19</td>
4294 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4295 <td>intr</td>
4296 <td>243</td>
4297 </tr>
4298 <tr class="row-odd"><td>&#160;</td>
4299 <td>&#160;</td>
4300 <td>&#160;</td>
4301 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4302 <td>intr</td>
4303 <td>243</td>
4304 </tr>
4305 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4306 <td>98</td>
4307 <td>20</td>
4308 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4309 <td>intr</td>
4310 <td>244</td>
4311 </tr>
4312 <tr class="row-odd"><td>&#160;</td>
4313 <td>&#160;</td>
4314 <td>&#160;</td>
4315 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4316 <td>intr</td>
4317 <td>244</td>
4318 </tr>
4319 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4320 <td>98</td>
4321 <td>21</td>
4322 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4323 <td>intr</td>
4324 <td>245</td>
4325 </tr>
4326 <tr class="row-odd"><td>&#160;</td>
4327 <td>&#160;</td>
4328 <td>&#160;</td>
4329 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4330 <td>intr</td>
4331 <td>245</td>
4332 </tr>
4333 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4334 <td>98</td>
4335 <td>22</td>
4336 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4337 <td>intr</td>
4338 <td>246</td>
4339 </tr>
4340 <tr class="row-odd"><td>&#160;</td>
4341 <td>&#160;</td>
4342 <td>&#160;</td>
4343 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4344 <td>intr</td>
4345 <td>246</td>
4346 </tr>
4347 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4348 <td>98</td>
4349 <td>23</td>
4350 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4351 <td>intr</td>
4352 <td>247</td>
4353 </tr>
4354 <tr class="row-odd"><td>&#160;</td>
4355 <td>&#160;</td>
4356 <td>&#160;</td>
4357 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4358 <td>intr</td>
4359 <td>247</td>
4360 </tr>
4361 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4362 <td>98</td>
4363 <td>24</td>
4364 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4365 <td>intr</td>
4366 <td>248</td>
4367 </tr>
4368 <tr class="row-odd"><td>&#160;</td>
4369 <td>&#160;</td>
4370 <td>&#160;</td>
4371 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4372 <td>intr</td>
4373 <td>248</td>
4374 </tr>
4375 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4376 <td>98</td>
4377 <td>25</td>
4378 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4379 <td>intr</td>
4380 <td>249</td>
4381 </tr>
4382 <tr class="row-odd"><td>&#160;</td>
4383 <td>&#160;</td>
4384 <td>&#160;</td>
4385 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4386 <td>intr</td>
4387 <td>249</td>
4388 </tr>
4389 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4390 <td>98</td>
4391 <td>26</td>
4392 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4393 <td>intr</td>
4394 <td>250</td>
4395 </tr>
4396 <tr class="row-odd"><td>&#160;</td>
4397 <td>&#160;</td>
4398 <td>&#160;</td>
4399 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4400 <td>intr</td>
4401 <td>250</td>
4402 </tr>
4403 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4404 <td>98</td>
4405 <td>27</td>
4406 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4407 <td>intr</td>
4408 <td>251</td>
4409 </tr>
4410 <tr class="row-odd"><td>&#160;</td>
4411 <td>&#160;</td>
4412 <td>&#160;</td>
4413 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4414 <td>intr</td>
4415 <td>251</td>
4416 </tr>
4417 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4418 <td>98</td>
4419 <td>28</td>
4420 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4421 <td>intr</td>
4422 <td>252</td>
4423 </tr>
4424 <tr class="row-odd"><td>&#160;</td>
4425 <td>&#160;</td>
4426 <td>&#160;</td>
4427 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4428 <td>intr</td>
4429 <td>252</td>
4430 </tr>
4431 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4432 <td>98</td>
4433 <td>29</td>
4434 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4435 <td>intr</td>
4436 <td>253</td>
4437 </tr>
4438 <tr class="row-odd"><td>&#160;</td>
4439 <td>&#160;</td>
4440 <td>&#160;</td>
4441 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4442 <td>intr</td>
4443 <td>253</td>
4444 </tr>
4445 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4446 <td>98</td>
4447 <td>30</td>
4448 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4449 <td>intr</td>
4450 <td>254</td>
4451 </tr>
4452 <tr class="row-odd"><td>&#160;</td>
4453 <td>&#160;</td>
4454 <td>&#160;</td>
4455 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4456 <td>intr</td>
4457 <td>254</td>
4458 </tr>
4459 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4460 <td>98</td>
4461 <td>31</td>
4462 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4463 <td>intr</td>
4464 <td>255</td>
4465 </tr>
4466 <tr class="row-odd"><td>&#160;</td>
4467 <td>&#160;</td>
4468 <td>&#160;</td>
4469 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4470 <td>intr</td>
4471 <td>255</td>
4472 </tr>
4473 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4474 <td>98</td>
4475 <td>32</td>
4476 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4477 <td>intr</td>
4478 <td>256</td>
4479 </tr>
4480 <tr class="row-odd"><td>&#160;</td>
4481 <td>&#160;</td>
4482 <td>&#160;</td>
4483 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4484 <td>intr</td>
4485 <td>256</td>
4486 </tr>
4487 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4488 <td>98</td>
4489 <td>33</td>
4490 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4491 <td>intr</td>
4492 <td>257</td>
4493 </tr>
4494 <tr class="row-odd"><td>&#160;</td>
4495 <td>&#160;</td>
4496 <td>&#160;</td>
4497 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4498 <td>intr</td>
4499 <td>257</td>
4500 </tr>
4501 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4502 <td>98</td>
4503 <td>34</td>
4504 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4505 <td>intr</td>
4506 <td>258</td>
4507 </tr>
4508 <tr class="row-odd"><td>&#160;</td>
4509 <td>&#160;</td>
4510 <td>&#160;</td>
4511 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4512 <td>intr</td>
4513 <td>258</td>
4514 </tr>
4515 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4516 <td>98</td>
4517 <td>35</td>
4518 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4519 <td>intr</td>
4520 <td>259</td>
4521 </tr>
4522 <tr class="row-odd"><td>&#160;</td>
4523 <td>&#160;</td>
4524 <td>&#160;</td>
4525 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4526 <td>intr</td>
4527 <td>259</td>
4528 </tr>
4529 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4530 <td>98</td>
4531 <td>36</td>
4532 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4533 <td>intr</td>
4534 <td>260</td>
4535 </tr>
4536 <tr class="row-odd"><td>&#160;</td>
4537 <td>&#160;</td>
4538 <td>&#160;</td>
4539 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4540 <td>intr</td>
4541 <td>260</td>
4542 </tr>
4543 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4544 <td>98</td>
4545 <td>37</td>
4546 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4547 <td>intr</td>
4548 <td>261</td>
4549 </tr>
4550 <tr class="row-odd"><td>&#160;</td>
4551 <td>&#160;</td>
4552 <td>&#160;</td>
4553 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4554 <td>intr</td>
4555 <td>261</td>
4556 </tr>
4557 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4558 <td>98</td>
4559 <td>38</td>
4560 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4561 <td>intr</td>
4562 <td>262</td>
4563 </tr>
4564 <tr class="row-odd"><td>&#160;</td>
4565 <td>&#160;</td>
4566 <td>&#160;</td>
4567 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4568 <td>intr</td>
4569 <td>262</td>
4570 </tr>
4571 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4572 <td>98</td>
4573 <td>39</td>
4574 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4575 <td>intr</td>
4576 <td>263</td>
4577 </tr>
4578 <tr class="row-odd"><td>&#160;</td>
4579 <td>&#160;</td>
4580 <td>&#160;</td>
4581 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4582 <td>intr</td>
4583 <td>263</td>
4584 </tr>
4585 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4586 <td>98</td>
4587 <td>40</td>
4588 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4589 <td>intr</td>
4590 <td>264</td>
4591 </tr>
4592 <tr class="row-odd"><td>&#160;</td>
4593 <td>&#160;</td>
4594 <td>&#160;</td>
4595 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4596 <td>intr</td>
4597 <td>264</td>
4598 </tr>
4599 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4600 <td>98</td>
4601 <td>41</td>
4602 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4603 <td>intr</td>
4604 <td>265</td>
4605 </tr>
4606 <tr class="row-odd"><td>&#160;</td>
4607 <td>&#160;</td>
4608 <td>&#160;</td>
4609 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4610 <td>intr</td>
4611 <td>265</td>
4612 </tr>
4613 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4614 <td>98</td>
4615 <td>42</td>
4616 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4617 <td>intr</td>
4618 <td>266</td>
4619 </tr>
4620 <tr class="row-odd"><td>&#160;</td>
4621 <td>&#160;</td>
4622 <td>&#160;</td>
4623 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4624 <td>intr</td>
4625 <td>266</td>
4626 </tr>
4627 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4628 <td>98</td>
4629 <td>43</td>
4630 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4631 <td>intr</td>
4632 <td>267</td>
4633 </tr>
4634 <tr class="row-odd"><td>&#160;</td>
4635 <td>&#160;</td>
4636 <td>&#160;</td>
4637 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4638 <td>intr</td>
4639 <td>267</td>
4640 </tr>
4641 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4642 <td>98</td>
4643 <td>44</td>
4644 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4645 <td>intr</td>
4646 <td>268</td>
4647 </tr>
4648 <tr class="row-odd"><td>&#160;</td>
4649 <td>&#160;</td>
4650 <td>&#160;</td>
4651 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4652 <td>intr</td>
4653 <td>268</td>
4654 </tr>
4655 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4656 <td>98</td>
4657 <td>45</td>
4658 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4659 <td>intr</td>
4660 <td>269</td>
4661 </tr>
4662 <tr class="row-odd"><td>&#160;</td>
4663 <td>&#160;</td>
4664 <td>&#160;</td>
4665 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4666 <td>intr</td>
4667 <td>269</td>
4668 </tr>
4669 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4670 <td>98</td>
4671 <td>46</td>
4672 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4673 <td>intr</td>
4674 <td>270</td>
4675 </tr>
4676 <tr class="row-odd"><td>&#160;</td>
4677 <td>&#160;</td>
4678 <td>&#160;</td>
4679 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4680 <td>intr</td>
4681 <td>270</td>
4682 </tr>
4683 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
4684 <td>98</td>
4685 <td>47</td>
4686 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
4687 <td>intr</td>
4688 <td>271</td>
4689 </tr>
4690 <tr class="row-odd"><td>&#160;</td>
4691 <td>&#160;</td>
4692 <td>&#160;</td>
4693 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
4694 <td>intr</td>
4695 <td>271</td>
4696 </tr>
4697 </tbody>
4698 </table>
4699 </div>
4700 <div class="section" id="gpiomux-intrtr0-interrupt-router-input-sources">
4701 <span id="pub-soc-am65x-sr2-gpiomux-intrtr0-input-src-list"></span><h2>GPIOMUX_INTRTR0 Interrupt Router Input Sources<a class="headerlink" href="#gpiomux-intrtr0-interrupt-router-input-sources" title="Permalink to this headline">¶</a></h2>
4702 <div class="admonition warning">
4703 <p class="first admonition-title">Warning</p>
4704 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
4705 host within the RM Board Configuration resource assignment array.  The RM
4706 Board Configuration is rejected if an overlap with a reserved resource is
4707 detected.</p>
4708 </div>
4709 <table border="1" class="docutils">
4710 <colgroup>
4711 <col width="23%" />
4712 <col width="15%" />
4713 <col width="16%" />
4714 <col width="14%" />
4715 <col width="18%" />
4716 <col width="15%" />
4717 </colgroup>
4718 <thead valign="bottom">
4719 <tr class="row-odd"><th class="head">IR Name</th>
4720 <th class="head">IR Device ID</th>
4721 <th class="head">IR Input Index</th>
4722 <th class="head">Source Name</th>
4723 <th class="head">Source Interface</th>
4724 <th class="head">Source Index</th>
4725 </tr>
4726 </thead>
4727 <tbody valign="top">
4728 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4729 <td>100</td>
4730 <td>0</td>
4731 <td>AM6_DEV_GPIO0</td>
4732 <td>gpio</td>
4733 <td>0</td>
4734 </tr>
4735 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4736 <td>100</td>
4737 <td>1</td>
4738 <td>AM6_DEV_GPIO0</td>
4739 <td>gpio</td>
4740 <td>1</td>
4741 </tr>
4742 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4743 <td>100</td>
4744 <td>2</td>
4745 <td>AM6_DEV_GPIO0</td>
4746 <td>gpio</td>
4747 <td>2</td>
4748 </tr>
4749 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4750 <td>100</td>
4751 <td>3</td>
4752 <td>AM6_DEV_GPIO0</td>
4753 <td>gpio</td>
4754 <td>3</td>
4755 </tr>
4756 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4757 <td>100</td>
4758 <td>4</td>
4759 <td>AM6_DEV_GPIO0</td>
4760 <td>gpio</td>
4761 <td>4</td>
4762 </tr>
4763 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4764 <td>100</td>
4765 <td>5</td>
4766 <td>AM6_DEV_GPIO0</td>
4767 <td>gpio</td>
4768 <td>5</td>
4769 </tr>
4770 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4771 <td>100</td>
4772 <td>6</td>
4773 <td>AM6_DEV_GPIO0</td>
4774 <td>gpio</td>
4775 <td>6</td>
4776 </tr>
4777 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4778 <td>100</td>
4779 <td>7</td>
4780 <td>AM6_DEV_GPIO0</td>
4781 <td>gpio</td>
4782 <td>7</td>
4783 </tr>
4784 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4785 <td>100</td>
4786 <td>8</td>
4787 <td>AM6_DEV_GPIO0</td>
4788 <td>gpio</td>
4789 <td>8</td>
4790 </tr>
4791 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4792 <td>100</td>
4793 <td>9</td>
4794 <td>AM6_DEV_GPIO0</td>
4795 <td>gpio</td>
4796 <td>9</td>
4797 </tr>
4798 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4799 <td>100</td>
4800 <td>10</td>
4801 <td>AM6_DEV_GPIO0</td>
4802 <td>gpio</td>
4803 <td>10</td>
4804 </tr>
4805 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4806 <td>100</td>
4807 <td>11</td>
4808 <td>AM6_DEV_GPIO0</td>
4809 <td>gpio</td>
4810 <td>11</td>
4811 </tr>
4812 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4813 <td>100</td>
4814 <td>12</td>
4815 <td>AM6_DEV_GPIO0</td>
4816 <td>gpio</td>
4817 <td>12</td>
4818 </tr>
4819 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4820 <td>100</td>
4821 <td>13</td>
4822 <td>AM6_DEV_GPIO0</td>
4823 <td>gpio</td>
4824 <td>13</td>
4825 </tr>
4826 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4827 <td>100</td>
4828 <td>14</td>
4829 <td>AM6_DEV_GPIO0</td>
4830 <td>gpio</td>
4831 <td>14</td>
4832 </tr>
4833 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4834 <td>100</td>
4835 <td>15</td>
4836 <td>AM6_DEV_GPIO0</td>
4837 <td>gpio</td>
4838 <td>15</td>
4839 </tr>
4840 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4841 <td>100</td>
4842 <td>16</td>
4843 <td>AM6_DEV_GPIO0</td>
4844 <td>gpio</td>
4845 <td>16</td>
4846 </tr>
4847 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4848 <td>100</td>
4849 <td>17</td>
4850 <td>AM6_DEV_GPIO0</td>
4851 <td>gpio</td>
4852 <td>17</td>
4853 </tr>
4854 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4855 <td>100</td>
4856 <td>18</td>
4857 <td>AM6_DEV_GPIO0</td>
4858 <td>gpio</td>
4859 <td>18</td>
4860 </tr>
4861 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4862 <td>100</td>
4863 <td>19</td>
4864 <td>AM6_DEV_GPIO0</td>
4865 <td>gpio</td>
4866 <td>19</td>
4867 </tr>
4868 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4869 <td>100</td>
4870 <td>20</td>
4871 <td>AM6_DEV_GPIO0</td>
4872 <td>gpio</td>
4873 <td>20</td>
4874 </tr>
4875 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4876 <td>100</td>
4877 <td>21</td>
4878 <td>AM6_DEV_GPIO0</td>
4879 <td>gpio</td>
4880 <td>21</td>
4881 </tr>
4882 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4883 <td>100</td>
4884 <td>22</td>
4885 <td>AM6_DEV_GPIO0</td>
4886 <td>gpio</td>
4887 <td>22</td>
4888 </tr>
4889 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4890 <td>100</td>
4891 <td>23</td>
4892 <td>AM6_DEV_GPIO0</td>
4893 <td>gpio</td>
4894 <td>23</td>
4895 </tr>
4896 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4897 <td>100</td>
4898 <td>24</td>
4899 <td>AM6_DEV_GPIO0</td>
4900 <td>gpio</td>
4901 <td>24</td>
4902 </tr>
4903 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4904 <td>100</td>
4905 <td>25</td>
4906 <td>AM6_DEV_GPIO0</td>
4907 <td>gpio</td>
4908 <td>25</td>
4909 </tr>
4910 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4911 <td>100</td>
4912 <td>26</td>
4913 <td>AM6_DEV_GPIO0</td>
4914 <td>gpio</td>
4915 <td>26</td>
4916 </tr>
4917 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4918 <td>100</td>
4919 <td>27</td>
4920 <td>AM6_DEV_GPIO0</td>
4921 <td>gpio</td>
4922 <td>27</td>
4923 </tr>
4924 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4925 <td>100</td>
4926 <td>28</td>
4927 <td>AM6_DEV_GPIO0</td>
4928 <td>gpio</td>
4929 <td>28</td>
4930 </tr>
4931 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4932 <td>100</td>
4933 <td>29</td>
4934 <td>AM6_DEV_GPIO0</td>
4935 <td>gpio</td>
4936 <td>29</td>
4937 </tr>
4938 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4939 <td>100</td>
4940 <td>30</td>
4941 <td>AM6_DEV_GPIO0</td>
4942 <td>gpio</td>
4943 <td>30</td>
4944 </tr>
4945 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4946 <td>100</td>
4947 <td>31</td>
4948 <td>AM6_DEV_GPIO0</td>
4949 <td>gpio</td>
4950 <td>31</td>
4951 </tr>
4952 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4953 <td>100</td>
4954 <td>32</td>
4955 <td>AM6_DEV_GPIO0</td>
4956 <td>gpio</td>
4957 <td>32</td>
4958 </tr>
4959 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4960 <td>100</td>
4961 <td>33</td>
4962 <td>AM6_DEV_GPIO0</td>
4963 <td>gpio</td>
4964 <td>33</td>
4965 </tr>
4966 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4967 <td>100</td>
4968 <td>34</td>
4969 <td>AM6_DEV_GPIO0</td>
4970 <td>gpio</td>
4971 <td>34</td>
4972 </tr>
4973 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4974 <td>100</td>
4975 <td>35</td>
4976 <td>AM6_DEV_GPIO0</td>
4977 <td>gpio</td>
4978 <td>35</td>
4979 </tr>
4980 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4981 <td>100</td>
4982 <td>36</td>
4983 <td>AM6_DEV_GPIO0</td>
4984 <td>gpio</td>
4985 <td>36</td>
4986 </tr>
4987 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4988 <td>100</td>
4989 <td>37</td>
4990 <td>AM6_DEV_GPIO0</td>
4991 <td>gpio</td>
4992 <td>37</td>
4993 </tr>
4994 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
4995 <td>100</td>
4996 <td>38</td>
4997 <td>AM6_DEV_GPIO0</td>
4998 <td>gpio</td>
4999 <td>38</td>
5000 </tr>
5001 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5002 <td>100</td>
5003 <td>39</td>
5004 <td>AM6_DEV_GPIO0</td>
5005 <td>gpio</td>
5006 <td>39</td>
5007 </tr>
5008 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5009 <td>100</td>
5010 <td>40</td>
5011 <td>AM6_DEV_GPIO0</td>
5012 <td>gpio</td>
5013 <td>40</td>
5014 </tr>
5015 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5016 <td>100</td>
5017 <td>41</td>
5018 <td>AM6_DEV_GPIO0</td>
5019 <td>gpio</td>
5020 <td>41</td>
5021 </tr>
5022 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5023 <td>100</td>
5024 <td>42</td>
5025 <td>AM6_DEV_GPIO0</td>
5026 <td>gpio</td>
5027 <td>42</td>
5028 </tr>
5029 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5030 <td>100</td>
5031 <td>43</td>
5032 <td>AM6_DEV_GPIO0</td>
5033 <td>gpio</td>
5034 <td>43</td>
5035 </tr>
5036 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5037 <td>100</td>
5038 <td>44</td>
5039 <td>AM6_DEV_GPIO0</td>
5040 <td>gpio</td>
5041 <td>44</td>
5042 </tr>
5043 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5044 <td>100</td>
5045 <td>45</td>
5046 <td>AM6_DEV_GPIO0</td>
5047 <td>gpio</td>
5048 <td>45</td>
5049 </tr>
5050 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5051 <td>100</td>
5052 <td>46</td>
5053 <td>AM6_DEV_GPIO0</td>
5054 <td>gpio</td>
5055 <td>46</td>
5056 </tr>
5057 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5058 <td>100</td>
5059 <td>47</td>
5060 <td>AM6_DEV_GPIO0</td>
5061 <td>gpio</td>
5062 <td>47</td>
5063 </tr>
5064 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5065 <td>100</td>
5066 <td>48</td>
5067 <td>AM6_DEV_GPIO0</td>
5068 <td>gpio</td>
5069 <td>48</td>
5070 </tr>
5071 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5072 <td>100</td>
5073 <td>49</td>
5074 <td>AM6_DEV_GPIO0</td>
5075 <td>gpio</td>
5076 <td>49</td>
5077 </tr>
5078 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5079 <td>100</td>
5080 <td>50</td>
5081 <td>AM6_DEV_GPIO0</td>
5082 <td>gpio</td>
5083 <td>50</td>
5084 </tr>
5085 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5086 <td>100</td>
5087 <td>51</td>
5088 <td>AM6_DEV_GPIO0</td>
5089 <td>gpio</td>
5090 <td>51</td>
5091 </tr>
5092 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5093 <td>100</td>
5094 <td>52</td>
5095 <td>AM6_DEV_GPIO0</td>
5096 <td>gpio</td>
5097 <td>52</td>
5098 </tr>
5099 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5100 <td>100</td>
5101 <td>53</td>
5102 <td>AM6_DEV_GPIO0</td>
5103 <td>gpio</td>
5104 <td>53</td>
5105 </tr>
5106 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5107 <td>100</td>
5108 <td>54</td>
5109 <td>AM6_DEV_GPIO0</td>
5110 <td>gpio</td>
5111 <td>54</td>
5112 </tr>
5113 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5114 <td>100</td>
5115 <td>55</td>
5116 <td>AM6_DEV_GPIO0</td>
5117 <td>gpio</td>
5118 <td>55</td>
5119 </tr>
5120 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5121 <td>100</td>
5122 <td>56</td>
5123 <td>AM6_DEV_GPIO0</td>
5124 <td>gpio</td>
5125 <td>56</td>
5126 </tr>
5127 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5128 <td>100</td>
5129 <td>57</td>
5130 <td>AM6_DEV_GPIO0</td>
5131 <td>gpio</td>
5132 <td>57</td>
5133 </tr>
5134 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5135 <td>100</td>
5136 <td>58</td>
5137 <td>AM6_DEV_GPIO0</td>
5138 <td>gpio</td>
5139 <td>58</td>
5140 </tr>
5141 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5142 <td>100</td>
5143 <td>59</td>
5144 <td>AM6_DEV_GPIO0</td>
5145 <td>gpio</td>
5146 <td>59</td>
5147 </tr>
5148 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5149 <td>100</td>
5150 <td>60</td>
5151 <td>AM6_DEV_GPIO0</td>
5152 <td>gpio</td>
5153 <td>60</td>
5154 </tr>
5155 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5156 <td>100</td>
5157 <td>61</td>
5158 <td>AM6_DEV_GPIO0</td>
5159 <td>gpio</td>
5160 <td>61</td>
5161 </tr>
5162 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5163 <td>100</td>
5164 <td>62</td>
5165 <td>AM6_DEV_GPIO0</td>
5166 <td>gpio</td>
5167 <td>62</td>
5168 </tr>
5169 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5170 <td>100</td>
5171 <td>63</td>
5172 <td>AM6_DEV_GPIO0</td>
5173 <td>gpio</td>
5174 <td>63</td>
5175 </tr>
5176 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5177 <td>100</td>
5178 <td>64</td>
5179 <td>AM6_DEV_GPIO0</td>
5180 <td>gpio</td>
5181 <td>64</td>
5182 </tr>
5183 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5184 <td>100</td>
5185 <td>65</td>
5186 <td>AM6_DEV_GPIO0</td>
5187 <td>gpio</td>
5188 <td>65</td>
5189 </tr>
5190 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5191 <td>100</td>
5192 <td>66</td>
5193 <td>AM6_DEV_GPIO0</td>
5194 <td>gpio</td>
5195 <td>66</td>
5196 </tr>
5197 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5198 <td>100</td>
5199 <td>67</td>
5200 <td>AM6_DEV_GPIO0</td>
5201 <td>gpio</td>
5202 <td>67</td>
5203 </tr>
5204 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5205 <td>100</td>
5206 <td>68</td>
5207 <td>AM6_DEV_GPIO0</td>
5208 <td>gpio</td>
5209 <td>68</td>
5210 </tr>
5211 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5212 <td>100</td>
5213 <td>69</td>
5214 <td>AM6_DEV_GPIO0</td>
5215 <td>gpio</td>
5216 <td>69</td>
5217 </tr>
5218 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5219 <td>100</td>
5220 <td>70</td>
5221 <td>AM6_DEV_GPIO0</td>
5222 <td>gpio</td>
5223 <td>70</td>
5224 </tr>
5225 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5226 <td>100</td>
5227 <td>71</td>
5228 <td>AM6_DEV_GPIO0</td>
5229 <td>gpio</td>
5230 <td>71</td>
5231 </tr>
5232 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5233 <td>100</td>
5234 <td>72</td>
5235 <td>AM6_DEV_GPIO0</td>
5236 <td>gpio</td>
5237 <td>72</td>
5238 </tr>
5239 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5240 <td>100</td>
5241 <td>73</td>
5242 <td>AM6_DEV_GPIO0</td>
5243 <td>gpio</td>
5244 <td>73</td>
5245 </tr>
5246 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5247 <td>100</td>
5248 <td>74</td>
5249 <td>AM6_DEV_GPIO0</td>
5250 <td>gpio</td>
5251 <td>74</td>
5252 </tr>
5253 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5254 <td>100</td>
5255 <td>75</td>
5256 <td>AM6_DEV_GPIO0</td>
5257 <td>gpio</td>
5258 <td>75</td>
5259 </tr>
5260 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5261 <td>100</td>
5262 <td>76</td>
5263 <td>AM6_DEV_GPIO0</td>
5264 <td>gpio</td>
5265 <td>76</td>
5266 </tr>
5267 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5268 <td>100</td>
5269 <td>77</td>
5270 <td>AM6_DEV_GPIO0</td>
5271 <td>gpio</td>
5272 <td>77</td>
5273 </tr>
5274 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5275 <td>100</td>
5276 <td>78</td>
5277 <td>AM6_DEV_GPIO0</td>
5278 <td>gpio</td>
5279 <td>78</td>
5280 </tr>
5281 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5282 <td>100</td>
5283 <td>79</td>
5284 <td>AM6_DEV_GPIO0</td>
5285 <td>gpio</td>
5286 <td>79</td>
5287 </tr>
5288 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5289 <td>100</td>
5290 <td>80</td>
5291 <td>AM6_DEV_GPIO0</td>
5292 <td>gpio</td>
5293 <td>80</td>
5294 </tr>
5295 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5296 <td>100</td>
5297 <td>81</td>
5298 <td>AM6_DEV_GPIO0</td>
5299 <td>gpio</td>
5300 <td>81</td>
5301 </tr>
5302 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5303 <td>100</td>
5304 <td>82</td>
5305 <td>AM6_DEV_GPIO0</td>
5306 <td>gpio</td>
5307 <td>82</td>
5308 </tr>
5309 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5310 <td>100</td>
5311 <td>83</td>
5312 <td>AM6_DEV_GPIO0</td>
5313 <td>gpio</td>
5314 <td>83</td>
5315 </tr>
5316 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5317 <td>100</td>
5318 <td>84</td>
5319 <td>AM6_DEV_GPIO0</td>
5320 <td>gpio</td>
5321 <td>84</td>
5322 </tr>
5323 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5324 <td>100</td>
5325 <td>85</td>
5326 <td>AM6_DEV_GPIO0</td>
5327 <td>gpio</td>
5328 <td>85</td>
5329 </tr>
5330 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5331 <td>100</td>
5332 <td>86</td>
5333 <td>AM6_DEV_GPIO0</td>
5334 <td>gpio</td>
5335 <td>86</td>
5336 </tr>
5337 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5338 <td>100</td>
5339 <td>87</td>
5340 <td>AM6_DEV_GPIO0</td>
5341 <td>gpio</td>
5342 <td>87</td>
5343 </tr>
5344 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5345 <td>100</td>
5346 <td>88</td>
5347 <td>AM6_DEV_GPIO0</td>
5348 <td>gpio</td>
5349 <td>88</td>
5350 </tr>
5351 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5352 <td>100</td>
5353 <td>89</td>
5354 <td>AM6_DEV_GPIO0</td>
5355 <td>gpio</td>
5356 <td>89</td>
5357 </tr>
5358 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5359 <td>100</td>
5360 <td>90</td>
5361 <td>AM6_DEV_GPIO0</td>
5362 <td>gpio</td>
5363 <td>90</td>
5364 </tr>
5365 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5366 <td>100</td>
5367 <td>91</td>
5368 <td>AM6_DEV_GPIO0</td>
5369 <td>gpio</td>
5370 <td>91</td>
5371 </tr>
5372 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5373 <td>100</td>
5374 <td>92</td>
5375 <td>AM6_DEV_GPIO0</td>
5376 <td>gpio</td>
5377 <td>92</td>
5378 </tr>
5379 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5380 <td>100</td>
5381 <td>93</td>
5382 <td>AM6_DEV_GPIO0</td>
5383 <td>gpio</td>
5384 <td>93</td>
5385 </tr>
5386 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5387 <td>100</td>
5388 <td>94</td>
5389 <td>AM6_DEV_GPIO0</td>
5390 <td>gpio</td>
5391 <td>94</td>
5392 </tr>
5393 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5394 <td>100</td>
5395 <td>95</td>
5396 <td>AM6_DEV_GPIO0</td>
5397 <td>gpio</td>
5398 <td>95</td>
5399 </tr>
5400 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5401 <td>100</td>
5402 <td>96</td>
5403 <td>AM6_DEV_GPIO1</td>
5404 <td>gpio</td>
5405 <td>0</td>
5406 </tr>
5407 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5408 <td>100</td>
5409 <td>97</td>
5410 <td>AM6_DEV_GPIO1</td>
5411 <td>gpio</td>
5412 <td>1</td>
5413 </tr>
5414 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5415 <td>100</td>
5416 <td>98</td>
5417 <td>AM6_DEV_GPIO1</td>
5418 <td>gpio</td>
5419 <td>2</td>
5420 </tr>
5421 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5422 <td>100</td>
5423 <td>99</td>
5424 <td>AM6_DEV_GPIO1</td>
5425 <td>gpio</td>
5426 <td>3</td>
5427 </tr>
5428 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5429 <td>100</td>
5430 <td>100</td>
5431 <td>AM6_DEV_GPIO1</td>
5432 <td>gpio</td>
5433 <td>4</td>
5434 </tr>
5435 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5436 <td>100</td>
5437 <td>101</td>
5438 <td>AM6_DEV_GPIO1</td>
5439 <td>gpio</td>
5440 <td>5</td>
5441 </tr>
5442 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5443 <td>100</td>
5444 <td>102</td>
5445 <td>AM6_DEV_GPIO1</td>
5446 <td>gpio</td>
5447 <td>6</td>
5448 </tr>
5449 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5450 <td>100</td>
5451 <td>103</td>
5452 <td>AM6_DEV_GPIO1</td>
5453 <td>gpio</td>
5454 <td>7</td>
5455 </tr>
5456 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5457 <td>100</td>
5458 <td>104</td>
5459 <td>AM6_DEV_GPIO1</td>
5460 <td>gpio</td>
5461 <td>8</td>
5462 </tr>
5463 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5464 <td>100</td>
5465 <td>105</td>
5466 <td>AM6_DEV_GPIO1</td>
5467 <td>gpio</td>
5468 <td>9</td>
5469 </tr>
5470 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5471 <td>100</td>
5472 <td>106</td>
5473 <td>AM6_DEV_GPIO1</td>
5474 <td>gpio</td>
5475 <td>10</td>
5476 </tr>
5477 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5478 <td>100</td>
5479 <td>107</td>
5480 <td>AM6_DEV_GPIO1</td>
5481 <td>gpio</td>
5482 <td>11</td>
5483 </tr>
5484 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5485 <td>100</td>
5486 <td>108</td>
5487 <td>AM6_DEV_GPIO1</td>
5488 <td>gpio</td>
5489 <td>12</td>
5490 </tr>
5491 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5492 <td>100</td>
5493 <td>109</td>
5494 <td>AM6_DEV_GPIO1</td>
5495 <td>gpio</td>
5496 <td>13</td>
5497 </tr>
5498 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5499 <td>100</td>
5500 <td>110</td>
5501 <td>AM6_DEV_GPIO1</td>
5502 <td>gpio</td>
5503 <td>14</td>
5504 </tr>
5505 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5506 <td>100</td>
5507 <td>111</td>
5508 <td>AM6_DEV_GPIO1</td>
5509 <td>gpio</td>
5510 <td>15</td>
5511 </tr>
5512 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5513 <td>100</td>
5514 <td>112</td>
5515 <td>AM6_DEV_GPIO1</td>
5516 <td>gpio</td>
5517 <td>16</td>
5518 </tr>
5519 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5520 <td>100</td>
5521 <td>113</td>
5522 <td>AM6_DEV_GPIO1</td>
5523 <td>gpio</td>
5524 <td>17</td>
5525 </tr>
5526 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5527 <td>100</td>
5528 <td>114</td>
5529 <td>AM6_DEV_GPIO1</td>
5530 <td>gpio</td>
5531 <td>18</td>
5532 </tr>
5533 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5534 <td>100</td>
5535 <td>115</td>
5536 <td>AM6_DEV_GPIO1</td>
5537 <td>gpio</td>
5538 <td>19</td>
5539 </tr>
5540 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5541 <td>100</td>
5542 <td>116</td>
5543 <td>AM6_DEV_GPIO1</td>
5544 <td>gpio</td>
5545 <td>20</td>
5546 </tr>
5547 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5548 <td>100</td>
5549 <td>117</td>
5550 <td>AM6_DEV_GPIO1</td>
5551 <td>gpio</td>
5552 <td>21</td>
5553 </tr>
5554 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5555 <td>100</td>
5556 <td>118</td>
5557 <td>AM6_DEV_GPIO1</td>
5558 <td>gpio</td>
5559 <td>22</td>
5560 </tr>
5561 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5562 <td>100</td>
5563 <td>119</td>
5564 <td>AM6_DEV_GPIO1</td>
5565 <td>gpio</td>
5566 <td>23</td>
5567 </tr>
5568 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5569 <td>100</td>
5570 <td>120</td>
5571 <td>AM6_DEV_GPIO1</td>
5572 <td>gpio</td>
5573 <td>24</td>
5574 </tr>
5575 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5576 <td>100</td>
5577 <td>121</td>
5578 <td>AM6_DEV_GPIO1</td>
5579 <td>gpio</td>
5580 <td>25</td>
5581 </tr>
5582 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5583 <td>100</td>
5584 <td>122</td>
5585 <td>AM6_DEV_GPIO1</td>
5586 <td>gpio</td>
5587 <td>26</td>
5588 </tr>
5589 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5590 <td>100</td>
5591 <td>123</td>
5592 <td>AM6_DEV_GPIO1</td>
5593 <td>gpio</td>
5594 <td>27</td>
5595 </tr>
5596 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5597 <td>100</td>
5598 <td>124</td>
5599 <td>AM6_DEV_GPIO1</td>
5600 <td>gpio</td>
5601 <td>28</td>
5602 </tr>
5603 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5604 <td>100</td>
5605 <td>125</td>
5606 <td>AM6_DEV_GPIO1</td>
5607 <td>gpio</td>
5608 <td>29</td>
5609 </tr>
5610 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5611 <td>100</td>
5612 <td>126</td>
5613 <td>AM6_DEV_GPIO1</td>
5614 <td>gpio</td>
5615 <td>30</td>
5616 </tr>
5617 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5618 <td>100</td>
5619 <td>127</td>
5620 <td>AM6_DEV_GPIO1</td>
5621 <td>gpio</td>
5622 <td>31</td>
5623 </tr>
5624 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5625 <td>100</td>
5626 <td>128</td>
5627 <td>AM6_DEV_GPIO1</td>
5628 <td>gpio</td>
5629 <td>32</td>
5630 </tr>
5631 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5632 <td>100</td>
5633 <td>129</td>
5634 <td>AM6_DEV_GPIO1</td>
5635 <td>gpio</td>
5636 <td>33</td>
5637 </tr>
5638 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5639 <td>100</td>
5640 <td>130</td>
5641 <td>AM6_DEV_GPIO1</td>
5642 <td>gpio</td>
5643 <td>34</td>
5644 </tr>
5645 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5646 <td>100</td>
5647 <td>131</td>
5648 <td>AM6_DEV_GPIO1</td>
5649 <td>gpio</td>
5650 <td>35</td>
5651 </tr>
5652 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5653 <td>100</td>
5654 <td>132</td>
5655 <td>AM6_DEV_GPIO1</td>
5656 <td>gpio</td>
5657 <td>36</td>
5658 </tr>
5659 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5660 <td>100</td>
5661 <td>133</td>
5662 <td>AM6_DEV_GPIO1</td>
5663 <td>gpio</td>
5664 <td>37</td>
5665 </tr>
5666 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5667 <td>100</td>
5668 <td>134</td>
5669 <td>AM6_DEV_GPIO1</td>
5670 <td>gpio</td>
5671 <td>38</td>
5672 </tr>
5673 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5674 <td>100</td>
5675 <td>135</td>
5676 <td>AM6_DEV_GPIO1</td>
5677 <td>gpio</td>
5678 <td>39</td>
5679 </tr>
5680 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5681 <td>100</td>
5682 <td>136</td>
5683 <td>AM6_DEV_GPIO1</td>
5684 <td>gpio</td>
5685 <td>40</td>
5686 </tr>
5687 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5688 <td>100</td>
5689 <td>137</td>
5690 <td>AM6_DEV_GPIO1</td>
5691 <td>gpio</td>
5692 <td>41</td>
5693 </tr>
5694 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5695 <td>100</td>
5696 <td>138</td>
5697 <td>AM6_DEV_GPIO1</td>
5698 <td>gpio</td>
5699 <td>42</td>
5700 </tr>
5701 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5702 <td>100</td>
5703 <td>139</td>
5704 <td>AM6_DEV_GPIO1</td>
5705 <td>gpio</td>
5706 <td>43</td>
5707 </tr>
5708 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5709 <td>100</td>
5710 <td>140</td>
5711 <td>AM6_DEV_GPIO1</td>
5712 <td>gpio</td>
5713 <td>44</td>
5714 </tr>
5715 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5716 <td>100</td>
5717 <td>141</td>
5718 <td>AM6_DEV_GPIO1</td>
5719 <td>gpio</td>
5720 <td>45</td>
5721 </tr>
5722 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5723 <td>100</td>
5724 <td>142</td>
5725 <td>AM6_DEV_GPIO1</td>
5726 <td>gpio</td>
5727 <td>46</td>
5728 </tr>
5729 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5730 <td>100</td>
5731 <td>143</td>
5732 <td>AM6_DEV_GPIO1</td>
5733 <td>gpio</td>
5734 <td>47</td>
5735 </tr>
5736 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5737 <td>100</td>
5738 <td>144</td>
5739 <td>AM6_DEV_GPIO1</td>
5740 <td>gpio</td>
5741 <td>48</td>
5742 </tr>
5743 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5744 <td>100</td>
5745 <td>145</td>
5746 <td>AM6_DEV_GPIO1</td>
5747 <td>gpio</td>
5748 <td>49</td>
5749 </tr>
5750 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5751 <td>100</td>
5752 <td>146</td>
5753 <td>AM6_DEV_GPIO1</td>
5754 <td>gpio</td>
5755 <td>50</td>
5756 </tr>
5757 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5758 <td>100</td>
5759 <td>147</td>
5760 <td>AM6_DEV_GPIO1</td>
5761 <td>gpio</td>
5762 <td>51</td>
5763 </tr>
5764 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5765 <td>100</td>
5766 <td>148</td>
5767 <td>AM6_DEV_GPIO1</td>
5768 <td>gpio</td>
5769 <td>52</td>
5770 </tr>
5771 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5772 <td>100</td>
5773 <td>149</td>
5774 <td>AM6_DEV_GPIO1</td>
5775 <td>gpio</td>
5776 <td>53</td>
5777 </tr>
5778 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5779 <td>100</td>
5780 <td>150</td>
5781 <td>AM6_DEV_GPIO1</td>
5782 <td>gpio</td>
5783 <td>54</td>
5784 </tr>
5785 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5786 <td>100</td>
5787 <td>151</td>
5788 <td>AM6_DEV_GPIO1</td>
5789 <td>gpio</td>
5790 <td>55</td>
5791 </tr>
5792 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5793 <td>100</td>
5794 <td>152</td>
5795 <td>AM6_DEV_GPIO1</td>
5796 <td>gpio</td>
5797 <td>56</td>
5798 </tr>
5799 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5800 <td>100</td>
5801 <td>153</td>
5802 <td>AM6_DEV_GPIO1</td>
5803 <td>gpio</td>
5804 <td>57</td>
5805 </tr>
5806 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5807 <td>100</td>
5808 <td>154</td>
5809 <td>AM6_DEV_GPIO1</td>
5810 <td>gpio</td>
5811 <td>58</td>
5812 </tr>
5813 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5814 <td>100</td>
5815 <td>155</td>
5816 <td>AM6_DEV_GPIO1</td>
5817 <td>gpio</td>
5818 <td>59</td>
5819 </tr>
5820 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5821 <td>100</td>
5822 <td>156</td>
5823 <td>AM6_DEV_GPIO1</td>
5824 <td>gpio</td>
5825 <td>60</td>
5826 </tr>
5827 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5828 <td>100</td>
5829 <td>157</td>
5830 <td>AM6_DEV_GPIO1</td>
5831 <td>gpio</td>
5832 <td>61</td>
5833 </tr>
5834 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5835 <td>100</td>
5836 <td>158</td>
5837 <td>AM6_DEV_GPIO1</td>
5838 <td>gpio</td>
5839 <td>62</td>
5840 </tr>
5841 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5842 <td>100</td>
5843 <td>159</td>
5844 <td>AM6_DEV_GPIO1</td>
5845 <td>gpio</td>
5846 <td>63</td>
5847 </tr>
5848 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5849 <td>100</td>
5850 <td>160</td>
5851 <td>AM6_DEV_GPIO1</td>
5852 <td>gpio</td>
5853 <td>64</td>
5854 </tr>
5855 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5856 <td>100</td>
5857 <td>161</td>
5858 <td>AM6_DEV_GPIO1</td>
5859 <td>gpio</td>
5860 <td>65</td>
5861 </tr>
5862 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5863 <td>100</td>
5864 <td>162</td>
5865 <td>AM6_DEV_GPIO1</td>
5866 <td>gpio</td>
5867 <td>66</td>
5868 </tr>
5869 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5870 <td>100</td>
5871 <td>163</td>
5872 <td>AM6_DEV_GPIO1</td>
5873 <td>gpio</td>
5874 <td>67</td>
5875 </tr>
5876 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5877 <td>100</td>
5878 <td>164</td>
5879 <td>AM6_DEV_GPIO1</td>
5880 <td>gpio</td>
5881 <td>68</td>
5882 </tr>
5883 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5884 <td>100</td>
5885 <td>165</td>
5886 <td>AM6_DEV_GPIO1</td>
5887 <td>gpio</td>
5888 <td>69</td>
5889 </tr>
5890 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5891 <td>100</td>
5892 <td>166</td>
5893 <td>AM6_DEV_GPIO1</td>
5894 <td>gpio</td>
5895 <td>70</td>
5896 </tr>
5897 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5898 <td>100</td>
5899 <td>167</td>
5900 <td>AM6_DEV_GPIO1</td>
5901 <td>gpio</td>
5902 <td>71</td>
5903 </tr>
5904 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5905 <td>100</td>
5906 <td>168</td>
5907 <td>AM6_DEV_GPIO1</td>
5908 <td>gpio</td>
5909 <td>72</td>
5910 </tr>
5911 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5912 <td>100</td>
5913 <td>169</td>
5914 <td>AM6_DEV_GPIO1</td>
5915 <td>gpio</td>
5916 <td>73</td>
5917 </tr>
5918 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5919 <td>100</td>
5920 <td>170</td>
5921 <td>AM6_DEV_GPIO1</td>
5922 <td>gpio</td>
5923 <td>74</td>
5924 </tr>
5925 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5926 <td>100</td>
5927 <td>171</td>
5928 <td>AM6_DEV_GPIO1</td>
5929 <td>gpio</td>
5930 <td>75</td>
5931 </tr>
5932 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5933 <td>100</td>
5934 <td>172</td>
5935 <td>AM6_DEV_GPIO1</td>
5936 <td>gpio</td>
5937 <td>76</td>
5938 </tr>
5939 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5940 <td>100</td>
5941 <td>173</td>
5942 <td>AM6_DEV_GPIO1</td>
5943 <td>gpio</td>
5944 <td>77</td>
5945 </tr>
5946 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5947 <td>100</td>
5948 <td>174</td>
5949 <td>AM6_DEV_GPIO1</td>
5950 <td>gpio</td>
5951 <td>78</td>
5952 </tr>
5953 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5954 <td>100</td>
5955 <td>175</td>
5956 <td>AM6_DEV_GPIO1</td>
5957 <td>gpio</td>
5958 <td>79</td>
5959 </tr>
5960 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5961 <td>100</td>
5962 <td>176</td>
5963 <td>AM6_DEV_GPIO1</td>
5964 <td>gpio</td>
5965 <td>80</td>
5966 </tr>
5967 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5968 <td>100</td>
5969 <td>177</td>
5970 <td>AM6_DEV_GPIO1</td>
5971 <td>gpio</td>
5972 <td>81</td>
5973 </tr>
5974 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5975 <td>100</td>
5976 <td>178</td>
5977 <td>AM6_DEV_GPIO1</td>
5978 <td>gpio</td>
5979 <td>82</td>
5980 </tr>
5981 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5982 <td>100</td>
5983 <td>179</td>
5984 <td>AM6_DEV_GPIO1</td>
5985 <td>gpio</td>
5986 <td>83</td>
5987 </tr>
5988 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5989 <td>100</td>
5990 <td>180</td>
5991 <td>AM6_DEV_GPIO1</td>
5992 <td>gpio</td>
5993 <td>84</td>
5994 </tr>
5995 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
5996 <td>100</td>
5997 <td>181</td>
5998 <td>AM6_DEV_GPIO1</td>
5999 <td>gpio</td>
6000 <td>85</td>
6001 </tr>
6002 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6003 <td>100</td>
6004 <td>182</td>
6005 <td>AM6_DEV_GPIO1</td>
6006 <td>gpio</td>
6007 <td>86</td>
6008 </tr>
6009 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6010 <td>100</td>
6011 <td>183</td>
6012 <td>AM6_DEV_GPIO1</td>
6013 <td>gpio</td>
6014 <td>87</td>
6015 </tr>
6016 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6017 <td>100</td>
6018 <td>184</td>
6019 <td>AM6_DEV_GPIO1</td>
6020 <td>gpio</td>
6021 <td>88</td>
6022 </tr>
6023 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6024 <td>100</td>
6025 <td>185</td>
6026 <td>AM6_DEV_GPIO1</td>
6027 <td>gpio</td>
6028 <td>89</td>
6029 </tr>
6030 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6031 <td>100</td>
6032 <td>186</td>
6033 <td>Not Connected</td>
6034 <td>&#160;</td>
6035 <td>&#160;</td>
6036 </tr>
6037 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6038 <td>100</td>
6039 <td>187</td>
6040 <td>Not Connected</td>
6041 <td>&#160;</td>
6042 <td>&#160;</td>
6043 </tr>
6044 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6045 <td>100</td>
6046 <td>188</td>
6047 <td>Not Connected</td>
6048 <td>&#160;</td>
6049 <td>&#160;</td>
6050 </tr>
6051 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6052 <td>100</td>
6053 <td>189</td>
6054 <td>Not Connected</td>
6055 <td>&#160;</td>
6056 <td>&#160;</td>
6057 </tr>
6058 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6059 <td>100</td>
6060 <td>190</td>
6061 <td>Not Connected</td>
6062 <td>&#160;</td>
6063 <td>&#160;</td>
6064 </tr>
6065 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6066 <td>100</td>
6067 <td>191</td>
6068 <td>Not Connected</td>
6069 <td>&#160;</td>
6070 <td>&#160;</td>
6071 </tr>
6072 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6073 <td>100</td>
6074 <td>192</td>
6075 <td>AM6_DEV_GPIO0</td>
6076 <td>gpio_bank</td>
6077 <td>0</td>
6078 </tr>
6079 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6080 <td>100</td>
6081 <td>193</td>
6082 <td>AM6_DEV_GPIO0</td>
6083 <td>gpio_bank</td>
6084 <td>1</td>
6085 </tr>
6086 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6087 <td>100</td>
6088 <td>194</td>
6089 <td>AM6_DEV_GPIO0</td>
6090 <td>gpio_bank</td>
6091 <td>2</td>
6092 </tr>
6093 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6094 <td>100</td>
6095 <td>195</td>
6096 <td>AM6_DEV_GPIO0</td>
6097 <td>gpio_bank</td>
6098 <td>3</td>
6099 </tr>
6100 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6101 <td>100</td>
6102 <td>196</td>
6103 <td>AM6_DEV_GPIO0</td>
6104 <td>gpio_bank</td>
6105 <td>4</td>
6106 </tr>
6107 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6108 <td>100</td>
6109 <td>197</td>
6110 <td>AM6_DEV_GPIO0</td>
6111 <td>gpio_bank</td>
6112 <td>5</td>
6113 </tr>
6114 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6115 <td>100</td>
6116 <td>198</td>
6117 <td>Not Connected</td>
6118 <td>&#160;</td>
6119 <td>&#160;</td>
6120 </tr>
6121 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6122 <td>100</td>
6123 <td>199</td>
6124 <td>Not Connected</td>
6125 <td>&#160;</td>
6126 <td>&#160;</td>
6127 </tr>
6128 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6129 <td>100</td>
6130 <td>200</td>
6131 <td>AM6_DEV_GPIO1</td>
6132 <td>gpio_bank</td>
6133 <td>0</td>
6134 </tr>
6135 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6136 <td>100</td>
6137 <td>201</td>
6138 <td>AM6_DEV_GPIO1</td>
6139 <td>gpio_bank</td>
6140 <td>1</td>
6141 </tr>
6142 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6143 <td>100</td>
6144 <td>202</td>
6145 <td>AM6_DEV_GPIO1</td>
6146 <td>gpio_bank</td>
6147 <td>2</td>
6148 </tr>
6149 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6150 <td>100</td>
6151 <td>203</td>
6152 <td>AM6_DEV_GPIO1</td>
6153 <td>gpio_bank</td>
6154 <td>3</td>
6155 </tr>
6156 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6157 <td>100</td>
6158 <td>204</td>
6159 <td>AM6_DEV_GPIO1</td>
6160 <td>gpio_bank</td>
6161 <td>4</td>
6162 </tr>
6163 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6164 <td>100</td>
6165 <td>205</td>
6166 <td>AM6_DEV_GPIO1</td>
6167 <td>gpio_bank</td>
6168 <td>5</td>
6169 </tr>
6170 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6171 <td>100</td>
6172 <td>206</td>
6173 <td>Not Connected</td>
6174 <td>&#160;</td>
6175 <td>&#160;</td>
6176 </tr>
6177 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6178 <td>100</td>
6179 <td>207</td>
6180 <td>Not Connected</td>
6181 <td>&#160;</td>
6182 <td>&#160;</td>
6183 </tr>
6184 </tbody>
6185 </table>
6186 </div>
6187 <div class="section" id="gpiomux-intrtr0-interrupt-router-output-destinations">
6188 <span id="pub-soc-am65x-sr2-gpiomux-intrtr0-output-src-list"></span><h2>GPIOMUX_INTRTR0 Interrupt Router Output Destinations<a class="headerlink" href="#gpiomux-intrtr0-interrupt-router-output-destinations" title="Permalink to this headline">¶</a></h2>
6189 <div class="admonition warning">
6190 <p class="first admonition-title">Warning</p>
6191 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
6192 host within the RM Board Configuration resource assignment array.  The RM
6193 Board Configuration is rejected if an overlap with a reserved resource is
6194 detected.</p>
6195 </div>
6196 <table border="1" class="docutils">
6197 <colgroup>
6198 <col width="20%" />
6199 <col width="13%" />
6200 <col width="15%" />
6201 <col width="16%" />
6202 <col width="20%" />
6203 <col width="17%" />
6204 </colgroup>
6205 <thead valign="bottom">
6206 <tr class="row-odd"><th class="head">IR Name</th>
6207 <th class="head">IR Device ID</th>
6208 <th class="head">IR Output Index</th>
6209 <th class="head">Destination Name</th>
6210 <th class="head">Destination Interface</th>
6211 <th class="head">Destination Index</th>
6212 </tr>
6213 </thead>
6214 <tbody valign="top">
6215 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6216 <td>100</td>
6217 <td>0</td>
6218 <td>AM6_DEV_ESM0</td>
6219 <td>esm_pls_event0</td>
6220 <td>248</td>
6221 </tr>
6222 <tr class="row-odd"><td>&#160;</td>
6223 <td>&#160;</td>
6224 <td>&#160;</td>
6225 <td>AM6_DEV_ESM0</td>
6226 <td>esm_pls_event1</td>
6227 <td>248</td>
6228 </tr>
6229 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6230 <td>100</td>
6231 <td>0</td>
6232 <td>AM6_DEV_ESM0</td>
6233 <td>esm_pls_event2</td>
6234 <td>248</td>
6235 </tr>
6236 <tr class="row-odd"><td>&#160;</td>
6237 <td>&#160;</td>
6238 <td>&#160;</td>
6239 <td>AM6_DEV_GIC0</td>
6240 <td>spi</td>
6241 <td>392</td>
6242 </tr>
6243 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6244 <td>100</td>
6245 <td>1</td>
6246 <td>AM6_DEV_ESM0</td>
6247 <td>esm_pls_event0</td>
6248 <td>249</td>
6249 </tr>
6250 <tr class="row-odd"><td>&#160;</td>
6251 <td>&#160;</td>
6252 <td>&#160;</td>
6253 <td>AM6_DEV_ESM0</td>
6254 <td>esm_pls_event1</td>
6255 <td>249</td>
6256 </tr>
6257 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6258 <td>100</td>
6259 <td>1</td>
6260 <td>AM6_DEV_ESM0</td>
6261 <td>esm_pls_event2</td>
6262 <td>249</td>
6263 </tr>
6264 <tr class="row-odd"><td>&#160;</td>
6265 <td>&#160;</td>
6266 <td>&#160;</td>
6267 <td>AM6_DEV_GIC0</td>
6268 <td>spi</td>
6269 <td>393</td>
6270 </tr>
6271 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6272 <td>100</td>
6273 <td>2</td>
6274 <td>AM6_DEV_ESM0</td>
6275 <td>esm_pls_event0</td>
6276 <td>250</td>
6277 </tr>
6278 <tr class="row-odd"><td>&#160;</td>
6279 <td>&#160;</td>
6280 <td>&#160;</td>
6281 <td>AM6_DEV_ESM0</td>
6282 <td>esm_pls_event1</td>
6283 <td>250</td>
6284 </tr>
6285 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6286 <td>100</td>
6287 <td>2</td>
6288 <td>AM6_DEV_ESM0</td>
6289 <td>esm_pls_event2</td>
6290 <td>250</td>
6291 </tr>
6292 <tr class="row-odd"><td>&#160;</td>
6293 <td>&#160;</td>
6294 <td>&#160;</td>
6295 <td>AM6_DEV_GIC0</td>
6296 <td>spi</td>
6297 <td>394</td>
6298 </tr>
6299 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6300 <td>100</td>
6301 <td>3</td>
6302 <td>AM6_DEV_ESM0</td>
6303 <td>esm_pls_event0</td>
6304 <td>251</td>
6305 </tr>
6306 <tr class="row-odd"><td>&#160;</td>
6307 <td>&#160;</td>
6308 <td>&#160;</td>
6309 <td>AM6_DEV_ESM0</td>
6310 <td>esm_pls_event1</td>
6311 <td>251</td>
6312 </tr>
6313 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6314 <td>100</td>
6315 <td>3</td>
6316 <td>AM6_DEV_ESM0</td>
6317 <td>esm_pls_event2</td>
6318 <td>251</td>
6319 </tr>
6320 <tr class="row-odd"><td>&#160;</td>
6321 <td>&#160;</td>
6322 <td>&#160;</td>
6323 <td>AM6_DEV_GIC0</td>
6324 <td>spi</td>
6325 <td>395</td>
6326 </tr>
6327 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6328 <td>100</td>
6329 <td>4</td>
6330 <td>AM6_DEV_ESM0</td>
6331 <td>esm_pls_event0</td>
6332 <td>252</td>
6333 </tr>
6334 <tr class="row-odd"><td>&#160;</td>
6335 <td>&#160;</td>
6336 <td>&#160;</td>
6337 <td>AM6_DEV_ESM0</td>
6338 <td>esm_pls_event1</td>
6339 <td>252</td>
6340 </tr>
6341 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6342 <td>100</td>
6343 <td>4</td>
6344 <td>AM6_DEV_ESM0</td>
6345 <td>esm_pls_event2</td>
6346 <td>252</td>
6347 </tr>
6348 <tr class="row-odd"><td>&#160;</td>
6349 <td>&#160;</td>
6350 <td>&#160;</td>
6351 <td>AM6_DEV_GIC0</td>
6352 <td>spi</td>
6353 <td>396</td>
6354 </tr>
6355 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6356 <td>100</td>
6357 <td>5</td>
6358 <td>AM6_DEV_ESM0</td>
6359 <td>esm_pls_event0</td>
6360 <td>253</td>
6361 </tr>
6362 <tr class="row-odd"><td>&#160;</td>
6363 <td>&#160;</td>
6364 <td>&#160;</td>
6365 <td>AM6_DEV_ESM0</td>
6366 <td>esm_pls_event1</td>
6367 <td>253</td>
6368 </tr>
6369 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6370 <td>100</td>
6371 <td>5</td>
6372 <td>AM6_DEV_ESM0</td>
6373 <td>esm_pls_event2</td>
6374 <td>253</td>
6375 </tr>
6376 <tr class="row-odd"><td>&#160;</td>
6377 <td>&#160;</td>
6378 <td>&#160;</td>
6379 <td>AM6_DEV_GIC0</td>
6380 <td>spi</td>
6381 <td>397</td>
6382 </tr>
6383 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6384 <td>100</td>
6385 <td>6</td>
6386 <td>AM6_DEV_ESM0</td>
6387 <td>esm_pls_event0</td>
6388 <td>254</td>
6389 </tr>
6390 <tr class="row-odd"><td>&#160;</td>
6391 <td>&#160;</td>
6392 <td>&#160;</td>
6393 <td>AM6_DEV_ESM0</td>
6394 <td>esm_pls_event1</td>
6395 <td>254</td>
6396 </tr>
6397 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6398 <td>100</td>
6399 <td>6</td>
6400 <td>AM6_DEV_ESM0</td>
6401 <td>esm_pls_event2</td>
6402 <td>254</td>
6403 </tr>
6404 <tr class="row-odd"><td>&#160;</td>
6405 <td>&#160;</td>
6406 <td>&#160;</td>
6407 <td>AM6_DEV_GIC0</td>
6408 <td>spi</td>
6409 <td>398</td>
6410 </tr>
6411 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6412 <td>100</td>
6413 <td>7</td>
6414 <td>AM6_DEV_ESM0</td>
6415 <td>esm_pls_event0</td>
6416 <td>255</td>
6417 </tr>
6418 <tr class="row-odd"><td>&#160;</td>
6419 <td>&#160;</td>
6420 <td>&#160;</td>
6421 <td>AM6_DEV_ESM0</td>
6422 <td>esm_pls_event1</td>
6423 <td>255</td>
6424 </tr>
6425 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6426 <td>100</td>
6427 <td>7</td>
6428 <td>AM6_DEV_ESM0</td>
6429 <td>esm_pls_event2</td>
6430 <td>255</td>
6431 </tr>
6432 <tr class="row-odd"><td>&#160;</td>
6433 <td>&#160;</td>
6434 <td>&#160;</td>
6435 <td>AM6_DEV_GIC0</td>
6436 <td>spi</td>
6437 <td>399</td>
6438 </tr>
6439 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6440 <td>100</td>
6441 <td>8</td>
6442 <td>AM6_DEV_GIC0</td>
6443 <td>spi</td>
6444 <td>400</td>
6445 </tr>
6446 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6447 <td>100</td>
6448 <td>9</td>
6449 <td>AM6_DEV_GIC0</td>
6450 <td>spi</td>
6451 <td>401</td>
6452 </tr>
6453 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6454 <td>100</td>
6455 <td>10</td>
6456 <td>AM6_DEV_GIC0</td>
6457 <td>spi</td>
6458 <td>402</td>
6459 </tr>
6460 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6461 <td>100</td>
6462 <td>11</td>
6463 <td>AM6_DEV_GIC0</td>
6464 <td>spi</td>
6465 <td>403</td>
6466 </tr>
6467 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6468 <td>100</td>
6469 <td>12</td>
6470 <td>AM6_DEV_GIC0</td>
6471 <td>spi</td>
6472 <td>404</td>
6473 </tr>
6474 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6475 <td>100</td>
6476 <td>13</td>
6477 <td>AM6_DEV_GIC0</td>
6478 <td>spi</td>
6479 <td>405</td>
6480 </tr>
6481 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6482 <td>100</td>
6483 <td>14</td>
6484 <td>AM6_DEV_GIC0</td>
6485 <td>spi</td>
6486 <td>406</td>
6487 </tr>
6488 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6489 <td>100</td>
6490 <td>15</td>
6491 <td>AM6_DEV_GIC0</td>
6492 <td>spi</td>
6493 <td>407</td>
6494 </tr>
6495 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6496 <td>100</td>
6497 <td>16</td>
6498 <td>AM6_DEV_GIC0</td>
6499 <td>spi</td>
6500 <td>408</td>
6501 </tr>
6502 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6503 <td>100</td>
6504 <td>17</td>
6505 <td>AM6_DEV_GIC0</td>
6506 <td>spi</td>
6507 <td>409</td>
6508 </tr>
6509 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6510 <td>100</td>
6511 <td>18</td>
6512 <td>AM6_DEV_GIC0</td>
6513 <td>spi</td>
6514 <td>410</td>
6515 </tr>
6516 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6517 <td>100</td>
6518 <td>19</td>
6519 <td>AM6_DEV_GIC0</td>
6520 <td>spi</td>
6521 <td>411</td>
6522 </tr>
6523 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6524 <td>100</td>
6525 <td>20</td>
6526 <td>AM6_DEV_GIC0</td>
6527 <td>spi</td>
6528 <td>412</td>
6529 </tr>
6530 <tr class="row-odd"><td>&#160;</td>
6531 <td>&#160;</td>
6532 <td>&#160;</td>
6533 <td>AM6_DEV_PRU_ICSSG0</td>
6534 <td>pr1_iep0_cap_intr_req</td>
6535 <td>0</td>
6536 </tr>
6537 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6538 <td>100</td>
6539 <td>20</td>
6540 <td>AM6_DEV_PRU_ICSSG1</td>
6541 <td>pr1_iep0_cap_intr_req</td>
6542 <td>0</td>
6543 </tr>
6544 <tr class="row-odd"><td>&#160;</td>
6545 <td>&#160;</td>
6546 <td>&#160;</td>
6547 <td>AM6_DEV_PRU_ICSSG2</td>
6548 <td>pr1_iep0_cap_intr_req</td>
6549 <td>0</td>
6550 </tr>
6551 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6552 <td>100</td>
6553 <td>21</td>
6554 <td>AM6_DEV_GIC0</td>
6555 <td>spi</td>
6556 <td>413</td>
6557 </tr>
6558 <tr class="row-odd"><td>&#160;</td>
6559 <td>&#160;</td>
6560 <td>&#160;</td>
6561 <td>AM6_DEV_PRU_ICSSG0</td>
6562 <td>pr1_iep0_cap_intr_req</td>
6563 <td>1</td>
6564 </tr>
6565 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6566 <td>100</td>
6567 <td>21</td>
6568 <td>AM6_DEV_PRU_ICSSG1</td>
6569 <td>pr1_iep0_cap_intr_req</td>
6570 <td>1</td>
6571 </tr>
6572 <tr class="row-odd"><td>&#160;</td>
6573 <td>&#160;</td>
6574 <td>&#160;</td>
6575 <td>AM6_DEV_PRU_ICSSG2</td>
6576 <td>pr1_iep0_cap_intr_req</td>
6577 <td>1</td>
6578 </tr>
6579 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6580 <td>100</td>
6581 <td>22</td>
6582 <td>AM6_DEV_GIC0</td>
6583 <td>spi</td>
6584 <td>414</td>
6585 </tr>
6586 <tr class="row-odd"><td>&#160;</td>
6587 <td>&#160;</td>
6588 <td>&#160;</td>
6589 <td>AM6_DEV_PRU_ICSSG0</td>
6590 <td>pr1_iep0_cap_intr_req</td>
6591 <td>2</td>
6592 </tr>
6593 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6594 <td>100</td>
6595 <td>22</td>
6596 <td>AM6_DEV_PRU_ICSSG1</td>
6597 <td>pr1_iep0_cap_intr_req</td>
6598 <td>2</td>
6599 </tr>
6600 <tr class="row-odd"><td>&#160;</td>
6601 <td>&#160;</td>
6602 <td>&#160;</td>
6603 <td>AM6_DEV_PRU_ICSSG2</td>
6604 <td>pr1_iep0_cap_intr_req</td>
6605 <td>2</td>
6606 </tr>
6607 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6608 <td>100</td>
6609 <td>23</td>
6610 <td>AM6_DEV_GIC0</td>
6611 <td>spi</td>
6612 <td>415</td>
6613 </tr>
6614 <tr class="row-odd"><td>&#160;</td>
6615 <td>&#160;</td>
6616 <td>&#160;</td>
6617 <td>AM6_DEV_PRU_ICSSG0</td>
6618 <td>pr1_iep0_cap_intr_req</td>
6619 <td>3</td>
6620 </tr>
6621 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6622 <td>100</td>
6623 <td>23</td>
6624 <td>AM6_DEV_PRU_ICSSG1</td>
6625 <td>pr1_iep0_cap_intr_req</td>
6626 <td>3</td>
6627 </tr>
6628 <tr class="row-odd"><td>&#160;</td>
6629 <td>&#160;</td>
6630 <td>&#160;</td>
6631 <td>AM6_DEV_PRU_ICSSG2</td>
6632 <td>pr1_iep0_cap_intr_req</td>
6633 <td>3</td>
6634 </tr>
6635 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6636 <td>100</td>
6637 <td>24</td>
6638 <td>AM6_DEV_GIC0</td>
6639 <td>spi</td>
6640 <td>416</td>
6641 </tr>
6642 <tr class="row-odd"><td>&#160;</td>
6643 <td>&#160;</td>
6644 <td>&#160;</td>
6645 <td>AM6_DEV_PRU_ICSSG0</td>
6646 <td>pr1_iep0_cap_intr_req</td>
6647 <td>4</td>
6648 </tr>
6649 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6650 <td>100</td>
6651 <td>24</td>
6652 <td>AM6_DEV_PRU_ICSSG0</td>
6653 <td>pr1_slv_intr</td>
6654 <td>88</td>
6655 </tr>
6656 <tr class="row-odd"><td>&#160;</td>
6657 <td>&#160;</td>
6658 <td>&#160;</td>
6659 <td>AM6_DEV_PRU_ICSSG1</td>
6660 <td>pr1_iep0_cap_intr_req</td>
6661 <td>4</td>
6662 </tr>
6663 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6664 <td>100</td>
6665 <td>24</td>
6666 <td>AM6_DEV_PRU_ICSSG1</td>
6667 <td>pr1_slv_intr</td>
6668 <td>88</td>
6669 </tr>
6670 <tr class="row-odd"><td>&#160;</td>
6671 <td>&#160;</td>
6672 <td>&#160;</td>
6673 <td>AM6_DEV_PRU_ICSSG2</td>
6674 <td>pr1_iep0_cap_intr_req</td>
6675 <td>4</td>
6676 </tr>
6677 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6678 <td>100</td>
6679 <td>24</td>
6680 <td>AM6_DEV_PRU_ICSSG2</td>
6681 <td>pr1_slv_intr</td>
6682 <td>88</td>
6683 </tr>
6684 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6685 <td>100</td>
6686 <td>25</td>
6687 <td>AM6_DEV_GIC0</td>
6688 <td>spi</td>
6689 <td>417</td>
6690 </tr>
6691 <tr class="row-even"><td>&#160;</td>
6692 <td>&#160;</td>
6693 <td>&#160;</td>
6694 <td>AM6_DEV_PRU_ICSSG0</td>
6695 <td>pr1_iep0_cap_intr_req</td>
6696 <td>5</td>
6697 </tr>
6698 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6699 <td>100</td>
6700 <td>25</td>
6701 <td>AM6_DEV_PRU_ICSSG0</td>
6702 <td>pr1_slv_intr</td>
6703 <td>89</td>
6704 </tr>
6705 <tr class="row-even"><td>&#160;</td>
6706 <td>&#160;</td>
6707 <td>&#160;</td>
6708 <td>AM6_DEV_PRU_ICSSG1</td>
6709 <td>pr1_iep0_cap_intr_req</td>
6710 <td>5</td>
6711 </tr>
6712 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6713 <td>100</td>
6714 <td>25</td>
6715 <td>AM6_DEV_PRU_ICSSG1</td>
6716 <td>pr1_slv_intr</td>
6717 <td>89</td>
6718 </tr>
6719 <tr class="row-even"><td>&#160;</td>
6720 <td>&#160;</td>
6721 <td>&#160;</td>
6722 <td>AM6_DEV_PRU_ICSSG2</td>
6723 <td>pr1_iep0_cap_intr_req</td>
6724 <td>5</td>
6725 </tr>
6726 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6727 <td>100</td>
6728 <td>25</td>
6729 <td>AM6_DEV_PRU_ICSSG2</td>
6730 <td>pr1_slv_intr</td>
6731 <td>89</td>
6732 </tr>
6733 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6734 <td>100</td>
6735 <td>26</td>
6736 <td>AM6_DEV_GIC0</td>
6737 <td>spi</td>
6738 <td>418</td>
6739 </tr>
6740 <tr class="row-odd"><td>&#160;</td>
6741 <td>&#160;</td>
6742 <td>&#160;</td>
6743 <td>AM6_DEV_PRU_ICSSG0</td>
6744 <td>pr1_iep1_cap_intr_req</td>
6745 <td>0</td>
6746 </tr>
6747 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6748 <td>100</td>
6749 <td>26</td>
6750 <td>AM6_DEV_PRU_ICSSG0</td>
6751 <td>pr1_slv_intr</td>
6752 <td>90</td>
6753 </tr>
6754 <tr class="row-odd"><td>&#160;</td>
6755 <td>&#160;</td>
6756 <td>&#160;</td>
6757 <td>AM6_DEV_PRU_ICSSG1</td>
6758 <td>pr1_iep1_cap_intr_req</td>
6759 <td>0</td>
6760 </tr>
6761 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6762 <td>100</td>
6763 <td>26</td>
6764 <td>AM6_DEV_PRU_ICSSG1</td>
6765 <td>pr1_slv_intr</td>
6766 <td>90</td>
6767 </tr>
6768 <tr class="row-odd"><td>&#160;</td>
6769 <td>&#160;</td>
6770 <td>&#160;</td>
6771 <td>AM6_DEV_PRU_ICSSG2</td>
6772 <td>pr1_iep1_cap_intr_req</td>
6773 <td>0</td>
6774 </tr>
6775 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6776 <td>100</td>
6777 <td>26</td>
6778 <td>AM6_DEV_PRU_ICSSG2</td>
6779 <td>pr1_slv_intr</td>
6780 <td>90</td>
6781 </tr>
6782 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6783 <td>100</td>
6784 <td>27</td>
6785 <td>AM6_DEV_GIC0</td>
6786 <td>spi</td>
6787 <td>419</td>
6788 </tr>
6789 <tr class="row-even"><td>&#160;</td>
6790 <td>&#160;</td>
6791 <td>&#160;</td>
6792 <td>AM6_DEV_PRU_ICSSG0</td>
6793 <td>pr1_iep1_cap_intr_req</td>
6794 <td>1</td>
6795 </tr>
6796 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6797 <td>100</td>
6798 <td>27</td>
6799 <td>AM6_DEV_PRU_ICSSG0</td>
6800 <td>pr1_slv_intr</td>
6801 <td>91</td>
6802 </tr>
6803 <tr class="row-even"><td>&#160;</td>
6804 <td>&#160;</td>
6805 <td>&#160;</td>
6806 <td>AM6_DEV_PRU_ICSSG1</td>
6807 <td>pr1_iep1_cap_intr_req</td>
6808 <td>1</td>
6809 </tr>
6810 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6811 <td>100</td>
6812 <td>27</td>
6813 <td>AM6_DEV_PRU_ICSSG1</td>
6814 <td>pr1_slv_intr</td>
6815 <td>91</td>
6816 </tr>
6817 <tr class="row-even"><td>&#160;</td>
6818 <td>&#160;</td>
6819 <td>&#160;</td>
6820 <td>AM6_DEV_PRU_ICSSG2</td>
6821 <td>pr1_iep1_cap_intr_req</td>
6822 <td>1</td>
6823 </tr>
6824 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6825 <td>100</td>
6826 <td>27</td>
6827 <td>AM6_DEV_PRU_ICSSG2</td>
6828 <td>pr1_slv_intr</td>
6829 <td>91</td>
6830 </tr>
6831 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6832 <td>100</td>
6833 <td>28</td>
6834 <td>AM6_DEV_GIC0</td>
6835 <td>spi</td>
6836 <td>420</td>
6837 </tr>
6838 <tr class="row-odd"><td>&#160;</td>
6839 <td>&#160;</td>
6840 <td>&#160;</td>
6841 <td>AM6_DEV_PRU_ICSSG0</td>
6842 <td>pr1_iep1_cap_intr_req</td>
6843 <td>2</td>
6844 </tr>
6845 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6846 <td>100</td>
6847 <td>28</td>
6848 <td>AM6_DEV_PRU_ICSSG0</td>
6849 <td>pr1_slv_intr</td>
6850 <td>92</td>
6851 </tr>
6852 <tr class="row-odd"><td>&#160;</td>
6853 <td>&#160;</td>
6854 <td>&#160;</td>
6855 <td>AM6_DEV_PRU_ICSSG1</td>
6856 <td>pr1_iep1_cap_intr_req</td>
6857 <td>2</td>
6858 </tr>
6859 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6860 <td>100</td>
6861 <td>28</td>
6862 <td>AM6_DEV_PRU_ICSSG1</td>
6863 <td>pr1_slv_intr</td>
6864 <td>92</td>
6865 </tr>
6866 <tr class="row-odd"><td>&#160;</td>
6867 <td>&#160;</td>
6868 <td>&#160;</td>
6869 <td>AM6_DEV_PRU_ICSSG2</td>
6870 <td>pr1_iep1_cap_intr_req</td>
6871 <td>2</td>
6872 </tr>
6873 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6874 <td>100</td>
6875 <td>28</td>
6876 <td>AM6_DEV_PRU_ICSSG2</td>
6877 <td>pr1_slv_intr</td>
6878 <td>92</td>
6879 </tr>
6880 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6881 <td>100</td>
6882 <td>29</td>
6883 <td>AM6_DEV_GIC0</td>
6884 <td>spi</td>
6885 <td>421</td>
6886 </tr>
6887 <tr class="row-even"><td>&#160;</td>
6888 <td>&#160;</td>
6889 <td>&#160;</td>
6890 <td>AM6_DEV_PRU_ICSSG0</td>
6891 <td>pr1_iep1_cap_intr_req</td>
6892 <td>3</td>
6893 </tr>
6894 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6895 <td>100</td>
6896 <td>29</td>
6897 <td>AM6_DEV_PRU_ICSSG0</td>
6898 <td>pr1_slv_intr</td>
6899 <td>93</td>
6900 </tr>
6901 <tr class="row-even"><td>&#160;</td>
6902 <td>&#160;</td>
6903 <td>&#160;</td>
6904 <td>AM6_DEV_PRU_ICSSG1</td>
6905 <td>pr1_iep1_cap_intr_req</td>
6906 <td>3</td>
6907 </tr>
6908 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6909 <td>100</td>
6910 <td>29</td>
6911 <td>AM6_DEV_PRU_ICSSG1</td>
6912 <td>pr1_slv_intr</td>
6913 <td>93</td>
6914 </tr>
6915 <tr class="row-even"><td>&#160;</td>
6916 <td>&#160;</td>
6917 <td>&#160;</td>
6918 <td>AM6_DEV_PRU_ICSSG2</td>
6919 <td>pr1_iep1_cap_intr_req</td>
6920 <td>3</td>
6921 </tr>
6922 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6923 <td>100</td>
6924 <td>29</td>
6925 <td>AM6_DEV_PRU_ICSSG2</td>
6926 <td>pr1_slv_intr</td>
6927 <td>93</td>
6928 </tr>
6929 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6930 <td>100</td>
6931 <td>30</td>
6932 <td>AM6_DEV_GIC0</td>
6933 <td>spi</td>
6934 <td>422</td>
6935 </tr>
6936 <tr class="row-odd"><td>&#160;</td>
6937 <td>&#160;</td>
6938 <td>&#160;</td>
6939 <td>AM6_DEV_PRU_ICSSG0</td>
6940 <td>pr1_iep1_cap_intr_req</td>
6941 <td>4</td>
6942 </tr>
6943 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6944 <td>100</td>
6945 <td>30</td>
6946 <td>AM6_DEV_PRU_ICSSG0</td>
6947 <td>pr1_slv_intr</td>
6948 <td>94</td>
6949 </tr>
6950 <tr class="row-odd"><td>&#160;</td>
6951 <td>&#160;</td>
6952 <td>&#160;</td>
6953 <td>AM6_DEV_PRU_ICSSG1</td>
6954 <td>pr1_iep1_cap_intr_req</td>
6955 <td>4</td>
6956 </tr>
6957 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6958 <td>100</td>
6959 <td>30</td>
6960 <td>AM6_DEV_PRU_ICSSG1</td>
6961 <td>pr1_slv_intr</td>
6962 <td>94</td>
6963 </tr>
6964 <tr class="row-odd"><td>&#160;</td>
6965 <td>&#160;</td>
6966 <td>&#160;</td>
6967 <td>AM6_DEV_PRU_ICSSG2</td>
6968 <td>pr1_iep1_cap_intr_req</td>
6969 <td>4</td>
6970 </tr>
6971 <tr class="row-even"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6972 <td>100</td>
6973 <td>30</td>
6974 <td>AM6_DEV_PRU_ICSSG2</td>
6975 <td>pr1_slv_intr</td>
6976 <td>94</td>
6977 </tr>
6978 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6979 <td>100</td>
6980 <td>31</td>
6981 <td>AM6_DEV_GIC0</td>
6982 <td>spi</td>
6983 <td>423</td>
6984 </tr>
6985 <tr class="row-even"><td>&#160;</td>
6986 <td>&#160;</td>
6987 <td>&#160;</td>
6988 <td>AM6_DEV_PRU_ICSSG0</td>
6989 <td>pr1_iep1_cap_intr_req</td>
6990 <td>5</td>
6991 </tr>
6992 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
6993 <td>100</td>
6994 <td>31</td>
6995 <td>AM6_DEV_PRU_ICSSG0</td>
6996 <td>pr1_slv_intr</td>
6997 <td>95</td>
6998 </tr>
6999 <tr class="row-even"><td>&#160;</td>
7000 <td>&#160;</td>
7001 <td>&#160;</td>
7002 <td>AM6_DEV_PRU_ICSSG1</td>
7003 <td>pr1_iep1_cap_intr_req</td>
7004 <td>5</td>
7005 </tr>
7006 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
7007 <td>100</td>
7008 <td>31</td>
7009 <td>AM6_DEV_PRU_ICSSG1</td>
7010 <td>pr1_slv_intr</td>
7011 <td>95</td>
7012 </tr>
7013 <tr class="row-even"><td>&#160;</td>
7014 <td>&#160;</td>
7015 <td>&#160;</td>
7016 <td>AM6_DEV_PRU_ICSSG2</td>
7017 <td>pr1_iep1_cap_intr_req</td>
7018 <td>5</td>
7019 </tr>
7020 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
7021 <td>100</td>
7022 <td>31</td>
7023 <td>AM6_DEV_PRU_ICSSG2</td>
7024 <td>pr1_slv_intr</td>
7025 <td>95</td>
7026 </tr>
7027 </tbody>
7028 </table>
7029 </div>
7030 <div class="section" id="navss0-intr-router-0-interrupt-router-input-sources">
7031 <span id="pub-soc-am65x-sr2-navss0-intr-router-0-input-src-list"></span><h2>navss0_intr_router_0 Interrupt Router Input Sources<a class="headerlink" href="#navss0-intr-router-0-interrupt-router-input-sources" title="Permalink to this headline">¶</a></h2>
7032 <div class="admonition warning">
7033 <p class="first admonition-title">Warning</p>
7034 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
7035 host within the RM Board Configuration resource assignment array.  The RM
7036 Board Configuration is rejected if an overlap with a reserved resource is
7037 detected.</p>
7038 </div>
7039 <table border="1" class="docutils">
7040 <colgroup>
7041 <col width="25%" />
7042 <col width="11%" />
7043 <col width="13%" />
7044 <col width="25%" />
7045 <col width="14%" />
7046 <col width="11%" />
7047 </colgroup>
7048 <thead valign="bottom">
7049 <tr class="row-odd"><th class="head">IR Name</th>
7050 <th class="head">IR Device ID</th>
7051 <th class="head">IR Input Index</th>
7052 <th class="head">Source Name</th>
7053 <th class="head">Source Interface</th>
7054 <th class="head">Source Index</th>
7055 </tr>
7056 </thead>
7057 <tbody valign="top">
7058 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7059 (<strong>Reserved by System Firmware</strong>)</td>
7060 <td>182</td>
7061 <td>0</td>
7062 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7063 <td>intaggr_vintr_pend</td>
7064 <td>0</td>
7065 </tr>
7066 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7067 (<strong>Reserved by System Firmware</strong>)</td>
7068 <td>182</td>
7069 <td>1</td>
7070 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7071 <td>intaggr_vintr_pend</td>
7072 <td>1</td>
7073 </tr>
7074 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7075 (<strong>Reserved by System Firmware</strong>)</td>
7076 <td>182</td>
7077 <td>2</td>
7078 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7079 <td>intaggr_vintr_pend</td>
7080 <td>2</td>
7081 </tr>
7082 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7083 (<strong>Reserved by System Firmware</strong>)</td>
7084 <td>182</td>
7085 <td>3</td>
7086 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7087 <td>intaggr_vintr_pend</td>
7088 <td>3</td>
7089 </tr>
7090 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7091 (<strong>Reserved by System Firmware</strong>)</td>
7092 <td>182</td>
7093 <td>4</td>
7094 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7095 <td>intaggr_vintr_pend</td>
7096 <td>4</td>
7097 </tr>
7098 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7099 (<strong>Reserved by System Firmware</strong>)</td>
7100 <td>182</td>
7101 <td>5</td>
7102 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7103 <td>intaggr_vintr_pend</td>
7104 <td>5</td>
7105 </tr>
7106 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7107 (<strong>Reserved by System Firmware</strong>)</td>
7108 <td>182</td>
7109 <td>6</td>
7110 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7111 <td>intaggr_vintr_pend</td>
7112 <td>6</td>
7113 </tr>
7114 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7115 (<strong>Reserved by System Firmware</strong>)</td>
7116 <td>182</td>
7117 <td>7</td>
7118 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7119 <td>intaggr_vintr_pend</td>
7120 <td>7</td>
7121 </tr>
7122 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7123 (<strong>Reserved by System Firmware</strong>)</td>
7124 <td>182</td>
7125 <td>8</td>
7126 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7127 <td>intaggr_vintr_pend</td>
7128 <td>8</td>
7129 </tr>
7130 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7131 (<strong>Reserved by System Firmware</strong>)</td>
7132 <td>182</td>
7133 <td>9</td>
7134 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7135 <td>intaggr_vintr_pend</td>
7136 <td>9</td>
7137 </tr>
7138 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7139 (<strong>Reserved by System Firmware</strong>)</td>
7140 <td>182</td>
7141 <td>10</td>
7142 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7143 <td>intaggr_vintr_pend</td>
7144 <td>10</td>
7145 </tr>
7146 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7147 (<strong>Reserved by System Firmware</strong>)</td>
7148 <td>182</td>
7149 <td>11</td>
7150 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7151 <td>intaggr_vintr_pend</td>
7152 <td>11</td>
7153 </tr>
7154 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7155 (<strong>Reserved by System Firmware</strong>)</td>
7156 <td>182</td>
7157 <td>12</td>
7158 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7159 <td>intaggr_vintr_pend</td>
7160 <td>12</td>
7161 </tr>
7162 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7163 (<strong>Reserved by System Firmware</strong>)</td>
7164 <td>182</td>
7165 <td>13</td>
7166 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7167 <td>intaggr_vintr_pend</td>
7168 <td>13</td>
7169 </tr>
7170 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7171 (<strong>Reserved by System Firmware</strong>)</td>
7172 <td>182</td>
7173 <td>14</td>
7174 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7175 <td>intaggr_vintr_pend</td>
7176 <td>14</td>
7177 </tr>
7178 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
7179 (<strong>Reserved by System Firmware</strong>)</td>
7180 <td>182</td>
7181 <td>15</td>
7182 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7183 <td>intaggr_vintr_pend</td>
7184 <td>15</td>
7185 </tr>
7186 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7187 <td>182</td>
7188 <td>16</td>
7189 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7190 <td>intaggr_vintr_pend</td>
7191 <td>16</td>
7192 </tr>
7193 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7194 <td>182</td>
7195 <td>17</td>
7196 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7197 <td>intaggr_vintr_pend</td>
7198 <td>17</td>
7199 </tr>
7200 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7201 <td>182</td>
7202 <td>18</td>
7203 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7204 <td>intaggr_vintr_pend</td>
7205 <td>18</td>
7206 </tr>
7207 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7208 <td>182</td>
7209 <td>19</td>
7210 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7211 <td>intaggr_vintr_pend</td>
7212 <td>19</td>
7213 </tr>
7214 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7215 <td>182</td>
7216 <td>20</td>
7217 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7218 <td>intaggr_vintr_pend</td>
7219 <td>20</td>
7220 </tr>
7221 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7222 <td>182</td>
7223 <td>21</td>
7224 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7225 <td>intaggr_vintr_pend</td>
7226 <td>21</td>
7227 </tr>
7228 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7229 <td>182</td>
7230 <td>22</td>
7231 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7232 <td>intaggr_vintr_pend</td>
7233 <td>22</td>
7234 </tr>
7235 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7236 <td>182</td>
7237 <td>23</td>
7238 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7239 <td>intaggr_vintr_pend</td>
7240 <td>23</td>
7241 </tr>
7242 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7243 <td>182</td>
7244 <td>24</td>
7245 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7246 <td>intaggr_vintr_pend</td>
7247 <td>24</td>
7248 </tr>
7249 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7250 <td>182</td>
7251 <td>25</td>
7252 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7253 <td>intaggr_vintr_pend</td>
7254 <td>25</td>
7255 </tr>
7256 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7257 <td>182</td>
7258 <td>26</td>
7259 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7260 <td>intaggr_vintr_pend</td>
7261 <td>26</td>
7262 </tr>
7263 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7264 <td>182</td>
7265 <td>27</td>
7266 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7267 <td>intaggr_vintr_pend</td>
7268 <td>27</td>
7269 </tr>
7270 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7271 <td>182</td>
7272 <td>28</td>
7273 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7274 <td>intaggr_vintr_pend</td>
7275 <td>28</td>
7276 </tr>
7277 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7278 <td>182</td>
7279 <td>29</td>
7280 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7281 <td>intaggr_vintr_pend</td>
7282 <td>29</td>
7283 </tr>
7284 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7285 <td>182</td>
7286 <td>30</td>
7287 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7288 <td>intaggr_vintr_pend</td>
7289 <td>30</td>
7290 </tr>
7291 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7292 <td>182</td>
7293 <td>31</td>
7294 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7295 <td>intaggr_vintr_pend</td>
7296 <td>31</td>
7297 </tr>
7298 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7299 <td>182</td>
7300 <td>32</td>
7301 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7302 <td>intaggr_vintr_pend</td>
7303 <td>32</td>
7304 </tr>
7305 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7306 <td>182</td>
7307 <td>33</td>
7308 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7309 <td>intaggr_vintr_pend</td>
7310 <td>33</td>
7311 </tr>
7312 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7313 <td>182</td>
7314 <td>34</td>
7315 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7316 <td>intaggr_vintr_pend</td>
7317 <td>34</td>
7318 </tr>
7319 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7320 <td>182</td>
7321 <td>35</td>
7322 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7323 <td>intaggr_vintr_pend</td>
7324 <td>35</td>
7325 </tr>
7326 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7327 <td>182</td>
7328 <td>36</td>
7329 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7330 <td>intaggr_vintr_pend</td>
7331 <td>36</td>
7332 </tr>
7333 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7334 <td>182</td>
7335 <td>37</td>
7336 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7337 <td>intaggr_vintr_pend</td>
7338 <td>37</td>
7339 </tr>
7340 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7341 <td>182</td>
7342 <td>38</td>
7343 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7344 <td>intaggr_vintr_pend</td>
7345 <td>38</td>
7346 </tr>
7347 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7348 <td>182</td>
7349 <td>39</td>
7350 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7351 <td>intaggr_vintr_pend</td>
7352 <td>39</td>
7353 </tr>
7354 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7355 <td>182</td>
7356 <td>40</td>
7357 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7358 <td>intaggr_vintr_pend</td>
7359 <td>40</td>
7360 </tr>
7361 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7362 <td>182</td>
7363 <td>41</td>
7364 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7365 <td>intaggr_vintr_pend</td>
7366 <td>41</td>
7367 </tr>
7368 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7369 <td>182</td>
7370 <td>42</td>
7371 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7372 <td>intaggr_vintr_pend</td>
7373 <td>42</td>
7374 </tr>
7375 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7376 <td>182</td>
7377 <td>43</td>
7378 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7379 <td>intaggr_vintr_pend</td>
7380 <td>43</td>
7381 </tr>
7382 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7383 <td>182</td>
7384 <td>44</td>
7385 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7386 <td>intaggr_vintr_pend</td>
7387 <td>44</td>
7388 </tr>
7389 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7390 <td>182</td>
7391 <td>45</td>
7392 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7393 <td>intaggr_vintr_pend</td>
7394 <td>45</td>
7395 </tr>
7396 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7397 <td>182</td>
7398 <td>46</td>
7399 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7400 <td>intaggr_vintr_pend</td>
7401 <td>46</td>
7402 </tr>
7403 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7404 <td>182</td>
7405 <td>47</td>
7406 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7407 <td>intaggr_vintr_pend</td>
7408 <td>47</td>
7409 </tr>
7410 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7411 <td>182</td>
7412 <td>48</td>
7413 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7414 <td>intaggr_vintr_pend</td>
7415 <td>48</td>
7416 </tr>
7417 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7418 <td>182</td>
7419 <td>49</td>
7420 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7421 <td>intaggr_vintr_pend</td>
7422 <td>49</td>
7423 </tr>
7424 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7425 <td>182</td>
7426 <td>50</td>
7427 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7428 <td>intaggr_vintr_pend</td>
7429 <td>50</td>
7430 </tr>
7431 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7432 <td>182</td>
7433 <td>51</td>
7434 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7435 <td>intaggr_vintr_pend</td>
7436 <td>51</td>
7437 </tr>
7438 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7439 <td>182</td>
7440 <td>52</td>
7441 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7442 <td>intaggr_vintr_pend</td>
7443 <td>52</td>
7444 </tr>
7445 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7446 <td>182</td>
7447 <td>53</td>
7448 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7449 <td>intaggr_vintr_pend</td>
7450 <td>53</td>
7451 </tr>
7452 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7453 <td>182</td>
7454 <td>54</td>
7455 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7456 <td>intaggr_vintr_pend</td>
7457 <td>54</td>
7458 </tr>
7459 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7460 <td>182</td>
7461 <td>55</td>
7462 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7463 <td>intaggr_vintr_pend</td>
7464 <td>55</td>
7465 </tr>
7466 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7467 <td>182</td>
7468 <td>56</td>
7469 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7470 <td>intaggr_vintr_pend</td>
7471 <td>56</td>
7472 </tr>
7473 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7474 <td>182</td>
7475 <td>57</td>
7476 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7477 <td>intaggr_vintr_pend</td>
7478 <td>57</td>
7479 </tr>
7480 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7481 <td>182</td>
7482 <td>58</td>
7483 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7484 <td>intaggr_vintr_pend</td>
7485 <td>58</td>
7486 </tr>
7487 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7488 <td>182</td>
7489 <td>59</td>
7490 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7491 <td>intaggr_vintr_pend</td>
7492 <td>59</td>
7493 </tr>
7494 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7495 <td>182</td>
7496 <td>60</td>
7497 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7498 <td>intaggr_vintr_pend</td>
7499 <td>60</td>
7500 </tr>
7501 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7502 <td>182</td>
7503 <td>61</td>
7504 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7505 <td>intaggr_vintr_pend</td>
7506 <td>61</td>
7507 </tr>
7508 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7509 <td>182</td>
7510 <td>62</td>
7511 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7512 <td>intaggr_vintr_pend</td>
7513 <td>62</td>
7514 </tr>
7515 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7516 <td>182</td>
7517 <td>63</td>
7518 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7519 <td>intaggr_vintr_pend</td>
7520 <td>63</td>
7521 </tr>
7522 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7523 <td>182</td>
7524 <td>64</td>
7525 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7526 <td>intaggr_vintr_pend</td>
7527 <td>64</td>
7528 </tr>
7529 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7530 <td>182</td>
7531 <td>65</td>
7532 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7533 <td>intaggr_vintr_pend</td>
7534 <td>65</td>
7535 </tr>
7536 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7537 <td>182</td>
7538 <td>66</td>
7539 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7540 <td>intaggr_vintr_pend</td>
7541 <td>66</td>
7542 </tr>
7543 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7544 <td>182</td>
7545 <td>67</td>
7546 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7547 <td>intaggr_vintr_pend</td>
7548 <td>67</td>
7549 </tr>
7550 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7551 <td>182</td>
7552 <td>68</td>
7553 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7554 <td>intaggr_vintr_pend</td>
7555 <td>68</td>
7556 </tr>
7557 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7558 <td>182</td>
7559 <td>69</td>
7560 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7561 <td>intaggr_vintr_pend</td>
7562 <td>69</td>
7563 </tr>
7564 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7565 <td>182</td>
7566 <td>70</td>
7567 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7568 <td>intaggr_vintr_pend</td>
7569 <td>70</td>
7570 </tr>
7571 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7572 <td>182</td>
7573 <td>71</td>
7574 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7575 <td>intaggr_vintr_pend</td>
7576 <td>71</td>
7577 </tr>
7578 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7579 <td>182</td>
7580 <td>72</td>
7581 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7582 <td>intaggr_vintr_pend</td>
7583 <td>72</td>
7584 </tr>
7585 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7586 <td>182</td>
7587 <td>73</td>
7588 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7589 <td>intaggr_vintr_pend</td>
7590 <td>73</td>
7591 </tr>
7592 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7593 <td>182</td>
7594 <td>74</td>
7595 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7596 <td>intaggr_vintr_pend</td>
7597 <td>74</td>
7598 </tr>
7599 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7600 <td>182</td>
7601 <td>75</td>
7602 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7603 <td>intaggr_vintr_pend</td>
7604 <td>75</td>
7605 </tr>
7606 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7607 <td>182</td>
7608 <td>76</td>
7609 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7610 <td>intaggr_vintr_pend</td>
7611 <td>76</td>
7612 </tr>
7613 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7614 <td>182</td>
7615 <td>77</td>
7616 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7617 <td>intaggr_vintr_pend</td>
7618 <td>77</td>
7619 </tr>
7620 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7621 <td>182</td>
7622 <td>78</td>
7623 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7624 <td>intaggr_vintr_pend</td>
7625 <td>78</td>
7626 </tr>
7627 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7628 <td>182</td>
7629 <td>79</td>
7630 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7631 <td>intaggr_vintr_pend</td>
7632 <td>79</td>
7633 </tr>
7634 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7635 <td>182</td>
7636 <td>80</td>
7637 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7638 <td>intaggr_vintr_pend</td>
7639 <td>80</td>
7640 </tr>
7641 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7642 <td>182</td>
7643 <td>81</td>
7644 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7645 <td>intaggr_vintr_pend</td>
7646 <td>81</td>
7647 </tr>
7648 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7649 <td>182</td>
7650 <td>82</td>
7651 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7652 <td>intaggr_vintr_pend</td>
7653 <td>82</td>
7654 </tr>
7655 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7656 <td>182</td>
7657 <td>83</td>
7658 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7659 <td>intaggr_vintr_pend</td>
7660 <td>83</td>
7661 </tr>
7662 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7663 <td>182</td>
7664 <td>84</td>
7665 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7666 <td>intaggr_vintr_pend</td>
7667 <td>84</td>
7668 </tr>
7669 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7670 <td>182</td>
7671 <td>85</td>
7672 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7673 <td>intaggr_vintr_pend</td>
7674 <td>85</td>
7675 </tr>
7676 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7677 <td>182</td>
7678 <td>86</td>
7679 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7680 <td>intaggr_vintr_pend</td>
7681 <td>86</td>
7682 </tr>
7683 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7684 <td>182</td>
7685 <td>87</td>
7686 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7687 <td>intaggr_vintr_pend</td>
7688 <td>87</td>
7689 </tr>
7690 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7691 <td>182</td>
7692 <td>88</td>
7693 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7694 <td>intaggr_vintr_pend</td>
7695 <td>88</td>
7696 </tr>
7697 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7698 <td>182</td>
7699 <td>89</td>
7700 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7701 <td>intaggr_vintr_pend</td>
7702 <td>89</td>
7703 </tr>
7704 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7705 <td>182</td>
7706 <td>90</td>
7707 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7708 <td>intaggr_vintr_pend</td>
7709 <td>90</td>
7710 </tr>
7711 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7712 <td>182</td>
7713 <td>91</td>
7714 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7715 <td>intaggr_vintr_pend</td>
7716 <td>91</td>
7717 </tr>
7718 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7719 <td>182</td>
7720 <td>92</td>
7721 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7722 <td>intaggr_vintr_pend</td>
7723 <td>92</td>
7724 </tr>
7725 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7726 <td>182</td>
7727 <td>93</td>
7728 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7729 <td>intaggr_vintr_pend</td>
7730 <td>93</td>
7731 </tr>
7732 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7733 <td>182</td>
7734 <td>94</td>
7735 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7736 <td>intaggr_vintr_pend</td>
7737 <td>94</td>
7738 </tr>
7739 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7740 <td>182</td>
7741 <td>95</td>
7742 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7743 <td>intaggr_vintr_pend</td>
7744 <td>95</td>
7745 </tr>
7746 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7747 <td>182</td>
7748 <td>96</td>
7749 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7750 <td>intaggr_vintr_pend</td>
7751 <td>96</td>
7752 </tr>
7753 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7754 <td>182</td>
7755 <td>97</td>
7756 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7757 <td>intaggr_vintr_pend</td>
7758 <td>97</td>
7759 </tr>
7760 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7761 <td>182</td>
7762 <td>98</td>
7763 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7764 <td>intaggr_vintr_pend</td>
7765 <td>98</td>
7766 </tr>
7767 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7768 <td>182</td>
7769 <td>99</td>
7770 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7771 <td>intaggr_vintr_pend</td>
7772 <td>99</td>
7773 </tr>
7774 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7775 <td>182</td>
7776 <td>100</td>
7777 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7778 <td>intaggr_vintr_pend</td>
7779 <td>100</td>
7780 </tr>
7781 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7782 <td>182</td>
7783 <td>101</td>
7784 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7785 <td>intaggr_vintr_pend</td>
7786 <td>101</td>
7787 </tr>
7788 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7789 <td>182</td>
7790 <td>102</td>
7791 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7792 <td>intaggr_vintr_pend</td>
7793 <td>102</td>
7794 </tr>
7795 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7796 <td>182</td>
7797 <td>103</td>
7798 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7799 <td>intaggr_vintr_pend</td>
7800 <td>103</td>
7801 </tr>
7802 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7803 <td>182</td>
7804 <td>104</td>
7805 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7806 <td>intaggr_vintr_pend</td>
7807 <td>104</td>
7808 </tr>
7809 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7810 <td>182</td>
7811 <td>105</td>
7812 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7813 <td>intaggr_vintr_pend</td>
7814 <td>105</td>
7815 </tr>
7816 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7817 <td>182</td>
7818 <td>106</td>
7819 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7820 <td>intaggr_vintr_pend</td>
7821 <td>106</td>
7822 </tr>
7823 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7824 <td>182</td>
7825 <td>107</td>
7826 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7827 <td>intaggr_vintr_pend</td>
7828 <td>107</td>
7829 </tr>
7830 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7831 <td>182</td>
7832 <td>108</td>
7833 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7834 <td>intaggr_vintr_pend</td>
7835 <td>108</td>
7836 </tr>
7837 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7838 <td>182</td>
7839 <td>109</td>
7840 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7841 <td>intaggr_vintr_pend</td>
7842 <td>109</td>
7843 </tr>
7844 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7845 <td>182</td>
7846 <td>110</td>
7847 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7848 <td>intaggr_vintr_pend</td>
7849 <td>110</td>
7850 </tr>
7851 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7852 <td>182</td>
7853 <td>111</td>
7854 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7855 <td>intaggr_vintr_pend</td>
7856 <td>111</td>
7857 </tr>
7858 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7859 <td>182</td>
7860 <td>112</td>
7861 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7862 <td>intaggr_vintr_pend</td>
7863 <td>112</td>
7864 </tr>
7865 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7866 <td>182</td>
7867 <td>113</td>
7868 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7869 <td>intaggr_vintr_pend</td>
7870 <td>113</td>
7871 </tr>
7872 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7873 <td>182</td>
7874 <td>114</td>
7875 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7876 <td>intaggr_vintr_pend</td>
7877 <td>114</td>
7878 </tr>
7879 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7880 <td>182</td>
7881 <td>115</td>
7882 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7883 <td>intaggr_vintr_pend</td>
7884 <td>115</td>
7885 </tr>
7886 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7887 <td>182</td>
7888 <td>116</td>
7889 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7890 <td>intaggr_vintr_pend</td>
7891 <td>116</td>
7892 </tr>
7893 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7894 <td>182</td>
7895 <td>117</td>
7896 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7897 <td>intaggr_vintr_pend</td>
7898 <td>117</td>
7899 </tr>
7900 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7901 <td>182</td>
7902 <td>118</td>
7903 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7904 <td>intaggr_vintr_pend</td>
7905 <td>118</td>
7906 </tr>
7907 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7908 <td>182</td>
7909 <td>119</td>
7910 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7911 <td>intaggr_vintr_pend</td>
7912 <td>119</td>
7913 </tr>
7914 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7915 <td>182</td>
7916 <td>120</td>
7917 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7918 <td>intaggr_vintr_pend</td>
7919 <td>120</td>
7920 </tr>
7921 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7922 <td>182</td>
7923 <td>121</td>
7924 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7925 <td>intaggr_vintr_pend</td>
7926 <td>121</td>
7927 </tr>
7928 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7929 <td>182</td>
7930 <td>122</td>
7931 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7932 <td>intaggr_vintr_pend</td>
7933 <td>122</td>
7934 </tr>
7935 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7936 <td>182</td>
7937 <td>123</td>
7938 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7939 <td>intaggr_vintr_pend</td>
7940 <td>123</td>
7941 </tr>
7942 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7943 <td>182</td>
7944 <td>124</td>
7945 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7946 <td>intaggr_vintr_pend</td>
7947 <td>124</td>
7948 </tr>
7949 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7950 <td>182</td>
7951 <td>125</td>
7952 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7953 <td>intaggr_vintr_pend</td>
7954 <td>125</td>
7955 </tr>
7956 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7957 <td>182</td>
7958 <td>126</td>
7959 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7960 <td>intaggr_vintr_pend</td>
7961 <td>126</td>
7962 </tr>
7963 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7964 <td>182</td>
7965 <td>127</td>
7966 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7967 <td>intaggr_vintr_pend</td>
7968 <td>127</td>
7969 </tr>
7970 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7971 <td>182</td>
7972 <td>128</td>
7973 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7974 <td>intaggr_vintr_pend</td>
7975 <td>128</td>
7976 </tr>
7977 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7978 <td>182</td>
7979 <td>129</td>
7980 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7981 <td>intaggr_vintr_pend</td>
7982 <td>129</td>
7983 </tr>
7984 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7985 <td>182</td>
7986 <td>130</td>
7987 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7988 <td>intaggr_vintr_pend</td>
7989 <td>130</td>
7990 </tr>
7991 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7992 <td>182</td>
7993 <td>131</td>
7994 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
7995 <td>intaggr_vintr_pend</td>
7996 <td>131</td>
7997 </tr>
7998 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
7999 <td>182</td>
8000 <td>132</td>
8001 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8002 <td>intaggr_vintr_pend</td>
8003 <td>132</td>
8004 </tr>
8005 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8006 <td>182</td>
8007 <td>133</td>
8008 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8009 <td>intaggr_vintr_pend</td>
8010 <td>133</td>
8011 </tr>
8012 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8013 <td>182</td>
8014 <td>134</td>
8015 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8016 <td>intaggr_vintr_pend</td>
8017 <td>134</td>
8018 </tr>
8019 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8020 <td>182</td>
8021 <td>135</td>
8022 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8023 <td>intaggr_vintr_pend</td>
8024 <td>135</td>
8025 </tr>
8026 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8027 <td>182</td>
8028 <td>136</td>
8029 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8030 <td>intaggr_vintr_pend</td>
8031 <td>136</td>
8032 </tr>
8033 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8034 <td>182</td>
8035 <td>137</td>
8036 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8037 <td>intaggr_vintr_pend</td>
8038 <td>137</td>
8039 </tr>
8040 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8041 <td>182</td>
8042 <td>138</td>
8043 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8044 <td>intaggr_vintr_pend</td>
8045 <td>138</td>
8046 </tr>
8047 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8048 <td>182</td>
8049 <td>139</td>
8050 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8051 <td>intaggr_vintr_pend</td>
8052 <td>139</td>
8053 </tr>
8054 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8055 <td>182</td>
8056 <td>140</td>
8057 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8058 <td>intaggr_vintr_pend</td>
8059 <td>140</td>
8060 </tr>
8061 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8062 <td>182</td>
8063 <td>141</td>
8064 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8065 <td>intaggr_vintr_pend</td>
8066 <td>141</td>
8067 </tr>
8068 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8069 <td>182</td>
8070 <td>142</td>
8071 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8072 <td>intaggr_vintr_pend</td>
8073 <td>142</td>
8074 </tr>
8075 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8076 <td>182</td>
8077 <td>143</td>
8078 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8079 <td>intaggr_vintr_pend</td>
8080 <td>143</td>
8081 </tr>
8082 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8083 <td>182</td>
8084 <td>144</td>
8085 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8086 <td>intaggr_vintr_pend</td>
8087 <td>144</td>
8088 </tr>
8089 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8090 <td>182</td>
8091 <td>145</td>
8092 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8093 <td>intaggr_vintr_pend</td>
8094 <td>145</td>
8095 </tr>
8096 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8097 <td>182</td>
8098 <td>146</td>
8099 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8100 <td>intaggr_vintr_pend</td>
8101 <td>146</td>
8102 </tr>
8103 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8104 <td>182</td>
8105 <td>147</td>
8106 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8107 <td>intaggr_vintr_pend</td>
8108 <td>147</td>
8109 </tr>
8110 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8111 <td>182</td>
8112 <td>148</td>
8113 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8114 <td>intaggr_vintr_pend</td>
8115 <td>148</td>
8116 </tr>
8117 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8118 <td>182</td>
8119 <td>149</td>
8120 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8121 <td>intaggr_vintr_pend</td>
8122 <td>149</td>
8123 </tr>
8124 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8125 <td>182</td>
8126 <td>150</td>
8127 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8128 <td>intaggr_vintr_pend</td>
8129 <td>150</td>
8130 </tr>
8131 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8132 <td>182</td>
8133 <td>151</td>
8134 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8135 <td>intaggr_vintr_pend</td>
8136 <td>151</td>
8137 </tr>
8138 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8139 <td>182</td>
8140 <td>152</td>
8141 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8142 <td>intaggr_vintr_pend</td>
8143 <td>152</td>
8144 </tr>
8145 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8146 <td>182</td>
8147 <td>153</td>
8148 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8149 <td>intaggr_vintr_pend</td>
8150 <td>153</td>
8151 </tr>
8152 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8153 <td>182</td>
8154 <td>154</td>
8155 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8156 <td>intaggr_vintr_pend</td>
8157 <td>154</td>
8158 </tr>
8159 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8160 <td>182</td>
8161 <td>155</td>
8162 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8163 <td>intaggr_vintr_pend</td>
8164 <td>155</td>
8165 </tr>
8166 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8167 <td>182</td>
8168 <td>156</td>
8169 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8170 <td>intaggr_vintr_pend</td>
8171 <td>156</td>
8172 </tr>
8173 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8174 <td>182</td>
8175 <td>157</td>
8176 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8177 <td>intaggr_vintr_pend</td>
8178 <td>157</td>
8179 </tr>
8180 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8181 <td>182</td>
8182 <td>158</td>
8183 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8184 <td>intaggr_vintr_pend</td>
8185 <td>158</td>
8186 </tr>
8187 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8188 <td>182</td>
8189 <td>159</td>
8190 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8191 <td>intaggr_vintr_pend</td>
8192 <td>159</td>
8193 </tr>
8194 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8195 <td>182</td>
8196 <td>160</td>
8197 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8198 <td>intaggr_vintr_pend</td>
8199 <td>160</td>
8200 </tr>
8201 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8202 <td>182</td>
8203 <td>161</td>
8204 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8205 <td>intaggr_vintr_pend</td>
8206 <td>161</td>
8207 </tr>
8208 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8209 <td>182</td>
8210 <td>162</td>
8211 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8212 <td>intaggr_vintr_pend</td>
8213 <td>162</td>
8214 </tr>
8215 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8216 <td>182</td>
8217 <td>163</td>
8218 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8219 <td>intaggr_vintr_pend</td>
8220 <td>163</td>
8221 </tr>
8222 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8223 <td>182</td>
8224 <td>164</td>
8225 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8226 <td>intaggr_vintr_pend</td>
8227 <td>164</td>
8228 </tr>
8229 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8230 <td>182</td>
8231 <td>165</td>
8232 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8233 <td>intaggr_vintr_pend</td>
8234 <td>165</td>
8235 </tr>
8236 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8237 <td>182</td>
8238 <td>166</td>
8239 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8240 <td>intaggr_vintr_pend</td>
8241 <td>166</td>
8242 </tr>
8243 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8244 <td>182</td>
8245 <td>167</td>
8246 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8247 <td>intaggr_vintr_pend</td>
8248 <td>167</td>
8249 </tr>
8250 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8251 <td>182</td>
8252 <td>168</td>
8253 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8254 <td>intaggr_vintr_pend</td>
8255 <td>168</td>
8256 </tr>
8257 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8258 <td>182</td>
8259 <td>169</td>
8260 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8261 <td>intaggr_vintr_pend</td>
8262 <td>169</td>
8263 </tr>
8264 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8265 <td>182</td>
8266 <td>170</td>
8267 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8268 <td>intaggr_vintr_pend</td>
8269 <td>170</td>
8270 </tr>
8271 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8272 <td>182</td>
8273 <td>171</td>
8274 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8275 <td>intaggr_vintr_pend</td>
8276 <td>171</td>
8277 </tr>
8278 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8279 <td>182</td>
8280 <td>172</td>
8281 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8282 <td>intaggr_vintr_pend</td>
8283 <td>172</td>
8284 </tr>
8285 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8286 <td>182</td>
8287 <td>173</td>
8288 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8289 <td>intaggr_vintr_pend</td>
8290 <td>173</td>
8291 </tr>
8292 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8293 <td>182</td>
8294 <td>174</td>
8295 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8296 <td>intaggr_vintr_pend</td>
8297 <td>174</td>
8298 </tr>
8299 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8300 <td>182</td>
8301 <td>175</td>
8302 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8303 <td>intaggr_vintr_pend</td>
8304 <td>175</td>
8305 </tr>
8306 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8307 <td>182</td>
8308 <td>176</td>
8309 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8310 <td>intaggr_vintr_pend</td>
8311 <td>176</td>
8312 </tr>
8313 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8314 <td>182</td>
8315 <td>177</td>
8316 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8317 <td>intaggr_vintr_pend</td>
8318 <td>177</td>
8319 </tr>
8320 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8321 <td>182</td>
8322 <td>178</td>
8323 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8324 <td>intaggr_vintr_pend</td>
8325 <td>178</td>
8326 </tr>
8327 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8328 <td>182</td>
8329 <td>179</td>
8330 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8331 <td>intaggr_vintr_pend</td>
8332 <td>179</td>
8333 </tr>
8334 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8335 <td>182</td>
8336 <td>180</td>
8337 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8338 <td>intaggr_vintr_pend</td>
8339 <td>180</td>
8340 </tr>
8341 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8342 <td>182</td>
8343 <td>181</td>
8344 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8345 <td>intaggr_vintr_pend</td>
8346 <td>181</td>
8347 </tr>
8348 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8349 <td>182</td>
8350 <td>182</td>
8351 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8352 <td>intaggr_vintr_pend</td>
8353 <td>182</td>
8354 </tr>
8355 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8356 <td>182</td>
8357 <td>183</td>
8358 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8359 <td>intaggr_vintr_pend</td>
8360 <td>183</td>
8361 </tr>
8362 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8363 <td>182</td>
8364 <td>184</td>
8365 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8366 <td>intaggr_vintr_pend</td>
8367 <td>184</td>
8368 </tr>
8369 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8370 <td>182</td>
8371 <td>185</td>
8372 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8373 <td>intaggr_vintr_pend</td>
8374 <td>185</td>
8375 </tr>
8376 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8377 <td>182</td>
8378 <td>186</td>
8379 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8380 <td>intaggr_vintr_pend</td>
8381 <td>186</td>
8382 </tr>
8383 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8384 <td>182</td>
8385 <td>187</td>
8386 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8387 <td>intaggr_vintr_pend</td>
8388 <td>187</td>
8389 </tr>
8390 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8391 <td>182</td>
8392 <td>188</td>
8393 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8394 <td>intaggr_vintr_pend</td>
8395 <td>188</td>
8396 </tr>
8397 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8398 <td>182</td>
8399 <td>189</td>
8400 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8401 <td>intaggr_vintr_pend</td>
8402 <td>189</td>
8403 </tr>
8404 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8405 <td>182</td>
8406 <td>190</td>
8407 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8408 <td>intaggr_vintr_pend</td>
8409 <td>190</td>
8410 </tr>
8411 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8412 <td>182</td>
8413 <td>191</td>
8414 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8415 <td>intaggr_vintr_pend</td>
8416 <td>191</td>
8417 </tr>
8418 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8419 <td>182</td>
8420 <td>192</td>
8421 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8422 <td>intaggr_vintr_pend</td>
8423 <td>192</td>
8424 </tr>
8425 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8426 <td>182</td>
8427 <td>193</td>
8428 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8429 <td>intaggr_vintr_pend</td>
8430 <td>193</td>
8431 </tr>
8432 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8433 <td>182</td>
8434 <td>194</td>
8435 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8436 <td>intaggr_vintr_pend</td>
8437 <td>194</td>
8438 </tr>
8439 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8440 <td>182</td>
8441 <td>195</td>
8442 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8443 <td>intaggr_vintr_pend</td>
8444 <td>195</td>
8445 </tr>
8446 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8447 <td>182</td>
8448 <td>196</td>
8449 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8450 <td>intaggr_vintr_pend</td>
8451 <td>196</td>
8452 </tr>
8453 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8454 <td>182</td>
8455 <td>197</td>
8456 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8457 <td>intaggr_vintr_pend</td>
8458 <td>197</td>
8459 </tr>
8460 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8461 <td>182</td>
8462 <td>198</td>
8463 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8464 <td>intaggr_vintr_pend</td>
8465 <td>198</td>
8466 </tr>
8467 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8468 <td>182</td>
8469 <td>199</td>
8470 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8471 <td>intaggr_vintr_pend</td>
8472 <td>199</td>
8473 </tr>
8474 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8475 <td>182</td>
8476 <td>200</td>
8477 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8478 <td>intaggr_vintr_pend</td>
8479 <td>200</td>
8480 </tr>
8481 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8482 <td>182</td>
8483 <td>201</td>
8484 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8485 <td>intaggr_vintr_pend</td>
8486 <td>201</td>
8487 </tr>
8488 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8489 <td>182</td>
8490 <td>202</td>
8491 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8492 <td>intaggr_vintr_pend</td>
8493 <td>202</td>
8494 </tr>
8495 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8496 <td>182</td>
8497 <td>203</td>
8498 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8499 <td>intaggr_vintr_pend</td>
8500 <td>203</td>
8501 </tr>
8502 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8503 <td>182</td>
8504 <td>204</td>
8505 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8506 <td>intaggr_vintr_pend</td>
8507 <td>204</td>
8508 </tr>
8509 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8510 <td>182</td>
8511 <td>205</td>
8512 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8513 <td>intaggr_vintr_pend</td>
8514 <td>205</td>
8515 </tr>
8516 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8517 <td>182</td>
8518 <td>206</td>
8519 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8520 <td>intaggr_vintr_pend</td>
8521 <td>206</td>
8522 </tr>
8523 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8524 <td>182</td>
8525 <td>207</td>
8526 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8527 <td>intaggr_vintr_pend</td>
8528 <td>207</td>
8529 </tr>
8530 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8531 <td>182</td>
8532 <td>208</td>
8533 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8534 <td>intaggr_vintr_pend</td>
8535 <td>208</td>
8536 </tr>
8537 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8538 <td>182</td>
8539 <td>209</td>
8540 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8541 <td>intaggr_vintr_pend</td>
8542 <td>209</td>
8543 </tr>
8544 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8545 <td>182</td>
8546 <td>210</td>
8547 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8548 <td>intaggr_vintr_pend</td>
8549 <td>210</td>
8550 </tr>
8551 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8552 <td>182</td>
8553 <td>211</td>
8554 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8555 <td>intaggr_vintr_pend</td>
8556 <td>211</td>
8557 </tr>
8558 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8559 <td>182</td>
8560 <td>212</td>
8561 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8562 <td>intaggr_vintr_pend</td>
8563 <td>212</td>
8564 </tr>
8565 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8566 <td>182</td>
8567 <td>213</td>
8568 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8569 <td>intaggr_vintr_pend</td>
8570 <td>213</td>
8571 </tr>
8572 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8573 <td>182</td>
8574 <td>214</td>
8575 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8576 <td>intaggr_vintr_pend</td>
8577 <td>214</td>
8578 </tr>
8579 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8580 <td>182</td>
8581 <td>215</td>
8582 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8583 <td>intaggr_vintr_pend</td>
8584 <td>215</td>
8585 </tr>
8586 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8587 <td>182</td>
8588 <td>216</td>
8589 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8590 <td>intaggr_vintr_pend</td>
8591 <td>216</td>
8592 </tr>
8593 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8594 <td>182</td>
8595 <td>217</td>
8596 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8597 <td>intaggr_vintr_pend</td>
8598 <td>217</td>
8599 </tr>
8600 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8601 <td>182</td>
8602 <td>218</td>
8603 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8604 <td>intaggr_vintr_pend</td>
8605 <td>218</td>
8606 </tr>
8607 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8608 <td>182</td>
8609 <td>219</td>
8610 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8611 <td>intaggr_vintr_pend</td>
8612 <td>219</td>
8613 </tr>
8614 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8615 <td>182</td>
8616 <td>220</td>
8617 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8618 <td>intaggr_vintr_pend</td>
8619 <td>220</td>
8620 </tr>
8621 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8622 <td>182</td>
8623 <td>221</td>
8624 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8625 <td>intaggr_vintr_pend</td>
8626 <td>221</td>
8627 </tr>
8628 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8629 <td>182</td>
8630 <td>222</td>
8631 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8632 <td>intaggr_vintr_pend</td>
8633 <td>222</td>
8634 </tr>
8635 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8636 <td>182</td>
8637 <td>223</td>
8638 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8639 <td>intaggr_vintr_pend</td>
8640 <td>223</td>
8641 </tr>
8642 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8643 <td>182</td>
8644 <td>224</td>
8645 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8646 <td>intaggr_vintr_pend</td>
8647 <td>224</td>
8648 </tr>
8649 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8650 <td>182</td>
8651 <td>225</td>
8652 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8653 <td>intaggr_vintr_pend</td>
8654 <td>225</td>
8655 </tr>
8656 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8657 <td>182</td>
8658 <td>226</td>
8659 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8660 <td>intaggr_vintr_pend</td>
8661 <td>226</td>
8662 </tr>
8663 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8664 <td>182</td>
8665 <td>227</td>
8666 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8667 <td>intaggr_vintr_pend</td>
8668 <td>227</td>
8669 </tr>
8670 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8671 <td>182</td>
8672 <td>228</td>
8673 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8674 <td>intaggr_vintr_pend</td>
8675 <td>228</td>
8676 </tr>
8677 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8678 <td>182</td>
8679 <td>229</td>
8680 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8681 <td>intaggr_vintr_pend</td>
8682 <td>229</td>
8683 </tr>
8684 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8685 <td>182</td>
8686 <td>230</td>
8687 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8688 <td>intaggr_vintr_pend</td>
8689 <td>230</td>
8690 </tr>
8691 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8692 <td>182</td>
8693 <td>231</td>
8694 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8695 <td>intaggr_vintr_pend</td>
8696 <td>231</td>
8697 </tr>
8698 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8699 <td>182</td>
8700 <td>232</td>
8701 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8702 <td>intaggr_vintr_pend</td>
8703 <td>232</td>
8704 </tr>
8705 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8706 <td>182</td>
8707 <td>233</td>
8708 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8709 <td>intaggr_vintr_pend</td>
8710 <td>233</td>
8711 </tr>
8712 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8713 <td>182</td>
8714 <td>234</td>
8715 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8716 <td>intaggr_vintr_pend</td>
8717 <td>234</td>
8718 </tr>
8719 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8720 <td>182</td>
8721 <td>235</td>
8722 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8723 <td>intaggr_vintr_pend</td>
8724 <td>235</td>
8725 </tr>
8726 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8727 <td>182</td>
8728 <td>236</td>
8729 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8730 <td>intaggr_vintr_pend</td>
8731 <td>236</td>
8732 </tr>
8733 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8734 <td>182</td>
8735 <td>237</td>
8736 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8737 <td>intaggr_vintr_pend</td>
8738 <td>237</td>
8739 </tr>
8740 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8741 <td>182</td>
8742 <td>238</td>
8743 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8744 <td>intaggr_vintr_pend</td>
8745 <td>238</td>
8746 </tr>
8747 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8748 <td>182</td>
8749 <td>239</td>
8750 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8751 <td>intaggr_vintr_pend</td>
8752 <td>239</td>
8753 </tr>
8754 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8755 <td>182</td>
8756 <td>240</td>
8757 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8758 <td>intaggr_vintr_pend</td>
8759 <td>240</td>
8760 </tr>
8761 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8762 <td>182</td>
8763 <td>241</td>
8764 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8765 <td>intaggr_vintr_pend</td>
8766 <td>241</td>
8767 </tr>
8768 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8769 <td>182</td>
8770 <td>242</td>
8771 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8772 <td>intaggr_vintr_pend</td>
8773 <td>242</td>
8774 </tr>
8775 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8776 <td>182</td>
8777 <td>243</td>
8778 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8779 <td>intaggr_vintr_pend</td>
8780 <td>243</td>
8781 </tr>
8782 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8783 <td>182</td>
8784 <td>244</td>
8785 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8786 <td>intaggr_vintr_pend</td>
8787 <td>244</td>
8788 </tr>
8789 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8790 <td>182</td>
8791 <td>245</td>
8792 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8793 <td>intaggr_vintr_pend</td>
8794 <td>245</td>
8795 </tr>
8796 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8797 <td>182</td>
8798 <td>246</td>
8799 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8800 <td>intaggr_vintr_pend</td>
8801 <td>246</td>
8802 </tr>
8803 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8804 <td>182</td>
8805 <td>247</td>
8806 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8807 <td>intaggr_vintr_pend</td>
8808 <td>247</td>
8809 </tr>
8810 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8811 <td>182</td>
8812 <td>248</td>
8813 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8814 <td>intaggr_vintr_pend</td>
8815 <td>248</td>
8816 </tr>
8817 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8818 <td>182</td>
8819 <td>249</td>
8820 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8821 <td>intaggr_vintr_pend</td>
8822 <td>249</td>
8823 </tr>
8824 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8825 <td>182</td>
8826 <td>250</td>
8827 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8828 <td>intaggr_vintr_pend</td>
8829 <td>250</td>
8830 </tr>
8831 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8832 <td>182</td>
8833 <td>251</td>
8834 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8835 <td>intaggr_vintr_pend</td>
8836 <td>251</td>
8837 </tr>
8838 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8839 <td>182</td>
8840 <td>252</td>
8841 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8842 <td>intaggr_vintr_pend</td>
8843 <td>252</td>
8844 </tr>
8845 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8846 <td>182</td>
8847 <td>253</td>
8848 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8849 <td>intaggr_vintr_pend</td>
8850 <td>253</td>
8851 </tr>
8852 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8853 <td>182</td>
8854 <td>254</td>
8855 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8856 <td>intaggr_vintr_pend</td>
8857 <td>254</td>
8858 </tr>
8859 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8860 <td>182</td>
8861 <td>255</td>
8862 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
8863 <td>intaggr_vintr_pend</td>
8864 <td>255</td>
8865 </tr>
8866 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8867 <td>182</td>
8868 <td>256</td>
8869 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8870 <td>intaggr_vintr_pend</td>
8871 <td>0</td>
8872 </tr>
8873 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8874 <td>182</td>
8875 <td>257</td>
8876 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8877 <td>intaggr_vintr_pend</td>
8878 <td>1</td>
8879 </tr>
8880 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8881 <td>182</td>
8882 <td>258</td>
8883 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8884 <td>intaggr_vintr_pend</td>
8885 <td>2</td>
8886 </tr>
8887 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8888 <td>182</td>
8889 <td>259</td>
8890 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8891 <td>intaggr_vintr_pend</td>
8892 <td>3</td>
8893 </tr>
8894 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8895 <td>182</td>
8896 <td>260</td>
8897 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8898 <td>intaggr_vintr_pend</td>
8899 <td>4</td>
8900 </tr>
8901 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8902 <td>182</td>
8903 <td>261</td>
8904 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8905 <td>intaggr_vintr_pend</td>
8906 <td>5</td>
8907 </tr>
8908 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8909 <td>182</td>
8910 <td>262</td>
8911 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8912 <td>intaggr_vintr_pend</td>
8913 <td>6</td>
8914 </tr>
8915 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8916 <td>182</td>
8917 <td>263</td>
8918 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8919 <td>intaggr_vintr_pend</td>
8920 <td>7</td>
8921 </tr>
8922 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8923 <td>182</td>
8924 <td>264</td>
8925 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8926 <td>intaggr_vintr_pend</td>
8927 <td>8</td>
8928 </tr>
8929 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8930 <td>182</td>
8931 <td>265</td>
8932 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8933 <td>intaggr_vintr_pend</td>
8934 <td>9</td>
8935 </tr>
8936 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8937 <td>182</td>
8938 <td>266</td>
8939 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8940 <td>intaggr_vintr_pend</td>
8941 <td>10</td>
8942 </tr>
8943 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8944 <td>182</td>
8945 <td>267</td>
8946 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8947 <td>intaggr_vintr_pend</td>
8948 <td>11</td>
8949 </tr>
8950 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8951 <td>182</td>
8952 <td>268</td>
8953 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8954 <td>intaggr_vintr_pend</td>
8955 <td>12</td>
8956 </tr>
8957 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8958 <td>182</td>
8959 <td>269</td>
8960 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8961 <td>intaggr_vintr_pend</td>
8962 <td>13</td>
8963 </tr>
8964 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8965 <td>182</td>
8966 <td>270</td>
8967 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8968 <td>intaggr_vintr_pend</td>
8969 <td>14</td>
8970 </tr>
8971 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8972 <td>182</td>
8973 <td>271</td>
8974 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8975 <td>intaggr_vintr_pend</td>
8976 <td>15</td>
8977 </tr>
8978 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8979 <td>182</td>
8980 <td>272</td>
8981 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8982 <td>intaggr_vintr_pend</td>
8983 <td>16</td>
8984 </tr>
8985 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8986 <td>182</td>
8987 <td>273</td>
8988 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8989 <td>intaggr_vintr_pend</td>
8990 <td>17</td>
8991 </tr>
8992 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
8993 <td>182</td>
8994 <td>274</td>
8995 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
8996 <td>intaggr_vintr_pend</td>
8997 <td>18</td>
8998 </tr>
8999 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9000 <td>182</td>
9001 <td>275</td>
9002 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9003 <td>intaggr_vintr_pend</td>
9004 <td>19</td>
9005 </tr>
9006 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9007 <td>182</td>
9008 <td>276</td>
9009 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9010 <td>intaggr_vintr_pend</td>
9011 <td>20</td>
9012 </tr>
9013 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9014 <td>182</td>
9015 <td>277</td>
9016 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9017 <td>intaggr_vintr_pend</td>
9018 <td>21</td>
9019 </tr>
9020 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9021 <td>182</td>
9022 <td>278</td>
9023 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9024 <td>intaggr_vintr_pend</td>
9025 <td>22</td>
9026 </tr>
9027 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9028 <td>182</td>
9029 <td>279</td>
9030 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9031 <td>intaggr_vintr_pend</td>
9032 <td>23</td>
9033 </tr>
9034 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9035 <td>182</td>
9036 <td>280</td>
9037 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9038 <td>intaggr_vintr_pend</td>
9039 <td>24</td>
9040 </tr>
9041 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9042 <td>182</td>
9043 <td>281</td>
9044 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9045 <td>intaggr_vintr_pend</td>
9046 <td>25</td>
9047 </tr>
9048 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9049 <td>182</td>
9050 <td>282</td>
9051 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9052 <td>intaggr_vintr_pend</td>
9053 <td>26</td>
9054 </tr>
9055 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9056 <td>182</td>
9057 <td>283</td>
9058 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9059 <td>intaggr_vintr_pend</td>
9060 <td>27</td>
9061 </tr>
9062 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9063 <td>182</td>
9064 <td>284</td>
9065 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9066 <td>intaggr_vintr_pend</td>
9067 <td>28</td>
9068 </tr>
9069 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9070 <td>182</td>
9071 <td>285</td>
9072 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9073 <td>intaggr_vintr_pend</td>
9074 <td>29</td>
9075 </tr>
9076 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9077 <td>182</td>
9078 <td>286</td>
9079 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9080 <td>intaggr_vintr_pend</td>
9081 <td>30</td>
9082 </tr>
9083 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9084 <td>182</td>
9085 <td>287</td>
9086 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9087 <td>intaggr_vintr_pend</td>
9088 <td>31</td>
9089 </tr>
9090 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9091 <td>182</td>
9092 <td>288</td>
9093 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9094 <td>intaggr_vintr_pend</td>
9095 <td>32</td>
9096 </tr>
9097 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9098 <td>182</td>
9099 <td>289</td>
9100 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9101 <td>intaggr_vintr_pend</td>
9102 <td>33</td>
9103 </tr>
9104 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9105 <td>182</td>
9106 <td>290</td>
9107 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9108 <td>intaggr_vintr_pend</td>
9109 <td>34</td>
9110 </tr>
9111 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9112 <td>182</td>
9113 <td>291</td>
9114 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9115 <td>intaggr_vintr_pend</td>
9116 <td>35</td>
9117 </tr>
9118 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9119 <td>182</td>
9120 <td>292</td>
9121 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9122 <td>intaggr_vintr_pend</td>
9123 <td>36</td>
9124 </tr>
9125 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9126 <td>182</td>
9127 <td>293</td>
9128 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9129 <td>intaggr_vintr_pend</td>
9130 <td>37</td>
9131 </tr>
9132 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9133 <td>182</td>
9134 <td>294</td>
9135 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9136 <td>intaggr_vintr_pend</td>
9137 <td>38</td>
9138 </tr>
9139 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9140 <td>182</td>
9141 <td>295</td>
9142 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9143 <td>intaggr_vintr_pend</td>
9144 <td>39</td>
9145 </tr>
9146 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9147 <td>182</td>
9148 <td>296</td>
9149 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9150 <td>intaggr_vintr_pend</td>
9151 <td>40</td>
9152 </tr>
9153 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9154 <td>182</td>
9155 <td>297</td>
9156 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9157 <td>intaggr_vintr_pend</td>
9158 <td>41</td>
9159 </tr>
9160 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9161 <td>182</td>
9162 <td>298</td>
9163 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9164 <td>intaggr_vintr_pend</td>
9165 <td>42</td>
9166 </tr>
9167 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9168 <td>182</td>
9169 <td>299</td>
9170 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9171 <td>intaggr_vintr_pend</td>
9172 <td>43</td>
9173 </tr>
9174 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9175 <td>182</td>
9176 <td>300</td>
9177 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9178 <td>intaggr_vintr_pend</td>
9179 <td>44</td>
9180 </tr>
9181 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9182 <td>182</td>
9183 <td>301</td>
9184 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9185 <td>intaggr_vintr_pend</td>
9186 <td>45</td>
9187 </tr>
9188 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9189 <td>182</td>
9190 <td>302</td>
9191 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9192 <td>intaggr_vintr_pend</td>
9193 <td>46</td>
9194 </tr>
9195 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9196 <td>182</td>
9197 <td>303</td>
9198 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9199 <td>intaggr_vintr_pend</td>
9200 <td>47</td>
9201 </tr>
9202 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9203 <td>182</td>
9204 <td>304</td>
9205 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9206 <td>intaggr_vintr_pend</td>
9207 <td>48</td>
9208 </tr>
9209 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9210 <td>182</td>
9211 <td>305</td>
9212 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9213 <td>intaggr_vintr_pend</td>
9214 <td>49</td>
9215 </tr>
9216 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9217 <td>182</td>
9218 <td>306</td>
9219 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9220 <td>intaggr_vintr_pend</td>
9221 <td>50</td>
9222 </tr>
9223 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9224 <td>182</td>
9225 <td>307</td>
9226 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9227 <td>intaggr_vintr_pend</td>
9228 <td>51</td>
9229 </tr>
9230 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9231 <td>182</td>
9232 <td>308</td>
9233 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9234 <td>intaggr_vintr_pend</td>
9235 <td>52</td>
9236 </tr>
9237 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9238 <td>182</td>
9239 <td>309</td>
9240 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9241 <td>intaggr_vintr_pend</td>
9242 <td>53</td>
9243 </tr>
9244 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9245 <td>182</td>
9246 <td>310</td>
9247 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9248 <td>intaggr_vintr_pend</td>
9249 <td>54</td>
9250 </tr>
9251 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9252 <td>182</td>
9253 <td>311</td>
9254 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9255 <td>intaggr_vintr_pend</td>
9256 <td>55</td>
9257 </tr>
9258 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9259 <td>182</td>
9260 <td>312</td>
9261 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9262 <td>intaggr_vintr_pend</td>
9263 <td>56</td>
9264 </tr>
9265 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9266 <td>182</td>
9267 <td>313</td>
9268 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9269 <td>intaggr_vintr_pend</td>
9270 <td>57</td>
9271 </tr>
9272 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9273 <td>182</td>
9274 <td>314</td>
9275 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9276 <td>intaggr_vintr_pend</td>
9277 <td>58</td>
9278 </tr>
9279 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9280 <td>182</td>
9281 <td>315</td>
9282 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9283 <td>intaggr_vintr_pend</td>
9284 <td>59</td>
9285 </tr>
9286 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9287 <td>182</td>
9288 <td>316</td>
9289 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9290 <td>intaggr_vintr_pend</td>
9291 <td>60</td>
9292 </tr>
9293 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9294 <td>182</td>
9295 <td>317</td>
9296 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9297 <td>intaggr_vintr_pend</td>
9298 <td>61</td>
9299 </tr>
9300 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9301 <td>182</td>
9302 <td>318</td>
9303 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9304 <td>intaggr_vintr_pend</td>
9305 <td>62</td>
9306 </tr>
9307 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9308 <td>182</td>
9309 <td>319</td>
9310 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
9311 <td>intaggr_vintr_pend</td>
9312 <td>63</td>
9313 </tr>
9314 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9315 <td>182</td>
9316 <td>320</td>
9317 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9318 <td>intaggr_vintr_pend</td>
9319 <td>0</td>
9320 </tr>
9321 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9322 <td>182</td>
9323 <td>321</td>
9324 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9325 <td>intaggr_vintr_pend</td>
9326 <td>1</td>
9327 </tr>
9328 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9329 <td>182</td>
9330 <td>322</td>
9331 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9332 <td>intaggr_vintr_pend</td>
9333 <td>2</td>
9334 </tr>
9335 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9336 <td>182</td>
9337 <td>323</td>
9338 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9339 <td>intaggr_vintr_pend</td>
9340 <td>3</td>
9341 </tr>
9342 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9343 <td>182</td>
9344 <td>324</td>
9345 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9346 <td>intaggr_vintr_pend</td>
9347 <td>4</td>
9348 </tr>
9349 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9350 <td>182</td>
9351 <td>325</td>
9352 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9353 <td>intaggr_vintr_pend</td>
9354 <td>5</td>
9355 </tr>
9356 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9357 <td>182</td>
9358 <td>326</td>
9359 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9360 <td>intaggr_vintr_pend</td>
9361 <td>6</td>
9362 </tr>
9363 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9364 <td>182</td>
9365 <td>327</td>
9366 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9367 <td>intaggr_vintr_pend</td>
9368 <td>7</td>
9369 </tr>
9370 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9371 <td>182</td>
9372 <td>328</td>
9373 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9374 <td>intaggr_vintr_pend</td>
9375 <td>8</td>
9376 </tr>
9377 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9378 <td>182</td>
9379 <td>329</td>
9380 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9381 <td>intaggr_vintr_pend</td>
9382 <td>9</td>
9383 </tr>
9384 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9385 <td>182</td>
9386 <td>330</td>
9387 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9388 <td>intaggr_vintr_pend</td>
9389 <td>10</td>
9390 </tr>
9391 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9392 <td>182</td>
9393 <td>331</td>
9394 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9395 <td>intaggr_vintr_pend</td>
9396 <td>11</td>
9397 </tr>
9398 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9399 <td>182</td>
9400 <td>332</td>
9401 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9402 <td>intaggr_vintr_pend</td>
9403 <td>12</td>
9404 </tr>
9405 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9406 <td>182</td>
9407 <td>333</td>
9408 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9409 <td>intaggr_vintr_pend</td>
9410 <td>13</td>
9411 </tr>
9412 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9413 <td>182</td>
9414 <td>334</td>
9415 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9416 <td>intaggr_vintr_pend</td>
9417 <td>14</td>
9418 </tr>
9419 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9420 <td>182</td>
9421 <td>335</td>
9422 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9423 <td>intaggr_vintr_pend</td>
9424 <td>15</td>
9425 </tr>
9426 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9427 <td>182</td>
9428 <td>336</td>
9429 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9430 <td>intaggr_vintr_pend</td>
9431 <td>16</td>
9432 </tr>
9433 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9434 <td>182</td>
9435 <td>337</td>
9436 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9437 <td>intaggr_vintr_pend</td>
9438 <td>17</td>
9439 </tr>
9440 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9441 <td>182</td>
9442 <td>338</td>
9443 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9444 <td>intaggr_vintr_pend</td>
9445 <td>18</td>
9446 </tr>
9447 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9448 <td>182</td>
9449 <td>339</td>
9450 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9451 <td>intaggr_vintr_pend</td>
9452 <td>19</td>
9453 </tr>
9454 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9455 <td>182</td>
9456 <td>340</td>
9457 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9458 <td>intaggr_vintr_pend</td>
9459 <td>20</td>
9460 </tr>
9461 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9462 <td>182</td>
9463 <td>341</td>
9464 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9465 <td>intaggr_vintr_pend</td>
9466 <td>21</td>
9467 </tr>
9468 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9469 <td>182</td>
9470 <td>342</td>
9471 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9472 <td>intaggr_vintr_pend</td>
9473 <td>22</td>
9474 </tr>
9475 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9476 <td>182</td>
9477 <td>343</td>
9478 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9479 <td>intaggr_vintr_pend</td>
9480 <td>23</td>
9481 </tr>
9482 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9483 <td>182</td>
9484 <td>344</td>
9485 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9486 <td>intaggr_vintr_pend</td>
9487 <td>24</td>
9488 </tr>
9489 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9490 <td>182</td>
9491 <td>345</td>
9492 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9493 <td>intaggr_vintr_pend</td>
9494 <td>25</td>
9495 </tr>
9496 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9497 <td>182</td>
9498 <td>346</td>
9499 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9500 <td>intaggr_vintr_pend</td>
9501 <td>26</td>
9502 </tr>
9503 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9504 <td>182</td>
9505 <td>347</td>
9506 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9507 <td>intaggr_vintr_pend</td>
9508 <td>27</td>
9509 </tr>
9510 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9511 <td>182</td>
9512 <td>348</td>
9513 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9514 <td>intaggr_vintr_pend</td>
9515 <td>28</td>
9516 </tr>
9517 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9518 <td>182</td>
9519 <td>349</td>
9520 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9521 <td>intaggr_vintr_pend</td>
9522 <td>29</td>
9523 </tr>
9524 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9525 <td>182</td>
9526 <td>350</td>
9527 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9528 <td>intaggr_vintr_pend</td>
9529 <td>30</td>
9530 </tr>
9531 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9532 <td>182</td>
9533 <td>351</td>
9534 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9535 <td>intaggr_vintr_pend</td>
9536 <td>31</td>
9537 </tr>
9538 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9539 <td>182</td>
9540 <td>352</td>
9541 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9542 <td>intaggr_vintr_pend</td>
9543 <td>32</td>
9544 </tr>
9545 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9546 <td>182</td>
9547 <td>353</td>
9548 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9549 <td>intaggr_vintr_pend</td>
9550 <td>33</td>
9551 </tr>
9552 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9553 <td>182</td>
9554 <td>354</td>
9555 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9556 <td>intaggr_vintr_pend</td>
9557 <td>34</td>
9558 </tr>
9559 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9560 <td>182</td>
9561 <td>355</td>
9562 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9563 <td>intaggr_vintr_pend</td>
9564 <td>35</td>
9565 </tr>
9566 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9567 <td>182</td>
9568 <td>356</td>
9569 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9570 <td>intaggr_vintr_pend</td>
9571 <td>36</td>
9572 </tr>
9573 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9574 <td>182</td>
9575 <td>357</td>
9576 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9577 <td>intaggr_vintr_pend</td>
9578 <td>37</td>
9579 </tr>
9580 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9581 <td>182</td>
9582 <td>358</td>
9583 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9584 <td>intaggr_vintr_pend</td>
9585 <td>38</td>
9586 </tr>
9587 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9588 <td>182</td>
9589 <td>359</td>
9590 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9591 <td>intaggr_vintr_pend</td>
9592 <td>39</td>
9593 </tr>
9594 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9595 <td>182</td>
9596 <td>360</td>
9597 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9598 <td>intaggr_vintr_pend</td>
9599 <td>40</td>
9600 </tr>
9601 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9602 <td>182</td>
9603 <td>361</td>
9604 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9605 <td>intaggr_vintr_pend</td>
9606 <td>41</td>
9607 </tr>
9608 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9609 <td>182</td>
9610 <td>362</td>
9611 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9612 <td>intaggr_vintr_pend</td>
9613 <td>42</td>
9614 </tr>
9615 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9616 <td>182</td>
9617 <td>363</td>
9618 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9619 <td>intaggr_vintr_pend</td>
9620 <td>43</td>
9621 </tr>
9622 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9623 <td>182</td>
9624 <td>364</td>
9625 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9626 <td>intaggr_vintr_pend</td>
9627 <td>44</td>
9628 </tr>
9629 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9630 <td>182</td>
9631 <td>365</td>
9632 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9633 <td>intaggr_vintr_pend</td>
9634 <td>45</td>
9635 </tr>
9636 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9637 <td>182</td>
9638 <td>366</td>
9639 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9640 <td>intaggr_vintr_pend</td>
9641 <td>46</td>
9642 </tr>
9643 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9644 <td>182</td>
9645 <td>367</td>
9646 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9647 <td>intaggr_vintr_pend</td>
9648 <td>47</td>
9649 </tr>
9650 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9651 <td>182</td>
9652 <td>368</td>
9653 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9654 <td>intaggr_vintr_pend</td>
9655 <td>48</td>
9656 </tr>
9657 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9658 <td>182</td>
9659 <td>369</td>
9660 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9661 <td>intaggr_vintr_pend</td>
9662 <td>49</td>
9663 </tr>
9664 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9665 <td>182</td>
9666 <td>370</td>
9667 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9668 <td>intaggr_vintr_pend</td>
9669 <td>50</td>
9670 </tr>
9671 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9672 <td>182</td>
9673 <td>371</td>
9674 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9675 <td>intaggr_vintr_pend</td>
9676 <td>51</td>
9677 </tr>
9678 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9679 <td>182</td>
9680 <td>372</td>
9681 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9682 <td>intaggr_vintr_pend</td>
9683 <td>52</td>
9684 </tr>
9685 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9686 <td>182</td>
9687 <td>373</td>
9688 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9689 <td>intaggr_vintr_pend</td>
9690 <td>53</td>
9691 </tr>
9692 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9693 <td>182</td>
9694 <td>374</td>
9695 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9696 <td>intaggr_vintr_pend</td>
9697 <td>54</td>
9698 </tr>
9699 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9700 <td>182</td>
9701 <td>375</td>
9702 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9703 <td>intaggr_vintr_pend</td>
9704 <td>55</td>
9705 </tr>
9706 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9707 <td>182</td>
9708 <td>376</td>
9709 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9710 <td>intaggr_vintr_pend</td>
9711 <td>56</td>
9712 </tr>
9713 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9714 <td>182</td>
9715 <td>377</td>
9716 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9717 <td>intaggr_vintr_pend</td>
9718 <td>57</td>
9719 </tr>
9720 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9721 <td>182</td>
9722 <td>378</td>
9723 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9724 <td>intaggr_vintr_pend</td>
9725 <td>58</td>
9726 </tr>
9727 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9728 <td>182</td>
9729 <td>379</td>
9730 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9731 <td>intaggr_vintr_pend</td>
9732 <td>59</td>
9733 </tr>
9734 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9735 <td>182</td>
9736 <td>380</td>
9737 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9738 <td>intaggr_vintr_pend</td>
9739 <td>60</td>
9740 </tr>
9741 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9742 <td>182</td>
9743 <td>381</td>
9744 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9745 <td>intaggr_vintr_pend</td>
9746 <td>61</td>
9747 </tr>
9748 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9749 <td>182</td>
9750 <td>382</td>
9751 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9752 <td>intaggr_vintr_pend</td>
9753 <td>62</td>
9754 </tr>
9755 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9756 <td>182</td>
9757 <td>383</td>
9758 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
9759 <td>intaggr_vintr_pend</td>
9760 <td>63</td>
9761 </tr>
9762 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9763 <td>182</td>
9764 <td>384</td>
9765 <td>AM6_DEV_NAVSS0_MCRC0</td>
9766 <td>dma_event_intr</td>
9767 <td>0</td>
9768 </tr>
9769 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9770 <td>182</td>
9771 <td>385</td>
9772 <td>AM6_DEV_NAVSS0_MCRC0</td>
9773 <td>dma_event_intr</td>
9774 <td>1</td>
9775 </tr>
9776 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9777 <td>182</td>
9778 <td>386</td>
9779 <td>AM6_DEV_NAVSS0_MCRC0</td>
9780 <td>dma_event_intr</td>
9781 <td>2</td>
9782 </tr>
9783 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9784 <td>182</td>
9785 <td>387</td>
9786 <td>AM6_DEV_NAVSS0_MCRC0</td>
9787 <td>dma_event_intr</td>
9788 <td>3</td>
9789 </tr>
9790 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9791 <td>182</td>
9792 <td>388</td>
9793 <td>AM6_DEV_NAVSS0_MCRC0</td>
9794 <td>intaggr_vintr_pend</td>
9795 <td>0</td>
9796 </tr>
9797 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9798 <td>182</td>
9799 <td>389</td>
9800 <td>AM6_DEV_NAVSS0_PVU1</td>
9801 <td>exp_intr</td>
9802 <td>0</td>
9803 </tr>
9804 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9805 <td>182</td>
9806 <td>390</td>
9807 <td>AM6_DEV_NAVSS0_PVU0</td>
9808 <td>exp_intr</td>
9809 <td>0</td>
9810 </tr>
9811 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9812 <td>182</td>
9813 <td>391</td>
9814 <td>AM6_DEV_NAVSS0_CPTS0</td>
9815 <td>event_pend_intr</td>
9816 <td>0</td>
9817 </tr>
9818 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9819 <td>182</td>
9820 <td>392</td>
9821 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11</td>
9822 <td>pend_intr</td>
9823 <td>0</td>
9824 </tr>
9825 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9826 <td>182</td>
9827 <td>393</td>
9828 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11</td>
9829 <td>pend_intr</td>
9830 <td>1</td>
9831 </tr>
9832 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9833 <td>182</td>
9834 <td>394</td>
9835 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11</td>
9836 <td>pend_intr</td>
9837 <td>2</td>
9838 </tr>
9839 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9840 <td>182</td>
9841 <td>395</td>
9842 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11</td>
9843 <td>pend_intr</td>
9844 <td>3</td>
9845 </tr>
9846 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9847 <td>182</td>
9848 <td>396</td>
9849 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10</td>
9850 <td>pend_intr</td>
9851 <td>0</td>
9852 </tr>
9853 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9854 <td>182</td>
9855 <td>397</td>
9856 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10</td>
9857 <td>pend_intr</td>
9858 <td>1</td>
9859 </tr>
9860 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9861 <td>182</td>
9862 <td>398</td>
9863 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10</td>
9864 <td>pend_intr</td>
9865 <td>2</td>
9866 </tr>
9867 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9868 <td>182</td>
9869 <td>399</td>
9870 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10</td>
9871 <td>pend_intr</td>
9872 <td>3</td>
9873 </tr>
9874 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9875 <td>182</td>
9876 <td>400</td>
9877 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9</td>
9878 <td>pend_intr</td>
9879 <td>0</td>
9880 </tr>
9881 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9882 <td>182</td>
9883 <td>401</td>
9884 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9</td>
9885 <td>pend_intr</td>
9886 <td>1</td>
9887 </tr>
9888 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9889 <td>182</td>
9890 <td>402</td>
9891 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9</td>
9892 <td>pend_intr</td>
9893 <td>2</td>
9894 </tr>
9895 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9896 <td>182</td>
9897 <td>403</td>
9898 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9</td>
9899 <td>pend_intr</td>
9900 <td>3</td>
9901 </tr>
9902 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9903 <td>182</td>
9904 <td>404</td>
9905 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8</td>
9906 <td>pend_intr</td>
9907 <td>0</td>
9908 </tr>
9909 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9910 <td>182</td>
9911 <td>405</td>
9912 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8</td>
9913 <td>pend_intr</td>
9914 <td>1</td>
9915 </tr>
9916 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9917 <td>182</td>
9918 <td>406</td>
9919 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8</td>
9920 <td>pend_intr</td>
9921 <td>2</td>
9922 </tr>
9923 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9924 <td>182</td>
9925 <td>407</td>
9926 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8</td>
9927 <td>pend_intr</td>
9928 <td>3</td>
9929 </tr>
9930 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9931 <td>182</td>
9932 <td>408</td>
9933 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7</td>
9934 <td>pend_intr</td>
9935 <td>0</td>
9936 </tr>
9937 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9938 <td>182</td>
9939 <td>409</td>
9940 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7</td>
9941 <td>pend_intr</td>
9942 <td>1</td>
9943 </tr>
9944 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9945 <td>182</td>
9946 <td>410</td>
9947 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7</td>
9948 <td>pend_intr</td>
9949 <td>2</td>
9950 </tr>
9951 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9952 <td>182</td>
9953 <td>411</td>
9954 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7</td>
9955 <td>pend_intr</td>
9956 <td>3</td>
9957 </tr>
9958 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9959 <td>182</td>
9960 <td>412</td>
9961 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6</td>
9962 <td>pend_intr</td>
9963 <td>0</td>
9964 </tr>
9965 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9966 <td>182</td>
9967 <td>413</td>
9968 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6</td>
9969 <td>pend_intr</td>
9970 <td>1</td>
9971 </tr>
9972 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9973 <td>182</td>
9974 <td>414</td>
9975 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6</td>
9976 <td>pend_intr</td>
9977 <td>2</td>
9978 </tr>
9979 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9980 <td>182</td>
9981 <td>415</td>
9982 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6</td>
9983 <td>pend_intr</td>
9984 <td>3</td>
9985 </tr>
9986 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9987 <td>182</td>
9988 <td>416</td>
9989 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5</td>
9990 <td>pend_intr</td>
9991 <td>0</td>
9992 </tr>
9993 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
9994 <td>182</td>
9995 <td>417</td>
9996 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5</td>
9997 <td>pend_intr</td>
9998 <td>1</td>
9999 </tr>
10000 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10001 <td>182</td>
10002 <td>418</td>
10003 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5</td>
10004 <td>pend_intr</td>
10005 <td>2</td>
10006 </tr>
10007 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10008 <td>182</td>
10009 <td>419</td>
10010 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5</td>
10011 <td>pend_intr</td>
10012 <td>3</td>
10013 </tr>
10014 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10015 <td>182</td>
10016 <td>420</td>
10017 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4</td>
10018 <td>pend_intr</td>
10019 <td>0</td>
10020 </tr>
10021 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10022 <td>182</td>
10023 <td>421</td>
10024 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4</td>
10025 <td>pend_intr</td>
10026 <td>1</td>
10027 </tr>
10028 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10029 <td>182</td>
10030 <td>422</td>
10031 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4</td>
10032 <td>pend_intr</td>
10033 <td>2</td>
10034 </tr>
10035 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10036 <td>182</td>
10037 <td>423</td>
10038 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4</td>
10039 <td>pend_intr</td>
10040 <td>3</td>
10041 </tr>
10042 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10043 <td>182</td>
10044 <td>424</td>
10045 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3</td>
10046 <td>pend_intr</td>
10047 <td>0</td>
10048 </tr>
10049 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10050 <td>182</td>
10051 <td>425</td>
10052 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3</td>
10053 <td>pend_intr</td>
10054 <td>1</td>
10055 </tr>
10056 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10057 <td>182</td>
10058 <td>426</td>
10059 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3</td>
10060 <td>pend_intr</td>
10061 <td>2</td>
10062 </tr>
10063 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10064 <td>182</td>
10065 <td>427</td>
10066 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3</td>
10067 <td>pend_intr</td>
10068 <td>3</td>
10069 </tr>
10070 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10071 <td>182</td>
10072 <td>428</td>
10073 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2</td>
10074 <td>pend_intr</td>
10075 <td>0</td>
10076 </tr>
10077 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10078 <td>182</td>
10079 <td>429</td>
10080 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2</td>
10081 <td>pend_intr</td>
10082 <td>1</td>
10083 </tr>
10084 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10085 <td>182</td>
10086 <td>430</td>
10087 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2</td>
10088 <td>pend_intr</td>
10089 <td>2</td>
10090 </tr>
10091 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10092 <td>182</td>
10093 <td>431</td>
10094 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2</td>
10095 <td>pend_intr</td>
10096 <td>3</td>
10097 </tr>
10098 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10099 <td>182</td>
10100 <td>432</td>
10101 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1</td>
10102 <td>pend_intr</td>
10103 <td>0</td>
10104 </tr>
10105 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10106 <td>182</td>
10107 <td>433</td>
10108 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1</td>
10109 <td>pend_intr</td>
10110 <td>1</td>
10111 </tr>
10112 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10113 <td>182</td>
10114 <td>434</td>
10115 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1</td>
10116 <td>pend_intr</td>
10117 <td>2</td>
10118 </tr>
10119 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10120 <td>182</td>
10121 <td>435</td>
10122 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1</td>
10123 <td>pend_intr</td>
10124 <td>3</td>
10125 </tr>
10126 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10127 <td>182</td>
10128 <td>436</td>
10129 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0</td>
10130 <td>pend_intr</td>
10131 <td>0</td>
10132 </tr>
10133 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10134 <td>182</td>
10135 <td>437</td>
10136 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0</td>
10137 <td>pend_intr</td>
10138 <td>1</td>
10139 </tr>
10140 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10141 <td>182</td>
10142 <td>438</td>
10143 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0</td>
10144 <td>pend_intr</td>
10145 <td>2</td>
10146 </tr>
10147 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10148 <td>182</td>
10149 <td>439</td>
10150 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0</td>
10151 <td>pend_intr</td>
10152 <td>3</td>
10153 </tr>
10154 </tbody>
10155 </table>
10156 </div>
10157 <div class="section" id="navss0-intr-router-0-interrupt-router-output-destinations">
10158 <span id="pub-soc-am65x-sr2-navss0-intr-router-0-output-src-list"></span><h2>navss0_intr_router_0 Interrupt Router Output Destinations<a class="headerlink" href="#navss0-intr-router-0-interrupt-router-output-destinations" title="Permalink to this headline">¶</a></h2>
10159 <div class="admonition warning">
10160 <p class="first admonition-title">Warning</p>
10161 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
10162 host within the RM Board Configuration resource assignment array.  The RM
10163 Board Configuration is rejected if an overlap with a reserved resource is
10164 detected.</p>
10165 </div>
10166 <table border="1" class="docutils">
10167 <colgroup>
10168 <col width="24%" />
10169 <col width="11%" />
10170 <col width="13%" />
10171 <col width="21%" />
10172 <col width="17%" />
10173 <col width="14%" />
10174 </colgroup>
10175 <thead valign="bottom">
10176 <tr class="row-odd"><th class="head">IR Name</th>
10177 <th class="head">IR Device ID</th>
10178 <th class="head">IR Output Index</th>
10179 <th class="head">Destination Name</th>
10180 <th class="head">Destination Interface</th>
10181 <th class="head">Destination Index</th>
10182 </tr>
10183 </thead>
10184 <tbody valign="top">
10185 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10186 (<strong>Reserved by System Firmware</strong>)</td>
10187 <td>182</td>
10188 <td>0</td>
10189 <td>AM6_DEV_GIC0</td>
10190 <td>spi</td>
10191 <td>64</td>
10192 </tr>
10193 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10194 (<strong>Reserved by System Firmware</strong>)</td>
10195 <td>182</td>
10196 <td>1</td>
10197 <td>AM6_DEV_GIC0</td>
10198 <td>spi</td>
10199 <td>65</td>
10200 </tr>
10201 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10202 (<strong>Reserved by System Firmware</strong>)</td>
10203 <td>182</td>
10204 <td>2</td>
10205 <td>AM6_DEV_GIC0</td>
10206 <td>spi</td>
10207 <td>66</td>
10208 </tr>
10209 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10210 (<strong>Reserved by System Firmware</strong>)</td>
10211 <td>182</td>
10212 <td>3</td>
10213 <td>AM6_DEV_GIC0</td>
10214 <td>spi</td>
10215 <td>67</td>
10216 </tr>
10217 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10218 (<strong>Reserved by System Firmware</strong>)</td>
10219 <td>182</td>
10220 <td>4</td>
10221 <td>AM6_DEV_GIC0</td>
10222 <td>spi</td>
10223 <td>68</td>
10224 </tr>
10225 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10226 (<strong>Reserved by System Firmware</strong>)</td>
10227 <td>182</td>
10228 <td>5</td>
10229 <td>AM6_DEV_GIC0</td>
10230 <td>spi</td>
10231 <td>69</td>
10232 </tr>
10233 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10234 (<strong>Reserved by System Firmware</strong>)</td>
10235 <td>182</td>
10236 <td>6</td>
10237 <td>AM6_DEV_GIC0</td>
10238 <td>spi</td>
10239 <td>70</td>
10240 </tr>
10241 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10242 (<strong>Reserved by System Firmware</strong>)</td>
10243 <td>182</td>
10244 <td>7</td>
10245 <td>AM6_DEV_GIC0</td>
10246 <td>spi</td>
10247 <td>71</td>
10248 </tr>
10249 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10250 (<strong>Reserved by System Firmware</strong>)</td>
10251 <td>182</td>
10252 <td>8</td>
10253 <td>AM6_DEV_GIC0</td>
10254 <td>spi</td>
10255 <td>72</td>
10256 </tr>
10257 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10258 (<strong>Reserved by System Firmware</strong>)</td>
10259 <td>182</td>
10260 <td>9</td>
10261 <td>AM6_DEV_GIC0</td>
10262 <td>spi</td>
10263 <td>73</td>
10264 </tr>
10265 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10266 (<strong>Reserved by System Firmware</strong>)</td>
10267 <td>182</td>
10268 <td>10</td>
10269 <td>AM6_DEV_GIC0</td>
10270 <td>spi</td>
10271 <td>74</td>
10272 </tr>
10273 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10274 (<strong>Reserved by System Firmware</strong>)</td>
10275 <td>182</td>
10276 <td>11</td>
10277 <td>AM6_DEV_GIC0</td>
10278 <td>spi</td>
10279 <td>75</td>
10280 </tr>
10281 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10282 (<strong>Reserved by System Firmware</strong>)</td>
10283 <td>182</td>
10284 <td>12</td>
10285 <td>AM6_DEV_GIC0</td>
10286 <td>spi</td>
10287 <td>76</td>
10288 </tr>
10289 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10290 (<strong>Reserved by System Firmware</strong>)</td>
10291 <td>182</td>
10292 <td>13</td>
10293 <td>AM6_DEV_GIC0</td>
10294 <td>spi</td>
10295 <td>77</td>
10296 </tr>
10297 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10298 (<strong>Reserved by System Firmware</strong>)</td>
10299 <td>182</td>
10300 <td>14</td>
10301 <td>AM6_DEV_GIC0</td>
10302 <td>spi</td>
10303 <td>78</td>
10304 </tr>
10305 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0
10306 (<strong>Reserved by System Firmware</strong>)</td>
10307 <td>182</td>
10308 <td>15</td>
10309 <td>AM6_DEV_GIC0</td>
10310 <td>spi</td>
10311 <td>79</td>
10312 </tr>
10313 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10314 <td>182</td>
10315 <td>16</td>
10316 <td>AM6_DEV_GIC0</td>
10317 <td>spi</td>
10318 <td>80</td>
10319 </tr>
10320 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10321 <td>182</td>
10322 <td>17</td>
10323 <td>AM6_DEV_GIC0</td>
10324 <td>spi</td>
10325 <td>81</td>
10326 </tr>
10327 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10328 <td>182</td>
10329 <td>18</td>
10330 <td>AM6_DEV_GIC0</td>
10331 <td>spi</td>
10332 <td>82</td>
10333 </tr>
10334 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10335 <td>182</td>
10336 <td>19</td>
10337 <td>AM6_DEV_GIC0</td>
10338 <td>spi</td>
10339 <td>83</td>
10340 </tr>
10341 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10342 <td>182</td>
10343 <td>20</td>
10344 <td>AM6_DEV_GIC0</td>
10345 <td>spi</td>
10346 <td>84</td>
10347 </tr>
10348 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10349 <td>182</td>
10350 <td>21</td>
10351 <td>AM6_DEV_GIC0</td>
10352 <td>spi</td>
10353 <td>85</td>
10354 </tr>
10355 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10356 <td>182</td>
10357 <td>22</td>
10358 <td>AM6_DEV_GIC0</td>
10359 <td>spi</td>
10360 <td>86</td>
10361 </tr>
10362 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10363 <td>182</td>
10364 <td>23</td>
10365 <td>AM6_DEV_GIC0</td>
10366 <td>spi</td>
10367 <td>87</td>
10368 </tr>
10369 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10370 <td>182</td>
10371 <td>24</td>
10372 <td>AM6_DEV_GIC0</td>
10373 <td>spi</td>
10374 <td>88</td>
10375 </tr>
10376 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10377 <td>182</td>
10378 <td>25</td>
10379 <td>AM6_DEV_GIC0</td>
10380 <td>spi</td>
10381 <td>89</td>
10382 </tr>
10383 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10384 <td>182</td>
10385 <td>26</td>
10386 <td>AM6_DEV_GIC0</td>
10387 <td>spi</td>
10388 <td>90</td>
10389 </tr>
10390 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10391 <td>182</td>
10392 <td>27</td>
10393 <td>AM6_DEV_GIC0</td>
10394 <td>spi</td>
10395 <td>91</td>
10396 </tr>
10397 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10398 <td>182</td>
10399 <td>28</td>
10400 <td>AM6_DEV_GIC0</td>
10401 <td>spi</td>
10402 <td>92</td>
10403 </tr>
10404 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10405 <td>182</td>
10406 <td>29</td>
10407 <td>AM6_DEV_GIC0</td>
10408 <td>spi</td>
10409 <td>93</td>
10410 </tr>
10411 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10412 <td>182</td>
10413 <td>30</td>
10414 <td>AM6_DEV_GIC0</td>
10415 <td>spi</td>
10416 <td>94</td>
10417 </tr>
10418 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10419 <td>182</td>
10420 <td>31</td>
10421 <td>AM6_DEV_GIC0</td>
10422 <td>spi</td>
10423 <td>95</td>
10424 </tr>
10425 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10426 <td>182</td>
10427 <td>32</td>
10428 <td>AM6_DEV_GIC0</td>
10429 <td>spi</td>
10430 <td>96</td>
10431 </tr>
10432 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10433 <td>182</td>
10434 <td>33</td>
10435 <td>AM6_DEV_GIC0</td>
10436 <td>spi</td>
10437 <td>97</td>
10438 </tr>
10439 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10440 <td>182</td>
10441 <td>34</td>
10442 <td>AM6_DEV_GIC0</td>
10443 <td>spi</td>
10444 <td>98</td>
10445 </tr>
10446 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10447 <td>182</td>
10448 <td>35</td>
10449 <td>AM6_DEV_GIC0</td>
10450 <td>spi</td>
10451 <td>99</td>
10452 </tr>
10453 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10454 <td>182</td>
10455 <td>36</td>
10456 <td>AM6_DEV_GIC0</td>
10457 <td>spi</td>
10458 <td>100</td>
10459 </tr>
10460 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10461 <td>182</td>
10462 <td>37</td>
10463 <td>AM6_DEV_GIC0</td>
10464 <td>spi</td>
10465 <td>101</td>
10466 </tr>
10467 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10468 <td>182</td>
10469 <td>38</td>
10470 <td>AM6_DEV_GIC0</td>
10471 <td>spi</td>
10472 <td>102</td>
10473 </tr>
10474 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10475 <td>182</td>
10476 <td>39</td>
10477 <td>AM6_DEV_GIC0</td>
10478 <td>spi</td>
10479 <td>103</td>
10480 </tr>
10481 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10482 <td>182</td>
10483 <td>40</td>
10484 <td>AM6_DEV_GIC0</td>
10485 <td>spi</td>
10486 <td>104</td>
10487 </tr>
10488 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10489 <td>182</td>
10490 <td>41</td>
10491 <td>AM6_DEV_GIC0</td>
10492 <td>spi</td>
10493 <td>105</td>
10494 </tr>
10495 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10496 <td>182</td>
10497 <td>42</td>
10498 <td>AM6_DEV_GIC0</td>
10499 <td>spi</td>
10500 <td>106</td>
10501 </tr>
10502 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10503 <td>182</td>
10504 <td>43</td>
10505 <td>AM6_DEV_GIC0</td>
10506 <td>spi</td>
10507 <td>107</td>
10508 </tr>
10509 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10510 <td>182</td>
10511 <td>44</td>
10512 <td>AM6_DEV_GIC0</td>
10513 <td>spi</td>
10514 <td>108</td>
10515 </tr>
10516 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10517 <td>182</td>
10518 <td>45</td>
10519 <td>AM6_DEV_GIC0</td>
10520 <td>spi</td>
10521 <td>109</td>
10522 </tr>
10523 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10524 <td>182</td>
10525 <td>46</td>
10526 <td>AM6_DEV_GIC0</td>
10527 <td>spi</td>
10528 <td>110</td>
10529 </tr>
10530 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10531 <td>182</td>
10532 <td>47</td>
10533 <td>AM6_DEV_GIC0</td>
10534 <td>spi</td>
10535 <td>111</td>
10536 </tr>
10537 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10538 <td>182</td>
10539 <td>48</td>
10540 <td>AM6_DEV_GIC0</td>
10541 <td>spi</td>
10542 <td>112</td>
10543 </tr>
10544 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10545 <td>182</td>
10546 <td>49</td>
10547 <td>AM6_DEV_GIC0</td>
10548 <td>spi</td>
10549 <td>113</td>
10550 </tr>
10551 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10552 <td>182</td>
10553 <td>50</td>
10554 <td>AM6_DEV_GIC0</td>
10555 <td>spi</td>
10556 <td>114</td>
10557 </tr>
10558 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10559 <td>182</td>
10560 <td>51</td>
10561 <td>AM6_DEV_GIC0</td>
10562 <td>spi</td>
10563 <td>115</td>
10564 </tr>
10565 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10566 <td>182</td>
10567 <td>52</td>
10568 <td>AM6_DEV_GIC0</td>
10569 <td>spi</td>
10570 <td>116</td>
10571 </tr>
10572 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10573 <td>182</td>
10574 <td>53</td>
10575 <td>AM6_DEV_GIC0</td>
10576 <td>spi</td>
10577 <td>117</td>
10578 </tr>
10579 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10580 <td>182</td>
10581 <td>54</td>
10582 <td>AM6_DEV_GIC0</td>
10583 <td>spi</td>
10584 <td>118</td>
10585 </tr>
10586 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10587 <td>182</td>
10588 <td>55</td>
10589 <td>AM6_DEV_GIC0</td>
10590 <td>spi</td>
10591 <td>119</td>
10592 </tr>
10593 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10594 <td>182</td>
10595 <td>56</td>
10596 <td>AM6_DEV_GIC0</td>
10597 <td>spi</td>
10598 <td>120</td>
10599 </tr>
10600 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10601 <td>182</td>
10602 <td>57</td>
10603 <td>AM6_DEV_GIC0</td>
10604 <td>spi</td>
10605 <td>121</td>
10606 </tr>
10607 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10608 <td>182</td>
10609 <td>58</td>
10610 <td>AM6_DEV_GIC0</td>
10611 <td>spi</td>
10612 <td>122</td>
10613 </tr>
10614 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10615 <td>182</td>
10616 <td>59</td>
10617 <td>AM6_DEV_GIC0</td>
10618 <td>spi</td>
10619 <td>123</td>
10620 </tr>
10621 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10622 <td>182</td>
10623 <td>60</td>
10624 <td>AM6_DEV_GIC0</td>
10625 <td>spi</td>
10626 <td>124</td>
10627 </tr>
10628 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10629 <td>182</td>
10630 <td>61</td>
10631 <td>AM6_DEV_GIC0</td>
10632 <td>spi</td>
10633 <td>125</td>
10634 </tr>
10635 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10636 <td>182</td>
10637 <td>62</td>
10638 <td>AM6_DEV_GIC0</td>
10639 <td>spi</td>
10640 <td>126</td>
10641 </tr>
10642 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10643 <td>182</td>
10644 <td>63</td>
10645 <td>AM6_DEV_GIC0</td>
10646 <td>spi</td>
10647 <td>127</td>
10648 </tr>
10649 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10650 <td>182</td>
10651 <td>64</td>
10652 <td>AM6_DEV_GIC0</td>
10653 <td>spi</td>
10654 <td>448</td>
10655 </tr>
10656 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10657 <td>182</td>
10658 <td>65</td>
10659 <td>AM6_DEV_GIC0</td>
10660 <td>spi</td>
10661 <td>449</td>
10662 </tr>
10663 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10664 <td>182</td>
10665 <td>66</td>
10666 <td>AM6_DEV_GIC0</td>
10667 <td>spi</td>
10668 <td>450</td>
10669 </tr>
10670 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10671 <td>182</td>
10672 <td>67</td>
10673 <td>AM6_DEV_GIC0</td>
10674 <td>spi</td>
10675 <td>451</td>
10676 </tr>
10677 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10678 <td>182</td>
10679 <td>68</td>
10680 <td>AM6_DEV_GIC0</td>
10681 <td>spi</td>
10682 <td>452</td>
10683 </tr>
10684 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10685 <td>182</td>
10686 <td>69</td>
10687 <td>AM6_DEV_GIC0</td>
10688 <td>spi</td>
10689 <td>453</td>
10690 </tr>
10691 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10692 <td>182</td>
10693 <td>70</td>
10694 <td>AM6_DEV_GIC0</td>
10695 <td>spi</td>
10696 <td>454</td>
10697 </tr>
10698 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10699 <td>182</td>
10700 <td>71</td>
10701 <td>AM6_DEV_GIC0</td>
10702 <td>spi</td>
10703 <td>455</td>
10704 </tr>
10705 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10706 <td>182</td>
10707 <td>72</td>
10708 <td>AM6_DEV_GIC0</td>
10709 <td>spi</td>
10710 <td>456</td>
10711 </tr>
10712 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10713 <td>182</td>
10714 <td>73</td>
10715 <td>AM6_DEV_GIC0</td>
10716 <td>spi</td>
10717 <td>457</td>
10718 </tr>
10719 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10720 <td>182</td>
10721 <td>74</td>
10722 <td>AM6_DEV_GIC0</td>
10723 <td>spi</td>
10724 <td>458</td>
10725 </tr>
10726 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10727 <td>182</td>
10728 <td>75</td>
10729 <td>AM6_DEV_GIC0</td>
10730 <td>spi</td>
10731 <td>459</td>
10732 </tr>
10733 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10734 <td>182</td>
10735 <td>76</td>
10736 <td>AM6_DEV_GIC0</td>
10737 <td>spi</td>
10738 <td>460</td>
10739 </tr>
10740 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10741 <td>182</td>
10742 <td>77</td>
10743 <td>AM6_DEV_GIC0</td>
10744 <td>spi</td>
10745 <td>461</td>
10746 </tr>
10747 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10748 <td>182</td>
10749 <td>78</td>
10750 <td>AM6_DEV_GIC0</td>
10751 <td>spi</td>
10752 <td>462</td>
10753 </tr>
10754 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10755 <td>182</td>
10756 <td>79</td>
10757 <td>AM6_DEV_GIC0</td>
10758 <td>spi</td>
10759 <td>463</td>
10760 </tr>
10761 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10762 <td>182</td>
10763 <td>80</td>
10764 <td>AM6_DEV_GIC0</td>
10765 <td>spi</td>
10766 <td>464</td>
10767 </tr>
10768 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10769 <td>182</td>
10770 <td>81</td>
10771 <td>AM6_DEV_GIC0</td>
10772 <td>spi</td>
10773 <td>465</td>
10774 </tr>
10775 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10776 <td>182</td>
10777 <td>82</td>
10778 <td>AM6_DEV_GIC0</td>
10779 <td>spi</td>
10780 <td>466</td>
10781 </tr>
10782 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10783 <td>182</td>
10784 <td>83</td>
10785 <td>AM6_DEV_GIC0</td>
10786 <td>spi</td>
10787 <td>467</td>
10788 </tr>
10789 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10790 <td>182</td>
10791 <td>84</td>
10792 <td>AM6_DEV_GIC0</td>
10793 <td>spi</td>
10794 <td>468</td>
10795 </tr>
10796 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10797 <td>182</td>
10798 <td>85</td>
10799 <td>AM6_DEV_GIC0</td>
10800 <td>spi</td>
10801 <td>469</td>
10802 </tr>
10803 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10804 <td>182</td>
10805 <td>86</td>
10806 <td>AM6_DEV_GIC0</td>
10807 <td>spi</td>
10808 <td>470</td>
10809 </tr>
10810 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10811 <td>182</td>
10812 <td>87</td>
10813 <td>AM6_DEV_GIC0</td>
10814 <td>spi</td>
10815 <td>471</td>
10816 </tr>
10817 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10818 <td>182</td>
10819 <td>88</td>
10820 <td>AM6_DEV_GIC0</td>
10821 <td>spi</td>
10822 <td>472</td>
10823 </tr>
10824 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10825 <td>182</td>
10826 <td>89</td>
10827 <td>AM6_DEV_GIC0</td>
10828 <td>spi</td>
10829 <td>473</td>
10830 </tr>
10831 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10832 <td>182</td>
10833 <td>90</td>
10834 <td>AM6_DEV_GIC0</td>
10835 <td>spi</td>
10836 <td>474</td>
10837 </tr>
10838 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10839 <td>182</td>
10840 <td>91</td>
10841 <td>AM6_DEV_GIC0</td>
10842 <td>spi</td>
10843 <td>475</td>
10844 </tr>
10845 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10846 <td>182</td>
10847 <td>92</td>
10848 <td>AM6_DEV_GIC0</td>
10849 <td>spi</td>
10850 <td>476</td>
10851 </tr>
10852 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10853 <td>182</td>
10854 <td>93</td>
10855 <td>AM6_DEV_GIC0</td>
10856 <td>spi</td>
10857 <td>477</td>
10858 </tr>
10859 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10860 <td>182</td>
10861 <td>94</td>
10862 <td>AM6_DEV_GIC0</td>
10863 <td>spi</td>
10864 <td>478</td>
10865 </tr>
10866 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10867 <td>182</td>
10868 <td>95</td>
10869 <td>AM6_DEV_GIC0</td>
10870 <td>spi</td>
10871 <td>479</td>
10872 </tr>
10873 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10874 <td>182</td>
10875 <td>96</td>
10876 <td>AM6_DEV_GIC0</td>
10877 <td>spi</td>
10878 <td>480</td>
10879 </tr>
10880 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10881 <td>182</td>
10882 <td>97</td>
10883 <td>AM6_DEV_GIC0</td>
10884 <td>spi</td>
10885 <td>481</td>
10886 </tr>
10887 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10888 <td>182</td>
10889 <td>98</td>
10890 <td>AM6_DEV_GIC0</td>
10891 <td>spi</td>
10892 <td>482</td>
10893 </tr>
10894 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10895 <td>182</td>
10896 <td>99</td>
10897 <td>AM6_DEV_GIC0</td>
10898 <td>spi</td>
10899 <td>483</td>
10900 </tr>
10901 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10902 <td>182</td>
10903 <td>100</td>
10904 <td>AM6_DEV_GIC0</td>
10905 <td>spi</td>
10906 <td>484</td>
10907 </tr>
10908 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10909 <td>182</td>
10910 <td>101</td>
10911 <td>AM6_DEV_GIC0</td>
10912 <td>spi</td>
10913 <td>485</td>
10914 </tr>
10915 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10916 <td>182</td>
10917 <td>102</td>
10918 <td>AM6_DEV_GIC0</td>
10919 <td>spi</td>
10920 <td>486</td>
10921 </tr>
10922 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10923 <td>182</td>
10924 <td>103</td>
10925 <td>AM6_DEV_GIC0</td>
10926 <td>spi</td>
10927 <td>487</td>
10928 </tr>
10929 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10930 <td>182</td>
10931 <td>104</td>
10932 <td>AM6_DEV_GIC0</td>
10933 <td>spi</td>
10934 <td>488</td>
10935 </tr>
10936 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10937 <td>182</td>
10938 <td>105</td>
10939 <td>AM6_DEV_GIC0</td>
10940 <td>spi</td>
10941 <td>489</td>
10942 </tr>
10943 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10944 <td>182</td>
10945 <td>106</td>
10946 <td>AM6_DEV_GIC0</td>
10947 <td>spi</td>
10948 <td>490</td>
10949 </tr>
10950 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10951 <td>182</td>
10952 <td>107</td>
10953 <td>AM6_DEV_GIC0</td>
10954 <td>spi</td>
10955 <td>491</td>
10956 </tr>
10957 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10958 <td>182</td>
10959 <td>108</td>
10960 <td>AM6_DEV_GIC0</td>
10961 <td>spi</td>
10962 <td>492</td>
10963 </tr>
10964 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10965 <td>182</td>
10966 <td>109</td>
10967 <td>AM6_DEV_GIC0</td>
10968 <td>spi</td>
10969 <td>493</td>
10970 </tr>
10971 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10972 <td>182</td>
10973 <td>110</td>
10974 <td>AM6_DEV_GIC0</td>
10975 <td>spi</td>
10976 <td>494</td>
10977 </tr>
10978 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10979 <td>182</td>
10980 <td>111</td>
10981 <td>AM6_DEV_GIC0</td>
10982 <td>spi</td>
10983 <td>495</td>
10984 </tr>
10985 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10986 <td>182</td>
10987 <td>112</td>
10988 <td>AM6_DEV_GIC0</td>
10989 <td>spi</td>
10990 <td>496</td>
10991 </tr>
10992 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
10993 <td>182</td>
10994 <td>113</td>
10995 <td>AM6_DEV_GIC0</td>
10996 <td>spi</td>
10997 <td>497</td>
10998 </tr>
10999 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11000 <td>182</td>
11001 <td>114</td>
11002 <td>AM6_DEV_GIC0</td>
11003 <td>spi</td>
11004 <td>498</td>
11005 </tr>
11006 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11007 <td>182</td>
11008 <td>115</td>
11009 <td>AM6_DEV_GIC0</td>
11010 <td>spi</td>
11011 <td>499</td>
11012 </tr>
11013 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11014 <td>182</td>
11015 <td>116</td>
11016 <td>AM6_DEV_GIC0</td>
11017 <td>spi</td>
11018 <td>500</td>
11019 </tr>
11020 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11021 <td>182</td>
11022 <td>117</td>
11023 <td>AM6_DEV_GIC0</td>
11024 <td>spi</td>
11025 <td>501</td>
11026 </tr>
11027 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11028 <td>182</td>
11029 <td>118</td>
11030 <td>AM6_DEV_GIC0</td>
11031 <td>spi</td>
11032 <td>502</td>
11033 </tr>
11034 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11035 <td>182</td>
11036 <td>119</td>
11037 <td>AM6_DEV_GIC0</td>
11038 <td>spi</td>
11039 <td>503</td>
11040 </tr>
11041 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11042 <td>182</td>
11043 <td>120</td>
11044 <td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
11045 <td>in</td>
11046 <td>184</td>
11047 </tr>
11048 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11049 <td>182</td>
11050 <td>121</td>
11051 <td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
11052 <td>in</td>
11053 <td>185</td>
11054 </tr>
11055 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11056 <td>182</td>
11057 <td>122</td>
11058 <td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
11059 <td>in</td>
11060 <td>186</td>
11061 </tr>
11062 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11063 <td>182</td>
11064 <td>123</td>
11065 <td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
11066 <td>in</td>
11067 <td>187</td>
11068 </tr>
11069 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11070 <td>182</td>
11071 <td>124</td>
11072 <td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
11073 <td>in</td>
11074 <td>188</td>
11075 </tr>
11076 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11077 <td>182</td>
11078 <td>125</td>
11079 <td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
11080 <td>in</td>
11081 <td>189</td>
11082 </tr>
11083 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11084 <td>182</td>
11085 <td>126</td>
11086 <td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
11087 <td>in</td>
11088 <td>190</td>
11089 </tr>
11090 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11091 <td>182</td>
11092 <td>127</td>
11093 <td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
11094 <td>in</td>
11095 <td>191</td>
11096 </tr>
11097 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11098 <td>182</td>
11099 <td>128</td>
11100 <td>AM6_DEV_PRU_ICSSG0</td>
11101 <td>pr1_slv_intr</td>
11102 <td>46</td>
11103 </tr>
11104 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11105 <td>182</td>
11106 <td>129</td>
11107 <td>AM6_DEV_PRU_ICSSG0</td>
11108 <td>pr1_slv_intr</td>
11109 <td>47</td>
11110 </tr>
11111 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11112 <td>182</td>
11113 <td>130</td>
11114 <td>AM6_DEV_PRU_ICSSG0</td>
11115 <td>pr1_slv_intr</td>
11116 <td>48</td>
11117 </tr>
11118 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11119 <td>182</td>
11120 <td>131</td>
11121 <td>AM6_DEV_PRU_ICSSG0</td>
11122 <td>pr1_slv_intr</td>
11123 <td>49</td>
11124 </tr>
11125 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11126 <td>182</td>
11127 <td>132</td>
11128 <td>AM6_DEV_PRU_ICSSG0</td>
11129 <td>pr1_slv_intr</td>
11130 <td>50</td>
11131 </tr>
11132 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11133 <td>182</td>
11134 <td>133</td>
11135 <td>AM6_DEV_PRU_ICSSG0</td>
11136 <td>pr1_slv_intr</td>
11137 <td>51</td>
11138 </tr>
11139 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11140 <td>182</td>
11141 <td>134</td>
11142 <td>AM6_DEV_PRU_ICSSG0</td>
11143 <td>pr1_slv_intr</td>
11144 <td>52</td>
11145 </tr>
11146 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11147 <td>182</td>
11148 <td>135</td>
11149 <td>AM6_DEV_PRU_ICSSG0</td>
11150 <td>pr1_slv_intr</td>
11151 <td>53</td>
11152 </tr>
11153 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11154 <td>182</td>
11155 <td>136</td>
11156 <td>AM6_DEV_PRU_ICSSG1</td>
11157 <td>pr1_slv_intr</td>
11158 <td>46</td>
11159 </tr>
11160 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11161 <td>182</td>
11162 <td>137</td>
11163 <td>AM6_DEV_PRU_ICSSG1</td>
11164 <td>pr1_slv_intr</td>
11165 <td>47</td>
11166 </tr>
11167 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11168 <td>182</td>
11169 <td>138</td>
11170 <td>AM6_DEV_PRU_ICSSG1</td>
11171 <td>pr1_slv_intr</td>
11172 <td>48</td>
11173 </tr>
11174 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11175 <td>182</td>
11176 <td>139</td>
11177 <td>AM6_DEV_PRU_ICSSG1</td>
11178 <td>pr1_slv_intr</td>
11179 <td>49</td>
11180 </tr>
11181 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11182 <td>182</td>
11183 <td>140</td>
11184 <td>AM6_DEV_PRU_ICSSG1</td>
11185 <td>pr1_slv_intr</td>
11186 <td>50</td>
11187 </tr>
11188 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11189 <td>182</td>
11190 <td>141</td>
11191 <td>AM6_DEV_PRU_ICSSG1</td>
11192 <td>pr1_slv_intr</td>
11193 <td>51</td>
11194 </tr>
11195 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11196 <td>182</td>
11197 <td>142</td>
11198 <td>AM6_DEV_PRU_ICSSG1</td>
11199 <td>pr1_slv_intr</td>
11200 <td>52</td>
11201 </tr>
11202 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11203 <td>182</td>
11204 <td>143</td>
11205 <td>AM6_DEV_PRU_ICSSG1</td>
11206 <td>pr1_slv_intr</td>
11207 <td>53</td>
11208 </tr>
11209 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11210 <td>182</td>
11211 <td>144</td>
11212 <td>AM6_DEV_PRU_ICSSG2</td>
11213 <td>pr1_slv_intr</td>
11214 <td>46</td>
11215 </tr>
11216 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11217 <td>182</td>
11218 <td>145</td>
11219 <td>AM6_DEV_PRU_ICSSG2</td>
11220 <td>pr1_slv_intr</td>
11221 <td>47</td>
11222 </tr>
11223 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11224 <td>182</td>
11225 <td>146</td>
11226 <td>AM6_DEV_PRU_ICSSG2</td>
11227 <td>pr1_slv_intr</td>
11228 <td>48</td>
11229 </tr>
11230 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11231 <td>182</td>
11232 <td>147</td>
11233 <td>AM6_DEV_PRU_ICSSG2</td>
11234 <td>pr1_slv_intr</td>
11235 <td>49</td>
11236 </tr>
11237 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11238 <td>182</td>
11239 <td>148</td>
11240 <td>AM6_DEV_PRU_ICSSG2</td>
11241 <td>pr1_slv_intr</td>
11242 <td>50</td>
11243 </tr>
11244 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11245 <td>182</td>
11246 <td>149</td>
11247 <td>AM6_DEV_PRU_ICSSG2</td>
11248 <td>pr1_slv_intr</td>
11249 <td>51</td>
11250 </tr>
11251 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11252 <td>182</td>
11253 <td>150</td>
11254 <td>AM6_DEV_PRU_ICSSG2</td>
11255 <td>pr1_slv_intr</td>
11256 <td>52</td>
11257 </tr>
11258 <tr class="row-odd"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
11259 <td>182</td>
11260 <td>151</td>
11261 <td>AM6_DEV_PRU_ICSSG2</td>
11262 <td>pr1_slv_intr</td>
11263 <td>53</td>
11264 </tr>
11265 </tbody>
11266 </table>
11267 </div>
11268 <div class="section" id="mcu-navss0-intr-router-0-interrupt-router-input-sources">
11269 <span id="pub-soc-am65x-sr2-mcu-navss0-intr-router-0-input-src-list"></span><h2>mcu_navss0_intr_router_0 Interrupt Router Input Sources<a class="headerlink" href="#mcu-navss0-intr-router-0-interrupt-router-input-sources" title="Permalink to this headline">¶</a></h2>
11270 <div class="admonition warning">
11271 <p class="first admonition-title">Warning</p>
11272 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
11273 host within the RM Board Configuration resource assignment array.  The RM
11274 Board Configuration is rejected if an overlap with a reserved resource is
11275 detected.</p>
11276 </div>
11277 <table border="1" class="docutils">
11278 <colgroup>
11279 <col width="26%" />
11280 <col width="12%" />
11281 <col width="13%" />
11282 <col width="23%" />
11283 <col width="15%" />
11284 <col width="12%" />
11285 </colgroup>
11286 <thead valign="bottom">
11287 <tr class="row-odd"><th class="head">IR Name</th>
11288 <th class="head">IR Device ID</th>
11289 <th class="head">IR Input Index</th>
11290 <th class="head">Source Name</th>
11291 <th class="head">Source Interface</th>
11292 <th class="head">Source Index</th>
11293 </tr>
11294 </thead>
11295 <tbody valign="top">
11296 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
11297 (<strong>Reserved by System Firmware</strong>)</td>
11298 <td>190</td>
11299 <td>0</td>
11300 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11301 <td>intaggr_vintr_pend</td>
11302 <td>0</td>
11303 </tr>
11304 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
11305 (<strong>Reserved by System Firmware</strong>)</td>
11306 <td>190</td>
11307 <td>1</td>
11308 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11309 <td>intaggr_vintr_pend</td>
11310 <td>1</td>
11311 </tr>
11312 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
11313 (<strong>Reserved by System Firmware</strong>)</td>
11314 <td>190</td>
11315 <td>2</td>
11316 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11317 <td>intaggr_vintr_pend</td>
11318 <td>2</td>
11319 </tr>
11320 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
11321 (<strong>Reserved by System Firmware</strong>)</td>
11322 <td>190</td>
11323 <td>3</td>
11324 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11325 <td>intaggr_vintr_pend</td>
11326 <td>3</td>
11327 </tr>
11328 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
11329 (<strong>Reserved by System Firmware</strong>)</td>
11330 <td>190</td>
11331 <td>4</td>
11332 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11333 <td>intaggr_vintr_pend</td>
11334 <td>4</td>
11335 </tr>
11336 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
11337 (<strong>Reserved by System Firmware</strong>)</td>
11338 <td>190</td>
11339 <td>5</td>
11340 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11341 <td>intaggr_vintr_pend</td>
11342 <td>5</td>
11343 </tr>
11344 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
11345 (<strong>Reserved by System Firmware</strong>)</td>
11346 <td>190</td>
11347 <td>6</td>
11348 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11349 <td>intaggr_vintr_pend</td>
11350 <td>6</td>
11351 </tr>
11352 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
11353 (<strong>Reserved by System Firmware</strong>)</td>
11354 <td>190</td>
11355 <td>7</td>
11356 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11357 <td>intaggr_vintr_pend</td>
11358 <td>7</td>
11359 </tr>
11360 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11361 <td>190</td>
11362 <td>8</td>
11363 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11364 <td>intaggr_vintr_pend</td>
11365 <td>8</td>
11366 </tr>
11367 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11368 <td>190</td>
11369 <td>9</td>
11370 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11371 <td>intaggr_vintr_pend</td>
11372 <td>9</td>
11373 </tr>
11374 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11375 <td>190</td>
11376 <td>10</td>
11377 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11378 <td>intaggr_vintr_pend</td>
11379 <td>10</td>
11380 </tr>
11381 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11382 <td>190</td>
11383 <td>11</td>
11384 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11385 <td>intaggr_vintr_pend</td>
11386 <td>11</td>
11387 </tr>
11388 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11389 <td>190</td>
11390 <td>12</td>
11391 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11392 <td>intaggr_vintr_pend</td>
11393 <td>12</td>
11394 </tr>
11395 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11396 <td>190</td>
11397 <td>13</td>
11398 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11399 <td>intaggr_vintr_pend</td>
11400 <td>13</td>
11401 </tr>
11402 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11403 <td>190</td>
11404 <td>14</td>
11405 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11406 <td>intaggr_vintr_pend</td>
11407 <td>14</td>
11408 </tr>
11409 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11410 <td>190</td>
11411 <td>15</td>
11412 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11413 <td>intaggr_vintr_pend</td>
11414 <td>15</td>
11415 </tr>
11416 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11417 <td>190</td>
11418 <td>16</td>
11419 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11420 <td>intaggr_vintr_pend</td>
11421 <td>16</td>
11422 </tr>
11423 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11424 <td>190</td>
11425 <td>17</td>
11426 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11427 <td>intaggr_vintr_pend</td>
11428 <td>17</td>
11429 </tr>
11430 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11431 <td>190</td>
11432 <td>18</td>
11433 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11434 <td>intaggr_vintr_pend</td>
11435 <td>18</td>
11436 </tr>
11437 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11438 <td>190</td>
11439 <td>19</td>
11440 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11441 <td>intaggr_vintr_pend</td>
11442 <td>19</td>
11443 </tr>
11444 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11445 <td>190</td>
11446 <td>20</td>
11447 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11448 <td>intaggr_vintr_pend</td>
11449 <td>20</td>
11450 </tr>
11451 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11452 <td>190</td>
11453 <td>21</td>
11454 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11455 <td>intaggr_vintr_pend</td>
11456 <td>21</td>
11457 </tr>
11458 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11459 <td>190</td>
11460 <td>22</td>
11461 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11462 <td>intaggr_vintr_pend</td>
11463 <td>22</td>
11464 </tr>
11465 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11466 <td>190</td>
11467 <td>23</td>
11468 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11469 <td>intaggr_vintr_pend</td>
11470 <td>23</td>
11471 </tr>
11472 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11473 <td>190</td>
11474 <td>24</td>
11475 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11476 <td>intaggr_vintr_pend</td>
11477 <td>24</td>
11478 </tr>
11479 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11480 <td>190</td>
11481 <td>25</td>
11482 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11483 <td>intaggr_vintr_pend</td>
11484 <td>25</td>
11485 </tr>
11486 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11487 <td>190</td>
11488 <td>26</td>
11489 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11490 <td>intaggr_vintr_pend</td>
11491 <td>26</td>
11492 </tr>
11493 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11494 <td>190</td>
11495 <td>27</td>
11496 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11497 <td>intaggr_vintr_pend</td>
11498 <td>27</td>
11499 </tr>
11500 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11501 <td>190</td>
11502 <td>28</td>
11503 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11504 <td>intaggr_vintr_pend</td>
11505 <td>28</td>
11506 </tr>
11507 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11508 <td>190</td>
11509 <td>29</td>
11510 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11511 <td>intaggr_vintr_pend</td>
11512 <td>29</td>
11513 </tr>
11514 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11515 <td>190</td>
11516 <td>30</td>
11517 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11518 <td>intaggr_vintr_pend</td>
11519 <td>30</td>
11520 </tr>
11521 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11522 <td>190</td>
11523 <td>31</td>
11524 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11525 <td>intaggr_vintr_pend</td>
11526 <td>31</td>
11527 </tr>
11528 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11529 <td>190</td>
11530 <td>32</td>
11531 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11532 <td>intaggr_vintr_pend</td>
11533 <td>32</td>
11534 </tr>
11535 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11536 <td>190</td>
11537 <td>33</td>
11538 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11539 <td>intaggr_vintr_pend</td>
11540 <td>33</td>
11541 </tr>
11542 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11543 <td>190</td>
11544 <td>34</td>
11545 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11546 <td>intaggr_vintr_pend</td>
11547 <td>34</td>
11548 </tr>
11549 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11550 <td>190</td>
11551 <td>35</td>
11552 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11553 <td>intaggr_vintr_pend</td>
11554 <td>35</td>
11555 </tr>
11556 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11557 <td>190</td>
11558 <td>36</td>
11559 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11560 <td>intaggr_vintr_pend</td>
11561 <td>36</td>
11562 </tr>
11563 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11564 <td>190</td>
11565 <td>37</td>
11566 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11567 <td>intaggr_vintr_pend</td>
11568 <td>37</td>
11569 </tr>
11570 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11571 <td>190</td>
11572 <td>38</td>
11573 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11574 <td>intaggr_vintr_pend</td>
11575 <td>38</td>
11576 </tr>
11577 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11578 <td>190</td>
11579 <td>39</td>
11580 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11581 <td>intaggr_vintr_pend</td>
11582 <td>39</td>
11583 </tr>
11584 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11585 <td>190</td>
11586 <td>40</td>
11587 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11588 <td>intaggr_vintr_pend</td>
11589 <td>40</td>
11590 </tr>
11591 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11592 <td>190</td>
11593 <td>41</td>
11594 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11595 <td>intaggr_vintr_pend</td>
11596 <td>41</td>
11597 </tr>
11598 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11599 <td>190</td>
11600 <td>42</td>
11601 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11602 <td>intaggr_vintr_pend</td>
11603 <td>42</td>
11604 </tr>
11605 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11606 <td>190</td>
11607 <td>43</td>
11608 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11609 <td>intaggr_vintr_pend</td>
11610 <td>43</td>
11611 </tr>
11612 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11613 <td>190</td>
11614 <td>44</td>
11615 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11616 <td>intaggr_vintr_pend</td>
11617 <td>44</td>
11618 </tr>
11619 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11620 <td>190</td>
11621 <td>45</td>
11622 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11623 <td>intaggr_vintr_pend</td>
11624 <td>45</td>
11625 </tr>
11626 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11627 <td>190</td>
11628 <td>46</td>
11629 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11630 <td>intaggr_vintr_pend</td>
11631 <td>46</td>
11632 </tr>
11633 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11634 <td>190</td>
11635 <td>47</td>
11636 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11637 <td>intaggr_vintr_pend</td>
11638 <td>47</td>
11639 </tr>
11640 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11641 <td>190</td>
11642 <td>48</td>
11643 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11644 <td>intaggr_vintr_pend</td>
11645 <td>48</td>
11646 </tr>
11647 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11648 <td>190</td>
11649 <td>49</td>
11650 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11651 <td>intaggr_vintr_pend</td>
11652 <td>49</td>
11653 </tr>
11654 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11655 <td>190</td>
11656 <td>50</td>
11657 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11658 <td>intaggr_vintr_pend</td>
11659 <td>50</td>
11660 </tr>
11661 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11662 <td>190</td>
11663 <td>51</td>
11664 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11665 <td>intaggr_vintr_pend</td>
11666 <td>51</td>
11667 </tr>
11668 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11669 <td>190</td>
11670 <td>52</td>
11671 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11672 <td>intaggr_vintr_pend</td>
11673 <td>52</td>
11674 </tr>
11675 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11676 <td>190</td>
11677 <td>53</td>
11678 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11679 <td>intaggr_vintr_pend</td>
11680 <td>53</td>
11681 </tr>
11682 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11683 <td>190</td>
11684 <td>54</td>
11685 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11686 <td>intaggr_vintr_pend</td>
11687 <td>54</td>
11688 </tr>
11689 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11690 <td>190</td>
11691 <td>55</td>
11692 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11693 <td>intaggr_vintr_pend</td>
11694 <td>55</td>
11695 </tr>
11696 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11697 <td>190</td>
11698 <td>56</td>
11699 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11700 <td>intaggr_vintr_pend</td>
11701 <td>56</td>
11702 </tr>
11703 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11704 <td>190</td>
11705 <td>57</td>
11706 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11707 <td>intaggr_vintr_pend</td>
11708 <td>57</td>
11709 </tr>
11710 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11711 <td>190</td>
11712 <td>58</td>
11713 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11714 <td>intaggr_vintr_pend</td>
11715 <td>58</td>
11716 </tr>
11717 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11718 <td>190</td>
11719 <td>59</td>
11720 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11721 <td>intaggr_vintr_pend</td>
11722 <td>59</td>
11723 </tr>
11724 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11725 <td>190</td>
11726 <td>60</td>
11727 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11728 <td>intaggr_vintr_pend</td>
11729 <td>60</td>
11730 </tr>
11731 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11732 <td>190</td>
11733 <td>61</td>
11734 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11735 <td>intaggr_vintr_pend</td>
11736 <td>61</td>
11737 </tr>
11738 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11739 <td>190</td>
11740 <td>62</td>
11741 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11742 <td>intaggr_vintr_pend</td>
11743 <td>62</td>
11744 </tr>
11745 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11746 <td>190</td>
11747 <td>63</td>
11748 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11749 <td>intaggr_vintr_pend</td>
11750 <td>63</td>
11751 </tr>
11752 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11753 <td>190</td>
11754 <td>64</td>
11755 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11756 <td>intaggr_vintr_pend</td>
11757 <td>64</td>
11758 </tr>
11759 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11760 <td>190</td>
11761 <td>65</td>
11762 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11763 <td>intaggr_vintr_pend</td>
11764 <td>65</td>
11765 </tr>
11766 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11767 <td>190</td>
11768 <td>66</td>
11769 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11770 <td>intaggr_vintr_pend</td>
11771 <td>66</td>
11772 </tr>
11773 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11774 <td>190</td>
11775 <td>67</td>
11776 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11777 <td>intaggr_vintr_pend</td>
11778 <td>67</td>
11779 </tr>
11780 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11781 <td>190</td>
11782 <td>68</td>
11783 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11784 <td>intaggr_vintr_pend</td>
11785 <td>68</td>
11786 </tr>
11787 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11788 <td>190</td>
11789 <td>69</td>
11790 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11791 <td>intaggr_vintr_pend</td>
11792 <td>69</td>
11793 </tr>
11794 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11795 <td>190</td>
11796 <td>70</td>
11797 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11798 <td>intaggr_vintr_pend</td>
11799 <td>70</td>
11800 </tr>
11801 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11802 <td>190</td>
11803 <td>71</td>
11804 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11805 <td>intaggr_vintr_pend</td>
11806 <td>71</td>
11807 </tr>
11808 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11809 <td>190</td>
11810 <td>72</td>
11811 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11812 <td>intaggr_vintr_pend</td>
11813 <td>72</td>
11814 </tr>
11815 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11816 <td>190</td>
11817 <td>73</td>
11818 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11819 <td>intaggr_vintr_pend</td>
11820 <td>73</td>
11821 </tr>
11822 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11823 <td>190</td>
11824 <td>74</td>
11825 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11826 <td>intaggr_vintr_pend</td>
11827 <td>74</td>
11828 </tr>
11829 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11830 <td>190</td>
11831 <td>75</td>
11832 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11833 <td>intaggr_vintr_pend</td>
11834 <td>75</td>
11835 </tr>
11836 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11837 <td>190</td>
11838 <td>76</td>
11839 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11840 <td>intaggr_vintr_pend</td>
11841 <td>76</td>
11842 </tr>
11843 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11844 <td>190</td>
11845 <td>77</td>
11846 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11847 <td>intaggr_vintr_pend</td>
11848 <td>77</td>
11849 </tr>
11850 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11851 <td>190</td>
11852 <td>78</td>
11853 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11854 <td>intaggr_vintr_pend</td>
11855 <td>78</td>
11856 </tr>
11857 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11858 <td>190</td>
11859 <td>79</td>
11860 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11861 <td>intaggr_vintr_pend</td>
11862 <td>79</td>
11863 </tr>
11864 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11865 <td>190</td>
11866 <td>80</td>
11867 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11868 <td>intaggr_vintr_pend</td>
11869 <td>80</td>
11870 </tr>
11871 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11872 <td>190</td>
11873 <td>81</td>
11874 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11875 <td>intaggr_vintr_pend</td>
11876 <td>81</td>
11877 </tr>
11878 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11879 <td>190</td>
11880 <td>82</td>
11881 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11882 <td>intaggr_vintr_pend</td>
11883 <td>82</td>
11884 </tr>
11885 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11886 <td>190</td>
11887 <td>83</td>
11888 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11889 <td>intaggr_vintr_pend</td>
11890 <td>83</td>
11891 </tr>
11892 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11893 <td>190</td>
11894 <td>84</td>
11895 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11896 <td>intaggr_vintr_pend</td>
11897 <td>84</td>
11898 </tr>
11899 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11900 <td>190</td>
11901 <td>85</td>
11902 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11903 <td>intaggr_vintr_pend</td>
11904 <td>85</td>
11905 </tr>
11906 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11907 <td>190</td>
11908 <td>86</td>
11909 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11910 <td>intaggr_vintr_pend</td>
11911 <td>86</td>
11912 </tr>
11913 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11914 <td>190</td>
11915 <td>87</td>
11916 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11917 <td>intaggr_vintr_pend</td>
11918 <td>87</td>
11919 </tr>
11920 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11921 <td>190</td>
11922 <td>88</td>
11923 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11924 <td>intaggr_vintr_pend</td>
11925 <td>88</td>
11926 </tr>
11927 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11928 <td>190</td>
11929 <td>89</td>
11930 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11931 <td>intaggr_vintr_pend</td>
11932 <td>89</td>
11933 </tr>
11934 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11935 <td>190</td>
11936 <td>90</td>
11937 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11938 <td>intaggr_vintr_pend</td>
11939 <td>90</td>
11940 </tr>
11941 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11942 <td>190</td>
11943 <td>91</td>
11944 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11945 <td>intaggr_vintr_pend</td>
11946 <td>91</td>
11947 </tr>
11948 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11949 <td>190</td>
11950 <td>92</td>
11951 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11952 <td>intaggr_vintr_pend</td>
11953 <td>92</td>
11954 </tr>
11955 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11956 <td>190</td>
11957 <td>93</td>
11958 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11959 <td>intaggr_vintr_pend</td>
11960 <td>93</td>
11961 </tr>
11962 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11963 <td>190</td>
11964 <td>94</td>
11965 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11966 <td>intaggr_vintr_pend</td>
11967 <td>94</td>
11968 </tr>
11969 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11970 <td>190</td>
11971 <td>95</td>
11972 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11973 <td>intaggr_vintr_pend</td>
11974 <td>95</td>
11975 </tr>
11976 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11977 <td>190</td>
11978 <td>96</td>
11979 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11980 <td>intaggr_vintr_pend</td>
11981 <td>96</td>
11982 </tr>
11983 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11984 <td>190</td>
11985 <td>97</td>
11986 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11987 <td>intaggr_vintr_pend</td>
11988 <td>97</td>
11989 </tr>
11990 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11991 <td>190</td>
11992 <td>98</td>
11993 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
11994 <td>intaggr_vintr_pend</td>
11995 <td>98</td>
11996 </tr>
11997 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
11998 <td>190</td>
11999 <td>99</td>
12000 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12001 <td>intaggr_vintr_pend</td>
12002 <td>99</td>
12003 </tr>
12004 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12005 <td>190</td>
12006 <td>100</td>
12007 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12008 <td>intaggr_vintr_pend</td>
12009 <td>100</td>
12010 </tr>
12011 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12012 <td>190</td>
12013 <td>101</td>
12014 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12015 <td>intaggr_vintr_pend</td>
12016 <td>101</td>
12017 </tr>
12018 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12019 <td>190</td>
12020 <td>102</td>
12021 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12022 <td>intaggr_vintr_pend</td>
12023 <td>102</td>
12024 </tr>
12025 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12026 <td>190</td>
12027 <td>103</td>
12028 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12029 <td>intaggr_vintr_pend</td>
12030 <td>103</td>
12031 </tr>
12032 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12033 <td>190</td>
12034 <td>104</td>
12035 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12036 <td>intaggr_vintr_pend</td>
12037 <td>104</td>
12038 </tr>
12039 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12040 <td>190</td>
12041 <td>105</td>
12042 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12043 <td>intaggr_vintr_pend</td>
12044 <td>105</td>
12045 </tr>
12046 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12047 <td>190</td>
12048 <td>106</td>
12049 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12050 <td>intaggr_vintr_pend</td>
12051 <td>106</td>
12052 </tr>
12053 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12054 <td>190</td>
12055 <td>107</td>
12056 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12057 <td>intaggr_vintr_pend</td>
12058 <td>107</td>
12059 </tr>
12060 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12061 <td>190</td>
12062 <td>108</td>
12063 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12064 <td>intaggr_vintr_pend</td>
12065 <td>108</td>
12066 </tr>
12067 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12068 <td>190</td>
12069 <td>109</td>
12070 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12071 <td>intaggr_vintr_pend</td>
12072 <td>109</td>
12073 </tr>
12074 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12075 <td>190</td>
12076 <td>110</td>
12077 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12078 <td>intaggr_vintr_pend</td>
12079 <td>110</td>
12080 </tr>
12081 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12082 <td>190</td>
12083 <td>111</td>
12084 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12085 <td>intaggr_vintr_pend</td>
12086 <td>111</td>
12087 </tr>
12088 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12089 <td>190</td>
12090 <td>112</td>
12091 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12092 <td>intaggr_vintr_pend</td>
12093 <td>112</td>
12094 </tr>
12095 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12096 <td>190</td>
12097 <td>113</td>
12098 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12099 <td>intaggr_vintr_pend</td>
12100 <td>113</td>
12101 </tr>
12102 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12103 <td>190</td>
12104 <td>114</td>
12105 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12106 <td>intaggr_vintr_pend</td>
12107 <td>114</td>
12108 </tr>
12109 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12110 <td>190</td>
12111 <td>115</td>
12112 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12113 <td>intaggr_vintr_pend</td>
12114 <td>115</td>
12115 </tr>
12116 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12117 <td>190</td>
12118 <td>116</td>
12119 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12120 <td>intaggr_vintr_pend</td>
12121 <td>116</td>
12122 </tr>
12123 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12124 <td>190</td>
12125 <td>117</td>
12126 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12127 <td>intaggr_vintr_pend</td>
12128 <td>117</td>
12129 </tr>
12130 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12131 <td>190</td>
12132 <td>118</td>
12133 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12134 <td>intaggr_vintr_pend</td>
12135 <td>118</td>
12136 </tr>
12137 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12138 <td>190</td>
12139 <td>119</td>
12140 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12141 <td>intaggr_vintr_pend</td>
12142 <td>119</td>
12143 </tr>
12144 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12145 <td>190</td>
12146 <td>120</td>
12147 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12148 <td>intaggr_vintr_pend</td>
12149 <td>120</td>
12150 </tr>
12151 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12152 <td>190</td>
12153 <td>121</td>
12154 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12155 <td>intaggr_vintr_pend</td>
12156 <td>121</td>
12157 </tr>
12158 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12159 <td>190</td>
12160 <td>122</td>
12161 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12162 <td>intaggr_vintr_pend</td>
12163 <td>122</td>
12164 </tr>
12165 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12166 <td>190</td>
12167 <td>123</td>
12168 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12169 <td>intaggr_vintr_pend</td>
12170 <td>123</td>
12171 </tr>
12172 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12173 <td>190</td>
12174 <td>124</td>
12175 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12176 <td>intaggr_vintr_pend</td>
12177 <td>124</td>
12178 </tr>
12179 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12180 <td>190</td>
12181 <td>125</td>
12182 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12183 <td>intaggr_vintr_pend</td>
12184 <td>125</td>
12185 </tr>
12186 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12187 <td>190</td>
12188 <td>126</td>
12189 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12190 <td>intaggr_vintr_pend</td>
12191 <td>126</td>
12192 </tr>
12193 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12194 <td>190</td>
12195 <td>127</td>
12196 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12197 <td>intaggr_vintr_pend</td>
12198 <td>127</td>
12199 </tr>
12200 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12201 <td>190</td>
12202 <td>128</td>
12203 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12204 <td>intaggr_vintr_pend</td>
12205 <td>128</td>
12206 </tr>
12207 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12208 <td>190</td>
12209 <td>129</td>
12210 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12211 <td>intaggr_vintr_pend</td>
12212 <td>129</td>
12213 </tr>
12214 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12215 <td>190</td>
12216 <td>130</td>
12217 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12218 <td>intaggr_vintr_pend</td>
12219 <td>130</td>
12220 </tr>
12221 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12222 <td>190</td>
12223 <td>131</td>
12224 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12225 <td>intaggr_vintr_pend</td>
12226 <td>131</td>
12227 </tr>
12228 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12229 <td>190</td>
12230 <td>132</td>
12231 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12232 <td>intaggr_vintr_pend</td>
12233 <td>132</td>
12234 </tr>
12235 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12236 <td>190</td>
12237 <td>133</td>
12238 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12239 <td>intaggr_vintr_pend</td>
12240 <td>133</td>
12241 </tr>
12242 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12243 <td>190</td>
12244 <td>134</td>
12245 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12246 <td>intaggr_vintr_pend</td>
12247 <td>134</td>
12248 </tr>
12249 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12250 <td>190</td>
12251 <td>135</td>
12252 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12253 <td>intaggr_vintr_pend</td>
12254 <td>135</td>
12255 </tr>
12256 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12257 <td>190</td>
12258 <td>136</td>
12259 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12260 <td>intaggr_vintr_pend</td>
12261 <td>136</td>
12262 </tr>
12263 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12264 <td>190</td>
12265 <td>137</td>
12266 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12267 <td>intaggr_vintr_pend</td>
12268 <td>137</td>
12269 </tr>
12270 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12271 <td>190</td>
12272 <td>138</td>
12273 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12274 <td>intaggr_vintr_pend</td>
12275 <td>138</td>
12276 </tr>
12277 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12278 <td>190</td>
12279 <td>139</td>
12280 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12281 <td>intaggr_vintr_pend</td>
12282 <td>139</td>
12283 </tr>
12284 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12285 <td>190</td>
12286 <td>140</td>
12287 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12288 <td>intaggr_vintr_pend</td>
12289 <td>140</td>
12290 </tr>
12291 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12292 <td>190</td>
12293 <td>141</td>
12294 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12295 <td>intaggr_vintr_pend</td>
12296 <td>141</td>
12297 </tr>
12298 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12299 <td>190</td>
12300 <td>142</td>
12301 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12302 <td>intaggr_vintr_pend</td>
12303 <td>142</td>
12304 </tr>
12305 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12306 <td>190</td>
12307 <td>143</td>
12308 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12309 <td>intaggr_vintr_pend</td>
12310 <td>143</td>
12311 </tr>
12312 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12313 <td>190</td>
12314 <td>144</td>
12315 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12316 <td>intaggr_vintr_pend</td>
12317 <td>144</td>
12318 </tr>
12319 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12320 <td>190</td>
12321 <td>145</td>
12322 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12323 <td>intaggr_vintr_pend</td>
12324 <td>145</td>
12325 </tr>
12326 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12327 <td>190</td>
12328 <td>146</td>
12329 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12330 <td>intaggr_vintr_pend</td>
12331 <td>146</td>
12332 </tr>
12333 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12334 <td>190</td>
12335 <td>147</td>
12336 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12337 <td>intaggr_vintr_pend</td>
12338 <td>147</td>
12339 </tr>
12340 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12341 <td>190</td>
12342 <td>148</td>
12343 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12344 <td>intaggr_vintr_pend</td>
12345 <td>148</td>
12346 </tr>
12347 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12348 <td>190</td>
12349 <td>149</td>
12350 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12351 <td>intaggr_vintr_pend</td>
12352 <td>149</td>
12353 </tr>
12354 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12355 <td>190</td>
12356 <td>150</td>
12357 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12358 <td>intaggr_vintr_pend</td>
12359 <td>150</td>
12360 </tr>
12361 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12362 <td>190</td>
12363 <td>151</td>
12364 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12365 <td>intaggr_vintr_pend</td>
12366 <td>151</td>
12367 </tr>
12368 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12369 <td>190</td>
12370 <td>152</td>
12371 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12372 <td>intaggr_vintr_pend</td>
12373 <td>152</td>
12374 </tr>
12375 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12376 <td>190</td>
12377 <td>153</td>
12378 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12379 <td>intaggr_vintr_pend</td>
12380 <td>153</td>
12381 </tr>
12382 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12383 <td>190</td>
12384 <td>154</td>
12385 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12386 <td>intaggr_vintr_pend</td>
12387 <td>154</td>
12388 </tr>
12389 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12390 <td>190</td>
12391 <td>155</td>
12392 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12393 <td>intaggr_vintr_pend</td>
12394 <td>155</td>
12395 </tr>
12396 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12397 <td>190</td>
12398 <td>156</td>
12399 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12400 <td>intaggr_vintr_pend</td>
12401 <td>156</td>
12402 </tr>
12403 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12404 <td>190</td>
12405 <td>157</td>
12406 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12407 <td>intaggr_vintr_pend</td>
12408 <td>157</td>
12409 </tr>
12410 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12411 <td>190</td>
12412 <td>158</td>
12413 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12414 <td>intaggr_vintr_pend</td>
12415 <td>158</td>
12416 </tr>
12417 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12418 <td>190</td>
12419 <td>159</td>
12420 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12421 <td>intaggr_vintr_pend</td>
12422 <td>159</td>
12423 </tr>
12424 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12425 <td>190</td>
12426 <td>160</td>
12427 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12428 <td>intaggr_vintr_pend</td>
12429 <td>160</td>
12430 </tr>
12431 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12432 <td>190</td>
12433 <td>161</td>
12434 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12435 <td>intaggr_vintr_pend</td>
12436 <td>161</td>
12437 </tr>
12438 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12439 <td>190</td>
12440 <td>162</td>
12441 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12442 <td>intaggr_vintr_pend</td>
12443 <td>162</td>
12444 </tr>
12445 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12446 <td>190</td>
12447 <td>163</td>
12448 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12449 <td>intaggr_vintr_pend</td>
12450 <td>163</td>
12451 </tr>
12452 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12453 <td>190</td>
12454 <td>164</td>
12455 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12456 <td>intaggr_vintr_pend</td>
12457 <td>164</td>
12458 </tr>
12459 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12460 <td>190</td>
12461 <td>165</td>
12462 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12463 <td>intaggr_vintr_pend</td>
12464 <td>165</td>
12465 </tr>
12466 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12467 <td>190</td>
12468 <td>166</td>
12469 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12470 <td>intaggr_vintr_pend</td>
12471 <td>166</td>
12472 </tr>
12473 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12474 <td>190</td>
12475 <td>167</td>
12476 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12477 <td>intaggr_vintr_pend</td>
12478 <td>167</td>
12479 </tr>
12480 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12481 <td>190</td>
12482 <td>168</td>
12483 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12484 <td>intaggr_vintr_pend</td>
12485 <td>168</td>
12486 </tr>
12487 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12488 <td>190</td>
12489 <td>169</td>
12490 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12491 <td>intaggr_vintr_pend</td>
12492 <td>169</td>
12493 </tr>
12494 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12495 <td>190</td>
12496 <td>170</td>
12497 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12498 <td>intaggr_vintr_pend</td>
12499 <td>170</td>
12500 </tr>
12501 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12502 <td>190</td>
12503 <td>171</td>
12504 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12505 <td>intaggr_vintr_pend</td>
12506 <td>171</td>
12507 </tr>
12508 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12509 <td>190</td>
12510 <td>172</td>
12511 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12512 <td>intaggr_vintr_pend</td>
12513 <td>172</td>
12514 </tr>
12515 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12516 <td>190</td>
12517 <td>173</td>
12518 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12519 <td>intaggr_vintr_pend</td>
12520 <td>173</td>
12521 </tr>
12522 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12523 <td>190</td>
12524 <td>174</td>
12525 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12526 <td>intaggr_vintr_pend</td>
12527 <td>174</td>
12528 </tr>
12529 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12530 <td>190</td>
12531 <td>175</td>
12532 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12533 <td>intaggr_vintr_pend</td>
12534 <td>175</td>
12535 </tr>
12536 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12537 <td>190</td>
12538 <td>176</td>
12539 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12540 <td>intaggr_vintr_pend</td>
12541 <td>176</td>
12542 </tr>
12543 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12544 <td>190</td>
12545 <td>177</td>
12546 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12547 <td>intaggr_vintr_pend</td>
12548 <td>177</td>
12549 </tr>
12550 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12551 <td>190</td>
12552 <td>178</td>
12553 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12554 <td>intaggr_vintr_pend</td>
12555 <td>178</td>
12556 </tr>
12557 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12558 <td>190</td>
12559 <td>179</td>
12560 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12561 <td>intaggr_vintr_pend</td>
12562 <td>179</td>
12563 </tr>
12564 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12565 <td>190</td>
12566 <td>180</td>
12567 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12568 <td>intaggr_vintr_pend</td>
12569 <td>180</td>
12570 </tr>
12571 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12572 <td>190</td>
12573 <td>181</td>
12574 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12575 <td>intaggr_vintr_pend</td>
12576 <td>181</td>
12577 </tr>
12578 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12579 <td>190</td>
12580 <td>182</td>
12581 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12582 <td>intaggr_vintr_pend</td>
12583 <td>182</td>
12584 </tr>
12585 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12586 <td>190</td>
12587 <td>183</td>
12588 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12589 <td>intaggr_vintr_pend</td>
12590 <td>183</td>
12591 </tr>
12592 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12593 <td>190</td>
12594 <td>184</td>
12595 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12596 <td>intaggr_vintr_pend</td>
12597 <td>184</td>
12598 </tr>
12599 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12600 <td>190</td>
12601 <td>185</td>
12602 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12603 <td>intaggr_vintr_pend</td>
12604 <td>185</td>
12605 </tr>
12606 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12607 <td>190</td>
12608 <td>186</td>
12609 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12610 <td>intaggr_vintr_pend</td>
12611 <td>186</td>
12612 </tr>
12613 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12614 <td>190</td>
12615 <td>187</td>
12616 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12617 <td>intaggr_vintr_pend</td>
12618 <td>187</td>
12619 </tr>
12620 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12621 <td>190</td>
12622 <td>188</td>
12623 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12624 <td>intaggr_vintr_pend</td>
12625 <td>188</td>
12626 </tr>
12627 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12628 <td>190</td>
12629 <td>189</td>
12630 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12631 <td>intaggr_vintr_pend</td>
12632 <td>189</td>
12633 </tr>
12634 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12635 <td>190</td>
12636 <td>190</td>
12637 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12638 <td>intaggr_vintr_pend</td>
12639 <td>190</td>
12640 </tr>
12641 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12642 <td>190</td>
12643 <td>191</td>
12644 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12645 <td>intaggr_vintr_pend</td>
12646 <td>191</td>
12647 </tr>
12648 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12649 <td>190</td>
12650 <td>192</td>
12651 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12652 <td>intaggr_vintr_pend</td>
12653 <td>192</td>
12654 </tr>
12655 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12656 <td>190</td>
12657 <td>193</td>
12658 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12659 <td>intaggr_vintr_pend</td>
12660 <td>193</td>
12661 </tr>
12662 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12663 <td>190</td>
12664 <td>194</td>
12665 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12666 <td>intaggr_vintr_pend</td>
12667 <td>194</td>
12668 </tr>
12669 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12670 <td>190</td>
12671 <td>195</td>
12672 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12673 <td>intaggr_vintr_pend</td>
12674 <td>195</td>
12675 </tr>
12676 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12677 <td>190</td>
12678 <td>196</td>
12679 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12680 <td>intaggr_vintr_pend</td>
12681 <td>196</td>
12682 </tr>
12683 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12684 <td>190</td>
12685 <td>197</td>
12686 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12687 <td>intaggr_vintr_pend</td>
12688 <td>197</td>
12689 </tr>
12690 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12691 <td>190</td>
12692 <td>198</td>
12693 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12694 <td>intaggr_vintr_pend</td>
12695 <td>198</td>
12696 </tr>
12697 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12698 <td>190</td>
12699 <td>199</td>
12700 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12701 <td>intaggr_vintr_pend</td>
12702 <td>199</td>
12703 </tr>
12704 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12705 <td>190</td>
12706 <td>200</td>
12707 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12708 <td>intaggr_vintr_pend</td>
12709 <td>200</td>
12710 </tr>
12711 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12712 <td>190</td>
12713 <td>201</td>
12714 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12715 <td>intaggr_vintr_pend</td>
12716 <td>201</td>
12717 </tr>
12718 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12719 <td>190</td>
12720 <td>202</td>
12721 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12722 <td>intaggr_vintr_pend</td>
12723 <td>202</td>
12724 </tr>
12725 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12726 <td>190</td>
12727 <td>203</td>
12728 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12729 <td>intaggr_vintr_pend</td>
12730 <td>203</td>
12731 </tr>
12732 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12733 <td>190</td>
12734 <td>204</td>
12735 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12736 <td>intaggr_vintr_pend</td>
12737 <td>204</td>
12738 </tr>
12739 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12740 <td>190</td>
12741 <td>205</td>
12742 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12743 <td>intaggr_vintr_pend</td>
12744 <td>205</td>
12745 </tr>
12746 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12747 <td>190</td>
12748 <td>206</td>
12749 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12750 <td>intaggr_vintr_pend</td>
12751 <td>206</td>
12752 </tr>
12753 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12754 <td>190</td>
12755 <td>207</td>
12756 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12757 <td>intaggr_vintr_pend</td>
12758 <td>207</td>
12759 </tr>
12760 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12761 <td>190</td>
12762 <td>208</td>
12763 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12764 <td>intaggr_vintr_pend</td>
12765 <td>208</td>
12766 </tr>
12767 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12768 <td>190</td>
12769 <td>209</td>
12770 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12771 <td>intaggr_vintr_pend</td>
12772 <td>209</td>
12773 </tr>
12774 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12775 <td>190</td>
12776 <td>210</td>
12777 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12778 <td>intaggr_vintr_pend</td>
12779 <td>210</td>
12780 </tr>
12781 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12782 <td>190</td>
12783 <td>211</td>
12784 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12785 <td>intaggr_vintr_pend</td>
12786 <td>211</td>
12787 </tr>
12788 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12789 <td>190</td>
12790 <td>212</td>
12791 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12792 <td>intaggr_vintr_pend</td>
12793 <td>212</td>
12794 </tr>
12795 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12796 <td>190</td>
12797 <td>213</td>
12798 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12799 <td>intaggr_vintr_pend</td>
12800 <td>213</td>
12801 </tr>
12802 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12803 <td>190</td>
12804 <td>214</td>
12805 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12806 <td>intaggr_vintr_pend</td>
12807 <td>214</td>
12808 </tr>
12809 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12810 <td>190</td>
12811 <td>215</td>
12812 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12813 <td>intaggr_vintr_pend</td>
12814 <td>215</td>
12815 </tr>
12816 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12817 <td>190</td>
12818 <td>216</td>
12819 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12820 <td>intaggr_vintr_pend</td>
12821 <td>216</td>
12822 </tr>
12823 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12824 <td>190</td>
12825 <td>217</td>
12826 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12827 <td>intaggr_vintr_pend</td>
12828 <td>217</td>
12829 </tr>
12830 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12831 <td>190</td>
12832 <td>218</td>
12833 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12834 <td>intaggr_vintr_pend</td>
12835 <td>218</td>
12836 </tr>
12837 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12838 <td>190</td>
12839 <td>219</td>
12840 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12841 <td>intaggr_vintr_pend</td>
12842 <td>219</td>
12843 </tr>
12844 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12845 <td>190</td>
12846 <td>220</td>
12847 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12848 <td>intaggr_vintr_pend</td>
12849 <td>220</td>
12850 </tr>
12851 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12852 <td>190</td>
12853 <td>221</td>
12854 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12855 <td>intaggr_vintr_pend</td>
12856 <td>221</td>
12857 </tr>
12858 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12859 <td>190</td>
12860 <td>222</td>
12861 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12862 <td>intaggr_vintr_pend</td>
12863 <td>222</td>
12864 </tr>
12865 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12866 <td>190</td>
12867 <td>223</td>
12868 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12869 <td>intaggr_vintr_pend</td>
12870 <td>223</td>
12871 </tr>
12872 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12873 <td>190</td>
12874 <td>224</td>
12875 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12876 <td>intaggr_vintr_pend</td>
12877 <td>224</td>
12878 </tr>
12879 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12880 <td>190</td>
12881 <td>225</td>
12882 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12883 <td>intaggr_vintr_pend</td>
12884 <td>225</td>
12885 </tr>
12886 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12887 <td>190</td>
12888 <td>226</td>
12889 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12890 <td>intaggr_vintr_pend</td>
12891 <td>226</td>
12892 </tr>
12893 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12894 <td>190</td>
12895 <td>227</td>
12896 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12897 <td>intaggr_vintr_pend</td>
12898 <td>227</td>
12899 </tr>
12900 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12901 <td>190</td>
12902 <td>228</td>
12903 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12904 <td>intaggr_vintr_pend</td>
12905 <td>228</td>
12906 </tr>
12907 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12908 <td>190</td>
12909 <td>229</td>
12910 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12911 <td>intaggr_vintr_pend</td>
12912 <td>229</td>
12913 </tr>
12914 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12915 <td>190</td>
12916 <td>230</td>
12917 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12918 <td>intaggr_vintr_pend</td>
12919 <td>230</td>
12920 </tr>
12921 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12922 <td>190</td>
12923 <td>231</td>
12924 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12925 <td>intaggr_vintr_pend</td>
12926 <td>231</td>
12927 </tr>
12928 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12929 <td>190</td>
12930 <td>232</td>
12931 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12932 <td>intaggr_vintr_pend</td>
12933 <td>232</td>
12934 </tr>
12935 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12936 <td>190</td>
12937 <td>233</td>
12938 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12939 <td>intaggr_vintr_pend</td>
12940 <td>233</td>
12941 </tr>
12942 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12943 <td>190</td>
12944 <td>234</td>
12945 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12946 <td>intaggr_vintr_pend</td>
12947 <td>234</td>
12948 </tr>
12949 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12950 <td>190</td>
12951 <td>235</td>
12952 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12953 <td>intaggr_vintr_pend</td>
12954 <td>235</td>
12955 </tr>
12956 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12957 <td>190</td>
12958 <td>236</td>
12959 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12960 <td>intaggr_vintr_pend</td>
12961 <td>236</td>
12962 </tr>
12963 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12964 <td>190</td>
12965 <td>237</td>
12966 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12967 <td>intaggr_vintr_pend</td>
12968 <td>237</td>
12969 </tr>
12970 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12971 <td>190</td>
12972 <td>238</td>
12973 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12974 <td>intaggr_vintr_pend</td>
12975 <td>238</td>
12976 </tr>
12977 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12978 <td>190</td>
12979 <td>239</td>
12980 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12981 <td>intaggr_vintr_pend</td>
12982 <td>239</td>
12983 </tr>
12984 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12985 <td>190</td>
12986 <td>240</td>
12987 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12988 <td>intaggr_vintr_pend</td>
12989 <td>240</td>
12990 </tr>
12991 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12992 <td>190</td>
12993 <td>241</td>
12994 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
12995 <td>intaggr_vintr_pend</td>
12996 <td>241</td>
12997 </tr>
12998 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
12999 <td>190</td>
13000 <td>242</td>
13001 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13002 <td>intaggr_vintr_pend</td>
13003 <td>242</td>
13004 </tr>
13005 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13006 <td>190</td>
13007 <td>243</td>
13008 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13009 <td>intaggr_vintr_pend</td>
13010 <td>243</td>
13011 </tr>
13012 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13013 <td>190</td>
13014 <td>244</td>
13015 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13016 <td>intaggr_vintr_pend</td>
13017 <td>244</td>
13018 </tr>
13019 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13020 <td>190</td>
13021 <td>245</td>
13022 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13023 <td>intaggr_vintr_pend</td>
13024 <td>245</td>
13025 </tr>
13026 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13027 <td>190</td>
13028 <td>246</td>
13029 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13030 <td>intaggr_vintr_pend</td>
13031 <td>246</td>
13032 </tr>
13033 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13034 <td>190</td>
13035 <td>247</td>
13036 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13037 <td>intaggr_vintr_pend</td>
13038 <td>247</td>
13039 </tr>
13040 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13041 <td>190</td>
13042 <td>248</td>
13043 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13044 <td>intaggr_vintr_pend</td>
13045 <td>248</td>
13046 </tr>
13047 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13048 <td>190</td>
13049 <td>249</td>
13050 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13051 <td>intaggr_vintr_pend</td>
13052 <td>249</td>
13053 </tr>
13054 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13055 <td>190</td>
13056 <td>250</td>
13057 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13058 <td>intaggr_vintr_pend</td>
13059 <td>250</td>
13060 </tr>
13061 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13062 <td>190</td>
13063 <td>251</td>
13064 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13065 <td>intaggr_vintr_pend</td>
13066 <td>251</td>
13067 </tr>
13068 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13069 <td>190</td>
13070 <td>252</td>
13071 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13072 <td>intaggr_vintr_pend</td>
13073 <td>252</td>
13074 </tr>
13075 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13076 <td>190</td>
13077 <td>253</td>
13078 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13079 <td>intaggr_vintr_pend</td>
13080 <td>253</td>
13081 </tr>
13082 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13083 <td>190</td>
13084 <td>254</td>
13085 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13086 <td>intaggr_vintr_pend</td>
13087 <td>254</td>
13088 </tr>
13089 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13090 <td>190</td>
13091 <td>255</td>
13092 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
13093 <td>intaggr_vintr_pend</td>
13094 <td>255</td>
13095 </tr>
13096 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13097 <td>190</td>
13098 <td>256</td>
13099 <td>AM6_DEV_MCU_NAVSS0_MCRC0</td>
13100 <td>dma_event_intr</td>
13101 <td>0</td>
13102 </tr>
13103 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13104 <td>190</td>
13105 <td>257</td>
13106 <td>AM6_DEV_MCU_NAVSS0_MCRC0</td>
13107 <td>dma_event_intr</td>
13108 <td>1</td>
13109 </tr>
13110 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13111 <td>190</td>
13112 <td>258</td>
13113 <td>AM6_DEV_MCU_NAVSS0_MCRC0</td>
13114 <td>dma_event_intr</td>
13115 <td>2</td>
13116 </tr>
13117 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13118 <td>190</td>
13119 <td>259</td>
13120 <td>AM6_DEV_MCU_NAVSS0_MCRC0</td>
13121 <td>dma_event_intr</td>
13122 <td>3</td>
13123 </tr>
13124 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13125 <td>190</td>
13126 <td>260</td>
13127 <td>AM6_DEV_MCU_NAVSS0_MCRC0</td>
13128 <td>intaggr_vintr_pend</td>
13129 <td>0</td>
13130 </tr>
13131 </tbody>
13132 </table>
13133 </div>
13134 <div class="section" id="mcu-navss0-intr-router-0-interrupt-router-output-destinations">
13135 <span id="pub-soc-am65x-sr2-mcu-navss0-intr-router-0-output-src-list"></span><h2>mcu_navss0_intr_router_0 Interrupt Router Output Destinations<a class="headerlink" href="#mcu-navss0-intr-router-0-interrupt-router-output-destinations" title="Permalink to this headline">¶</a></h2>
13136 <div class="admonition warning">
13137 <p class="first admonition-title">Warning</p>
13138 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
13139 host within the RM Board Configuration resource assignment array.  The RM
13140 Board Configuration is rejected if an overlap with a reserved resource is
13141 detected.</p>
13142 </div>
13143 <table border="1" class="docutils">
13144 <colgroup>
13145 <col width="25%" />
13146 <col width="11%" />
13147 <col width="13%" />
13148 <col width="18%" />
13149 <col width="18%" />
13150 <col width="15%" />
13151 </colgroup>
13152 <thead valign="bottom">
13153 <tr class="row-odd"><th class="head">IR Name</th>
13154 <th class="head">IR Device ID</th>
13155 <th class="head">IR Output Index</th>
13156 <th class="head">Destination Name</th>
13157 <th class="head">Destination Interface</th>
13158 <th class="head">Destination Index</th>
13159 </tr>
13160 </thead>
13161 <tbody valign="top">
13162 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
13163 (<strong>Reserved by System Firmware</strong>)</td>
13164 <td>190</td>
13165 <td>0</td>
13166 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13167 <td>intr</td>
13168 <td>64</td>
13169 </tr>
13170 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
13171 (<strong>Reserved by System Firmware</strong>)</td>
13172 <td>190</td>
13173 <td>1</td>
13174 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13175 <td>intr</td>
13176 <td>65</td>
13177 </tr>
13178 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
13179 (<strong>Reserved by System Firmware</strong>)</td>
13180 <td>190</td>
13181 <td>2</td>
13182 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13183 <td>intr</td>
13184 <td>66</td>
13185 </tr>
13186 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
13187 (<strong>Reserved by System Firmware</strong>)</td>
13188 <td>190</td>
13189 <td>3</td>
13190 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13191 <td>intr</td>
13192 <td>67</td>
13193 </tr>
13194 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13195 <td>190</td>
13196 <td>4</td>
13197 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13198 <td>intr</td>
13199 <td>68</td>
13200 </tr>
13201 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13202 <td>190</td>
13203 <td>5</td>
13204 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13205 <td>intr</td>
13206 <td>69</td>
13207 </tr>
13208 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13209 <td>190</td>
13210 <td>6</td>
13211 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13212 <td>intr</td>
13213 <td>70</td>
13214 </tr>
13215 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13216 <td>190</td>
13217 <td>7</td>
13218 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13219 <td>intr</td>
13220 <td>71</td>
13221 </tr>
13222 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13223 <td>190</td>
13224 <td>8</td>
13225 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13226 <td>intr</td>
13227 <td>72</td>
13228 </tr>
13229 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13230 <td>190</td>
13231 <td>9</td>
13232 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13233 <td>intr</td>
13234 <td>73</td>
13235 </tr>
13236 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13237 <td>190</td>
13238 <td>10</td>
13239 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13240 <td>intr</td>
13241 <td>74</td>
13242 </tr>
13243 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13244 <td>190</td>
13245 <td>11</td>
13246 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13247 <td>intr</td>
13248 <td>75</td>
13249 </tr>
13250 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13251 <td>190</td>
13252 <td>12</td>
13253 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13254 <td>intr</td>
13255 <td>76</td>
13256 </tr>
13257 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13258 <td>190</td>
13259 <td>13</td>
13260 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13261 <td>intr</td>
13262 <td>77</td>
13263 </tr>
13264 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13265 <td>190</td>
13266 <td>14</td>
13267 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13268 <td>intr</td>
13269 <td>78</td>
13270 </tr>
13271 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13272 <td>190</td>
13273 <td>15</td>
13274 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13275 <td>intr</td>
13276 <td>79</td>
13277 </tr>
13278 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13279 <td>190</td>
13280 <td>16</td>
13281 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13282 <td>intr</td>
13283 <td>80</td>
13284 </tr>
13285 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13286 <td>190</td>
13287 <td>17</td>
13288 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13289 <td>intr</td>
13290 <td>81</td>
13291 </tr>
13292 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13293 <td>190</td>
13294 <td>18</td>
13295 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13296 <td>intr</td>
13297 <td>82</td>
13298 </tr>
13299 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13300 <td>190</td>
13301 <td>19</td>
13302 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13303 <td>intr</td>
13304 <td>83</td>
13305 </tr>
13306 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13307 <td>190</td>
13308 <td>20</td>
13309 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13310 <td>intr</td>
13311 <td>84</td>
13312 </tr>
13313 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13314 <td>190</td>
13315 <td>21</td>
13316 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13317 <td>intr</td>
13318 <td>85</td>
13319 </tr>
13320 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13321 <td>190</td>
13322 <td>22</td>
13323 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13324 <td>intr</td>
13325 <td>86</td>
13326 </tr>
13327 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13328 <td>190</td>
13329 <td>23</td>
13330 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13331 <td>intr</td>
13332 <td>87</td>
13333 </tr>
13334 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13335 <td>190</td>
13336 <td>24</td>
13337 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13338 <td>intr</td>
13339 <td>88</td>
13340 </tr>
13341 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13342 <td>190</td>
13343 <td>25</td>
13344 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13345 <td>intr</td>
13346 <td>89</td>
13347 </tr>
13348 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13349 <td>190</td>
13350 <td>26</td>
13351 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13352 <td>intr</td>
13353 <td>90</td>
13354 </tr>
13355 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13356 <td>190</td>
13357 <td>27</td>
13358 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13359 <td>intr</td>
13360 <td>91</td>
13361 </tr>
13362 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13363 <td>190</td>
13364 <td>28</td>
13365 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13366 <td>intr</td>
13367 <td>92</td>
13368 </tr>
13369 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13370 <td>190</td>
13371 <td>29</td>
13372 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13373 <td>intr</td>
13374 <td>93</td>
13375 </tr>
13376 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13377 <td>190</td>
13378 <td>30</td>
13379 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13380 <td>intr</td>
13381 <td>94</td>
13382 </tr>
13383 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13384 <td>190</td>
13385 <td>31</td>
13386 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
13387 <td>intr</td>
13388 <td>95</td>
13389 </tr>
13390 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
13391 (<strong>Reserved by System Firmware</strong>)</td>
13392 <td>190</td>
13393 <td>32</td>
13394 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13395 <td>intr</td>
13396 <td>64</td>
13397 </tr>
13398 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
13399 (<strong>Reserved by System Firmware</strong>)</td>
13400 <td>190</td>
13401 <td>33</td>
13402 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13403 <td>intr</td>
13404 <td>65</td>
13405 </tr>
13406 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
13407 (<strong>Reserved by System Firmware</strong>)</td>
13408 <td>190</td>
13409 <td>34</td>
13410 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13411 <td>intr</td>
13412 <td>66</td>
13413 </tr>
13414 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0
13415 (<strong>Reserved by System Firmware</strong>)</td>
13416 <td>190</td>
13417 <td>35</td>
13418 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13419 <td>intr</td>
13420 <td>67</td>
13421 </tr>
13422 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13423 <td>190</td>
13424 <td>36</td>
13425 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13426 <td>intr</td>
13427 <td>68</td>
13428 </tr>
13429 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13430 <td>190</td>
13431 <td>37</td>
13432 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13433 <td>intr</td>
13434 <td>69</td>
13435 </tr>
13436 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13437 <td>190</td>
13438 <td>38</td>
13439 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13440 <td>intr</td>
13441 <td>70</td>
13442 </tr>
13443 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13444 <td>190</td>
13445 <td>39</td>
13446 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13447 <td>intr</td>
13448 <td>71</td>
13449 </tr>
13450 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13451 <td>190</td>
13452 <td>40</td>
13453 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13454 <td>intr</td>
13455 <td>72</td>
13456 </tr>
13457 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13458 <td>190</td>
13459 <td>41</td>
13460 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13461 <td>intr</td>
13462 <td>73</td>
13463 </tr>
13464 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13465 <td>190</td>
13466 <td>42</td>
13467 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13468 <td>intr</td>
13469 <td>74</td>
13470 </tr>
13471 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13472 <td>190</td>
13473 <td>43</td>
13474 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13475 <td>intr</td>
13476 <td>75</td>
13477 </tr>
13478 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13479 <td>190</td>
13480 <td>44</td>
13481 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13482 <td>intr</td>
13483 <td>76</td>
13484 </tr>
13485 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13486 <td>190</td>
13487 <td>45</td>
13488 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13489 <td>intr</td>
13490 <td>77</td>
13491 </tr>
13492 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13493 <td>190</td>
13494 <td>46</td>
13495 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13496 <td>intr</td>
13497 <td>78</td>
13498 </tr>
13499 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13500 <td>190</td>
13501 <td>47</td>
13502 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13503 <td>intr</td>
13504 <td>79</td>
13505 </tr>
13506 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13507 <td>190</td>
13508 <td>48</td>
13509 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13510 <td>intr</td>
13511 <td>80</td>
13512 </tr>
13513 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13514 <td>190</td>
13515 <td>49</td>
13516 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13517 <td>intr</td>
13518 <td>81</td>
13519 </tr>
13520 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13521 <td>190</td>
13522 <td>50</td>
13523 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13524 <td>intr</td>
13525 <td>82</td>
13526 </tr>
13527 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13528 <td>190</td>
13529 <td>51</td>
13530 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13531 <td>intr</td>
13532 <td>83</td>
13533 </tr>
13534 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13535 <td>190</td>
13536 <td>52</td>
13537 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13538 <td>intr</td>
13539 <td>84</td>
13540 </tr>
13541 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13542 <td>190</td>
13543 <td>53</td>
13544 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13545 <td>intr</td>
13546 <td>85</td>
13547 </tr>
13548 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13549 <td>190</td>
13550 <td>54</td>
13551 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13552 <td>intr</td>
13553 <td>86</td>
13554 </tr>
13555 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13556 <td>190</td>
13557 <td>55</td>
13558 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13559 <td>intr</td>
13560 <td>87</td>
13561 </tr>
13562 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13563 <td>190</td>
13564 <td>56</td>
13565 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13566 <td>intr</td>
13567 <td>88</td>
13568 </tr>
13569 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13570 <td>190</td>
13571 <td>57</td>
13572 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13573 <td>intr</td>
13574 <td>89</td>
13575 </tr>
13576 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13577 <td>190</td>
13578 <td>58</td>
13579 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13580 <td>intr</td>
13581 <td>90</td>
13582 </tr>
13583 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13584 <td>190</td>
13585 <td>59</td>
13586 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13587 <td>intr</td>
13588 <td>91</td>
13589 </tr>
13590 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13591 <td>190</td>
13592 <td>60</td>
13593 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13594 <td>intr</td>
13595 <td>92</td>
13596 </tr>
13597 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13598 <td>190</td>
13599 <td>61</td>
13600 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13601 <td>intr</td>
13602 <td>93</td>
13603 </tr>
13604 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13605 <td>190</td>
13606 <td>62</td>
13607 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13608 <td>intr</td>
13609 <td>94</td>
13610 </tr>
13611 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
13612 <td>190</td>
13613 <td>63</td>
13614 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
13615 <td>intr</td>
13616 <td>95</td>
13617 </tr>
13618 </tbody>
13619 </table>
13620 </div>
13621 <div class="section" id="timesync-intrtr0-interrupt-router-input-sources">
13622 <span id="pub-soc-am65x-sr2-timesync-intrtr0-input-src-list"></span><h2>TIMESYNC_INTRTR0 Interrupt Router Input Sources<a class="headerlink" href="#timesync-intrtr0-interrupt-router-input-sources" title="Permalink to this headline">¶</a></h2>
13623 <div class="admonition warning">
13624 <p class="first admonition-title">Warning</p>
13625 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
13626 host within the RM Board Configuration resource assignment array.  The RM
13627 Board Configuration is rejected if an overlap with a reserved resource is
13628 detected.</p>
13629 </div>
13630 <table border="1" class="docutils">
13631 <colgroup>
13632 <col width="22%" />
13633 <col width="14%" />
13634 <col width="16%" />
13635 <col width="17%" />
13636 <col width="17%" />
13637 <col width="14%" />
13638 </colgroup>
13639 <thead valign="bottom">
13640 <tr class="row-odd"><th class="head">IR Name</th>
13641 <th class="head">IR Device ID</th>
13642 <th class="head">IR Input Index</th>
13643 <th class="head">Source Name</th>
13644 <th class="head">Source Interface</th>
13645 <th class="head">Source Index</th>
13646 </tr>
13647 </thead>
13648 <tbody valign="top">
13649 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13650 <td>145</td>
13651 <td>0</td>
13652 <td>Not Connected</td>
13653 <td>&#160;</td>
13654 <td>&#160;</td>
13655 </tr>
13656 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13657 <td>145</td>
13658 <td>1</td>
13659 <td>AM6_DEV_GTC0</td>
13660 <td>gtc_push_event</td>
13661 <td>0</td>
13662 </tr>
13663 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13664 <td>145</td>
13665 <td>2</td>
13666 <td>Not Connected</td>
13667 <td>&#160;</td>
13668 <td>&#160;</td>
13669 </tr>
13670 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13671 <td>145</td>
13672 <td>3</td>
13673 <td>Not Connected</td>
13674 <td>&#160;</td>
13675 <td>&#160;</td>
13676 </tr>
13677 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13678 <td>145</td>
13679 <td>4</td>
13680 <td>AM6_DEV_NAVSS0</td>
13681 <td>cpts0_genf0</td>
13682 <td>0</td>
13683 </tr>
13684 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13685 <td>145</td>
13686 <td>5</td>
13687 <td>AM6_DEV_NAVSS0</td>
13688 <td>cpts0_genf1</td>
13689 <td>0</td>
13690 </tr>
13691 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13692 <td>145</td>
13693 <td>6</td>
13694 <td>AM6_DEV_NAVSS0</td>
13695 <td>cpts0_genf2</td>
13696 <td>0</td>
13697 </tr>
13698 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13699 <td>145</td>
13700 <td>7</td>
13701 <td>AM6_DEV_NAVSS0</td>
13702 <td>cpts0_genf3</td>
13703 <td>0</td>
13704 </tr>
13705 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13706 <td>145</td>
13707 <td>8</td>
13708 <td>AM6_DEV_NAVSS0</td>
13709 <td>cpts0_genf4</td>
13710 <td>0</td>
13711 </tr>
13712 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13713 <td>145</td>
13714 <td>9</td>
13715 <td>AM6_DEV_NAVSS0</td>
13716 <td>cpts0_genf5</td>
13717 <td>0</td>
13718 </tr>
13719 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13720 <td>145</td>
13721 <td>10</td>
13722 <td>AM6_DEV_PCIE0</td>
13723 <td>pcie_cpts_genf0</td>
13724 <td>0</td>
13725 </tr>
13726 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13727 <td>145</td>
13728 <td>11</td>
13729 <td>AM6_DEV_PCIE1</td>
13730 <td>pcie_cpts_genf0</td>
13731 <td>0</td>
13732 </tr>
13733 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13734 <td>145</td>
13735 <td>12</td>
13736 <td>AM6_DEV_MCU_CPSW0</td>
13737 <td>cpts_genf0</td>
13738 <td>0</td>
13739 </tr>
13740 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13741 <td>145</td>
13742 <td>13</td>
13743 <td>AM6_DEV_MCU_CPSW0</td>
13744 <td>cpts_genf1</td>
13745 <td>0</td>
13746 </tr>
13747 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13748 <td>145</td>
13749 <td>14</td>
13750 <td>AM6_DEV_PCIE0</td>
13751 <td>pcie_cpts_hw1_push</td>
13752 <td>0</td>
13753 </tr>
13754 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13755 <td>145</td>
13756 <td>15</td>
13757 <td>AM6_DEV_PCIE1</td>
13758 <td>pcie_cpts_hw1_push</td>
13759 <td>0</td>
13760 </tr>
13761 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13762 <td>145</td>
13763 <td>16</td>
13764 <td>AM6_DEV_PRU_ICSSG0</td>
13765 <td>pr1_edc0_sync0_out</td>
13766 <td>0</td>
13767 </tr>
13768 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13769 <td>145</td>
13770 <td>17</td>
13771 <td>AM6_DEV_PRU_ICSSG0</td>
13772 <td>pr1_edc0_sync1_out</td>
13773 <td>0</td>
13774 </tr>
13775 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13776 <td>145</td>
13777 <td>18</td>
13778 <td>AM6_DEV_PRU_ICSSG0</td>
13779 <td>pr1_edc1_sync0_out</td>
13780 <td>0</td>
13781 </tr>
13782 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13783 <td>145</td>
13784 <td>19</td>
13785 <td>AM6_DEV_PRU_ICSSG0</td>
13786 <td>pr1_edc1_sync1_out</td>
13787 <td>0</td>
13788 </tr>
13789 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13790 <td>145</td>
13791 <td>20</td>
13792 <td>AM6_DEV_PRU_ICSSG1</td>
13793 <td>pr1_edc0_sync0_out</td>
13794 <td>0</td>
13795 </tr>
13796 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13797 <td>145</td>
13798 <td>21</td>
13799 <td>AM6_DEV_PRU_ICSSG1</td>
13800 <td>pr1_edc0_sync1_out</td>
13801 <td>0</td>
13802 </tr>
13803 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13804 <td>145</td>
13805 <td>22</td>
13806 <td>AM6_DEV_PRU_ICSSG1</td>
13807 <td>pr1_edc1_sync0_out</td>
13808 <td>0</td>
13809 </tr>
13810 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13811 <td>145</td>
13812 <td>23</td>
13813 <td>AM6_DEV_PRU_ICSSG1</td>
13814 <td>pr1_edc1_sync1_out</td>
13815 <td>0</td>
13816 </tr>
13817 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13818 <td>145</td>
13819 <td>24</td>
13820 <td>AM6_DEV_PRU_ICSSG2</td>
13821 <td>pr1_edc0_sync0_out</td>
13822 <td>0</td>
13823 </tr>
13824 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13825 <td>145</td>
13826 <td>25</td>
13827 <td>AM6_DEV_PRU_ICSSG2</td>
13828 <td>pr1_edc0_sync1_out</td>
13829 <td>0</td>
13830 </tr>
13831 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13832 <td>145</td>
13833 <td>26</td>
13834 <td>AM6_DEV_PRU_ICSSG2</td>
13835 <td>pr1_edc1_sync0_out</td>
13836 <td>0</td>
13837 </tr>
13838 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13839 <td>145</td>
13840 <td>27</td>
13841 <td>AM6_DEV_PRU_ICSSG2</td>
13842 <td>pr1_edc1_sync1_out</td>
13843 <td>0</td>
13844 </tr>
13845 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13846 <td>145</td>
13847 <td>28</td>
13848 <td>AM6_DEV_PCIE0</td>
13849 <td>pcie_cpts_sync</td>
13850 <td>0</td>
13851 </tr>
13852 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13853 <td>145</td>
13854 <td>29</td>
13855 <td>AM6_DEV_PCIE1</td>
13856 <td>pcie_cpts_sync</td>
13857 <td>0</td>
13858 </tr>
13859 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13860 <td>145</td>
13861 <td>30</td>
13862 <td>AM6_DEV_NAVSS0</td>
13863 <td>cpts0_sync</td>
13864 <td>0</td>
13865 </tr>
13866 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13867 <td>145</td>
13868 <td>31</td>
13869 <td>AM6_DEV_MCU_CPSW0</td>
13870 <td>cpts_sync</td>
13871 <td>0</td>
13872 </tr>
13873 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13874 <td>145</td>
13875 <td>32</td>
13876 <td>Not Connected</td>
13877 <td>&#160;</td>
13878 <td>&#160;</td>
13879 </tr>
13880 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13881 <td>145</td>
13882 <td>33</td>
13883 <td>Not Connected</td>
13884 <td>&#160;</td>
13885 <td>&#160;</td>
13886 </tr>
13887 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13888 <td>145</td>
13889 <td>34</td>
13890 <td>Not Connected</td>
13891 <td>&#160;</td>
13892 <td>&#160;</td>
13893 </tr>
13894 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13895 <td>145</td>
13896 <td>35</td>
13897 <td>Not Connected</td>
13898 <td>&#160;</td>
13899 <td>&#160;</td>
13900 </tr>
13901 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13902 <td>145</td>
13903 <td>36</td>
13904 <td>Not Connected</td>
13905 <td>&#160;</td>
13906 <td>&#160;</td>
13907 </tr>
13908 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13909 <td>145</td>
13910 <td>37</td>
13911 <td>Not Connected</td>
13912 <td>&#160;</td>
13913 <td>&#160;</td>
13914 </tr>
13915 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13916 <td>145</td>
13917 <td>38</td>
13918 <td>Not Connected</td>
13919 <td>&#160;</td>
13920 <td>&#160;</td>
13921 </tr>
13922 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13923 <td>145</td>
13924 <td>39</td>
13925 <td>Not Connected</td>
13926 <td>&#160;</td>
13927 <td>&#160;</td>
13928 </tr>
13929 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13930 <td>145</td>
13931 <td>40</td>
13932 <td>Not Connected</td>
13933 <td>&#160;</td>
13934 <td>&#160;</td>
13935 </tr>
13936 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13937 <td>145</td>
13938 <td>41</td>
13939 <td>Not Connected</td>
13940 <td>&#160;</td>
13941 <td>&#160;</td>
13942 </tr>
13943 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13944 <td>145</td>
13945 <td>42</td>
13946 <td>Not Connected</td>
13947 <td>&#160;</td>
13948 <td>&#160;</td>
13949 </tr>
13950 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13951 <td>145</td>
13952 <td>43</td>
13953 <td>Not Connected</td>
13954 <td>&#160;</td>
13955 <td>&#160;</td>
13956 </tr>
13957 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13958 <td>145</td>
13959 <td>44</td>
13960 <td>Not Connected</td>
13961 <td>&#160;</td>
13962 <td>&#160;</td>
13963 </tr>
13964 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13965 <td>145</td>
13966 <td>45</td>
13967 <td>Not Connected</td>
13968 <td>&#160;</td>
13969 <td>&#160;</td>
13970 </tr>
13971 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13972 <td>145</td>
13973 <td>46</td>
13974 <td>Not Connected</td>
13975 <td>&#160;</td>
13976 <td>&#160;</td>
13977 </tr>
13978 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
13979 <td>145</td>
13980 <td>47</td>
13981 <td>Not Connected</td>
13982 <td>&#160;</td>
13983 <td>&#160;</td>
13984 </tr>
13985 </tbody>
13986 </table>
13987 </div>
13988 <div class="section" id="timesync-intrtr0-interrupt-router-output-destinations">
13989 <span id="pub-soc-am65x-sr2-timesync-intrtr0-output-src-list"></span><h2>TIMESYNC_INTRTR0 Interrupt Router Output Destinations<a class="headerlink" href="#timesync-intrtr0-interrupt-router-output-destinations" title="Permalink to this headline">¶</a></h2>
13990 <div class="admonition warning">
13991 <p class="first admonition-title">Warning</p>
13992 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
13993 host within the RM Board Configuration resource assignment array.  The RM
13994 Board Configuration is rejected if an overlap with a reserved resource is
13995 detected.</p>
13996 </div>
13997 <table border="1" class="docutils">
13998 <colgroup>
13999 <col width="20%" />
14000 <col width="13%" />
14001 <col width="15%" />
14002 <col width="16%" />
14003 <col width="20%" />
14004 <col width="17%" />
14005 </colgroup>
14006 <thead valign="bottom">
14007 <tr class="row-odd"><th class="head">IR Name</th>
14008 <th class="head">IR Device ID</th>
14009 <th class="head">IR Output Index</th>
14010 <th class="head">Destination Name</th>
14011 <th class="head">Destination Interface</th>
14012 <th class="head">Destination Index</th>
14013 </tr>
14014 </thead>
14015 <tbody valign="top">
14016 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14017 <td>145</td>
14018 <td>0</td>
14019 <td>AM6_DEV_NAVSS0</td>
14020 <td>cpts0_hw1_push</td>
14021 <td>0</td>
14022 </tr>
14023 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14024 <td>145</td>
14025 <td>1</td>
14026 <td>AM6_DEV_NAVSS0</td>
14027 <td>cpts0_hw2_push</td>
14028 <td>0</td>
14029 </tr>
14030 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14031 <td>145</td>
14032 <td>2</td>
14033 <td>AM6_DEV_NAVSS0</td>
14034 <td>cpts0_hw3_push</td>
14035 <td>0</td>
14036 </tr>
14037 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14038 <td>145</td>
14039 <td>3</td>
14040 <td>AM6_DEV_NAVSS0</td>
14041 <td>cpts0_hw4_push</td>
14042 <td>0</td>
14043 </tr>
14044 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14045 <td>145</td>
14046 <td>4</td>
14047 <td>AM6_DEV_NAVSS0</td>
14048 <td>cpts0_hw5_push</td>
14049 <td>0</td>
14050 </tr>
14051 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14052 <td>145</td>
14053 <td>5</td>
14054 <td>AM6_DEV_NAVSS0</td>
14055 <td>cpts0_hw6_push</td>
14056 <td>0</td>
14057 </tr>
14058 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14059 <td>145</td>
14060 <td>6</td>
14061 <td>AM6_DEV_NAVSS0</td>
14062 <td>cpts0_hw7_push</td>
14063 <td>0</td>
14064 </tr>
14065 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14066 <td>145</td>
14067 <td>7</td>
14068 <td>AM6_DEV_NAVSS0</td>
14069 <td>cpts0_hw8_push</td>
14070 <td>0</td>
14071 </tr>
14072 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14073 <td>145</td>
14074 <td>8</td>
14075 <td>AM6_DEV_PRU_ICSSG0</td>
14076 <td>pr1_edc0_latch0_in</td>
14077 <td>0</td>
14078 </tr>
14079 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14080 <td>145</td>
14081 <td>9</td>
14082 <td>AM6_DEV_PRU_ICSSG0</td>
14083 <td>pr1_edc0_latch1_in</td>
14084 <td>0</td>
14085 </tr>
14086 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14087 <td>145</td>
14088 <td>10</td>
14089 <td>AM6_DEV_PRU_ICSSG0</td>
14090 <td>pr1_edc1_latch0_in</td>
14091 <td>0</td>
14092 </tr>
14093 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14094 <td>145</td>
14095 <td>11</td>
14096 <td>AM6_DEV_PRU_ICSSG0</td>
14097 <td>pr1_edc1_latch1_in</td>
14098 <td>0</td>
14099 </tr>
14100 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14101 <td>145</td>
14102 <td>12</td>
14103 <td>AM6_DEV_PRU_ICSSG1</td>
14104 <td>pr1_edc0_latch0_in</td>
14105 <td>0</td>
14106 </tr>
14107 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14108 <td>145</td>
14109 <td>13</td>
14110 <td>AM6_DEV_PRU_ICSSG1</td>
14111 <td>pr1_edc0_latch1_in</td>
14112 <td>0</td>
14113 </tr>
14114 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14115 <td>145</td>
14116 <td>14</td>
14117 <td>AM6_DEV_PRU_ICSSG1</td>
14118 <td>pr1_edc1_latch0_in</td>
14119 <td>0</td>
14120 </tr>
14121 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14122 <td>145</td>
14123 <td>15</td>
14124 <td>AM6_DEV_PRU_ICSSG1</td>
14125 <td>pr1_edc1_latch1_in</td>
14126 <td>0</td>
14127 </tr>
14128 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14129 <td>145</td>
14130 <td>16</td>
14131 <td>AM6_DEV_PRU_ICSSG2</td>
14132 <td>pr1_edc0_latch0_in</td>
14133 <td>0</td>
14134 </tr>
14135 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14136 <td>145</td>
14137 <td>17</td>
14138 <td>AM6_DEV_PRU_ICSSG2</td>
14139 <td>pr1_edc0_latch1_in</td>
14140 <td>0</td>
14141 </tr>
14142 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14143 <td>145</td>
14144 <td>18</td>
14145 <td>AM6_DEV_PRU_ICSSG2</td>
14146 <td>pr1_edc1_latch0_in</td>
14147 <td>0</td>
14148 </tr>
14149 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14150 <td>145</td>
14151 <td>19</td>
14152 <td>AM6_DEV_PRU_ICSSG2</td>
14153 <td>pr1_edc1_latch1_in</td>
14154 <td>0</td>
14155 </tr>
14156 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14157 <td>145</td>
14158 <td>20</td>
14159 <td>AM6_DEV_PCIE0</td>
14160 <td>pcie_cpts_hw2_push</td>
14161 <td>0</td>
14162 </tr>
14163 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14164 <td>145</td>
14165 <td>21</td>
14166 <td>AM6_DEV_PCIE1</td>
14167 <td>pcie_cpts_hw2_push</td>
14168 <td>0</td>
14169 </tr>
14170 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14171 <td>145</td>
14172 <td>22</td>
14173 <td>Not Connected</td>
14174 <td>&#160;</td>
14175 <td>&#160;</td>
14176 </tr>
14177 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14178 <td>145</td>
14179 <td>23</td>
14180 <td>Not Connected</td>
14181 <td>&#160;</td>
14182 <td>&#160;</td>
14183 </tr>
14184 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14185 <td>145</td>
14186 <td>24</td>
14187 <td>AM6_DEV_MCU_CPSW0</td>
14188 <td>cpts_hw3_push</td>
14189 <td>0</td>
14190 </tr>
14191 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14192 <td>145</td>
14193 <td>25</td>
14194 <td>AM6_DEV_MCU_CPSW0</td>
14195 <td>cpts_hw4_push</td>
14196 <td>0</td>
14197 </tr>
14198 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14199 <td>145</td>
14200 <td>26</td>
14201 <td>Not Connected</td>
14202 <td>&#160;</td>
14203 <td>&#160;</td>
14204 </tr>
14205 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14206 <td>145</td>
14207 <td>27</td>
14208 <td>Not Connected</td>
14209 <td>&#160;</td>
14210 <td>&#160;</td>
14211 </tr>
14212 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14213 <td>145</td>
14214 <td>28</td>
14215 <td>Not Connected</td>
14216 <td>&#160;</td>
14217 <td>&#160;</td>
14218 </tr>
14219 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14220 <td>145</td>
14221 <td>29</td>
14222 <td>Not Connected</td>
14223 <td>&#160;</td>
14224 <td>&#160;</td>
14225 </tr>
14226 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14227 <td>145</td>
14228 <td>30</td>
14229 <td>Not Connected</td>
14230 <td>&#160;</td>
14231 <td>&#160;</td>
14232 </tr>
14233 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14234 <td>145</td>
14235 <td>31</td>
14236 <td>Not Connected</td>
14237 <td>&#160;</td>
14238 <td>&#160;</td>
14239 </tr>
14240 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14241 <td>145</td>
14242 <td>32</td>
14243 <td>AM6_DEV_PDMA1</td>
14244 <td>levent_in</td>
14245 <td>0</td>
14246 </tr>
14247 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14248 <td>145</td>
14249 <td>33</td>
14250 <td>AM6_DEV_PDMA1</td>
14251 <td>levent_in</td>
14252 <td>1</td>
14253 </tr>
14254 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14255 <td>145</td>
14256 <td>34</td>
14257 <td>AM6_DEV_PDMA1</td>
14258 <td>levent_in</td>
14259 <td>2</td>
14260 </tr>
14261 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14262 <td>145</td>
14263 <td>35</td>
14264 <td>AM6_DEV_PDMA1</td>
14265 <td>levent_in</td>
14266 <td>3</td>
14267 </tr>
14268 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14269 <td>145</td>
14270 <td>36</td>
14271 <td>AM6_DEV_PDMA1</td>
14272 <td>levent_in</td>
14273 <td>4</td>
14274 </tr>
14275 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14276 <td>145</td>
14277 <td>37</td>
14278 <td>AM6_DEV_PDMA1</td>
14279 <td>levent_in</td>
14280 <td>5</td>
14281 </tr>
14282 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14283 <td>145</td>
14284 <td>38</td>
14285 <td>AM6_DEV_PDMA1</td>
14286 <td>levent_in</td>
14287 <td>6</td>
14288 </tr>
14289 <tr class="row-odd"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
14290 <td>145</td>
14291 <td>39</td>
14292 <td>AM6_DEV_PDMA1</td>
14293 <td>levent_in</td>
14294 <td>7</td>
14295 </tr>
14296 </tbody>
14297 </table>
14298 </div>
14299 <div class="section" id="wkup-gpiomux-intrtr0-interrupt-router-input-sources">
14300 <span id="pub-soc-am65x-sr2-wkup-gpiomux-intrtr0-input-src-list"></span><h2>WKUP_GPIOMUX_INTRTR0 Interrupt Router Input Sources<a class="headerlink" href="#wkup-gpiomux-intrtr0-interrupt-router-input-sources" title="Permalink to this headline">¶</a></h2>
14301 <div class="admonition warning">
14302 <p class="first admonition-title">Warning</p>
14303 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
14304 host within the RM Board Configuration resource assignment array.  The RM
14305 Board Configuration is rejected if an overlap with a reserved resource is
14306 detected.</p>
14307 </div>
14308 <table border="1" class="docutils">
14309 <colgroup>
14310 <col width="25%" />
14311 <col width="13%" />
14312 <col width="15%" />
14313 <col width="17%" />
14314 <col width="17%" />
14315 <col width="13%" />
14316 </colgroup>
14317 <thead valign="bottom">
14318 <tr class="row-odd"><th class="head">IR Name</th>
14319 <th class="head">IR Device ID</th>
14320 <th class="head">IR Input Index</th>
14321 <th class="head">Source Name</th>
14322 <th class="head">Source Interface</th>
14323 <th class="head">Source Index</th>
14324 </tr>
14325 </thead>
14326 <tbody valign="top">
14327 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14328 <td>156</td>
14329 <td>0</td>
14330 <td>AM6_DEV_WKUP_GPIO0</td>
14331 <td>gpio</td>
14332 <td>0</td>
14333 </tr>
14334 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14335 <td>156</td>
14336 <td>1</td>
14337 <td>AM6_DEV_WKUP_GPIO0</td>
14338 <td>gpio</td>
14339 <td>1</td>
14340 </tr>
14341 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14342 <td>156</td>
14343 <td>2</td>
14344 <td>AM6_DEV_WKUP_GPIO0</td>
14345 <td>gpio</td>
14346 <td>2</td>
14347 </tr>
14348 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14349 <td>156</td>
14350 <td>3</td>
14351 <td>AM6_DEV_WKUP_GPIO0</td>
14352 <td>gpio</td>
14353 <td>3</td>
14354 </tr>
14355 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14356 <td>156</td>
14357 <td>4</td>
14358 <td>AM6_DEV_WKUP_GPIO0</td>
14359 <td>gpio</td>
14360 <td>4</td>
14361 </tr>
14362 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14363 <td>156</td>
14364 <td>5</td>
14365 <td>AM6_DEV_WKUP_GPIO0</td>
14366 <td>gpio</td>
14367 <td>5</td>
14368 </tr>
14369 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14370 <td>156</td>
14371 <td>6</td>
14372 <td>AM6_DEV_WKUP_GPIO0</td>
14373 <td>gpio</td>
14374 <td>6</td>
14375 </tr>
14376 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14377 <td>156</td>
14378 <td>7</td>
14379 <td>AM6_DEV_WKUP_GPIO0</td>
14380 <td>gpio</td>
14381 <td>7</td>
14382 </tr>
14383 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14384 <td>156</td>
14385 <td>8</td>
14386 <td>AM6_DEV_WKUP_GPIO0</td>
14387 <td>gpio</td>
14388 <td>8</td>
14389 </tr>
14390 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14391 <td>156</td>
14392 <td>9</td>
14393 <td>AM6_DEV_WKUP_GPIO0</td>
14394 <td>gpio</td>
14395 <td>9</td>
14396 </tr>
14397 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14398 <td>156</td>
14399 <td>10</td>
14400 <td>AM6_DEV_WKUP_GPIO0</td>
14401 <td>gpio</td>
14402 <td>10</td>
14403 </tr>
14404 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14405 <td>156</td>
14406 <td>11</td>
14407 <td>AM6_DEV_WKUP_GPIO0</td>
14408 <td>gpio</td>
14409 <td>11</td>
14410 </tr>
14411 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14412 <td>156</td>
14413 <td>12</td>
14414 <td>AM6_DEV_WKUP_GPIO0</td>
14415 <td>gpio</td>
14416 <td>12</td>
14417 </tr>
14418 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14419 <td>156</td>
14420 <td>13</td>
14421 <td>AM6_DEV_WKUP_GPIO0</td>
14422 <td>gpio</td>
14423 <td>13</td>
14424 </tr>
14425 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14426 <td>156</td>
14427 <td>14</td>
14428 <td>AM6_DEV_WKUP_GPIO0</td>
14429 <td>gpio</td>
14430 <td>14</td>
14431 </tr>
14432 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14433 <td>156</td>
14434 <td>15</td>
14435 <td>AM6_DEV_WKUP_GPIO0</td>
14436 <td>gpio</td>
14437 <td>15</td>
14438 </tr>
14439 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14440 <td>156</td>
14441 <td>16</td>
14442 <td>AM6_DEV_WKUP_GPIO0</td>
14443 <td>gpio</td>
14444 <td>16</td>
14445 </tr>
14446 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14447 <td>156</td>
14448 <td>17</td>
14449 <td>AM6_DEV_WKUP_GPIO0</td>
14450 <td>gpio</td>
14451 <td>17</td>
14452 </tr>
14453 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14454 <td>156</td>
14455 <td>18</td>
14456 <td>AM6_DEV_WKUP_GPIO0</td>
14457 <td>gpio</td>
14458 <td>18</td>
14459 </tr>
14460 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14461 <td>156</td>
14462 <td>19</td>
14463 <td>AM6_DEV_WKUP_GPIO0</td>
14464 <td>gpio</td>
14465 <td>19</td>
14466 </tr>
14467 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14468 <td>156</td>
14469 <td>20</td>
14470 <td>AM6_DEV_WKUP_GPIO0</td>
14471 <td>gpio</td>
14472 <td>20</td>
14473 </tr>
14474 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14475 <td>156</td>
14476 <td>21</td>
14477 <td>AM6_DEV_WKUP_GPIO0</td>
14478 <td>gpio</td>
14479 <td>21</td>
14480 </tr>
14481 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14482 <td>156</td>
14483 <td>22</td>
14484 <td>AM6_DEV_WKUP_GPIO0</td>
14485 <td>gpio</td>
14486 <td>22</td>
14487 </tr>
14488 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14489 <td>156</td>
14490 <td>23</td>
14491 <td>AM6_DEV_WKUP_GPIO0</td>
14492 <td>gpio</td>
14493 <td>23</td>
14494 </tr>
14495 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14496 <td>156</td>
14497 <td>24</td>
14498 <td>AM6_DEV_WKUP_GPIO0</td>
14499 <td>gpio</td>
14500 <td>24</td>
14501 </tr>
14502 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14503 <td>156</td>
14504 <td>25</td>
14505 <td>AM6_DEV_WKUP_GPIO0</td>
14506 <td>gpio</td>
14507 <td>25</td>
14508 </tr>
14509 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14510 <td>156</td>
14511 <td>26</td>
14512 <td>AM6_DEV_WKUP_GPIO0</td>
14513 <td>gpio</td>
14514 <td>26</td>
14515 </tr>
14516 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14517 <td>156</td>
14518 <td>27</td>
14519 <td>AM6_DEV_WKUP_GPIO0</td>
14520 <td>gpio</td>
14521 <td>27</td>
14522 </tr>
14523 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14524 <td>156</td>
14525 <td>28</td>
14526 <td>AM6_DEV_WKUP_GPIO0</td>
14527 <td>gpio</td>
14528 <td>28</td>
14529 </tr>
14530 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14531 <td>156</td>
14532 <td>29</td>
14533 <td>AM6_DEV_WKUP_GPIO0</td>
14534 <td>gpio</td>
14535 <td>29</td>
14536 </tr>
14537 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14538 <td>156</td>
14539 <td>30</td>
14540 <td>AM6_DEV_WKUP_GPIO0</td>
14541 <td>gpio</td>
14542 <td>30</td>
14543 </tr>
14544 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14545 <td>156</td>
14546 <td>31</td>
14547 <td>AM6_DEV_WKUP_GPIO0</td>
14548 <td>gpio</td>
14549 <td>31</td>
14550 </tr>
14551 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14552 <td>156</td>
14553 <td>32</td>
14554 <td>AM6_DEV_WKUP_GPIO0</td>
14555 <td>gpio</td>
14556 <td>32</td>
14557 </tr>
14558 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14559 <td>156</td>
14560 <td>33</td>
14561 <td>AM6_DEV_WKUP_GPIO0</td>
14562 <td>gpio</td>
14563 <td>33</td>
14564 </tr>
14565 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14566 <td>156</td>
14567 <td>34</td>
14568 <td>AM6_DEV_WKUP_GPIO0</td>
14569 <td>gpio</td>
14570 <td>34</td>
14571 </tr>
14572 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14573 <td>156</td>
14574 <td>35</td>
14575 <td>AM6_DEV_WKUP_GPIO0</td>
14576 <td>gpio</td>
14577 <td>35</td>
14578 </tr>
14579 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14580 <td>156</td>
14581 <td>36</td>
14582 <td>AM6_DEV_WKUP_GPIO0</td>
14583 <td>gpio</td>
14584 <td>36</td>
14585 </tr>
14586 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14587 <td>156</td>
14588 <td>37</td>
14589 <td>AM6_DEV_WKUP_GPIO0</td>
14590 <td>gpio</td>
14591 <td>37</td>
14592 </tr>
14593 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14594 <td>156</td>
14595 <td>38</td>
14596 <td>AM6_DEV_WKUP_GPIO0</td>
14597 <td>gpio</td>
14598 <td>38</td>
14599 </tr>
14600 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14601 <td>156</td>
14602 <td>39</td>
14603 <td>AM6_DEV_WKUP_GPIO0</td>
14604 <td>gpio</td>
14605 <td>39</td>
14606 </tr>
14607 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14608 <td>156</td>
14609 <td>40</td>
14610 <td>AM6_DEV_WKUP_GPIO0</td>
14611 <td>gpio</td>
14612 <td>40</td>
14613 </tr>
14614 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14615 <td>156</td>
14616 <td>41</td>
14617 <td>AM6_DEV_WKUP_GPIO0</td>
14618 <td>gpio</td>
14619 <td>41</td>
14620 </tr>
14621 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14622 <td>156</td>
14623 <td>42</td>
14624 <td>AM6_DEV_WKUP_GPIO0</td>
14625 <td>gpio</td>
14626 <td>42</td>
14627 </tr>
14628 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14629 <td>156</td>
14630 <td>43</td>
14631 <td>AM6_DEV_WKUP_GPIO0</td>
14632 <td>gpio</td>
14633 <td>43</td>
14634 </tr>
14635 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14636 <td>156</td>
14637 <td>44</td>
14638 <td>AM6_DEV_WKUP_GPIO0</td>
14639 <td>gpio</td>
14640 <td>44</td>
14641 </tr>
14642 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14643 <td>156</td>
14644 <td>45</td>
14645 <td>AM6_DEV_WKUP_GPIO0</td>
14646 <td>gpio</td>
14647 <td>45</td>
14648 </tr>
14649 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14650 <td>156</td>
14651 <td>46</td>
14652 <td>AM6_DEV_WKUP_GPIO0</td>
14653 <td>gpio</td>
14654 <td>46</td>
14655 </tr>
14656 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14657 <td>156</td>
14658 <td>47</td>
14659 <td>AM6_DEV_WKUP_GPIO0</td>
14660 <td>gpio</td>
14661 <td>47</td>
14662 </tr>
14663 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14664 <td>156</td>
14665 <td>48</td>
14666 <td>AM6_DEV_WKUP_GPIO0</td>
14667 <td>gpio</td>
14668 <td>48</td>
14669 </tr>
14670 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14671 <td>156</td>
14672 <td>49</td>
14673 <td>AM6_DEV_WKUP_GPIO0</td>
14674 <td>gpio</td>
14675 <td>49</td>
14676 </tr>
14677 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14678 <td>156</td>
14679 <td>50</td>
14680 <td>AM6_DEV_WKUP_GPIO0</td>
14681 <td>gpio</td>
14682 <td>50</td>
14683 </tr>
14684 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14685 <td>156</td>
14686 <td>51</td>
14687 <td>AM6_DEV_WKUP_GPIO0</td>
14688 <td>gpio</td>
14689 <td>51</td>
14690 </tr>
14691 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14692 <td>156</td>
14693 <td>52</td>
14694 <td>AM6_DEV_WKUP_GPIO0</td>
14695 <td>gpio</td>
14696 <td>52</td>
14697 </tr>
14698 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14699 <td>156</td>
14700 <td>53</td>
14701 <td>AM6_DEV_WKUP_GPIO0</td>
14702 <td>gpio</td>
14703 <td>53</td>
14704 </tr>
14705 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14706 <td>156</td>
14707 <td>54</td>
14708 <td>AM6_DEV_WKUP_GPIO0</td>
14709 <td>gpio</td>
14710 <td>54</td>
14711 </tr>
14712 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14713 <td>156</td>
14714 <td>55</td>
14715 <td>AM6_DEV_WKUP_GPIO0</td>
14716 <td>gpio</td>
14717 <td>55</td>
14718 </tr>
14719 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14720 <td>156</td>
14721 <td>56</td>
14722 <td>Not Connected</td>
14723 <td>&#160;</td>
14724 <td>&#160;</td>
14725 </tr>
14726 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14727 <td>156</td>
14728 <td>57</td>
14729 <td>Not Connected</td>
14730 <td>&#160;</td>
14731 <td>&#160;</td>
14732 </tr>
14733 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14734 <td>156</td>
14735 <td>58</td>
14736 <td>Not Connected</td>
14737 <td>&#160;</td>
14738 <td>&#160;</td>
14739 </tr>
14740 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14741 <td>156</td>
14742 <td>59</td>
14743 <td>Not Connected</td>
14744 <td>&#160;</td>
14745 <td>&#160;</td>
14746 </tr>
14747 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14748 <td>156</td>
14749 <td>60</td>
14750 <td>AM6_DEV_WKUP_GPIO0</td>
14751 <td>gpio_bank</td>
14752 <td>0</td>
14753 </tr>
14754 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14755 <td>156</td>
14756 <td>61</td>
14757 <td>AM6_DEV_WKUP_GPIO0</td>
14758 <td>gpio_bank</td>
14759 <td>1</td>
14760 </tr>
14761 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14762 <td>156</td>
14763 <td>62</td>
14764 <td>AM6_DEV_WKUP_GPIO0</td>
14765 <td>gpio_bank</td>
14766 <td>2</td>
14767 </tr>
14768 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14769 <td>156</td>
14770 <td>63</td>
14771 <td>AM6_DEV_WKUP_GPIO0</td>
14772 <td>gpio_bank</td>
14773 <td>3</td>
14774 </tr>
14775 </tbody>
14776 </table>
14777 </div>
14778 <div class="section" id="wkup-gpiomux-intrtr0-interrupt-router-output-destinations">
14779 <span id="pub-soc-am65x-sr2-wkup-gpiomux-intrtr0-output-src-list"></span><h2>WKUP_GPIOMUX_INTRTR0 Interrupt Router Output Destinations<a class="headerlink" href="#wkup-gpiomux-intrtr0-interrupt-router-output-destinations" title="Permalink to this headline">¶</a></h2>
14780 <div class="admonition warning">
14781 <p class="first admonition-title">Warning</p>
14782 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
14783 host within the RM Board Configuration resource assignment array.  The RM
14784 Board Configuration is rejected if an overlap with a reserved resource is
14785 detected.</p>
14786 </div>
14787 <table border="1" class="docutils">
14788 <colgroup>
14789 <col width="21%" />
14790 <col width="11%" />
14791 <col width="13%" />
14792 <col width="22%" />
14793 <col width="17%" />
14794 <col width="15%" />
14795 </colgroup>
14796 <thead valign="bottom">
14797 <tr class="row-odd"><th class="head">IR Name</th>
14798 <th class="head">IR Device ID</th>
14799 <th class="head">IR Output Index</th>
14800 <th class="head">Destination Name</th>
14801 <th class="head">Destination Interface</th>
14802 <th class="head">Destination Index</th>
14803 </tr>
14804 </thead>
14805 <tbody valign="top">
14806 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14807 <td>156</td>
14808 <td>0</td>
14809 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
14810 <td>nvic</td>
14811 <td>184</td>
14812 </tr>
14813 <tr class="row-odd"><td>&#160;</td>
14814 <td>&#160;</td>
14815 <td>&#160;</td>
14816 <td>AM6_DEV_GIC0</td>
14817 <td>spi</td>
14818 <td>712</td>
14819 </tr>
14820 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14821 <td>156</td>
14822 <td>0</td>
14823 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
14824 <td>intr</td>
14825 <td>124</td>
14826 </tr>
14827 <tr class="row-odd"><td>&#160;</td>
14828 <td>&#160;</td>
14829 <td>&#160;</td>
14830 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
14831 <td>intr</td>
14832 <td>124</td>
14833 </tr>
14834 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14835 <td>156</td>
14836 <td>1</td>
14837 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
14838 <td>nvic</td>
14839 <td>185</td>
14840 </tr>
14841 <tr class="row-odd"><td>&#160;</td>
14842 <td>&#160;</td>
14843 <td>&#160;</td>
14844 <td>AM6_DEV_GIC0</td>
14845 <td>spi</td>
14846 <td>713</td>
14847 </tr>
14848 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14849 <td>156</td>
14850 <td>1</td>
14851 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
14852 <td>intr</td>
14853 <td>125</td>
14854 </tr>
14855 <tr class="row-odd"><td>&#160;</td>
14856 <td>&#160;</td>
14857 <td>&#160;</td>
14858 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
14859 <td>intr</td>
14860 <td>125</td>
14861 </tr>
14862 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14863 <td>156</td>
14864 <td>2</td>
14865 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
14866 <td>nvic</td>
14867 <td>186</td>
14868 </tr>
14869 <tr class="row-odd"><td>&#160;</td>
14870 <td>&#160;</td>
14871 <td>&#160;</td>
14872 <td>AM6_DEV_GIC0</td>
14873 <td>spi</td>
14874 <td>714</td>
14875 </tr>
14876 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14877 <td>156</td>
14878 <td>2</td>
14879 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
14880 <td>intr</td>
14881 <td>126</td>
14882 </tr>
14883 <tr class="row-odd"><td>&#160;</td>
14884 <td>&#160;</td>
14885 <td>&#160;</td>
14886 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
14887 <td>intr</td>
14888 <td>126</td>
14889 </tr>
14890 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14891 <td>156</td>
14892 <td>3</td>
14893 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
14894 <td>nvic</td>
14895 <td>187</td>
14896 </tr>
14897 <tr class="row-odd"><td>&#160;</td>
14898 <td>&#160;</td>
14899 <td>&#160;</td>
14900 <td>AM6_DEV_GIC0</td>
14901 <td>spi</td>
14902 <td>715</td>
14903 </tr>
14904 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14905 <td>156</td>
14906 <td>3</td>
14907 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
14908 <td>intr</td>
14909 <td>127</td>
14910 </tr>
14911 <tr class="row-odd"><td>&#160;</td>
14912 <td>&#160;</td>
14913 <td>&#160;</td>
14914 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
14915 <td>intr</td>
14916 <td>127</td>
14917 </tr>
14918 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14919 <td>156</td>
14920 <td>4</td>
14921 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
14922 <td>nvic</td>
14923 <td>188</td>
14924 </tr>
14925 <tr class="row-odd"><td>&#160;</td>
14926 <td>&#160;</td>
14927 <td>&#160;</td>
14928 <td>AM6_DEV_GIC0</td>
14929 <td>spi</td>
14930 <td>716</td>
14931 </tr>
14932 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14933 <td>156</td>
14934 <td>4</td>
14935 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
14936 <td>intr</td>
14937 <td>128</td>
14938 </tr>
14939 <tr class="row-odd"><td>&#160;</td>
14940 <td>&#160;</td>
14941 <td>&#160;</td>
14942 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
14943 <td>intr</td>
14944 <td>128</td>
14945 </tr>
14946 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14947 <td>156</td>
14948 <td>5</td>
14949 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
14950 <td>nvic</td>
14951 <td>189</td>
14952 </tr>
14953 <tr class="row-odd"><td>&#160;</td>
14954 <td>&#160;</td>
14955 <td>&#160;</td>
14956 <td>AM6_DEV_GIC0</td>
14957 <td>spi</td>
14958 <td>717</td>
14959 </tr>
14960 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14961 <td>156</td>
14962 <td>5</td>
14963 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
14964 <td>intr</td>
14965 <td>129</td>
14966 </tr>
14967 <tr class="row-odd"><td>&#160;</td>
14968 <td>&#160;</td>
14969 <td>&#160;</td>
14970 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
14971 <td>intr</td>
14972 <td>129</td>
14973 </tr>
14974 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14975 <td>156</td>
14976 <td>6</td>
14977 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
14978 <td>nvic</td>
14979 <td>190</td>
14980 </tr>
14981 <tr class="row-odd"><td>&#160;</td>
14982 <td>&#160;</td>
14983 <td>&#160;</td>
14984 <td>AM6_DEV_GIC0</td>
14985 <td>spi</td>
14986 <td>718</td>
14987 </tr>
14988 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
14989 <td>156</td>
14990 <td>6</td>
14991 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
14992 <td>intr</td>
14993 <td>130</td>
14994 </tr>
14995 <tr class="row-odd"><td>&#160;</td>
14996 <td>&#160;</td>
14997 <td>&#160;</td>
14998 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
14999 <td>intr</td>
15000 <td>130</td>
15001 </tr>
15002 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15003 <td>156</td>
15004 <td>7</td>
15005 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
15006 <td>nvic</td>
15007 <td>191</td>
15008 </tr>
15009 <tr class="row-odd"><td>&#160;</td>
15010 <td>&#160;</td>
15011 <td>&#160;</td>
15012 <td>AM6_DEV_GIC0</td>
15013 <td>spi</td>
15014 <td>719</td>
15015 </tr>
15016 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15017 <td>156</td>
15018 <td>7</td>
15019 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
15020 <td>intr</td>
15021 <td>131</td>
15022 </tr>
15023 <tr class="row-odd"><td>&#160;</td>
15024 <td>&#160;</td>
15025 <td>&#160;</td>
15026 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
15027 <td>intr</td>
15028 <td>131</td>
15029 </tr>
15030 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15031 <td>156</td>
15032 <td>8</td>
15033 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
15034 <td>nvic</td>
15035 <td>192</td>
15036 </tr>
15037 <tr class="row-odd"><td>&#160;</td>
15038 <td>&#160;</td>
15039 <td>&#160;</td>
15040 <td>AM6_DEV_WKUP_ESM0</td>
15041 <td>esm_pls_event0</td>
15042 <td>88</td>
15043 </tr>
15044 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15045 <td>156</td>
15046 <td>8</td>
15047 <td>AM6_DEV_WKUP_ESM0</td>
15048 <td>esm_pls_event1</td>
15049 <td>88</td>
15050 </tr>
15051 <tr class="row-odd"><td>&#160;</td>
15052 <td>&#160;</td>
15053 <td>&#160;</td>
15054 <td>AM6_DEV_WKUP_ESM0</td>
15055 <td>esm_pls_event2</td>
15056 <td>88</td>
15057 </tr>
15058 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15059 <td>156</td>
15060 <td>8</td>
15061 <td>AM6_DEV_GIC0</td>
15062 <td>spi</td>
15063 <td>720</td>
15064 </tr>
15065 <tr class="row-odd"><td>&#160;</td>
15066 <td>&#160;</td>
15067 <td>&#160;</td>
15068 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
15069 <td>intr</td>
15070 <td>132</td>
15071 </tr>
15072 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15073 <td>156</td>
15074 <td>8</td>
15075 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
15076 <td>intr</td>
15077 <td>132</td>
15078 </tr>
15079 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15080 <td>156</td>
15081 <td>9</td>
15082 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
15083 <td>nvic</td>
15084 <td>193</td>
15085 </tr>
15086 <tr class="row-even"><td>&#160;</td>
15087 <td>&#160;</td>
15088 <td>&#160;</td>
15089 <td>AM6_DEV_WKUP_ESM0</td>
15090 <td>esm_pls_event0</td>
15091 <td>89</td>
15092 </tr>
15093 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15094 <td>156</td>
15095 <td>9</td>
15096 <td>AM6_DEV_WKUP_ESM0</td>
15097 <td>esm_pls_event1</td>
15098 <td>89</td>
15099 </tr>
15100 <tr class="row-even"><td>&#160;</td>
15101 <td>&#160;</td>
15102 <td>&#160;</td>
15103 <td>AM6_DEV_WKUP_ESM0</td>
15104 <td>esm_pls_event2</td>
15105 <td>89</td>
15106 </tr>
15107 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15108 <td>156</td>
15109 <td>9</td>
15110 <td>AM6_DEV_GIC0</td>
15111 <td>spi</td>
15112 <td>721</td>
15113 </tr>
15114 <tr class="row-even"><td>&#160;</td>
15115 <td>&#160;</td>
15116 <td>&#160;</td>
15117 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
15118 <td>intr</td>
15119 <td>133</td>
15120 </tr>
15121 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15122 <td>156</td>
15123 <td>9</td>
15124 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
15125 <td>intr</td>
15126 <td>133</td>
15127 </tr>
15128 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15129 <td>156</td>
15130 <td>10</td>
15131 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
15132 <td>nvic</td>
15133 <td>194</td>
15134 </tr>
15135 <tr class="row-odd"><td>&#160;</td>
15136 <td>&#160;</td>
15137 <td>&#160;</td>
15138 <td>AM6_DEV_WKUP_ESM0</td>
15139 <td>esm_pls_event0</td>
15140 <td>90</td>
15141 </tr>
15142 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15143 <td>156</td>
15144 <td>10</td>
15145 <td>AM6_DEV_WKUP_ESM0</td>
15146 <td>esm_pls_event1</td>
15147 <td>90</td>
15148 </tr>
15149 <tr class="row-odd"><td>&#160;</td>
15150 <td>&#160;</td>
15151 <td>&#160;</td>
15152 <td>AM6_DEV_WKUP_ESM0</td>
15153 <td>esm_pls_event2</td>
15154 <td>90</td>
15155 </tr>
15156 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15157 <td>156</td>
15158 <td>10</td>
15159 <td>AM6_DEV_GIC0</td>
15160 <td>spi</td>
15161 <td>722</td>
15162 </tr>
15163 <tr class="row-odd"><td>&#160;</td>
15164 <td>&#160;</td>
15165 <td>&#160;</td>
15166 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
15167 <td>intr</td>
15168 <td>134</td>
15169 </tr>
15170 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15171 <td>156</td>
15172 <td>10</td>
15173 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
15174 <td>intr</td>
15175 <td>134</td>
15176 </tr>
15177 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15178 <td>156</td>
15179 <td>11</td>
15180 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
15181 <td>nvic</td>
15182 <td>195</td>
15183 </tr>
15184 <tr class="row-even"><td>&#160;</td>
15185 <td>&#160;</td>
15186 <td>&#160;</td>
15187 <td>AM6_DEV_WKUP_ESM0</td>
15188 <td>esm_pls_event0</td>
15189 <td>91</td>
15190 </tr>
15191 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15192 <td>156</td>
15193 <td>11</td>
15194 <td>AM6_DEV_WKUP_ESM0</td>
15195 <td>esm_pls_event1</td>
15196 <td>91</td>
15197 </tr>
15198 <tr class="row-even"><td>&#160;</td>
15199 <td>&#160;</td>
15200 <td>&#160;</td>
15201 <td>AM6_DEV_WKUP_ESM0</td>
15202 <td>esm_pls_event2</td>
15203 <td>91</td>
15204 </tr>
15205 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15206 <td>156</td>
15207 <td>11</td>
15208 <td>AM6_DEV_GIC0</td>
15209 <td>spi</td>
15210 <td>723</td>
15211 </tr>
15212 <tr class="row-even"><td>&#160;</td>
15213 <td>&#160;</td>
15214 <td>&#160;</td>
15215 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
15216 <td>intr</td>
15217 <td>135</td>
15218 </tr>
15219 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15220 <td>156</td>
15221 <td>11</td>
15222 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
15223 <td>intr</td>
15224 <td>135</td>
15225 </tr>
15226 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15227 <td>156</td>
15228 <td>12</td>
15229 <td>AM6_DEV_WKUP_ESM0</td>
15230 <td>esm_pls_event0</td>
15231 <td>92</td>
15232 </tr>
15233 <tr class="row-odd"><td>&#160;</td>
15234 <td>&#160;</td>
15235 <td>&#160;</td>
15236 <td>AM6_DEV_WKUP_ESM0</td>
15237 <td>esm_pls_event1</td>
15238 <td>92</td>
15239 </tr>
15240 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15241 <td>156</td>
15242 <td>12</td>
15243 <td>AM6_DEV_WKUP_ESM0</td>
15244 <td>esm_pls_event2</td>
15245 <td>92</td>
15246 </tr>
15247 <tr class="row-odd"><td>&#160;</td>
15248 <td>&#160;</td>
15249 <td>&#160;</td>
15250 <td>AM6_DEV_GIC0</td>
15251 <td>spi</td>
15252 <td>724</td>
15253 </tr>
15254 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15255 <td>156</td>
15256 <td>12</td>
15257 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
15258 <td>intr</td>
15259 <td>136</td>
15260 </tr>
15261 <tr class="row-odd"><td>&#160;</td>
15262 <td>&#160;</td>
15263 <td>&#160;</td>
15264 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
15265 <td>intr</td>
15266 <td>136</td>
15267 </tr>
15268 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15269 <td>156</td>
15270 <td>13</td>
15271 <td>AM6_DEV_WKUP_ESM0</td>
15272 <td>esm_pls_event0</td>
15273 <td>93</td>
15274 </tr>
15275 <tr class="row-odd"><td>&#160;</td>
15276 <td>&#160;</td>
15277 <td>&#160;</td>
15278 <td>AM6_DEV_WKUP_ESM0</td>
15279 <td>esm_pls_event1</td>
15280 <td>93</td>
15281 </tr>
15282 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15283 <td>156</td>
15284 <td>13</td>
15285 <td>AM6_DEV_WKUP_ESM0</td>
15286 <td>esm_pls_event2</td>
15287 <td>93</td>
15288 </tr>
15289 <tr class="row-odd"><td>&#160;</td>
15290 <td>&#160;</td>
15291 <td>&#160;</td>
15292 <td>AM6_DEV_GIC0</td>
15293 <td>spi</td>
15294 <td>725</td>
15295 </tr>
15296 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15297 <td>156</td>
15298 <td>13</td>
15299 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
15300 <td>intr</td>
15301 <td>137</td>
15302 </tr>
15303 <tr class="row-odd"><td>&#160;</td>
15304 <td>&#160;</td>
15305 <td>&#160;</td>
15306 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
15307 <td>intr</td>
15308 <td>137</td>
15309 </tr>
15310 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15311 <td>156</td>
15312 <td>14</td>
15313 <td>AM6_DEV_WKUP_ESM0</td>
15314 <td>esm_pls_event0</td>
15315 <td>94</td>
15316 </tr>
15317 <tr class="row-odd"><td>&#160;</td>
15318 <td>&#160;</td>
15319 <td>&#160;</td>
15320 <td>AM6_DEV_WKUP_ESM0</td>
15321 <td>esm_pls_event1</td>
15322 <td>94</td>
15323 </tr>
15324 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15325 <td>156</td>
15326 <td>14</td>
15327 <td>AM6_DEV_WKUP_ESM0</td>
15328 <td>esm_pls_event2</td>
15329 <td>94</td>
15330 </tr>
15331 <tr class="row-odd"><td>&#160;</td>
15332 <td>&#160;</td>
15333 <td>&#160;</td>
15334 <td>AM6_DEV_GIC0</td>
15335 <td>spi</td>
15336 <td>726</td>
15337 </tr>
15338 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15339 <td>156</td>
15340 <td>14</td>
15341 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
15342 <td>intr</td>
15343 <td>138</td>
15344 </tr>
15345 <tr class="row-odd"><td>&#160;</td>
15346 <td>&#160;</td>
15347 <td>&#160;</td>
15348 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
15349 <td>intr</td>
15350 <td>138</td>
15351 </tr>
15352 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15353 <td>156</td>
15354 <td>15</td>
15355 <td>AM6_DEV_WKUP_ESM0</td>
15356 <td>esm_pls_event0</td>
15357 <td>95</td>
15358 </tr>
15359 <tr class="row-odd"><td>&#160;</td>
15360 <td>&#160;</td>
15361 <td>&#160;</td>
15362 <td>AM6_DEV_WKUP_ESM0</td>
15363 <td>esm_pls_event1</td>
15364 <td>95</td>
15365 </tr>
15366 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15367 <td>156</td>
15368 <td>15</td>
15369 <td>AM6_DEV_WKUP_ESM0</td>
15370 <td>esm_pls_event2</td>
15371 <td>95</td>
15372 </tr>
15373 <tr class="row-odd"><td>&#160;</td>
15374 <td>&#160;</td>
15375 <td>&#160;</td>
15376 <td>AM6_DEV_GIC0</td>
15377 <td>spi</td>
15378 <td>727</td>
15379 </tr>
15380 <tr class="row-even"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
15381 <td>156</td>
15382 <td>15</td>
15383 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
15384 <td>intr</td>
15385 <td>139</td>
15386 </tr>
15387 <tr class="row-odd"><td>&#160;</td>
15388 <td>&#160;</td>
15389 <td>&#160;</td>
15390 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
15391 <td>intr</td>
15392 <td>139</td>
15393 </tr>
15394 </tbody>
15395 </table>
15396 </div>
15397 <div class="section" id="interrupt-aggregator-device-ids">
15398 <span id="pub-soc-am65x-sr2-ia-device-ids"></span><h2>Interrupt Aggregator Device IDs<a class="headerlink" href="#interrupt-aggregator-device-ids" title="Permalink to this headline">¶</a></h2>
15399 <p>Some System Firmware TISCI message APIs require the Interrupt Aggregator device
15400 ID be provided as part of the request. Based on <a class="reference internal" href="devices.html"><span class="doc">AM65X_SR2 Device IDs</span></a> these are the valid Interrupt Aggregator device IDs.</p>
15401 <table border="1" class="docutils">
15402 <colgroup>
15403 <col width="51%" />
15404 <col width="49%" />
15405 </colgroup>
15406 <thead valign="bottom">
15407 <tr class="row-odd"><th class="head">Interrupt Aggregator Device Name</th>
15408 <th class="head">Interrupt Aggregator Device ID</th>
15409 </tr>
15410 </thead>
15411 <tbody valign="top">
15412 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15413 <td>180</td>
15414 </tr>
15415 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
15416 <td>181</td>
15417 </tr>
15418 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
15419 <td>179</td>
15420 </tr>
15421 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
15422 <td>189</td>
15423 </tr>
15424 </tbody>
15425 </table>
15426 </div>
15427 <div class="section" id="interrupt-aggregator-virtual-interrupts">
15428 <span id="pub-soc-am65x-sr2-ia-vints"></span><h2>Interrupt Aggregator Virtual Interrupts<a class="headerlink" href="#interrupt-aggregator-virtual-interrupts" title="Permalink to this headline">¶</a></h2>
15429 <p>This section describes Interrupt Aggregator virtual interrupts.  The virtual
15430 interrupts are used in interrupt management based TISCI messages.</p>
15431 <div class="admonition warning">
15432 <p class="first admonition-title">Warning</p>
15433 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
15434 host within the RM Board Configuration resource assignment array.  The RM
15435 Board Configuration is rejected if an overlap with a reserved resource is
15436 detected.</p>
15437 </div>
15438 <table border="1" class="docutils">
15439 <colgroup>
15440 <col width="56%" />
15441 <col width="44%" />
15442 </colgroup>
15443 <thead valign="bottom">
15444 <tr class="row-odd"><th class="head">Interrupt Aggregator Name</th>
15445 <th class="head">Virtual Interrupt Range</th>
15446 </tr>
15447 </thead>
15448 <tbody valign="top">
15449 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15450 <td>0 to 63</td>
15451 </tr>
15452 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
15453 <td>0 to 63</td>
15454 </tr>
15455 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
15456 (<strong>RESERVED BY SYSTEM FIRMWARE</strong>)</td>
15457 <td>0 to 15</td>
15458 </tr>
15459 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
15460 <td>16 to 255</td>
15461 </tr>
15462 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0
15463 (<strong>RESERVED BY SYSTEM FIRMWARE</strong>)</td>
15464 <td>0 to 7</td>
15465 </tr>
15466 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
15467 <td>8 to 255</td>
15468 </tr>
15469 </tbody>
15470 </table>
15471 </div>
15472 <div class="section" id="navss0-modss-inta0-interrupt-aggregator-virtual-interrupt-destinations">
15473 <span id="pub-soc-am65x-sr2-navss0-modss-inta0-vint-output-dst-list"></span><h2>navss0_modss_inta0 Interrupt Aggregator Virtual Interrupt Destinations<a class="headerlink" href="#navss0-modss-inta0-interrupt-aggregator-virtual-interrupt-destinations" title="Permalink to this headline">¶</a></h2>
15474 <div class="admonition warning">
15475 <p class="first admonition-title">Warning</p>
15476 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
15477 host within the RM Board Configuration resource assignment array.  The RM
15478 Board Configuration is rejected if an overlap with a reserved resource is
15479 detected.</p>
15480 </div>
15481 <table border="1" class="docutils">
15482 <colgroup>
15483 <col width="20%" />
15484 <col width="12%" />
15485 <col width="12%" />
15486 <col width="22%" />
15487 <col width="18%" />
15488 <col width="15%" />
15489 </colgroup>
15490 <thead valign="bottom">
15491 <tr class="row-odd"><th class="head">IA Name</th>
15492 <th class="head">IA Device ID</th>
15493 <th class="head">IA VINT Index</th>
15494 <th class="head">Destination Name</th>
15495 <th class="head">Destination Interface</th>
15496 <th class="head">Destination Index</th>
15497 </tr>
15498 </thead>
15499 <tbody valign="top">
15500 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15501 <td>180</td>
15502 <td>0</td>
15503 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15504 <td>in_intr</td>
15505 <td>320</td>
15506 </tr>
15507 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15508 <td>180</td>
15509 <td>1</td>
15510 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15511 <td>in_intr</td>
15512 <td>321</td>
15513 </tr>
15514 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15515 <td>180</td>
15516 <td>2</td>
15517 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15518 <td>in_intr</td>
15519 <td>322</td>
15520 </tr>
15521 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15522 <td>180</td>
15523 <td>3</td>
15524 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15525 <td>in_intr</td>
15526 <td>323</td>
15527 </tr>
15528 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15529 <td>180</td>
15530 <td>4</td>
15531 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15532 <td>in_intr</td>
15533 <td>324</td>
15534 </tr>
15535 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15536 <td>180</td>
15537 <td>5</td>
15538 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15539 <td>in_intr</td>
15540 <td>325</td>
15541 </tr>
15542 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15543 <td>180</td>
15544 <td>6</td>
15545 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15546 <td>in_intr</td>
15547 <td>326</td>
15548 </tr>
15549 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15550 <td>180</td>
15551 <td>7</td>
15552 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15553 <td>in_intr</td>
15554 <td>327</td>
15555 </tr>
15556 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15557 <td>180</td>
15558 <td>8</td>
15559 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15560 <td>in_intr</td>
15561 <td>328</td>
15562 </tr>
15563 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15564 <td>180</td>
15565 <td>9</td>
15566 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15567 <td>in_intr</td>
15568 <td>329</td>
15569 </tr>
15570 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15571 <td>180</td>
15572 <td>10</td>
15573 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15574 <td>in_intr</td>
15575 <td>330</td>
15576 </tr>
15577 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15578 <td>180</td>
15579 <td>11</td>
15580 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15581 <td>in_intr</td>
15582 <td>331</td>
15583 </tr>
15584 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15585 <td>180</td>
15586 <td>12</td>
15587 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15588 <td>in_intr</td>
15589 <td>332</td>
15590 </tr>
15591 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15592 <td>180</td>
15593 <td>13</td>
15594 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15595 <td>in_intr</td>
15596 <td>333</td>
15597 </tr>
15598 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15599 <td>180</td>
15600 <td>14</td>
15601 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15602 <td>in_intr</td>
15603 <td>334</td>
15604 </tr>
15605 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15606 <td>180</td>
15607 <td>15</td>
15608 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15609 <td>in_intr</td>
15610 <td>335</td>
15611 </tr>
15612 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15613 <td>180</td>
15614 <td>16</td>
15615 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15616 <td>in_intr</td>
15617 <td>336</td>
15618 </tr>
15619 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15620 <td>180</td>
15621 <td>17</td>
15622 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15623 <td>in_intr</td>
15624 <td>337</td>
15625 </tr>
15626 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15627 <td>180</td>
15628 <td>18</td>
15629 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15630 <td>in_intr</td>
15631 <td>338</td>
15632 </tr>
15633 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15634 <td>180</td>
15635 <td>19</td>
15636 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15637 <td>in_intr</td>
15638 <td>339</td>
15639 </tr>
15640 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15641 <td>180</td>
15642 <td>20</td>
15643 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15644 <td>in_intr</td>
15645 <td>340</td>
15646 </tr>
15647 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15648 <td>180</td>
15649 <td>21</td>
15650 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15651 <td>in_intr</td>
15652 <td>341</td>
15653 </tr>
15654 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15655 <td>180</td>
15656 <td>22</td>
15657 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15658 <td>in_intr</td>
15659 <td>342</td>
15660 </tr>
15661 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15662 <td>180</td>
15663 <td>23</td>
15664 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15665 <td>in_intr</td>
15666 <td>343</td>
15667 </tr>
15668 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15669 <td>180</td>
15670 <td>24</td>
15671 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15672 <td>in_intr</td>
15673 <td>344</td>
15674 </tr>
15675 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15676 <td>180</td>
15677 <td>25</td>
15678 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15679 <td>in_intr</td>
15680 <td>345</td>
15681 </tr>
15682 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15683 <td>180</td>
15684 <td>26</td>
15685 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15686 <td>in_intr</td>
15687 <td>346</td>
15688 </tr>
15689 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15690 <td>180</td>
15691 <td>27</td>
15692 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15693 <td>in_intr</td>
15694 <td>347</td>
15695 </tr>
15696 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15697 <td>180</td>
15698 <td>28</td>
15699 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15700 <td>in_intr</td>
15701 <td>348</td>
15702 </tr>
15703 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15704 <td>180</td>
15705 <td>29</td>
15706 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15707 <td>in_intr</td>
15708 <td>349</td>
15709 </tr>
15710 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15711 <td>180</td>
15712 <td>30</td>
15713 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15714 <td>in_intr</td>
15715 <td>350</td>
15716 </tr>
15717 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15718 <td>180</td>
15719 <td>31</td>
15720 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15721 <td>in_intr</td>
15722 <td>351</td>
15723 </tr>
15724 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15725 <td>180</td>
15726 <td>32</td>
15727 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15728 <td>in_intr</td>
15729 <td>352</td>
15730 </tr>
15731 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15732 <td>180</td>
15733 <td>33</td>
15734 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15735 <td>in_intr</td>
15736 <td>353</td>
15737 </tr>
15738 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15739 <td>180</td>
15740 <td>34</td>
15741 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15742 <td>in_intr</td>
15743 <td>354</td>
15744 </tr>
15745 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15746 <td>180</td>
15747 <td>35</td>
15748 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15749 <td>in_intr</td>
15750 <td>355</td>
15751 </tr>
15752 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15753 <td>180</td>
15754 <td>36</td>
15755 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15756 <td>in_intr</td>
15757 <td>356</td>
15758 </tr>
15759 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15760 <td>180</td>
15761 <td>37</td>
15762 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15763 <td>in_intr</td>
15764 <td>357</td>
15765 </tr>
15766 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15767 <td>180</td>
15768 <td>38</td>
15769 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15770 <td>in_intr</td>
15771 <td>358</td>
15772 </tr>
15773 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15774 <td>180</td>
15775 <td>39</td>
15776 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15777 <td>in_intr</td>
15778 <td>359</td>
15779 </tr>
15780 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15781 <td>180</td>
15782 <td>40</td>
15783 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15784 <td>in_intr</td>
15785 <td>360</td>
15786 </tr>
15787 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15788 <td>180</td>
15789 <td>41</td>
15790 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15791 <td>in_intr</td>
15792 <td>361</td>
15793 </tr>
15794 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15795 <td>180</td>
15796 <td>42</td>
15797 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15798 <td>in_intr</td>
15799 <td>362</td>
15800 </tr>
15801 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15802 <td>180</td>
15803 <td>43</td>
15804 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15805 <td>in_intr</td>
15806 <td>363</td>
15807 </tr>
15808 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15809 <td>180</td>
15810 <td>44</td>
15811 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15812 <td>in_intr</td>
15813 <td>364</td>
15814 </tr>
15815 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15816 <td>180</td>
15817 <td>45</td>
15818 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15819 <td>in_intr</td>
15820 <td>365</td>
15821 </tr>
15822 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15823 <td>180</td>
15824 <td>46</td>
15825 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15826 <td>in_intr</td>
15827 <td>366</td>
15828 </tr>
15829 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15830 <td>180</td>
15831 <td>47</td>
15832 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15833 <td>in_intr</td>
15834 <td>367</td>
15835 </tr>
15836 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15837 <td>180</td>
15838 <td>48</td>
15839 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15840 <td>in_intr</td>
15841 <td>368</td>
15842 </tr>
15843 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15844 <td>180</td>
15845 <td>49</td>
15846 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15847 <td>in_intr</td>
15848 <td>369</td>
15849 </tr>
15850 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15851 <td>180</td>
15852 <td>50</td>
15853 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15854 <td>in_intr</td>
15855 <td>370</td>
15856 </tr>
15857 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15858 <td>180</td>
15859 <td>51</td>
15860 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15861 <td>in_intr</td>
15862 <td>371</td>
15863 </tr>
15864 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15865 <td>180</td>
15866 <td>52</td>
15867 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15868 <td>in_intr</td>
15869 <td>372</td>
15870 </tr>
15871 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15872 <td>180</td>
15873 <td>53</td>
15874 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15875 <td>in_intr</td>
15876 <td>373</td>
15877 </tr>
15878 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15879 <td>180</td>
15880 <td>54</td>
15881 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15882 <td>in_intr</td>
15883 <td>374</td>
15884 </tr>
15885 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15886 <td>180</td>
15887 <td>55</td>
15888 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15889 <td>in_intr</td>
15890 <td>375</td>
15891 </tr>
15892 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15893 <td>180</td>
15894 <td>56</td>
15895 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15896 <td>in_intr</td>
15897 <td>376</td>
15898 </tr>
15899 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15900 <td>180</td>
15901 <td>57</td>
15902 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15903 <td>in_intr</td>
15904 <td>377</td>
15905 </tr>
15906 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15907 <td>180</td>
15908 <td>58</td>
15909 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15910 <td>in_intr</td>
15911 <td>378</td>
15912 </tr>
15913 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15914 <td>180</td>
15915 <td>59</td>
15916 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15917 <td>in_intr</td>
15918 <td>379</td>
15919 </tr>
15920 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15921 <td>180</td>
15922 <td>60</td>
15923 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15924 <td>in_intr</td>
15925 <td>380</td>
15926 </tr>
15927 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15928 <td>180</td>
15929 <td>61</td>
15930 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15931 <td>in_intr</td>
15932 <td>381</td>
15933 </tr>
15934 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15935 <td>180</td>
15936 <td>62</td>
15937 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15938 <td>in_intr</td>
15939 <td>382</td>
15940 </tr>
15941 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
15942 <td>180</td>
15943 <td>63</td>
15944 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15945 <td>in_intr</td>
15946 <td>383</td>
15947 </tr>
15948 </tbody>
15949 </table>
15950 </div>
15951 <div class="section" id="navss0-modss-inta1-interrupt-aggregator-virtual-interrupt-destinations">
15952 <span id="pub-soc-am65x-sr2-navss0-modss-inta1-vint-output-dst-list"></span><h2>navss0_modss_inta1 Interrupt Aggregator Virtual Interrupt Destinations<a class="headerlink" href="#navss0-modss-inta1-interrupt-aggregator-virtual-interrupt-destinations" title="Permalink to this headline">¶</a></h2>
15953 <div class="admonition warning">
15954 <p class="first admonition-title">Warning</p>
15955 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
15956 host within the RM Board Configuration resource assignment array.  The RM
15957 Board Configuration is rejected if an overlap with a reserved resource is
15958 detected.</p>
15959 </div>
15960 <table border="1" class="docutils">
15961 <colgroup>
15962 <col width="20%" />
15963 <col width="12%" />
15964 <col width="12%" />
15965 <col width="22%" />
15966 <col width="18%" />
15967 <col width="15%" />
15968 </colgroup>
15969 <thead valign="bottom">
15970 <tr class="row-odd"><th class="head">IA Name</th>
15971 <th class="head">IA Device ID</th>
15972 <th class="head">IA VINT Index</th>
15973 <th class="head">Destination Name</th>
15974 <th class="head">Destination Interface</th>
15975 <th class="head">Destination Index</th>
15976 </tr>
15977 </thead>
15978 <tbody valign="top">
15979 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
15980 <td>181</td>
15981 <td>0</td>
15982 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15983 <td>in_intr</td>
15984 <td>256</td>
15985 </tr>
15986 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
15987 <td>181</td>
15988 <td>1</td>
15989 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15990 <td>in_intr</td>
15991 <td>257</td>
15992 </tr>
15993 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
15994 <td>181</td>
15995 <td>2</td>
15996 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
15997 <td>in_intr</td>
15998 <td>258</td>
15999 </tr>
16000 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16001 <td>181</td>
16002 <td>3</td>
16003 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16004 <td>in_intr</td>
16005 <td>259</td>
16006 </tr>
16007 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16008 <td>181</td>
16009 <td>4</td>
16010 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16011 <td>in_intr</td>
16012 <td>260</td>
16013 </tr>
16014 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16015 <td>181</td>
16016 <td>5</td>
16017 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16018 <td>in_intr</td>
16019 <td>261</td>
16020 </tr>
16021 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16022 <td>181</td>
16023 <td>6</td>
16024 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16025 <td>in_intr</td>
16026 <td>262</td>
16027 </tr>
16028 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16029 <td>181</td>
16030 <td>7</td>
16031 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16032 <td>in_intr</td>
16033 <td>263</td>
16034 </tr>
16035 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16036 <td>181</td>
16037 <td>8</td>
16038 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16039 <td>in_intr</td>
16040 <td>264</td>
16041 </tr>
16042 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16043 <td>181</td>
16044 <td>9</td>
16045 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16046 <td>in_intr</td>
16047 <td>265</td>
16048 </tr>
16049 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16050 <td>181</td>
16051 <td>10</td>
16052 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16053 <td>in_intr</td>
16054 <td>266</td>
16055 </tr>
16056 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16057 <td>181</td>
16058 <td>11</td>
16059 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16060 <td>in_intr</td>
16061 <td>267</td>
16062 </tr>
16063 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16064 <td>181</td>
16065 <td>12</td>
16066 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16067 <td>in_intr</td>
16068 <td>268</td>
16069 </tr>
16070 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16071 <td>181</td>
16072 <td>13</td>
16073 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16074 <td>in_intr</td>
16075 <td>269</td>
16076 </tr>
16077 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16078 <td>181</td>
16079 <td>14</td>
16080 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16081 <td>in_intr</td>
16082 <td>270</td>
16083 </tr>
16084 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16085 <td>181</td>
16086 <td>15</td>
16087 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16088 <td>in_intr</td>
16089 <td>271</td>
16090 </tr>
16091 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16092 <td>181</td>
16093 <td>16</td>
16094 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16095 <td>in_intr</td>
16096 <td>272</td>
16097 </tr>
16098 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16099 <td>181</td>
16100 <td>17</td>
16101 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16102 <td>in_intr</td>
16103 <td>273</td>
16104 </tr>
16105 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16106 <td>181</td>
16107 <td>18</td>
16108 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16109 <td>in_intr</td>
16110 <td>274</td>
16111 </tr>
16112 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16113 <td>181</td>
16114 <td>19</td>
16115 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16116 <td>in_intr</td>
16117 <td>275</td>
16118 </tr>
16119 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16120 <td>181</td>
16121 <td>20</td>
16122 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16123 <td>in_intr</td>
16124 <td>276</td>
16125 </tr>
16126 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16127 <td>181</td>
16128 <td>21</td>
16129 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16130 <td>in_intr</td>
16131 <td>277</td>
16132 </tr>
16133 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16134 <td>181</td>
16135 <td>22</td>
16136 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16137 <td>in_intr</td>
16138 <td>278</td>
16139 </tr>
16140 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16141 <td>181</td>
16142 <td>23</td>
16143 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16144 <td>in_intr</td>
16145 <td>279</td>
16146 </tr>
16147 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16148 <td>181</td>
16149 <td>24</td>
16150 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16151 <td>in_intr</td>
16152 <td>280</td>
16153 </tr>
16154 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16155 <td>181</td>
16156 <td>25</td>
16157 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16158 <td>in_intr</td>
16159 <td>281</td>
16160 </tr>
16161 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16162 <td>181</td>
16163 <td>26</td>
16164 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16165 <td>in_intr</td>
16166 <td>282</td>
16167 </tr>
16168 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16169 <td>181</td>
16170 <td>27</td>
16171 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16172 <td>in_intr</td>
16173 <td>283</td>
16174 </tr>
16175 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16176 <td>181</td>
16177 <td>28</td>
16178 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16179 <td>in_intr</td>
16180 <td>284</td>
16181 </tr>
16182 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16183 <td>181</td>
16184 <td>29</td>
16185 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16186 <td>in_intr</td>
16187 <td>285</td>
16188 </tr>
16189 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16190 <td>181</td>
16191 <td>30</td>
16192 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16193 <td>in_intr</td>
16194 <td>286</td>
16195 </tr>
16196 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16197 <td>181</td>
16198 <td>31</td>
16199 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16200 <td>in_intr</td>
16201 <td>287</td>
16202 </tr>
16203 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16204 <td>181</td>
16205 <td>32</td>
16206 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16207 <td>in_intr</td>
16208 <td>288</td>
16209 </tr>
16210 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16211 <td>181</td>
16212 <td>33</td>
16213 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16214 <td>in_intr</td>
16215 <td>289</td>
16216 </tr>
16217 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16218 <td>181</td>
16219 <td>34</td>
16220 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16221 <td>in_intr</td>
16222 <td>290</td>
16223 </tr>
16224 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16225 <td>181</td>
16226 <td>35</td>
16227 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16228 <td>in_intr</td>
16229 <td>291</td>
16230 </tr>
16231 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16232 <td>181</td>
16233 <td>36</td>
16234 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16235 <td>in_intr</td>
16236 <td>292</td>
16237 </tr>
16238 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16239 <td>181</td>
16240 <td>37</td>
16241 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16242 <td>in_intr</td>
16243 <td>293</td>
16244 </tr>
16245 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16246 <td>181</td>
16247 <td>38</td>
16248 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16249 <td>in_intr</td>
16250 <td>294</td>
16251 </tr>
16252 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16253 <td>181</td>
16254 <td>39</td>
16255 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16256 <td>in_intr</td>
16257 <td>295</td>
16258 </tr>
16259 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16260 <td>181</td>
16261 <td>40</td>
16262 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16263 <td>in_intr</td>
16264 <td>296</td>
16265 </tr>
16266 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16267 <td>181</td>
16268 <td>41</td>
16269 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16270 <td>in_intr</td>
16271 <td>297</td>
16272 </tr>
16273 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16274 <td>181</td>
16275 <td>42</td>
16276 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16277 <td>in_intr</td>
16278 <td>298</td>
16279 </tr>
16280 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16281 <td>181</td>
16282 <td>43</td>
16283 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16284 <td>in_intr</td>
16285 <td>299</td>
16286 </tr>
16287 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16288 <td>181</td>
16289 <td>44</td>
16290 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16291 <td>in_intr</td>
16292 <td>300</td>
16293 </tr>
16294 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16295 <td>181</td>
16296 <td>45</td>
16297 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16298 <td>in_intr</td>
16299 <td>301</td>
16300 </tr>
16301 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16302 <td>181</td>
16303 <td>46</td>
16304 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16305 <td>in_intr</td>
16306 <td>302</td>
16307 </tr>
16308 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16309 <td>181</td>
16310 <td>47</td>
16311 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16312 <td>in_intr</td>
16313 <td>303</td>
16314 </tr>
16315 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16316 <td>181</td>
16317 <td>48</td>
16318 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16319 <td>in_intr</td>
16320 <td>304</td>
16321 </tr>
16322 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16323 <td>181</td>
16324 <td>49</td>
16325 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16326 <td>in_intr</td>
16327 <td>305</td>
16328 </tr>
16329 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16330 <td>181</td>
16331 <td>50</td>
16332 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16333 <td>in_intr</td>
16334 <td>306</td>
16335 </tr>
16336 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16337 <td>181</td>
16338 <td>51</td>
16339 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16340 <td>in_intr</td>
16341 <td>307</td>
16342 </tr>
16343 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16344 <td>181</td>
16345 <td>52</td>
16346 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16347 <td>in_intr</td>
16348 <td>308</td>
16349 </tr>
16350 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16351 <td>181</td>
16352 <td>53</td>
16353 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16354 <td>in_intr</td>
16355 <td>309</td>
16356 </tr>
16357 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16358 <td>181</td>
16359 <td>54</td>
16360 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16361 <td>in_intr</td>
16362 <td>310</td>
16363 </tr>
16364 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16365 <td>181</td>
16366 <td>55</td>
16367 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16368 <td>in_intr</td>
16369 <td>311</td>
16370 </tr>
16371 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16372 <td>181</td>
16373 <td>56</td>
16374 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16375 <td>in_intr</td>
16376 <td>312</td>
16377 </tr>
16378 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16379 <td>181</td>
16380 <td>57</td>
16381 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16382 <td>in_intr</td>
16383 <td>313</td>
16384 </tr>
16385 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16386 <td>181</td>
16387 <td>58</td>
16388 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16389 <td>in_intr</td>
16390 <td>314</td>
16391 </tr>
16392 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16393 <td>181</td>
16394 <td>59</td>
16395 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16396 <td>in_intr</td>
16397 <td>315</td>
16398 </tr>
16399 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16400 <td>181</td>
16401 <td>60</td>
16402 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16403 <td>in_intr</td>
16404 <td>316</td>
16405 </tr>
16406 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16407 <td>181</td>
16408 <td>61</td>
16409 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16410 <td>in_intr</td>
16411 <td>317</td>
16412 </tr>
16413 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16414 <td>181</td>
16415 <td>62</td>
16416 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16417 <td>in_intr</td>
16418 <td>318</td>
16419 </tr>
16420 <tr class="row-odd"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
16421 <td>181</td>
16422 <td>63</td>
16423 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16424 <td>in_intr</td>
16425 <td>319</td>
16426 </tr>
16427 </tbody>
16428 </table>
16429 </div>
16430 <div class="section" id="navss0-udmass-inta0-interrupt-aggregator-virtual-interrupt-destinations">
16431 <span id="pub-soc-am65x-sr2-navss0-udmass-inta0-vint-output-dst-list"></span><h2>navss0_udmass_inta0 Interrupt Aggregator Virtual Interrupt Destinations<a class="headerlink" href="#navss0-udmass-inta0-interrupt-aggregator-virtual-interrupt-destinations" title="Permalink to this headline">¶</a></h2>
16432 <div class="admonition warning">
16433 <p class="first admonition-title">Warning</p>
16434 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
16435 host within the RM Board Configuration resource assignment array.  The RM
16436 Board Configuration is rejected if an overlap with a reserved resource is
16437 detected.</p>
16438 </div>
16439 <table border="1" class="docutils">
16440 <colgroup>
16441 <col width="24%" />
16442 <col width="11%" />
16443 <col width="12%" />
16444 <col width="21%" />
16445 <col width="17%" />
16446 <col width="15%" />
16447 </colgroup>
16448 <thead valign="bottom">
16449 <tr class="row-odd"><th class="head">IA Name</th>
16450 <th class="head">IA Device ID</th>
16451 <th class="head">IA VINT Index</th>
16452 <th class="head">Destination Name</th>
16453 <th class="head">Destination Interface</th>
16454 <th class="head">Destination Index</th>
16455 </tr>
16456 </thead>
16457 <tbody valign="top">
16458 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16459 (<strong>Reserved by System Firmware</strong>)</td>
16460 <td>179</td>
16461 <td>0</td>
16462 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16463 <td>in_intr</td>
16464 <td>0</td>
16465 </tr>
16466 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16467 (<strong>Reserved by System Firmware</strong>)</td>
16468 <td>179</td>
16469 <td>1</td>
16470 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16471 <td>in_intr</td>
16472 <td>1</td>
16473 </tr>
16474 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16475 (<strong>Reserved by System Firmware</strong>)</td>
16476 <td>179</td>
16477 <td>2</td>
16478 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16479 <td>in_intr</td>
16480 <td>2</td>
16481 </tr>
16482 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16483 (<strong>Reserved by System Firmware</strong>)</td>
16484 <td>179</td>
16485 <td>3</td>
16486 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16487 <td>in_intr</td>
16488 <td>3</td>
16489 </tr>
16490 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16491 (<strong>Reserved by System Firmware</strong>)</td>
16492 <td>179</td>
16493 <td>4</td>
16494 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16495 <td>in_intr</td>
16496 <td>4</td>
16497 </tr>
16498 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16499 (<strong>Reserved by System Firmware</strong>)</td>
16500 <td>179</td>
16501 <td>5</td>
16502 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16503 <td>in_intr</td>
16504 <td>5</td>
16505 </tr>
16506 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16507 (<strong>Reserved by System Firmware</strong>)</td>
16508 <td>179</td>
16509 <td>6</td>
16510 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16511 <td>in_intr</td>
16512 <td>6</td>
16513 </tr>
16514 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16515 (<strong>Reserved by System Firmware</strong>)</td>
16516 <td>179</td>
16517 <td>7</td>
16518 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16519 <td>in_intr</td>
16520 <td>7</td>
16521 </tr>
16522 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16523 (<strong>Reserved by System Firmware</strong>)</td>
16524 <td>179</td>
16525 <td>8</td>
16526 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16527 <td>in_intr</td>
16528 <td>8</td>
16529 </tr>
16530 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16531 (<strong>Reserved by System Firmware</strong>)</td>
16532 <td>179</td>
16533 <td>9</td>
16534 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16535 <td>in_intr</td>
16536 <td>9</td>
16537 </tr>
16538 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16539 (<strong>Reserved by System Firmware</strong>)</td>
16540 <td>179</td>
16541 <td>10</td>
16542 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16543 <td>in_intr</td>
16544 <td>10</td>
16545 </tr>
16546 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16547 (<strong>Reserved by System Firmware</strong>)</td>
16548 <td>179</td>
16549 <td>11</td>
16550 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16551 <td>in_intr</td>
16552 <td>11</td>
16553 </tr>
16554 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16555 (<strong>Reserved by System Firmware</strong>)</td>
16556 <td>179</td>
16557 <td>12</td>
16558 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16559 <td>in_intr</td>
16560 <td>12</td>
16561 </tr>
16562 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16563 (<strong>Reserved by System Firmware</strong>)</td>
16564 <td>179</td>
16565 <td>13</td>
16566 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16567 <td>in_intr</td>
16568 <td>13</td>
16569 </tr>
16570 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16571 (<strong>Reserved by System Firmware</strong>)</td>
16572 <td>179</td>
16573 <td>14</td>
16574 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16575 <td>in_intr</td>
16576 <td>14</td>
16577 </tr>
16578 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0
16579 (<strong>Reserved by System Firmware</strong>)</td>
16580 <td>179</td>
16581 <td>15</td>
16582 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16583 <td>in_intr</td>
16584 <td>15</td>
16585 </tr>
16586 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16587 <td>179</td>
16588 <td>16</td>
16589 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16590 <td>in_intr</td>
16591 <td>16</td>
16592 </tr>
16593 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16594 <td>179</td>
16595 <td>17</td>
16596 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16597 <td>in_intr</td>
16598 <td>17</td>
16599 </tr>
16600 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16601 <td>179</td>
16602 <td>18</td>
16603 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16604 <td>in_intr</td>
16605 <td>18</td>
16606 </tr>
16607 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16608 <td>179</td>
16609 <td>19</td>
16610 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16611 <td>in_intr</td>
16612 <td>19</td>
16613 </tr>
16614 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16615 <td>179</td>
16616 <td>20</td>
16617 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16618 <td>in_intr</td>
16619 <td>20</td>
16620 </tr>
16621 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16622 <td>179</td>
16623 <td>21</td>
16624 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16625 <td>in_intr</td>
16626 <td>21</td>
16627 </tr>
16628 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16629 <td>179</td>
16630 <td>22</td>
16631 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16632 <td>in_intr</td>
16633 <td>22</td>
16634 </tr>
16635 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16636 <td>179</td>
16637 <td>23</td>
16638 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16639 <td>in_intr</td>
16640 <td>23</td>
16641 </tr>
16642 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16643 <td>179</td>
16644 <td>24</td>
16645 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16646 <td>in_intr</td>
16647 <td>24</td>
16648 </tr>
16649 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16650 <td>179</td>
16651 <td>25</td>
16652 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16653 <td>in_intr</td>
16654 <td>25</td>
16655 </tr>
16656 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16657 <td>179</td>
16658 <td>26</td>
16659 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16660 <td>in_intr</td>
16661 <td>26</td>
16662 </tr>
16663 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16664 <td>179</td>
16665 <td>27</td>
16666 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16667 <td>in_intr</td>
16668 <td>27</td>
16669 </tr>
16670 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16671 <td>179</td>
16672 <td>28</td>
16673 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16674 <td>in_intr</td>
16675 <td>28</td>
16676 </tr>
16677 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16678 <td>179</td>
16679 <td>29</td>
16680 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16681 <td>in_intr</td>
16682 <td>29</td>
16683 </tr>
16684 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16685 <td>179</td>
16686 <td>30</td>
16687 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16688 <td>in_intr</td>
16689 <td>30</td>
16690 </tr>
16691 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16692 <td>179</td>
16693 <td>31</td>
16694 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16695 <td>in_intr</td>
16696 <td>31</td>
16697 </tr>
16698 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16699 <td>179</td>
16700 <td>32</td>
16701 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16702 <td>in_intr</td>
16703 <td>32</td>
16704 </tr>
16705 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16706 <td>179</td>
16707 <td>33</td>
16708 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16709 <td>in_intr</td>
16710 <td>33</td>
16711 </tr>
16712 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16713 <td>179</td>
16714 <td>34</td>
16715 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16716 <td>in_intr</td>
16717 <td>34</td>
16718 </tr>
16719 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16720 <td>179</td>
16721 <td>35</td>
16722 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16723 <td>in_intr</td>
16724 <td>35</td>
16725 </tr>
16726 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16727 <td>179</td>
16728 <td>36</td>
16729 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16730 <td>in_intr</td>
16731 <td>36</td>
16732 </tr>
16733 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16734 <td>179</td>
16735 <td>37</td>
16736 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16737 <td>in_intr</td>
16738 <td>37</td>
16739 </tr>
16740 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16741 <td>179</td>
16742 <td>38</td>
16743 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16744 <td>in_intr</td>
16745 <td>38</td>
16746 </tr>
16747 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16748 <td>179</td>
16749 <td>39</td>
16750 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16751 <td>in_intr</td>
16752 <td>39</td>
16753 </tr>
16754 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16755 <td>179</td>
16756 <td>40</td>
16757 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16758 <td>in_intr</td>
16759 <td>40</td>
16760 </tr>
16761 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16762 <td>179</td>
16763 <td>41</td>
16764 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16765 <td>in_intr</td>
16766 <td>41</td>
16767 </tr>
16768 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16769 <td>179</td>
16770 <td>42</td>
16771 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16772 <td>in_intr</td>
16773 <td>42</td>
16774 </tr>
16775 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16776 <td>179</td>
16777 <td>43</td>
16778 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16779 <td>in_intr</td>
16780 <td>43</td>
16781 </tr>
16782 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16783 <td>179</td>
16784 <td>44</td>
16785 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16786 <td>in_intr</td>
16787 <td>44</td>
16788 </tr>
16789 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16790 <td>179</td>
16791 <td>45</td>
16792 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16793 <td>in_intr</td>
16794 <td>45</td>
16795 </tr>
16796 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16797 <td>179</td>
16798 <td>46</td>
16799 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16800 <td>in_intr</td>
16801 <td>46</td>
16802 </tr>
16803 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16804 <td>179</td>
16805 <td>47</td>
16806 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16807 <td>in_intr</td>
16808 <td>47</td>
16809 </tr>
16810 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16811 <td>179</td>
16812 <td>48</td>
16813 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16814 <td>in_intr</td>
16815 <td>48</td>
16816 </tr>
16817 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16818 <td>179</td>
16819 <td>49</td>
16820 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16821 <td>in_intr</td>
16822 <td>49</td>
16823 </tr>
16824 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16825 <td>179</td>
16826 <td>50</td>
16827 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16828 <td>in_intr</td>
16829 <td>50</td>
16830 </tr>
16831 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16832 <td>179</td>
16833 <td>51</td>
16834 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16835 <td>in_intr</td>
16836 <td>51</td>
16837 </tr>
16838 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16839 <td>179</td>
16840 <td>52</td>
16841 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16842 <td>in_intr</td>
16843 <td>52</td>
16844 </tr>
16845 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16846 <td>179</td>
16847 <td>53</td>
16848 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16849 <td>in_intr</td>
16850 <td>53</td>
16851 </tr>
16852 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16853 <td>179</td>
16854 <td>54</td>
16855 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16856 <td>in_intr</td>
16857 <td>54</td>
16858 </tr>
16859 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16860 <td>179</td>
16861 <td>55</td>
16862 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16863 <td>in_intr</td>
16864 <td>55</td>
16865 </tr>
16866 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16867 <td>179</td>
16868 <td>56</td>
16869 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16870 <td>in_intr</td>
16871 <td>56</td>
16872 </tr>
16873 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16874 <td>179</td>
16875 <td>57</td>
16876 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16877 <td>in_intr</td>
16878 <td>57</td>
16879 </tr>
16880 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16881 <td>179</td>
16882 <td>58</td>
16883 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16884 <td>in_intr</td>
16885 <td>58</td>
16886 </tr>
16887 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16888 <td>179</td>
16889 <td>59</td>
16890 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16891 <td>in_intr</td>
16892 <td>59</td>
16893 </tr>
16894 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16895 <td>179</td>
16896 <td>60</td>
16897 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16898 <td>in_intr</td>
16899 <td>60</td>
16900 </tr>
16901 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16902 <td>179</td>
16903 <td>61</td>
16904 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16905 <td>in_intr</td>
16906 <td>61</td>
16907 </tr>
16908 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16909 <td>179</td>
16910 <td>62</td>
16911 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16912 <td>in_intr</td>
16913 <td>62</td>
16914 </tr>
16915 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16916 <td>179</td>
16917 <td>63</td>
16918 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16919 <td>in_intr</td>
16920 <td>63</td>
16921 </tr>
16922 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16923 <td>179</td>
16924 <td>64</td>
16925 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16926 <td>in_intr</td>
16927 <td>64</td>
16928 </tr>
16929 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16930 <td>179</td>
16931 <td>65</td>
16932 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16933 <td>in_intr</td>
16934 <td>65</td>
16935 </tr>
16936 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16937 <td>179</td>
16938 <td>66</td>
16939 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16940 <td>in_intr</td>
16941 <td>66</td>
16942 </tr>
16943 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16944 <td>179</td>
16945 <td>67</td>
16946 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16947 <td>in_intr</td>
16948 <td>67</td>
16949 </tr>
16950 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16951 <td>179</td>
16952 <td>68</td>
16953 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16954 <td>in_intr</td>
16955 <td>68</td>
16956 </tr>
16957 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16958 <td>179</td>
16959 <td>69</td>
16960 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16961 <td>in_intr</td>
16962 <td>69</td>
16963 </tr>
16964 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16965 <td>179</td>
16966 <td>70</td>
16967 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16968 <td>in_intr</td>
16969 <td>70</td>
16970 </tr>
16971 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16972 <td>179</td>
16973 <td>71</td>
16974 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16975 <td>in_intr</td>
16976 <td>71</td>
16977 </tr>
16978 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16979 <td>179</td>
16980 <td>72</td>
16981 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16982 <td>in_intr</td>
16983 <td>72</td>
16984 </tr>
16985 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16986 <td>179</td>
16987 <td>73</td>
16988 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16989 <td>in_intr</td>
16990 <td>73</td>
16991 </tr>
16992 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
16993 <td>179</td>
16994 <td>74</td>
16995 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
16996 <td>in_intr</td>
16997 <td>74</td>
16998 </tr>
16999 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17000 <td>179</td>
17001 <td>75</td>
17002 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17003 <td>in_intr</td>
17004 <td>75</td>
17005 </tr>
17006 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17007 <td>179</td>
17008 <td>76</td>
17009 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17010 <td>in_intr</td>
17011 <td>76</td>
17012 </tr>
17013 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17014 <td>179</td>
17015 <td>77</td>
17016 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17017 <td>in_intr</td>
17018 <td>77</td>
17019 </tr>
17020 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17021 <td>179</td>
17022 <td>78</td>
17023 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17024 <td>in_intr</td>
17025 <td>78</td>
17026 </tr>
17027 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17028 <td>179</td>
17029 <td>79</td>
17030 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17031 <td>in_intr</td>
17032 <td>79</td>
17033 </tr>
17034 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17035 <td>179</td>
17036 <td>80</td>
17037 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17038 <td>in_intr</td>
17039 <td>80</td>
17040 </tr>
17041 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17042 <td>179</td>
17043 <td>81</td>
17044 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17045 <td>in_intr</td>
17046 <td>81</td>
17047 </tr>
17048 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17049 <td>179</td>
17050 <td>82</td>
17051 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17052 <td>in_intr</td>
17053 <td>82</td>
17054 </tr>
17055 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17056 <td>179</td>
17057 <td>83</td>
17058 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17059 <td>in_intr</td>
17060 <td>83</td>
17061 </tr>
17062 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17063 <td>179</td>
17064 <td>84</td>
17065 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17066 <td>in_intr</td>
17067 <td>84</td>
17068 </tr>
17069 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17070 <td>179</td>
17071 <td>85</td>
17072 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17073 <td>in_intr</td>
17074 <td>85</td>
17075 </tr>
17076 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17077 <td>179</td>
17078 <td>86</td>
17079 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17080 <td>in_intr</td>
17081 <td>86</td>
17082 </tr>
17083 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17084 <td>179</td>
17085 <td>87</td>
17086 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17087 <td>in_intr</td>
17088 <td>87</td>
17089 </tr>
17090 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17091 <td>179</td>
17092 <td>88</td>
17093 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17094 <td>in_intr</td>
17095 <td>88</td>
17096 </tr>
17097 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17098 <td>179</td>
17099 <td>89</td>
17100 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17101 <td>in_intr</td>
17102 <td>89</td>
17103 </tr>
17104 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17105 <td>179</td>
17106 <td>90</td>
17107 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17108 <td>in_intr</td>
17109 <td>90</td>
17110 </tr>
17111 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17112 <td>179</td>
17113 <td>91</td>
17114 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17115 <td>in_intr</td>
17116 <td>91</td>
17117 </tr>
17118 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17119 <td>179</td>
17120 <td>92</td>
17121 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17122 <td>in_intr</td>
17123 <td>92</td>
17124 </tr>
17125 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17126 <td>179</td>
17127 <td>93</td>
17128 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17129 <td>in_intr</td>
17130 <td>93</td>
17131 </tr>
17132 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17133 <td>179</td>
17134 <td>94</td>
17135 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17136 <td>in_intr</td>
17137 <td>94</td>
17138 </tr>
17139 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17140 <td>179</td>
17141 <td>95</td>
17142 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17143 <td>in_intr</td>
17144 <td>95</td>
17145 </tr>
17146 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17147 <td>179</td>
17148 <td>96</td>
17149 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17150 <td>in_intr</td>
17151 <td>96</td>
17152 </tr>
17153 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17154 <td>179</td>
17155 <td>97</td>
17156 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17157 <td>in_intr</td>
17158 <td>97</td>
17159 </tr>
17160 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17161 <td>179</td>
17162 <td>98</td>
17163 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17164 <td>in_intr</td>
17165 <td>98</td>
17166 </tr>
17167 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17168 <td>179</td>
17169 <td>99</td>
17170 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17171 <td>in_intr</td>
17172 <td>99</td>
17173 </tr>
17174 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17175 <td>179</td>
17176 <td>100</td>
17177 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17178 <td>in_intr</td>
17179 <td>100</td>
17180 </tr>
17181 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17182 <td>179</td>
17183 <td>101</td>
17184 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17185 <td>in_intr</td>
17186 <td>101</td>
17187 </tr>
17188 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17189 <td>179</td>
17190 <td>102</td>
17191 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17192 <td>in_intr</td>
17193 <td>102</td>
17194 </tr>
17195 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17196 <td>179</td>
17197 <td>103</td>
17198 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17199 <td>in_intr</td>
17200 <td>103</td>
17201 </tr>
17202 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17203 <td>179</td>
17204 <td>104</td>
17205 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17206 <td>in_intr</td>
17207 <td>104</td>
17208 </tr>
17209 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17210 <td>179</td>
17211 <td>105</td>
17212 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17213 <td>in_intr</td>
17214 <td>105</td>
17215 </tr>
17216 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17217 <td>179</td>
17218 <td>106</td>
17219 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17220 <td>in_intr</td>
17221 <td>106</td>
17222 </tr>
17223 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17224 <td>179</td>
17225 <td>107</td>
17226 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17227 <td>in_intr</td>
17228 <td>107</td>
17229 </tr>
17230 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17231 <td>179</td>
17232 <td>108</td>
17233 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17234 <td>in_intr</td>
17235 <td>108</td>
17236 </tr>
17237 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17238 <td>179</td>
17239 <td>109</td>
17240 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17241 <td>in_intr</td>
17242 <td>109</td>
17243 </tr>
17244 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17245 <td>179</td>
17246 <td>110</td>
17247 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17248 <td>in_intr</td>
17249 <td>110</td>
17250 </tr>
17251 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17252 <td>179</td>
17253 <td>111</td>
17254 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17255 <td>in_intr</td>
17256 <td>111</td>
17257 </tr>
17258 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17259 <td>179</td>
17260 <td>112</td>
17261 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17262 <td>in_intr</td>
17263 <td>112</td>
17264 </tr>
17265 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17266 <td>179</td>
17267 <td>113</td>
17268 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17269 <td>in_intr</td>
17270 <td>113</td>
17271 </tr>
17272 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17273 <td>179</td>
17274 <td>114</td>
17275 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17276 <td>in_intr</td>
17277 <td>114</td>
17278 </tr>
17279 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17280 <td>179</td>
17281 <td>115</td>
17282 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17283 <td>in_intr</td>
17284 <td>115</td>
17285 </tr>
17286 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17287 <td>179</td>
17288 <td>116</td>
17289 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17290 <td>in_intr</td>
17291 <td>116</td>
17292 </tr>
17293 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17294 <td>179</td>
17295 <td>117</td>
17296 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17297 <td>in_intr</td>
17298 <td>117</td>
17299 </tr>
17300 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17301 <td>179</td>
17302 <td>118</td>
17303 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17304 <td>in_intr</td>
17305 <td>118</td>
17306 </tr>
17307 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17308 <td>179</td>
17309 <td>119</td>
17310 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17311 <td>in_intr</td>
17312 <td>119</td>
17313 </tr>
17314 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17315 <td>179</td>
17316 <td>120</td>
17317 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17318 <td>in_intr</td>
17319 <td>120</td>
17320 </tr>
17321 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17322 <td>179</td>
17323 <td>121</td>
17324 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17325 <td>in_intr</td>
17326 <td>121</td>
17327 </tr>
17328 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17329 <td>179</td>
17330 <td>122</td>
17331 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17332 <td>in_intr</td>
17333 <td>122</td>
17334 </tr>
17335 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17336 <td>179</td>
17337 <td>123</td>
17338 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17339 <td>in_intr</td>
17340 <td>123</td>
17341 </tr>
17342 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17343 <td>179</td>
17344 <td>124</td>
17345 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17346 <td>in_intr</td>
17347 <td>124</td>
17348 </tr>
17349 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17350 <td>179</td>
17351 <td>125</td>
17352 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17353 <td>in_intr</td>
17354 <td>125</td>
17355 </tr>
17356 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17357 <td>179</td>
17358 <td>126</td>
17359 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17360 <td>in_intr</td>
17361 <td>126</td>
17362 </tr>
17363 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17364 <td>179</td>
17365 <td>127</td>
17366 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17367 <td>in_intr</td>
17368 <td>127</td>
17369 </tr>
17370 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17371 <td>179</td>
17372 <td>128</td>
17373 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17374 <td>in_intr</td>
17375 <td>128</td>
17376 </tr>
17377 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17378 <td>179</td>
17379 <td>129</td>
17380 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17381 <td>in_intr</td>
17382 <td>129</td>
17383 </tr>
17384 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17385 <td>179</td>
17386 <td>130</td>
17387 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17388 <td>in_intr</td>
17389 <td>130</td>
17390 </tr>
17391 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17392 <td>179</td>
17393 <td>131</td>
17394 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17395 <td>in_intr</td>
17396 <td>131</td>
17397 </tr>
17398 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17399 <td>179</td>
17400 <td>132</td>
17401 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17402 <td>in_intr</td>
17403 <td>132</td>
17404 </tr>
17405 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17406 <td>179</td>
17407 <td>133</td>
17408 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17409 <td>in_intr</td>
17410 <td>133</td>
17411 </tr>
17412 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17413 <td>179</td>
17414 <td>134</td>
17415 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17416 <td>in_intr</td>
17417 <td>134</td>
17418 </tr>
17419 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17420 <td>179</td>
17421 <td>135</td>
17422 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17423 <td>in_intr</td>
17424 <td>135</td>
17425 </tr>
17426 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17427 <td>179</td>
17428 <td>136</td>
17429 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17430 <td>in_intr</td>
17431 <td>136</td>
17432 </tr>
17433 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17434 <td>179</td>
17435 <td>137</td>
17436 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17437 <td>in_intr</td>
17438 <td>137</td>
17439 </tr>
17440 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17441 <td>179</td>
17442 <td>138</td>
17443 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17444 <td>in_intr</td>
17445 <td>138</td>
17446 </tr>
17447 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17448 <td>179</td>
17449 <td>139</td>
17450 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17451 <td>in_intr</td>
17452 <td>139</td>
17453 </tr>
17454 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17455 <td>179</td>
17456 <td>140</td>
17457 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17458 <td>in_intr</td>
17459 <td>140</td>
17460 </tr>
17461 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17462 <td>179</td>
17463 <td>141</td>
17464 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17465 <td>in_intr</td>
17466 <td>141</td>
17467 </tr>
17468 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17469 <td>179</td>
17470 <td>142</td>
17471 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17472 <td>in_intr</td>
17473 <td>142</td>
17474 </tr>
17475 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17476 <td>179</td>
17477 <td>143</td>
17478 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17479 <td>in_intr</td>
17480 <td>143</td>
17481 </tr>
17482 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17483 <td>179</td>
17484 <td>144</td>
17485 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17486 <td>in_intr</td>
17487 <td>144</td>
17488 </tr>
17489 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17490 <td>179</td>
17491 <td>145</td>
17492 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17493 <td>in_intr</td>
17494 <td>145</td>
17495 </tr>
17496 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17497 <td>179</td>
17498 <td>146</td>
17499 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17500 <td>in_intr</td>
17501 <td>146</td>
17502 </tr>
17503 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17504 <td>179</td>
17505 <td>147</td>
17506 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17507 <td>in_intr</td>
17508 <td>147</td>
17509 </tr>
17510 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17511 <td>179</td>
17512 <td>148</td>
17513 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17514 <td>in_intr</td>
17515 <td>148</td>
17516 </tr>
17517 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17518 <td>179</td>
17519 <td>149</td>
17520 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17521 <td>in_intr</td>
17522 <td>149</td>
17523 </tr>
17524 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17525 <td>179</td>
17526 <td>150</td>
17527 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17528 <td>in_intr</td>
17529 <td>150</td>
17530 </tr>
17531 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17532 <td>179</td>
17533 <td>151</td>
17534 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17535 <td>in_intr</td>
17536 <td>151</td>
17537 </tr>
17538 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17539 <td>179</td>
17540 <td>152</td>
17541 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17542 <td>in_intr</td>
17543 <td>152</td>
17544 </tr>
17545 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17546 <td>179</td>
17547 <td>153</td>
17548 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17549 <td>in_intr</td>
17550 <td>153</td>
17551 </tr>
17552 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17553 <td>179</td>
17554 <td>154</td>
17555 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17556 <td>in_intr</td>
17557 <td>154</td>
17558 </tr>
17559 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17560 <td>179</td>
17561 <td>155</td>
17562 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17563 <td>in_intr</td>
17564 <td>155</td>
17565 </tr>
17566 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17567 <td>179</td>
17568 <td>156</td>
17569 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17570 <td>in_intr</td>
17571 <td>156</td>
17572 </tr>
17573 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17574 <td>179</td>
17575 <td>157</td>
17576 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17577 <td>in_intr</td>
17578 <td>157</td>
17579 </tr>
17580 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17581 <td>179</td>
17582 <td>158</td>
17583 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17584 <td>in_intr</td>
17585 <td>158</td>
17586 </tr>
17587 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17588 <td>179</td>
17589 <td>159</td>
17590 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17591 <td>in_intr</td>
17592 <td>159</td>
17593 </tr>
17594 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17595 <td>179</td>
17596 <td>160</td>
17597 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17598 <td>in_intr</td>
17599 <td>160</td>
17600 </tr>
17601 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17602 <td>179</td>
17603 <td>161</td>
17604 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17605 <td>in_intr</td>
17606 <td>161</td>
17607 </tr>
17608 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17609 <td>179</td>
17610 <td>162</td>
17611 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17612 <td>in_intr</td>
17613 <td>162</td>
17614 </tr>
17615 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17616 <td>179</td>
17617 <td>163</td>
17618 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17619 <td>in_intr</td>
17620 <td>163</td>
17621 </tr>
17622 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17623 <td>179</td>
17624 <td>164</td>
17625 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17626 <td>in_intr</td>
17627 <td>164</td>
17628 </tr>
17629 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17630 <td>179</td>
17631 <td>165</td>
17632 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17633 <td>in_intr</td>
17634 <td>165</td>
17635 </tr>
17636 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17637 <td>179</td>
17638 <td>166</td>
17639 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17640 <td>in_intr</td>
17641 <td>166</td>
17642 </tr>
17643 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17644 <td>179</td>
17645 <td>167</td>
17646 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17647 <td>in_intr</td>
17648 <td>167</td>
17649 </tr>
17650 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17651 <td>179</td>
17652 <td>168</td>
17653 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17654 <td>in_intr</td>
17655 <td>168</td>
17656 </tr>
17657 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17658 <td>179</td>
17659 <td>169</td>
17660 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17661 <td>in_intr</td>
17662 <td>169</td>
17663 </tr>
17664 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17665 <td>179</td>
17666 <td>170</td>
17667 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17668 <td>in_intr</td>
17669 <td>170</td>
17670 </tr>
17671 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17672 <td>179</td>
17673 <td>171</td>
17674 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17675 <td>in_intr</td>
17676 <td>171</td>
17677 </tr>
17678 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17679 <td>179</td>
17680 <td>172</td>
17681 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17682 <td>in_intr</td>
17683 <td>172</td>
17684 </tr>
17685 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17686 <td>179</td>
17687 <td>173</td>
17688 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17689 <td>in_intr</td>
17690 <td>173</td>
17691 </tr>
17692 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17693 <td>179</td>
17694 <td>174</td>
17695 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17696 <td>in_intr</td>
17697 <td>174</td>
17698 </tr>
17699 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17700 <td>179</td>
17701 <td>175</td>
17702 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17703 <td>in_intr</td>
17704 <td>175</td>
17705 </tr>
17706 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17707 <td>179</td>
17708 <td>176</td>
17709 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17710 <td>in_intr</td>
17711 <td>176</td>
17712 </tr>
17713 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17714 <td>179</td>
17715 <td>177</td>
17716 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17717 <td>in_intr</td>
17718 <td>177</td>
17719 </tr>
17720 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17721 <td>179</td>
17722 <td>178</td>
17723 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17724 <td>in_intr</td>
17725 <td>178</td>
17726 </tr>
17727 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17728 <td>179</td>
17729 <td>179</td>
17730 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17731 <td>in_intr</td>
17732 <td>179</td>
17733 </tr>
17734 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17735 <td>179</td>
17736 <td>180</td>
17737 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17738 <td>in_intr</td>
17739 <td>180</td>
17740 </tr>
17741 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17742 <td>179</td>
17743 <td>181</td>
17744 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17745 <td>in_intr</td>
17746 <td>181</td>
17747 </tr>
17748 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17749 <td>179</td>
17750 <td>182</td>
17751 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17752 <td>in_intr</td>
17753 <td>182</td>
17754 </tr>
17755 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17756 <td>179</td>
17757 <td>183</td>
17758 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17759 <td>in_intr</td>
17760 <td>183</td>
17761 </tr>
17762 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17763 <td>179</td>
17764 <td>184</td>
17765 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17766 <td>in_intr</td>
17767 <td>184</td>
17768 </tr>
17769 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17770 <td>179</td>
17771 <td>185</td>
17772 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17773 <td>in_intr</td>
17774 <td>185</td>
17775 </tr>
17776 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17777 <td>179</td>
17778 <td>186</td>
17779 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17780 <td>in_intr</td>
17781 <td>186</td>
17782 </tr>
17783 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17784 <td>179</td>
17785 <td>187</td>
17786 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17787 <td>in_intr</td>
17788 <td>187</td>
17789 </tr>
17790 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17791 <td>179</td>
17792 <td>188</td>
17793 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17794 <td>in_intr</td>
17795 <td>188</td>
17796 </tr>
17797 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17798 <td>179</td>
17799 <td>189</td>
17800 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17801 <td>in_intr</td>
17802 <td>189</td>
17803 </tr>
17804 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17805 <td>179</td>
17806 <td>190</td>
17807 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17808 <td>in_intr</td>
17809 <td>190</td>
17810 </tr>
17811 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17812 <td>179</td>
17813 <td>191</td>
17814 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17815 <td>in_intr</td>
17816 <td>191</td>
17817 </tr>
17818 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17819 <td>179</td>
17820 <td>192</td>
17821 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17822 <td>in_intr</td>
17823 <td>192</td>
17824 </tr>
17825 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17826 <td>179</td>
17827 <td>193</td>
17828 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17829 <td>in_intr</td>
17830 <td>193</td>
17831 </tr>
17832 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17833 <td>179</td>
17834 <td>194</td>
17835 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17836 <td>in_intr</td>
17837 <td>194</td>
17838 </tr>
17839 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17840 <td>179</td>
17841 <td>195</td>
17842 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17843 <td>in_intr</td>
17844 <td>195</td>
17845 </tr>
17846 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17847 <td>179</td>
17848 <td>196</td>
17849 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17850 <td>in_intr</td>
17851 <td>196</td>
17852 </tr>
17853 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17854 <td>179</td>
17855 <td>197</td>
17856 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17857 <td>in_intr</td>
17858 <td>197</td>
17859 </tr>
17860 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17861 <td>179</td>
17862 <td>198</td>
17863 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17864 <td>in_intr</td>
17865 <td>198</td>
17866 </tr>
17867 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17868 <td>179</td>
17869 <td>199</td>
17870 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17871 <td>in_intr</td>
17872 <td>199</td>
17873 </tr>
17874 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17875 <td>179</td>
17876 <td>200</td>
17877 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17878 <td>in_intr</td>
17879 <td>200</td>
17880 </tr>
17881 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17882 <td>179</td>
17883 <td>201</td>
17884 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17885 <td>in_intr</td>
17886 <td>201</td>
17887 </tr>
17888 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17889 <td>179</td>
17890 <td>202</td>
17891 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17892 <td>in_intr</td>
17893 <td>202</td>
17894 </tr>
17895 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17896 <td>179</td>
17897 <td>203</td>
17898 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17899 <td>in_intr</td>
17900 <td>203</td>
17901 </tr>
17902 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17903 <td>179</td>
17904 <td>204</td>
17905 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17906 <td>in_intr</td>
17907 <td>204</td>
17908 </tr>
17909 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17910 <td>179</td>
17911 <td>205</td>
17912 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17913 <td>in_intr</td>
17914 <td>205</td>
17915 </tr>
17916 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17917 <td>179</td>
17918 <td>206</td>
17919 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17920 <td>in_intr</td>
17921 <td>206</td>
17922 </tr>
17923 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17924 <td>179</td>
17925 <td>207</td>
17926 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17927 <td>in_intr</td>
17928 <td>207</td>
17929 </tr>
17930 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17931 <td>179</td>
17932 <td>208</td>
17933 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17934 <td>in_intr</td>
17935 <td>208</td>
17936 </tr>
17937 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17938 <td>179</td>
17939 <td>209</td>
17940 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17941 <td>in_intr</td>
17942 <td>209</td>
17943 </tr>
17944 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17945 <td>179</td>
17946 <td>210</td>
17947 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17948 <td>in_intr</td>
17949 <td>210</td>
17950 </tr>
17951 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17952 <td>179</td>
17953 <td>211</td>
17954 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17955 <td>in_intr</td>
17956 <td>211</td>
17957 </tr>
17958 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17959 <td>179</td>
17960 <td>212</td>
17961 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17962 <td>in_intr</td>
17963 <td>212</td>
17964 </tr>
17965 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17966 <td>179</td>
17967 <td>213</td>
17968 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17969 <td>in_intr</td>
17970 <td>213</td>
17971 </tr>
17972 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17973 <td>179</td>
17974 <td>214</td>
17975 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17976 <td>in_intr</td>
17977 <td>214</td>
17978 </tr>
17979 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17980 <td>179</td>
17981 <td>215</td>
17982 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17983 <td>in_intr</td>
17984 <td>215</td>
17985 </tr>
17986 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17987 <td>179</td>
17988 <td>216</td>
17989 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17990 <td>in_intr</td>
17991 <td>216</td>
17992 </tr>
17993 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
17994 <td>179</td>
17995 <td>217</td>
17996 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
17997 <td>in_intr</td>
17998 <td>217</td>
17999 </tr>
18000 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18001 <td>179</td>
18002 <td>218</td>
18003 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18004 <td>in_intr</td>
18005 <td>218</td>
18006 </tr>
18007 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18008 <td>179</td>
18009 <td>219</td>
18010 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18011 <td>in_intr</td>
18012 <td>219</td>
18013 </tr>
18014 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18015 <td>179</td>
18016 <td>220</td>
18017 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18018 <td>in_intr</td>
18019 <td>220</td>
18020 </tr>
18021 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18022 <td>179</td>
18023 <td>221</td>
18024 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18025 <td>in_intr</td>
18026 <td>221</td>
18027 </tr>
18028 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18029 <td>179</td>
18030 <td>222</td>
18031 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18032 <td>in_intr</td>
18033 <td>222</td>
18034 </tr>
18035 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18036 <td>179</td>
18037 <td>223</td>
18038 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18039 <td>in_intr</td>
18040 <td>223</td>
18041 </tr>
18042 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18043 <td>179</td>
18044 <td>224</td>
18045 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18046 <td>in_intr</td>
18047 <td>224</td>
18048 </tr>
18049 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18050 <td>179</td>
18051 <td>225</td>
18052 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18053 <td>in_intr</td>
18054 <td>225</td>
18055 </tr>
18056 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18057 <td>179</td>
18058 <td>226</td>
18059 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18060 <td>in_intr</td>
18061 <td>226</td>
18062 </tr>
18063 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18064 <td>179</td>
18065 <td>227</td>
18066 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18067 <td>in_intr</td>
18068 <td>227</td>
18069 </tr>
18070 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18071 <td>179</td>
18072 <td>228</td>
18073 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18074 <td>in_intr</td>
18075 <td>228</td>
18076 </tr>
18077 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18078 <td>179</td>
18079 <td>229</td>
18080 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18081 <td>in_intr</td>
18082 <td>229</td>
18083 </tr>
18084 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18085 <td>179</td>
18086 <td>230</td>
18087 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18088 <td>in_intr</td>
18089 <td>230</td>
18090 </tr>
18091 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18092 <td>179</td>
18093 <td>231</td>
18094 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18095 <td>in_intr</td>
18096 <td>231</td>
18097 </tr>
18098 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18099 <td>179</td>
18100 <td>232</td>
18101 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18102 <td>in_intr</td>
18103 <td>232</td>
18104 </tr>
18105 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18106 <td>179</td>
18107 <td>233</td>
18108 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18109 <td>in_intr</td>
18110 <td>233</td>
18111 </tr>
18112 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18113 <td>179</td>
18114 <td>234</td>
18115 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18116 <td>in_intr</td>
18117 <td>234</td>
18118 </tr>
18119 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18120 <td>179</td>
18121 <td>235</td>
18122 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18123 <td>in_intr</td>
18124 <td>235</td>
18125 </tr>
18126 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18127 <td>179</td>
18128 <td>236</td>
18129 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18130 <td>in_intr</td>
18131 <td>236</td>
18132 </tr>
18133 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18134 <td>179</td>
18135 <td>237</td>
18136 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18137 <td>in_intr</td>
18138 <td>237</td>
18139 </tr>
18140 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18141 <td>179</td>
18142 <td>238</td>
18143 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18144 <td>in_intr</td>
18145 <td>238</td>
18146 </tr>
18147 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18148 <td>179</td>
18149 <td>239</td>
18150 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18151 <td>in_intr</td>
18152 <td>239</td>
18153 </tr>
18154 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18155 <td>179</td>
18156 <td>240</td>
18157 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18158 <td>in_intr</td>
18159 <td>240</td>
18160 </tr>
18161 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18162 <td>179</td>
18163 <td>241</td>
18164 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18165 <td>in_intr</td>
18166 <td>241</td>
18167 </tr>
18168 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18169 <td>179</td>
18170 <td>242</td>
18171 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18172 <td>in_intr</td>
18173 <td>242</td>
18174 </tr>
18175 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18176 <td>179</td>
18177 <td>243</td>
18178 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18179 <td>in_intr</td>
18180 <td>243</td>
18181 </tr>
18182 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18183 <td>179</td>
18184 <td>244</td>
18185 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18186 <td>in_intr</td>
18187 <td>244</td>
18188 </tr>
18189 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18190 <td>179</td>
18191 <td>245</td>
18192 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18193 <td>in_intr</td>
18194 <td>245</td>
18195 </tr>
18196 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18197 <td>179</td>
18198 <td>246</td>
18199 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18200 <td>in_intr</td>
18201 <td>246</td>
18202 </tr>
18203 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18204 <td>179</td>
18205 <td>247</td>
18206 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18207 <td>in_intr</td>
18208 <td>247</td>
18209 </tr>
18210 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18211 <td>179</td>
18212 <td>248</td>
18213 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18214 <td>in_intr</td>
18215 <td>248</td>
18216 </tr>
18217 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18218 <td>179</td>
18219 <td>249</td>
18220 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18221 <td>in_intr</td>
18222 <td>249</td>
18223 </tr>
18224 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18225 <td>179</td>
18226 <td>250</td>
18227 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18228 <td>in_intr</td>
18229 <td>250</td>
18230 </tr>
18231 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18232 <td>179</td>
18233 <td>251</td>
18234 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18235 <td>in_intr</td>
18236 <td>251</td>
18237 </tr>
18238 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18239 <td>179</td>
18240 <td>252</td>
18241 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18242 <td>in_intr</td>
18243 <td>252</td>
18244 </tr>
18245 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18246 <td>179</td>
18247 <td>253</td>
18248 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18249 <td>in_intr</td>
18250 <td>253</td>
18251 </tr>
18252 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18253 <td>179</td>
18254 <td>254</td>
18255 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18256 <td>in_intr</td>
18257 <td>254</td>
18258 </tr>
18259 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
18260 <td>179</td>
18261 <td>255</td>
18262 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
18263 <td>in_intr</td>
18264 <td>255</td>
18265 </tr>
18266 </tbody>
18267 </table>
18268 </div>
18269 <div class="section" id="mcu-navss0-intr-aggr-0-interrupt-aggregator-virtual-interrupt-destinations">
18270 <span id="pub-soc-am65x-sr2-mcu-navss0-intr-aggr-0-vint-output-dst-list"></span><h2>mcu_navss0_intr_aggr_0 Interrupt Aggregator Virtual Interrupt Destinations<a class="headerlink" href="#mcu-navss0-intr-aggr-0-interrupt-aggregator-virtual-interrupt-destinations" title="Permalink to this headline">¶</a></h2>
18271 <div class="admonition warning">
18272 <p class="first admonition-title">Warning</p>
18273 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
18274 host within the RM Board Configuration resource assignment array.  The RM
18275 Board Configuration is rejected if an overlap with a reserved resource is
18276 detected.</p>
18277 </div>
18278 <table border="1" class="docutils">
18279 <colgroup>
18280 <col width="24%" />
18281 <col width="11%" />
18282 <col width="11%" />
18283 <col width="23%" />
18284 <col width="17%" />
18285 <col width="14%" />
18286 </colgroup>
18287 <thead valign="bottom">
18288 <tr class="row-odd"><th class="head">IA Name</th>
18289 <th class="head">IA Device ID</th>
18290 <th class="head">IA VINT Index</th>
18291 <th class="head">Destination Name</th>
18292 <th class="head">Destination Interface</th>
18293 <th class="head">Destination Index</th>
18294 </tr>
18295 </thead>
18296 <tbody valign="top">
18297 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0
18298 (<strong>Reserved by System Firmware</strong>)</td>
18299 <td>189</td>
18300 <td>0</td>
18301 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18302 <td>in_intr</td>
18303 <td>0</td>
18304 </tr>
18305 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0
18306 (<strong>Reserved by System Firmware</strong>)</td>
18307 <td>189</td>
18308 <td>1</td>
18309 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18310 <td>in_intr</td>
18311 <td>1</td>
18312 </tr>
18313 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0
18314 (<strong>Reserved by System Firmware</strong>)</td>
18315 <td>189</td>
18316 <td>2</td>
18317 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18318 <td>in_intr</td>
18319 <td>2</td>
18320 </tr>
18321 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0
18322 (<strong>Reserved by System Firmware</strong>)</td>
18323 <td>189</td>
18324 <td>3</td>
18325 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18326 <td>in_intr</td>
18327 <td>3</td>
18328 </tr>
18329 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0
18330 (<strong>Reserved by System Firmware</strong>)</td>
18331 <td>189</td>
18332 <td>4</td>
18333 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18334 <td>in_intr</td>
18335 <td>4</td>
18336 </tr>
18337 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0
18338 (<strong>Reserved by System Firmware</strong>)</td>
18339 <td>189</td>
18340 <td>5</td>
18341 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18342 <td>in_intr</td>
18343 <td>5</td>
18344 </tr>
18345 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0
18346 (<strong>Reserved by System Firmware</strong>)</td>
18347 <td>189</td>
18348 <td>6</td>
18349 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18350 <td>in_intr</td>
18351 <td>6</td>
18352 </tr>
18353 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0
18354 (<strong>Reserved by System Firmware</strong>)</td>
18355 <td>189</td>
18356 <td>7</td>
18357 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18358 <td>in_intr</td>
18359 <td>7</td>
18360 </tr>
18361 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18362 <td>189</td>
18363 <td>8</td>
18364 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18365 <td>in_intr</td>
18366 <td>8</td>
18367 </tr>
18368 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18369 <td>189</td>
18370 <td>9</td>
18371 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18372 <td>in_intr</td>
18373 <td>9</td>
18374 </tr>
18375 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18376 <td>189</td>
18377 <td>10</td>
18378 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18379 <td>in_intr</td>
18380 <td>10</td>
18381 </tr>
18382 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18383 <td>189</td>
18384 <td>11</td>
18385 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18386 <td>in_intr</td>
18387 <td>11</td>
18388 </tr>
18389 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18390 <td>189</td>
18391 <td>12</td>
18392 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18393 <td>in_intr</td>
18394 <td>12</td>
18395 </tr>
18396 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18397 <td>189</td>
18398 <td>13</td>
18399 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18400 <td>in_intr</td>
18401 <td>13</td>
18402 </tr>
18403 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18404 <td>189</td>
18405 <td>14</td>
18406 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18407 <td>in_intr</td>
18408 <td>14</td>
18409 </tr>
18410 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18411 <td>189</td>
18412 <td>15</td>
18413 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18414 <td>in_intr</td>
18415 <td>15</td>
18416 </tr>
18417 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18418 <td>189</td>
18419 <td>16</td>
18420 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18421 <td>in_intr</td>
18422 <td>16</td>
18423 </tr>
18424 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18425 <td>189</td>
18426 <td>17</td>
18427 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18428 <td>in_intr</td>
18429 <td>17</td>
18430 </tr>
18431 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18432 <td>189</td>
18433 <td>18</td>
18434 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18435 <td>in_intr</td>
18436 <td>18</td>
18437 </tr>
18438 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18439 <td>189</td>
18440 <td>19</td>
18441 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18442 <td>in_intr</td>
18443 <td>19</td>
18444 </tr>
18445 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18446 <td>189</td>
18447 <td>20</td>
18448 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18449 <td>in_intr</td>
18450 <td>20</td>
18451 </tr>
18452 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18453 <td>189</td>
18454 <td>21</td>
18455 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18456 <td>in_intr</td>
18457 <td>21</td>
18458 </tr>
18459 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18460 <td>189</td>
18461 <td>22</td>
18462 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18463 <td>in_intr</td>
18464 <td>22</td>
18465 </tr>
18466 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18467 <td>189</td>
18468 <td>23</td>
18469 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18470 <td>in_intr</td>
18471 <td>23</td>
18472 </tr>
18473 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18474 <td>189</td>
18475 <td>24</td>
18476 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18477 <td>in_intr</td>
18478 <td>24</td>
18479 </tr>
18480 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18481 <td>189</td>
18482 <td>25</td>
18483 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18484 <td>in_intr</td>
18485 <td>25</td>
18486 </tr>
18487 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18488 <td>189</td>
18489 <td>26</td>
18490 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18491 <td>in_intr</td>
18492 <td>26</td>
18493 </tr>
18494 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18495 <td>189</td>
18496 <td>27</td>
18497 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18498 <td>in_intr</td>
18499 <td>27</td>
18500 </tr>
18501 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18502 <td>189</td>
18503 <td>28</td>
18504 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18505 <td>in_intr</td>
18506 <td>28</td>
18507 </tr>
18508 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18509 <td>189</td>
18510 <td>29</td>
18511 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18512 <td>in_intr</td>
18513 <td>29</td>
18514 </tr>
18515 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18516 <td>189</td>
18517 <td>30</td>
18518 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18519 <td>in_intr</td>
18520 <td>30</td>
18521 </tr>
18522 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18523 <td>189</td>
18524 <td>31</td>
18525 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18526 <td>in_intr</td>
18527 <td>31</td>
18528 </tr>
18529 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18530 <td>189</td>
18531 <td>32</td>
18532 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18533 <td>in_intr</td>
18534 <td>32</td>
18535 </tr>
18536 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18537 <td>189</td>
18538 <td>33</td>
18539 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18540 <td>in_intr</td>
18541 <td>33</td>
18542 </tr>
18543 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18544 <td>189</td>
18545 <td>34</td>
18546 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18547 <td>in_intr</td>
18548 <td>34</td>
18549 </tr>
18550 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18551 <td>189</td>
18552 <td>35</td>
18553 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18554 <td>in_intr</td>
18555 <td>35</td>
18556 </tr>
18557 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18558 <td>189</td>
18559 <td>36</td>
18560 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18561 <td>in_intr</td>
18562 <td>36</td>
18563 </tr>
18564 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18565 <td>189</td>
18566 <td>37</td>
18567 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18568 <td>in_intr</td>
18569 <td>37</td>
18570 </tr>
18571 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18572 <td>189</td>
18573 <td>38</td>
18574 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18575 <td>in_intr</td>
18576 <td>38</td>
18577 </tr>
18578 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18579 <td>189</td>
18580 <td>39</td>
18581 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18582 <td>in_intr</td>
18583 <td>39</td>
18584 </tr>
18585 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18586 <td>189</td>
18587 <td>40</td>
18588 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18589 <td>in_intr</td>
18590 <td>40</td>
18591 </tr>
18592 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18593 <td>189</td>
18594 <td>41</td>
18595 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18596 <td>in_intr</td>
18597 <td>41</td>
18598 </tr>
18599 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18600 <td>189</td>
18601 <td>42</td>
18602 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18603 <td>in_intr</td>
18604 <td>42</td>
18605 </tr>
18606 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18607 <td>189</td>
18608 <td>43</td>
18609 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18610 <td>in_intr</td>
18611 <td>43</td>
18612 </tr>
18613 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18614 <td>189</td>
18615 <td>44</td>
18616 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18617 <td>in_intr</td>
18618 <td>44</td>
18619 </tr>
18620 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18621 <td>189</td>
18622 <td>45</td>
18623 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18624 <td>in_intr</td>
18625 <td>45</td>
18626 </tr>
18627 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18628 <td>189</td>
18629 <td>46</td>
18630 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18631 <td>in_intr</td>
18632 <td>46</td>
18633 </tr>
18634 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18635 <td>189</td>
18636 <td>47</td>
18637 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18638 <td>in_intr</td>
18639 <td>47</td>
18640 </tr>
18641 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18642 <td>189</td>
18643 <td>48</td>
18644 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18645 <td>in_intr</td>
18646 <td>48</td>
18647 </tr>
18648 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18649 <td>189</td>
18650 <td>49</td>
18651 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18652 <td>in_intr</td>
18653 <td>49</td>
18654 </tr>
18655 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18656 <td>189</td>
18657 <td>50</td>
18658 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18659 <td>in_intr</td>
18660 <td>50</td>
18661 </tr>
18662 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18663 <td>189</td>
18664 <td>51</td>
18665 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18666 <td>in_intr</td>
18667 <td>51</td>
18668 </tr>
18669 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18670 <td>189</td>
18671 <td>52</td>
18672 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18673 <td>in_intr</td>
18674 <td>52</td>
18675 </tr>
18676 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18677 <td>189</td>
18678 <td>53</td>
18679 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18680 <td>in_intr</td>
18681 <td>53</td>
18682 </tr>
18683 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18684 <td>189</td>
18685 <td>54</td>
18686 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18687 <td>in_intr</td>
18688 <td>54</td>
18689 </tr>
18690 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18691 <td>189</td>
18692 <td>55</td>
18693 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18694 <td>in_intr</td>
18695 <td>55</td>
18696 </tr>
18697 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18698 <td>189</td>
18699 <td>56</td>
18700 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18701 <td>in_intr</td>
18702 <td>56</td>
18703 </tr>
18704 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18705 <td>189</td>
18706 <td>57</td>
18707 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18708 <td>in_intr</td>
18709 <td>57</td>
18710 </tr>
18711 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18712 <td>189</td>
18713 <td>58</td>
18714 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18715 <td>in_intr</td>
18716 <td>58</td>
18717 </tr>
18718 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18719 <td>189</td>
18720 <td>59</td>
18721 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18722 <td>in_intr</td>
18723 <td>59</td>
18724 </tr>
18725 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18726 <td>189</td>
18727 <td>60</td>
18728 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18729 <td>in_intr</td>
18730 <td>60</td>
18731 </tr>
18732 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18733 <td>189</td>
18734 <td>61</td>
18735 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18736 <td>in_intr</td>
18737 <td>61</td>
18738 </tr>
18739 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18740 <td>189</td>
18741 <td>62</td>
18742 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18743 <td>in_intr</td>
18744 <td>62</td>
18745 </tr>
18746 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18747 <td>189</td>
18748 <td>63</td>
18749 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18750 <td>in_intr</td>
18751 <td>63</td>
18752 </tr>
18753 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18754 <td>189</td>
18755 <td>64</td>
18756 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18757 <td>in_intr</td>
18758 <td>64</td>
18759 </tr>
18760 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18761 <td>189</td>
18762 <td>65</td>
18763 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18764 <td>in_intr</td>
18765 <td>65</td>
18766 </tr>
18767 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18768 <td>189</td>
18769 <td>66</td>
18770 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18771 <td>in_intr</td>
18772 <td>66</td>
18773 </tr>
18774 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18775 <td>189</td>
18776 <td>67</td>
18777 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18778 <td>in_intr</td>
18779 <td>67</td>
18780 </tr>
18781 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18782 <td>189</td>
18783 <td>68</td>
18784 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18785 <td>in_intr</td>
18786 <td>68</td>
18787 </tr>
18788 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18789 <td>189</td>
18790 <td>69</td>
18791 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18792 <td>in_intr</td>
18793 <td>69</td>
18794 </tr>
18795 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18796 <td>189</td>
18797 <td>70</td>
18798 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18799 <td>in_intr</td>
18800 <td>70</td>
18801 </tr>
18802 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18803 <td>189</td>
18804 <td>71</td>
18805 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18806 <td>in_intr</td>
18807 <td>71</td>
18808 </tr>
18809 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18810 <td>189</td>
18811 <td>72</td>
18812 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18813 <td>in_intr</td>
18814 <td>72</td>
18815 </tr>
18816 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18817 <td>189</td>
18818 <td>73</td>
18819 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18820 <td>in_intr</td>
18821 <td>73</td>
18822 </tr>
18823 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18824 <td>189</td>
18825 <td>74</td>
18826 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18827 <td>in_intr</td>
18828 <td>74</td>
18829 </tr>
18830 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18831 <td>189</td>
18832 <td>75</td>
18833 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18834 <td>in_intr</td>
18835 <td>75</td>
18836 </tr>
18837 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18838 <td>189</td>
18839 <td>76</td>
18840 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18841 <td>in_intr</td>
18842 <td>76</td>
18843 </tr>
18844 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18845 <td>189</td>
18846 <td>77</td>
18847 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18848 <td>in_intr</td>
18849 <td>77</td>
18850 </tr>
18851 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18852 <td>189</td>
18853 <td>78</td>
18854 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18855 <td>in_intr</td>
18856 <td>78</td>
18857 </tr>
18858 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18859 <td>189</td>
18860 <td>79</td>
18861 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18862 <td>in_intr</td>
18863 <td>79</td>
18864 </tr>
18865 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18866 <td>189</td>
18867 <td>80</td>
18868 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18869 <td>in_intr</td>
18870 <td>80</td>
18871 </tr>
18872 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18873 <td>189</td>
18874 <td>81</td>
18875 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18876 <td>in_intr</td>
18877 <td>81</td>
18878 </tr>
18879 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18880 <td>189</td>
18881 <td>82</td>
18882 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18883 <td>in_intr</td>
18884 <td>82</td>
18885 </tr>
18886 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18887 <td>189</td>
18888 <td>83</td>
18889 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18890 <td>in_intr</td>
18891 <td>83</td>
18892 </tr>
18893 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18894 <td>189</td>
18895 <td>84</td>
18896 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18897 <td>in_intr</td>
18898 <td>84</td>
18899 </tr>
18900 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18901 <td>189</td>
18902 <td>85</td>
18903 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18904 <td>in_intr</td>
18905 <td>85</td>
18906 </tr>
18907 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18908 <td>189</td>
18909 <td>86</td>
18910 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18911 <td>in_intr</td>
18912 <td>86</td>
18913 </tr>
18914 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18915 <td>189</td>
18916 <td>87</td>
18917 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18918 <td>in_intr</td>
18919 <td>87</td>
18920 </tr>
18921 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18922 <td>189</td>
18923 <td>88</td>
18924 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18925 <td>in_intr</td>
18926 <td>88</td>
18927 </tr>
18928 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18929 <td>189</td>
18930 <td>89</td>
18931 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18932 <td>in_intr</td>
18933 <td>89</td>
18934 </tr>
18935 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18936 <td>189</td>
18937 <td>90</td>
18938 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18939 <td>in_intr</td>
18940 <td>90</td>
18941 </tr>
18942 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18943 <td>189</td>
18944 <td>91</td>
18945 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18946 <td>in_intr</td>
18947 <td>91</td>
18948 </tr>
18949 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18950 <td>189</td>
18951 <td>92</td>
18952 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18953 <td>in_intr</td>
18954 <td>92</td>
18955 </tr>
18956 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18957 <td>189</td>
18958 <td>93</td>
18959 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18960 <td>in_intr</td>
18961 <td>93</td>
18962 </tr>
18963 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18964 <td>189</td>
18965 <td>94</td>
18966 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18967 <td>in_intr</td>
18968 <td>94</td>
18969 </tr>
18970 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18971 <td>189</td>
18972 <td>95</td>
18973 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18974 <td>in_intr</td>
18975 <td>95</td>
18976 </tr>
18977 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18978 <td>189</td>
18979 <td>96</td>
18980 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18981 <td>in_intr</td>
18982 <td>96</td>
18983 </tr>
18984 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18985 <td>189</td>
18986 <td>97</td>
18987 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18988 <td>in_intr</td>
18989 <td>97</td>
18990 </tr>
18991 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18992 <td>189</td>
18993 <td>98</td>
18994 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
18995 <td>in_intr</td>
18996 <td>98</td>
18997 </tr>
18998 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
18999 <td>189</td>
19000 <td>99</td>
19001 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19002 <td>in_intr</td>
19003 <td>99</td>
19004 </tr>
19005 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19006 <td>189</td>
19007 <td>100</td>
19008 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19009 <td>in_intr</td>
19010 <td>100</td>
19011 </tr>
19012 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19013 <td>189</td>
19014 <td>101</td>
19015 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19016 <td>in_intr</td>
19017 <td>101</td>
19018 </tr>
19019 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19020 <td>189</td>
19021 <td>102</td>
19022 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19023 <td>in_intr</td>
19024 <td>102</td>
19025 </tr>
19026 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19027 <td>189</td>
19028 <td>103</td>
19029 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19030 <td>in_intr</td>
19031 <td>103</td>
19032 </tr>
19033 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19034 <td>189</td>
19035 <td>104</td>
19036 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19037 <td>in_intr</td>
19038 <td>104</td>
19039 </tr>
19040 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19041 <td>189</td>
19042 <td>105</td>
19043 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19044 <td>in_intr</td>
19045 <td>105</td>
19046 </tr>
19047 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19048 <td>189</td>
19049 <td>106</td>
19050 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19051 <td>in_intr</td>
19052 <td>106</td>
19053 </tr>
19054 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19055 <td>189</td>
19056 <td>107</td>
19057 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19058 <td>in_intr</td>
19059 <td>107</td>
19060 </tr>
19061 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19062 <td>189</td>
19063 <td>108</td>
19064 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19065 <td>in_intr</td>
19066 <td>108</td>
19067 </tr>
19068 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19069 <td>189</td>
19070 <td>109</td>
19071 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19072 <td>in_intr</td>
19073 <td>109</td>
19074 </tr>
19075 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19076 <td>189</td>
19077 <td>110</td>
19078 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19079 <td>in_intr</td>
19080 <td>110</td>
19081 </tr>
19082 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19083 <td>189</td>
19084 <td>111</td>
19085 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19086 <td>in_intr</td>
19087 <td>111</td>
19088 </tr>
19089 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19090 <td>189</td>
19091 <td>112</td>
19092 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19093 <td>in_intr</td>
19094 <td>112</td>
19095 </tr>
19096 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19097 <td>189</td>
19098 <td>113</td>
19099 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19100 <td>in_intr</td>
19101 <td>113</td>
19102 </tr>
19103 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19104 <td>189</td>
19105 <td>114</td>
19106 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19107 <td>in_intr</td>
19108 <td>114</td>
19109 </tr>
19110 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19111 <td>189</td>
19112 <td>115</td>
19113 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19114 <td>in_intr</td>
19115 <td>115</td>
19116 </tr>
19117 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19118 <td>189</td>
19119 <td>116</td>
19120 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19121 <td>in_intr</td>
19122 <td>116</td>
19123 </tr>
19124 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19125 <td>189</td>
19126 <td>117</td>
19127 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19128 <td>in_intr</td>
19129 <td>117</td>
19130 </tr>
19131 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19132 <td>189</td>
19133 <td>118</td>
19134 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19135 <td>in_intr</td>
19136 <td>118</td>
19137 </tr>
19138 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19139 <td>189</td>
19140 <td>119</td>
19141 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19142 <td>in_intr</td>
19143 <td>119</td>
19144 </tr>
19145 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19146 <td>189</td>
19147 <td>120</td>
19148 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19149 <td>in_intr</td>
19150 <td>120</td>
19151 </tr>
19152 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19153 <td>189</td>
19154 <td>121</td>
19155 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19156 <td>in_intr</td>
19157 <td>121</td>
19158 </tr>
19159 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19160 <td>189</td>
19161 <td>122</td>
19162 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19163 <td>in_intr</td>
19164 <td>122</td>
19165 </tr>
19166 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19167 <td>189</td>
19168 <td>123</td>
19169 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19170 <td>in_intr</td>
19171 <td>123</td>
19172 </tr>
19173 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19174 <td>189</td>
19175 <td>124</td>
19176 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19177 <td>in_intr</td>
19178 <td>124</td>
19179 </tr>
19180 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19181 <td>189</td>
19182 <td>125</td>
19183 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19184 <td>in_intr</td>
19185 <td>125</td>
19186 </tr>
19187 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19188 <td>189</td>
19189 <td>126</td>
19190 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19191 <td>in_intr</td>
19192 <td>126</td>
19193 </tr>
19194 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19195 <td>189</td>
19196 <td>127</td>
19197 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19198 <td>in_intr</td>
19199 <td>127</td>
19200 </tr>
19201 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19202 <td>189</td>
19203 <td>128</td>
19204 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19205 <td>in_intr</td>
19206 <td>128</td>
19207 </tr>
19208 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19209 <td>189</td>
19210 <td>129</td>
19211 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19212 <td>in_intr</td>
19213 <td>129</td>
19214 </tr>
19215 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19216 <td>189</td>
19217 <td>130</td>
19218 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19219 <td>in_intr</td>
19220 <td>130</td>
19221 </tr>
19222 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19223 <td>189</td>
19224 <td>131</td>
19225 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19226 <td>in_intr</td>
19227 <td>131</td>
19228 </tr>
19229 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19230 <td>189</td>
19231 <td>132</td>
19232 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19233 <td>in_intr</td>
19234 <td>132</td>
19235 </tr>
19236 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19237 <td>189</td>
19238 <td>133</td>
19239 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19240 <td>in_intr</td>
19241 <td>133</td>
19242 </tr>
19243 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19244 <td>189</td>
19245 <td>134</td>
19246 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19247 <td>in_intr</td>
19248 <td>134</td>
19249 </tr>
19250 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19251 <td>189</td>
19252 <td>135</td>
19253 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19254 <td>in_intr</td>
19255 <td>135</td>
19256 </tr>
19257 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19258 <td>189</td>
19259 <td>136</td>
19260 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19261 <td>in_intr</td>
19262 <td>136</td>
19263 </tr>
19264 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19265 <td>189</td>
19266 <td>137</td>
19267 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19268 <td>in_intr</td>
19269 <td>137</td>
19270 </tr>
19271 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19272 <td>189</td>
19273 <td>138</td>
19274 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19275 <td>in_intr</td>
19276 <td>138</td>
19277 </tr>
19278 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19279 <td>189</td>
19280 <td>139</td>
19281 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19282 <td>in_intr</td>
19283 <td>139</td>
19284 </tr>
19285 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19286 <td>189</td>
19287 <td>140</td>
19288 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19289 <td>in_intr</td>
19290 <td>140</td>
19291 </tr>
19292 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19293 <td>189</td>
19294 <td>141</td>
19295 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19296 <td>in_intr</td>
19297 <td>141</td>
19298 </tr>
19299 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19300 <td>189</td>
19301 <td>142</td>
19302 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19303 <td>in_intr</td>
19304 <td>142</td>
19305 </tr>
19306 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19307 <td>189</td>
19308 <td>143</td>
19309 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19310 <td>in_intr</td>
19311 <td>143</td>
19312 </tr>
19313 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19314 <td>189</td>
19315 <td>144</td>
19316 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19317 <td>in_intr</td>
19318 <td>144</td>
19319 </tr>
19320 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19321 <td>189</td>
19322 <td>145</td>
19323 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19324 <td>in_intr</td>
19325 <td>145</td>
19326 </tr>
19327 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19328 <td>189</td>
19329 <td>146</td>
19330 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19331 <td>in_intr</td>
19332 <td>146</td>
19333 </tr>
19334 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19335 <td>189</td>
19336 <td>147</td>
19337 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19338 <td>in_intr</td>
19339 <td>147</td>
19340 </tr>
19341 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19342 <td>189</td>
19343 <td>148</td>
19344 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19345 <td>in_intr</td>
19346 <td>148</td>
19347 </tr>
19348 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19349 <td>189</td>
19350 <td>149</td>
19351 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19352 <td>in_intr</td>
19353 <td>149</td>
19354 </tr>
19355 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19356 <td>189</td>
19357 <td>150</td>
19358 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19359 <td>in_intr</td>
19360 <td>150</td>
19361 </tr>
19362 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19363 <td>189</td>
19364 <td>151</td>
19365 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19366 <td>in_intr</td>
19367 <td>151</td>
19368 </tr>
19369 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19370 <td>189</td>
19371 <td>152</td>
19372 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19373 <td>in_intr</td>
19374 <td>152</td>
19375 </tr>
19376 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19377 <td>189</td>
19378 <td>153</td>
19379 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19380 <td>in_intr</td>
19381 <td>153</td>
19382 </tr>
19383 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19384 <td>189</td>
19385 <td>154</td>
19386 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19387 <td>in_intr</td>
19388 <td>154</td>
19389 </tr>
19390 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19391 <td>189</td>
19392 <td>155</td>
19393 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19394 <td>in_intr</td>
19395 <td>155</td>
19396 </tr>
19397 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19398 <td>189</td>
19399 <td>156</td>
19400 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19401 <td>in_intr</td>
19402 <td>156</td>
19403 </tr>
19404 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19405 <td>189</td>
19406 <td>157</td>
19407 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19408 <td>in_intr</td>
19409 <td>157</td>
19410 </tr>
19411 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19412 <td>189</td>
19413 <td>158</td>
19414 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19415 <td>in_intr</td>
19416 <td>158</td>
19417 </tr>
19418 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19419 <td>189</td>
19420 <td>159</td>
19421 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19422 <td>in_intr</td>
19423 <td>159</td>
19424 </tr>
19425 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19426 <td>189</td>
19427 <td>160</td>
19428 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19429 <td>in_intr</td>
19430 <td>160</td>
19431 </tr>
19432 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19433 <td>189</td>
19434 <td>161</td>
19435 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19436 <td>in_intr</td>
19437 <td>161</td>
19438 </tr>
19439 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19440 <td>189</td>
19441 <td>162</td>
19442 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19443 <td>in_intr</td>
19444 <td>162</td>
19445 </tr>
19446 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19447 <td>189</td>
19448 <td>163</td>
19449 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19450 <td>in_intr</td>
19451 <td>163</td>
19452 </tr>
19453 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19454 <td>189</td>
19455 <td>164</td>
19456 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19457 <td>in_intr</td>
19458 <td>164</td>
19459 </tr>
19460 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19461 <td>189</td>
19462 <td>165</td>
19463 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19464 <td>in_intr</td>
19465 <td>165</td>
19466 </tr>
19467 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19468 <td>189</td>
19469 <td>166</td>
19470 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19471 <td>in_intr</td>
19472 <td>166</td>
19473 </tr>
19474 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19475 <td>189</td>
19476 <td>167</td>
19477 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19478 <td>in_intr</td>
19479 <td>167</td>
19480 </tr>
19481 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19482 <td>189</td>
19483 <td>168</td>
19484 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19485 <td>in_intr</td>
19486 <td>168</td>
19487 </tr>
19488 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19489 <td>189</td>
19490 <td>169</td>
19491 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19492 <td>in_intr</td>
19493 <td>169</td>
19494 </tr>
19495 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19496 <td>189</td>
19497 <td>170</td>
19498 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19499 <td>in_intr</td>
19500 <td>170</td>
19501 </tr>
19502 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19503 <td>189</td>
19504 <td>171</td>
19505 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19506 <td>in_intr</td>
19507 <td>171</td>
19508 </tr>
19509 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19510 <td>189</td>
19511 <td>172</td>
19512 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19513 <td>in_intr</td>
19514 <td>172</td>
19515 </tr>
19516 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19517 <td>189</td>
19518 <td>173</td>
19519 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19520 <td>in_intr</td>
19521 <td>173</td>
19522 </tr>
19523 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19524 <td>189</td>
19525 <td>174</td>
19526 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19527 <td>in_intr</td>
19528 <td>174</td>
19529 </tr>
19530 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19531 <td>189</td>
19532 <td>175</td>
19533 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19534 <td>in_intr</td>
19535 <td>175</td>
19536 </tr>
19537 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19538 <td>189</td>
19539 <td>176</td>
19540 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19541 <td>in_intr</td>
19542 <td>176</td>
19543 </tr>
19544 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19545 <td>189</td>
19546 <td>177</td>
19547 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19548 <td>in_intr</td>
19549 <td>177</td>
19550 </tr>
19551 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19552 <td>189</td>
19553 <td>178</td>
19554 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19555 <td>in_intr</td>
19556 <td>178</td>
19557 </tr>
19558 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19559 <td>189</td>
19560 <td>179</td>
19561 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19562 <td>in_intr</td>
19563 <td>179</td>
19564 </tr>
19565 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19566 <td>189</td>
19567 <td>180</td>
19568 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19569 <td>in_intr</td>
19570 <td>180</td>
19571 </tr>
19572 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19573 <td>189</td>
19574 <td>181</td>
19575 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19576 <td>in_intr</td>
19577 <td>181</td>
19578 </tr>
19579 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19580 <td>189</td>
19581 <td>182</td>
19582 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19583 <td>in_intr</td>
19584 <td>182</td>
19585 </tr>
19586 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19587 <td>189</td>
19588 <td>183</td>
19589 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19590 <td>in_intr</td>
19591 <td>183</td>
19592 </tr>
19593 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19594 <td>189</td>
19595 <td>184</td>
19596 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19597 <td>in_intr</td>
19598 <td>184</td>
19599 </tr>
19600 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19601 <td>189</td>
19602 <td>185</td>
19603 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19604 <td>in_intr</td>
19605 <td>185</td>
19606 </tr>
19607 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19608 <td>189</td>
19609 <td>186</td>
19610 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19611 <td>in_intr</td>
19612 <td>186</td>
19613 </tr>
19614 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19615 <td>189</td>
19616 <td>187</td>
19617 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19618 <td>in_intr</td>
19619 <td>187</td>
19620 </tr>
19621 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19622 <td>189</td>
19623 <td>188</td>
19624 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19625 <td>in_intr</td>
19626 <td>188</td>
19627 </tr>
19628 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19629 <td>189</td>
19630 <td>189</td>
19631 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19632 <td>in_intr</td>
19633 <td>189</td>
19634 </tr>
19635 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19636 <td>189</td>
19637 <td>190</td>
19638 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19639 <td>in_intr</td>
19640 <td>190</td>
19641 </tr>
19642 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19643 <td>189</td>
19644 <td>191</td>
19645 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19646 <td>in_intr</td>
19647 <td>191</td>
19648 </tr>
19649 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19650 <td>189</td>
19651 <td>192</td>
19652 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19653 <td>in_intr</td>
19654 <td>192</td>
19655 </tr>
19656 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19657 <td>189</td>
19658 <td>193</td>
19659 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19660 <td>in_intr</td>
19661 <td>193</td>
19662 </tr>
19663 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19664 <td>189</td>
19665 <td>194</td>
19666 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19667 <td>in_intr</td>
19668 <td>194</td>
19669 </tr>
19670 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19671 <td>189</td>
19672 <td>195</td>
19673 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19674 <td>in_intr</td>
19675 <td>195</td>
19676 </tr>
19677 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19678 <td>189</td>
19679 <td>196</td>
19680 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19681 <td>in_intr</td>
19682 <td>196</td>
19683 </tr>
19684 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19685 <td>189</td>
19686 <td>197</td>
19687 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19688 <td>in_intr</td>
19689 <td>197</td>
19690 </tr>
19691 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19692 <td>189</td>
19693 <td>198</td>
19694 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19695 <td>in_intr</td>
19696 <td>198</td>
19697 </tr>
19698 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19699 <td>189</td>
19700 <td>199</td>
19701 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19702 <td>in_intr</td>
19703 <td>199</td>
19704 </tr>
19705 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19706 <td>189</td>
19707 <td>200</td>
19708 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19709 <td>in_intr</td>
19710 <td>200</td>
19711 </tr>
19712 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19713 <td>189</td>
19714 <td>201</td>
19715 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19716 <td>in_intr</td>
19717 <td>201</td>
19718 </tr>
19719 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19720 <td>189</td>
19721 <td>202</td>
19722 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19723 <td>in_intr</td>
19724 <td>202</td>
19725 </tr>
19726 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19727 <td>189</td>
19728 <td>203</td>
19729 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19730 <td>in_intr</td>
19731 <td>203</td>
19732 </tr>
19733 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19734 <td>189</td>
19735 <td>204</td>
19736 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19737 <td>in_intr</td>
19738 <td>204</td>
19739 </tr>
19740 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19741 <td>189</td>
19742 <td>205</td>
19743 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19744 <td>in_intr</td>
19745 <td>205</td>
19746 </tr>
19747 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19748 <td>189</td>
19749 <td>206</td>
19750 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19751 <td>in_intr</td>
19752 <td>206</td>
19753 </tr>
19754 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19755 <td>189</td>
19756 <td>207</td>
19757 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19758 <td>in_intr</td>
19759 <td>207</td>
19760 </tr>
19761 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19762 <td>189</td>
19763 <td>208</td>
19764 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19765 <td>in_intr</td>
19766 <td>208</td>
19767 </tr>
19768 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19769 <td>189</td>
19770 <td>209</td>
19771 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19772 <td>in_intr</td>
19773 <td>209</td>
19774 </tr>
19775 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19776 <td>189</td>
19777 <td>210</td>
19778 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19779 <td>in_intr</td>
19780 <td>210</td>
19781 </tr>
19782 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19783 <td>189</td>
19784 <td>211</td>
19785 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19786 <td>in_intr</td>
19787 <td>211</td>
19788 </tr>
19789 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19790 <td>189</td>
19791 <td>212</td>
19792 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19793 <td>in_intr</td>
19794 <td>212</td>
19795 </tr>
19796 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19797 <td>189</td>
19798 <td>213</td>
19799 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19800 <td>in_intr</td>
19801 <td>213</td>
19802 </tr>
19803 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19804 <td>189</td>
19805 <td>214</td>
19806 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19807 <td>in_intr</td>
19808 <td>214</td>
19809 </tr>
19810 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19811 <td>189</td>
19812 <td>215</td>
19813 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19814 <td>in_intr</td>
19815 <td>215</td>
19816 </tr>
19817 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19818 <td>189</td>
19819 <td>216</td>
19820 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19821 <td>in_intr</td>
19822 <td>216</td>
19823 </tr>
19824 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19825 <td>189</td>
19826 <td>217</td>
19827 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19828 <td>in_intr</td>
19829 <td>217</td>
19830 </tr>
19831 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19832 <td>189</td>
19833 <td>218</td>
19834 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19835 <td>in_intr</td>
19836 <td>218</td>
19837 </tr>
19838 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19839 <td>189</td>
19840 <td>219</td>
19841 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19842 <td>in_intr</td>
19843 <td>219</td>
19844 </tr>
19845 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19846 <td>189</td>
19847 <td>220</td>
19848 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19849 <td>in_intr</td>
19850 <td>220</td>
19851 </tr>
19852 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19853 <td>189</td>
19854 <td>221</td>
19855 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19856 <td>in_intr</td>
19857 <td>221</td>
19858 </tr>
19859 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19860 <td>189</td>
19861 <td>222</td>
19862 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19863 <td>in_intr</td>
19864 <td>222</td>
19865 </tr>
19866 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19867 <td>189</td>
19868 <td>223</td>
19869 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19870 <td>in_intr</td>
19871 <td>223</td>
19872 </tr>
19873 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19874 <td>189</td>
19875 <td>224</td>
19876 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19877 <td>in_intr</td>
19878 <td>224</td>
19879 </tr>
19880 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19881 <td>189</td>
19882 <td>225</td>
19883 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19884 <td>in_intr</td>
19885 <td>225</td>
19886 </tr>
19887 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19888 <td>189</td>
19889 <td>226</td>
19890 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19891 <td>in_intr</td>
19892 <td>226</td>
19893 </tr>
19894 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19895 <td>189</td>
19896 <td>227</td>
19897 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19898 <td>in_intr</td>
19899 <td>227</td>
19900 </tr>
19901 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19902 <td>189</td>
19903 <td>228</td>
19904 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19905 <td>in_intr</td>
19906 <td>228</td>
19907 </tr>
19908 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19909 <td>189</td>
19910 <td>229</td>
19911 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19912 <td>in_intr</td>
19913 <td>229</td>
19914 </tr>
19915 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19916 <td>189</td>
19917 <td>230</td>
19918 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19919 <td>in_intr</td>
19920 <td>230</td>
19921 </tr>
19922 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19923 <td>189</td>
19924 <td>231</td>
19925 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19926 <td>in_intr</td>
19927 <td>231</td>
19928 </tr>
19929 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19930 <td>189</td>
19931 <td>232</td>
19932 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19933 <td>in_intr</td>
19934 <td>232</td>
19935 </tr>
19936 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19937 <td>189</td>
19938 <td>233</td>
19939 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19940 <td>in_intr</td>
19941 <td>233</td>
19942 </tr>
19943 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19944 <td>189</td>
19945 <td>234</td>
19946 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19947 <td>in_intr</td>
19948 <td>234</td>
19949 </tr>
19950 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19951 <td>189</td>
19952 <td>235</td>
19953 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19954 <td>in_intr</td>
19955 <td>235</td>
19956 </tr>
19957 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19958 <td>189</td>
19959 <td>236</td>
19960 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19961 <td>in_intr</td>
19962 <td>236</td>
19963 </tr>
19964 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19965 <td>189</td>
19966 <td>237</td>
19967 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19968 <td>in_intr</td>
19969 <td>237</td>
19970 </tr>
19971 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19972 <td>189</td>
19973 <td>238</td>
19974 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19975 <td>in_intr</td>
19976 <td>238</td>
19977 </tr>
19978 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19979 <td>189</td>
19980 <td>239</td>
19981 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19982 <td>in_intr</td>
19983 <td>239</td>
19984 </tr>
19985 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19986 <td>189</td>
19987 <td>240</td>
19988 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19989 <td>in_intr</td>
19990 <td>240</td>
19991 </tr>
19992 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
19993 <td>189</td>
19994 <td>241</td>
19995 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
19996 <td>in_intr</td>
19997 <td>241</td>
19998 </tr>
19999 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20000 <td>189</td>
20001 <td>242</td>
20002 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20003 <td>in_intr</td>
20004 <td>242</td>
20005 </tr>
20006 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20007 <td>189</td>
20008 <td>243</td>
20009 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20010 <td>in_intr</td>
20011 <td>243</td>
20012 </tr>
20013 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20014 <td>189</td>
20015 <td>244</td>
20016 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20017 <td>in_intr</td>
20018 <td>244</td>
20019 </tr>
20020 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20021 <td>189</td>
20022 <td>245</td>
20023 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20024 <td>in_intr</td>
20025 <td>245</td>
20026 </tr>
20027 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20028 <td>189</td>
20029 <td>246</td>
20030 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20031 <td>in_intr</td>
20032 <td>246</td>
20033 </tr>
20034 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20035 <td>189</td>
20036 <td>247</td>
20037 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20038 <td>in_intr</td>
20039 <td>247</td>
20040 </tr>
20041 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20042 <td>189</td>
20043 <td>248</td>
20044 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20045 <td>in_intr</td>
20046 <td>248</td>
20047 </tr>
20048 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20049 <td>189</td>
20050 <td>249</td>
20051 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20052 <td>in_intr</td>
20053 <td>249</td>
20054 </tr>
20055 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20056 <td>189</td>
20057 <td>250</td>
20058 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20059 <td>in_intr</td>
20060 <td>250</td>
20061 </tr>
20062 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20063 <td>189</td>
20064 <td>251</td>
20065 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20066 <td>in_intr</td>
20067 <td>251</td>
20068 </tr>
20069 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20070 <td>189</td>
20071 <td>252</td>
20072 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20073 <td>in_intr</td>
20074 <td>252</td>
20075 </tr>
20076 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20077 <td>189</td>
20078 <td>253</td>
20079 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20080 <td>in_intr</td>
20081 <td>253</td>
20082 </tr>
20083 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20084 <td>189</td>
20085 <td>254</td>
20086 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20087 <td>in_intr</td>
20088 <td>254</td>
20089 </tr>
20090 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
20091 <td>189</td>
20092 <td>255</td>
20093 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
20094 <td>in_intr</td>
20095 <td>255</td>
20096 </tr>
20097 </tbody>
20098 </table>
20099 </div>
20100 <div class="section" id="global-events">
20101 <span id="pub-soc-am65x-sr2-global-events"></span><h2>Global Events<a class="headerlink" href="#global-events" title="Permalink to this headline">¶</a></h2>
20102 <p>This section describes AM65X_SR2 global events.  The global events are used in
20103 interrupt management based TISCI messages.</p>
20104 <div class="admonition warning">
20105 <p class="first admonition-title">Warning</p>
20106 <p class="last">Resources marked as reserved for use by DMSC <strong>cannot</strong> be assigned to a
20107 host within the RM Board Configuration resource assignment array.  The RM
20108 Board Configuration is rejected if an overlap with a reserved resource is
20109 detected.</p>
20110 </div>
20111 <table border="1" class="docutils">
20112 <colgroup>
20113 <col width="61%" />
20114 <col width="39%" />
20115 </colgroup>
20116 <thead valign="bottom">
20117 <tr class="row-odd"><th class="head">Global Event Name</th>
20118 <th class="head">Global Event Range</th>
20119 </tr>
20120 </thead>
20121 <tbody valign="top">
20122 <tr class="row-even"><td>NAVSS0_UDMASS_INTA0 SEVT
20123 (<strong>RESERVED BY SYSTEM FIRMWARE</strong>)</td>
20124 <td>0 to 15</td>
20125 </tr>
20126 <tr class="row-odd"><td>NAVSS0_UDMASS_INTA0 SEVT</td>
20127 <td>16 to 4607</td>
20128 </tr>
20129 <tr class="row-even"><td>MCU_NAVSS0_INTR_AGGR_0 SEVT
20130 (<strong>RESERVED BY SYSTEM FIRMWARE</strong>)</td>
20131 <td>16384 to 16391</td>
20132 </tr>
20133 <tr class="row-odd"><td>MCU_NAVSS0_INTR_AGGR_0 SEVT</td>
20134 <td>16392 to 17919</td>
20135 </tr>
20136 <tr class="row-even"><td>NAVSS0_MODSS_INTA0 SEVT</td>
20137 <td>20480 to 21503</td>
20138 </tr>
20139 <tr class="row-odd"><td>NAVSS0_MODSS_INTA1 SEVT</td>
20140 <td>22528 to 23551</td>
20141 </tr>
20142 <tr class="row-even"><td>NAVSS0_UDMASS_INTA0 MEVT</td>
20143 <td>32768 to 33279</td>
20144 </tr>
20145 <tr class="row-odd"><td>MCU_NAVSS0_INTR_AGGR_0 MEVT</td>
20146 <td>34816 to 34943</td>
20147 </tr>
20148 <tr class="row-even"><td>NAVSS0_UDMASS_INTA0 GEVT</td>
20149 <td>36864 to 37375</td>
20150 </tr>
20151 <tr class="row-odd"><td>MCU_NAVSS0_INTR_AGGR_0 GEVT</td>
20152 <td>39936 to 40191</td>
20153 </tr>
20154 <tr class="row-even"><td>NAVSS0_UDMAP0 TRIGGER</td>
20155 <td>49152 to 50175</td>
20156 </tr>
20157 <tr class="row-odd"><td>MCU_NAVSS0_UDMAP0 TRIGGER</td>
20158 <td>56320 to 56575</td>
20159 </tr>
20160 </tbody>
20161 </table>
20162 </div>
20163 <div class="section" id="event-based-interrupt-source-ids">
20164 <span id="pub-soc-am65x-sr2-event-int-src-list"></span><h2>Event-Based Interrupt Source IDs<a class="headerlink" href="#event-based-interrupt-source-ids" title="Permalink to this headline">¶</a></h2>
20165 <table border="1" class="docutils">
20166 <colgroup>
20167 <col width="25%" />
20168 <col width="11%" />
20169 <col width="40%" />
20170 <col width="23%" />
20171 </colgroup>
20172 <thead valign="bottom">
20173 <tr class="row-odd"><th class="head">Device Name</th>
20174 <th class="head">Device ID</th>
20175 <th class="head">Interrupt Source Name</th>
20176 <th class="head">Interrupt Source Index</th>
20177 </tr>
20178 </thead>
20179 <tbody valign="top">
20180 <tr class="row-even"><td>AM6_DEV_NAVSS0_RINGACC0</td>
20181 <td>187</td>
20182 <td>Ring events</td>
20183 <td>0 to 767</td>
20184 </tr>
20185 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_RINGACC0</td>
20186 <td>195</td>
20187 <td>Ring events</td>
20188 <td>0 to 255</td>
20189 </tr>
20190 <tr class="row-even"><td>AM6_DEV_NAVSS0_RINGACC0</td>
20191 <td>187</td>
20192 <td>Ring monitor events</td>
20193 <td>1024 to 1055</td>
20194 </tr>
20195 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_RINGACC0</td>
20196 <td>195</td>
20197 <td>Ring monitor events</td>
20198 <td>1024 to 1055</td>
20199 </tr>
20200 <tr class="row-even"><td>AM6_DEV_NAVSS0_RINGACC0</td>
20201 <td>187</td>
20202 <td>Ring global error event</td>
20203 <td>2048</td>
20204 </tr>
20205 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_RINGACC0</td>
20206 <td>195</td>
20207 <td>Ring global error event</td>
20208 <td>2048</td>
20209 </tr>
20210 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMAP0</td>
20211 <td>188</td>
20212 <td>UDMA transmit channel OES events</td>
20213 <td>0 to 151</td>
20214 </tr>
20215 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMAP0</td>
20216 <td>188</td>
20217 <td>UDMA transmit channel EOES events</td>
20218 <td>256 to 407</td>
20219 </tr>
20220 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMAP0</td>
20221 <td>188</td>
20222 <td>UDMA receive channel OES events</td>
20223 <td>512 to 661</td>
20224 </tr>
20225 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMAP0</td>
20226 <td>188</td>
20227 <td>UDMA receive channel EOES events</td>
20228 <td>768 to 917</td>
20229 </tr>
20230 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMAP0</td>
20231 <td>188</td>
20232 <td>UDMA global configuration invalid flow event</td>
20233 <td>1024</td>
20234 </tr>
20235 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_UDMAP0</td>
20236 <td>194</td>
20237 <td>UDMA transmit channel OES events</td>
20238 <td>0 to 47</td>
20239 </tr>
20240 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_UDMAP0</td>
20241 <td>194</td>
20242 <td>UDMA transmit channel EOES events</td>
20243 <td>256 to 303</td>
20244 </tr>
20245 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_UDMAP0</td>
20246 <td>194</td>
20247 <td>UDMA receive channel OES events</td>
20248 <td>512 to 559</td>
20249 </tr>
20250 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_UDMAP0</td>
20251 <td>194</td>
20252 <td>UDMA receive channel EOES events</td>
20253 <td>768 to 815</td>
20254 </tr>
20255 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_UDMAP0</td>
20256 <td>194</td>
20257 <td>UDMA global configuration invalid flow event</td>
20258 <td>1024</td>
20259 </tr>
20260 </tbody>
20261 </table>
20262 </div>
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