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184 <div class="section" id="am65x-sr2-psi-l-device-descriptions">
185 <h1>AM65X_SR2 PSI-L Device Descriptions<a class="headerlink" href="#am65x-sr2-psi-l-device-descriptions" title="Permalink to this headline">¶</a></h1>
186 <div class="section" id="introduction">
187 <h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
188 <p>This chapter provides information on the PSI-L devices in the AM65X_SR2 SoC.
189 Some System Firmware TISCI messages take device specific inputs. This chapter
190 provides information on the valid values for PSI-L TISCI message parameters.</p>
191 </div>
192 <div class="section" id="psi-l-proxy-device-ids">
193 <span id="pub-soc-am65x-sr2-psil-proxy-device-ids"></span><h2>PSI-L Proxy Device IDs<a class="headerlink" href="#psi-l-proxy-device-ids" title="Permalink to this headline">¶</a></h2>
194 <p>Some System Firmware TISCI message APIs require the PSI-L Proxy device ID be
195 provided as part of the request. Based on <a class="reference internal" href="devices.html"><span class="doc">AM65X_SR2 Device IDs</span></a>
196 these are the valid PSI-L Proxy device IDs.</p>
197 <table border="1" class="docutils">
198 <colgroup>
199 <col width="52%" />
200 <col width="48%" />
201 </colgroup>
202 <thead valign="bottom">
203 <tr class="row-odd"><th class="head">PSI-L Proxy Device Name</th>
204 <th class="head">PSI-L Proxy Device ID</th>
205 </tr>
206 </thead>
207 <tbody valign="top">
208 <tr class="row-even"><td>AM6_DEV_NAVSS0</td>
209 <td>118</td>
210 </tr>
211 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0</td>
212 <td>119</td>
213 </tr>
214 </tbody>
215 </table>
216 </div>
217 <div class="section" id="psi-l-source-and-destination-thread-ids">
218 <span id="pub-soc-am65x-sr2-psil-thread-ids"></span><h2>PSI-L Source and Destination Thread IDs<a class="headerlink" href="#psi-l-source-and-destination-thread-ids" title="Permalink to this headline">¶</a></h2>
219 <p>This section describes valid PSI-L source and destination thread IDs for each
220 thread type. The thread IDs are used in the PSI-L based TISCI messages.</p>
221 <div class="admonition warning">
222 <p class="first admonition-title">Warning</p>
223 <p class="last">PSI-L threads marked as reserved for use by DMSC <strong>cannot</strong> be linked to
224 another thread.</p>
225 </div>
226 <table border="1" class="docutils">
227 <colgroup>
228 <col width="66%" />
229 <col width="34%" />
230 </colgroup>
231 <thead valign="bottom">
232 <tr class="row-odd"><th class="head">Thread Type</th>
233 <th class="head">Thread Range</th>
234 </tr>
235 </thead>
236 <tbody valign="top">
237 <tr class="row-even"><td>udmap0_trstrm_tx</td>
238 <td>0x8 to 0x8</td>
239 </tr>
240 <tr class="row-odd"><td>udmap0_cfgstrm_tx</td>
241 <td>0x20 to 0x20</td>
242 </tr>
243 <tr class="row-even"><td>udmap0_tx
244 (<strong>Reserved by System Firmware</strong>)</td>
245 <td>0x1000 to 0x1000</td>
246 </tr>
247 <tr class="row-odd"><td>udmap0_tx</td>
248 <td>0x1001 to 0x1077</td>
249 </tr>
250 <tr class="row-even"><td>saul0_rx
251 (<strong>Reserved by System Firmware</strong>)</td>
252 <td>0x4000 to 0x4000</td>
253 </tr>
254 <tr class="row-odd"><td>saul0_rx</td>
255 <td>0x4001 to 0x4003</td>
256 </tr>
257 <tr class="row-even"><td>icssg0_rx</td>
258 <td>0x4100 to 0x4104</td>
259 </tr>
260 <tr class="row-odd"><td>icssg1_rx</td>
261 <td>0x4200 to 0x4204</td>
262 </tr>
263 <tr class="row-even"><td>icssg2_rx</td>
264 <td>0x4300 to 0x4304</td>
265 </tr>
266 <tr class="row-odd"><td>pdma_main0_mcasp0_rx</td>
267 <td>0x4400 to 0x4400</td>
268 </tr>
269 <tr class="row-even"><td>pdma_main0_mcasp1_rx</td>
270 <td>0x4401 to 0x4401</td>
271 </tr>
272 <tr class="row-odd"><td>pdma_main0_mcasp2_rx</td>
273 <td>0x4402 to 0x4402</td>
274 </tr>
275 <tr class="row-even"><td>pdma_main1_spi0_rx</td>
276 <td>0x4500 to 0x4503</td>
277 </tr>
278 <tr class="row-odd"><td>pdma_main1_spi1_rx</td>
279 <td>0x4504 to 0x4507</td>
280 </tr>
281 <tr class="row-even"><td>pdma_main1_spi2_rx</td>
282 <td>0x4508 to 0x450b</td>
283 </tr>
284 <tr class="row-odd"><td>pdma_main1_spi3_rx</td>
285 <td>0x450c to 0x450f</td>
286 </tr>
287 <tr class="row-even"><td>pdma_main1_spi4_rx</td>
288 <td>0x4510 to 0x4513</td>
289 </tr>
290 <tr class="row-odd"><td>pdma_main1_usart0_rx</td>
291 <td>0x4514 to 0x4514</td>
292 </tr>
293 <tr class="row-even"><td>pdma_main1_usart1_rx</td>
294 <td>0x4515 to 0x4515</td>
295 </tr>
296 <tr class="row-odd"><td>pdma_main1_usart2_rx</td>
297 <td>0x4516 to 0x4516</td>
298 </tr>
299 <tr class="row-even"><td>pdma_debug_mcu_rx</td>
300 <td>0x4600 to 0x4600</td>
301 </tr>
302 <tr class="row-odd"><td>pdma_debug_main_rx</td>
303 <td>0x4601 to 0x4601</td>
304 </tr>
305 <tr class="row-even"><td>pdma_debug_cc_rx</td>
306 <td>0x4602 to 0x4602</td>
307 </tr>
308 <tr class="row-odd"><td>cal0_rx</td>
309 <td>0x4700 to 0x4707</td>
310 </tr>
311 <tr class="row-even"><td>msmc0_rx</td>
312 <td>0x4800 to 0x481f</td>
313 </tr>
314 <tr class="row-odd"><td>udmap_tx</td>
315 <td>0x6000 to 0x602f</td>
316 </tr>
317 <tr class="row-even"><td>pdma_cpsw0_rx</td>
318 <td>0x7000 to 0x7000</td>
319 </tr>
320 <tr class="row-odd"><td>pdma_mcu0_adc12_rx</td>
321 <td>0x7100 to 0x7103</td>
322 </tr>
323 <tr class="row-even"><td>pdma_mcu1_spi0_rx</td>
324 <td>0x7200 to 0x7203</td>
325 </tr>
326 <tr class="row-odd"><td>pdma_mcu1_spi1_rx</td>
327 <td>0x7204 to 0x7207</td>
328 </tr>
329 <tr class="row-even"><td>pdma_mcu1_spi2_rx</td>
330 <td>0x7208 to 0x720b</td>
331 </tr>
332 <tr class="row-odd"><td>pdma_mcu1_mcan0_rx</td>
333 <td>0x720c to 0x720e</td>
334 </tr>
335 <tr class="row-even"><td>pdma_mcu1_mcan1_rx</td>
336 <td>0x720f to 0x7211</td>
337 </tr>
338 <tr class="row-odd"><td>pdma_mcu1_usart0_rx</td>
339 <td>0x7212 to 0x7212</td>
340 </tr>
341 <tr class="row-even"><td>udmap0_rx
342 (<strong>Reserved by System Firmware</strong>)</td>
343 <td>0x9000 to 0x9001</td>
344 </tr>
345 <tr class="row-odd"><td>udmap0_rx</td>
346 <td>0x9002 to 0x9095</td>
347 </tr>
348 <tr class="row-even"><td>saul0_tx
349 (<strong>Reserved by System Firmware</strong>)</td>
350 <td>0xc000 to 0xc000</td>
351 </tr>
352 <tr class="row-odd"><td>saul0_tx</td>
353 <td>0xc001 to 0xc001</td>
354 </tr>
355 <tr class="row-even"><td>icssg0_tx</td>
356 <td>0xc100 to 0xc108</td>
357 </tr>
358 <tr class="row-odd"><td>icssg1_tx</td>
359 <td>0xc200 to 0xc208</td>
360 </tr>
361 <tr class="row-even"><td>icssg2_tx</td>
362 <td>0xc300 to 0xc308</td>
363 </tr>
364 <tr class="row-odd"><td>pdma_main0_mcasp0_tx</td>
365 <td>0xc400 to 0xc400</td>
366 </tr>
367 <tr class="row-even"><td>pdma_main0_mcasp1_tx</td>
368 <td>0xc401 to 0xc401</td>
369 </tr>
370 <tr class="row-odd"><td>pdma_main0_mcasp2_tx</td>
371 <td>0xc402 to 0xc402</td>
372 </tr>
373 <tr class="row-even"><td>pdma_main1_spi0_tx</td>
374 <td>0xc500 to 0xc503</td>
375 </tr>
376 <tr class="row-odd"><td>pdma_main1_spi1_tx</td>
377 <td>0xc504 to 0xc507</td>
378 </tr>
379 <tr class="row-even"><td>pdma_main1_spi2_tx</td>
380 <td>0xc508 to 0xc50b</td>
381 </tr>
382 <tr class="row-odd"><td>pdma_main1_spi3_tx</td>
383 <td>0xc50c to 0xc50f</td>
384 </tr>
385 <tr class="row-even"><td>pdma_main1_spi4_tx</td>
386 <td>0xc510 to 0xc513</td>
387 </tr>
388 <tr class="row-odd"><td>pdma_main1_usart0_tx</td>
389 <td>0xc514 to 0xc514</td>
390 </tr>
391 <tr class="row-even"><td>pdma_main1_usart1_tx</td>
392 <td>0xc515 to 0xc515</td>
393 </tr>
394 <tr class="row-odd"><td>pdma_main1_usart2_tx</td>
395 <td>0xc516 to 0xc516</td>
396 </tr>
397 <tr class="row-even"><td>msmc0_tx</td>
398 <td>0xc800 to 0xc81f</td>
399 </tr>
400 <tr class="row-odd"><td>udmap_rx</td>
401 <td>0xe000 to 0xe02f</td>
402 </tr>
403 <tr class="row-even"><td>pdma_cpsw0_tx</td>
404 <td>0xf000 to 0xf007</td>
405 </tr>
406 <tr class="row-odd"><td>pdma_mcu0_adc12_tx</td>
407 <td>0xf100 to 0xf103</td>
408 </tr>
409 <tr class="row-even"><td>pdma_mcu1_spi0_tx</td>
410 <td>0xf200 to 0xf203</td>
411 </tr>
412 <tr class="row-odd"><td>pdma_mcu1_spi1_tx</td>
413 <td>0xf204 to 0xf207</td>
414 </tr>
415 <tr class="row-even"><td>pdma_mcu1_spi2_tx</td>
416 <td>0xf208 to 0xf20b</td>
417 </tr>
418 <tr class="row-odd"><td>pdma_mcu1_mcan0_tx</td>
419 <td>0xf20c to 0xf20e</td>
420 </tr>
421 <tr class="row-even"><td>pdma_mcu1_mcan1_tx</td>
422 <td>0xf20f to 0xf211</td>
423 </tr>
424 <tr class="row-odd"><td>pdma_mcu1_usart0_tx</td>
425 <td>0xf212 to 0xf212</td>
426 </tr>
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