packages/ti/drv/sciclient/soc/sysfw/binaries/system-firmware-public-documentation/5_soc_doc/am6x/devices.html

   1
   2
   3 <!DOCTYPE html>
   4 <!--[if IE 8]><html class="no-js lt-ie9" lang="en" > <![endif]-->
   5 <!--[if gt IE 8]><!--> <html class="no-js" lang="en" > <!--<![endif]-->
   6 <head>
   7   <meta charset="utf-8">
   8
   9   <meta name="viewport" content="width=device-width, initial-scale=1.0">
  10
  11   <title>AM6 Devices Descriptions &mdash; TISCI User Guide</title>
  12
  13
  14
  15
  16     <link rel="shortcut icon" href="../../_static/favicon.ico"/>
  17
  18
  19
  20
  21
  22
  23
  24
  25
  26
  27
  28
  29     <link rel="stylesheet" href="../../_static/css/theme.css" type="text/css" />
  30
  31
  32
  33     <link rel="stylesheet" href="../../_static/theme_overrides.css" type="text/css" />
  34
  35
  36
  37         <link rel="index" title="Index"
  38               href="../../genindex.html"/>
  39         <link rel="search" title="Search" href="../../search.html"/>
  40     <link rel="top" title="TISCI User Guide" href="../../index.html"/>
  41         <link rel="up" title="Chapter 5: SoC Family Specific Documentation" href="../index.html"/>
  42         <link rel="next" title="AM6 Clock Identifiers" href="clocks.html"/>
  43         <link rel="prev" title="AM6 Host Descriptions" href="hosts.html"/>
  44
  45
  46   <script src="../../_static/js/modernizr.min.js"></script>
  47
  48 </head>
  49
  50 <body class="wy-body-for-nav" role="document">
  51   <header id="tiHeader">
  52     <div class="top">
  53       <ul>
  54         <li id="top_logo">
  55           <a href="http://www.ti.com">
  56             <img src="../../_static/img/ti_logo.png"/>
  57           </a>
  58         </li>
  59       </ul>
  60     </div>
  61     <div class="nav"></div>
  62   </header>
  63   <div class="wy-grid-for-nav">
  64
  65
  66     <nav data-toggle="wy-nav-shift" class="wy-nav-side">
  67       <div class="wy-side-scroll">
  68         <div class="wy-side-nav-search">
  69
  70
  71
  72             <a href="../../index.html" class="icon icon-home"> TISCI
  73
  74
  75
  76           </a>
  77
  78
  79
  80
  81               <div class="version">
  82                 20.05.00
  83               </div>
  84
  85
  86
  87
  88 <div role="search">
  89   <form id="rtd-search-form" class="wy-form" action="../../search.html" method="get">
  90     <input type="text" name="q" placeholder="Search docs" />
  91     <input type="hidden" name="check_keywords" value="yes" />
  92     <input type="hidden" name="area" value="default" />
  93   </form>
  94 </div>
  95
  96
  97         </div>
  98
  99         <div class="wy-menu wy-menu-vertical" data-spy="affix" role="navigation" aria-label="main navigation">
 100
 101
 102
 103                 <ul class="current">
 104 <li class="toctree-l1"><a class="reference internal" href="../../1_intro/index.html">Chapter 1: Introduction</a></li>
 105 <li class="toctree-l1"><a class="reference internal" href="../../2_tisci_msgs/index.html">Chapter 2: TISCI Message Documentation</a></li>
 106 <li class="toctree-l1"><a class="reference internal" href="../../3_boardcfg/index.html">Chapter 3: Board Configuration</a></li>
 107 <li class="toctree-l1"><a class="reference internal" href="../../4_trace/index.html">Chapter 4: Interpreting Trace Data</a></li>
 108 <li class="toctree-l1 current"><a class="reference internal" href="../index.html">Chapter 5: SoC Family Specific Documentation</a><ul class="current">
 109 <li class="toctree-l2 current"><a class="reference internal" href="../index.html#am65x-sr1">AM65x SR1</a><ul class="current">
 110 <li class="toctree-l3"><a class="reference internal" href="hosts.html">AM6 Host Descriptions</a></li>
 111 <li class="toctree-l3 current"><a class="current reference internal" href="#">AM6 Devices Descriptions</a><ul>
 112 <li class="toctree-l4"><a class="reference internal" href="#introduction">Introduction</a></li>
 113 <li class="toctree-l4"><a class="reference internal" href="#enumeration-of-device-ids">Enumeration of Device IDs</a></li>
 114 </ul>
 115 </li>
 116 <li class="toctree-l3"><a class="reference internal" href="clocks.html">AM6 Clock Identifiers</a></li>
 117 <li class="toctree-l3"><a class="reference internal" href="pll_data.html">AM6 PLL Defaults</a></li>
 118 <li class="toctree-l3"><a class="reference internal" href="resasg_types.html">AM6 Board Configuration Resource Assignment Type Descriptions</a></li>
 119 <li class="toctree-l3"><a class="reference internal" href="interrupt_cfg.html">AM6 Interrupt Management Device Descriptions</a></li>
 120 <li class="toctree-l3"><a class="reference internal" href="ra_cfg.html">AM6 Ring Accelerator Device Descriptions</a></li>
 121 <li class="toctree-l3"><a class="reference internal" href="dma_cfg.html">AM6 DMA Device Descriptions</a></li>
 122 <li class="toctree-l3"><a class="reference internal" href="psil_cfg.html">AM6 PSI-L Device Descriptions</a></li>
 123 <li class="toctree-l3"><a class="reference internal" href="proxy_cfg.html">AM6 Proxy Device Descriptions</a></li>
 124 <li class="toctree-l3"><a class="reference internal" href="sec_proxy.html">AM6 Secure Proxy Descriptions</a></li>
 125 <li class="toctree-l3"><a class="reference internal" href="processors.html">AM6 Processor Descriptions</a></li>
 126 <li class="toctree-l3"><a class="reference internal" href="runtime_keystore.html">AM6 Runtime Keystore</a></li>
 127 <li class="toctree-l3"><a class="reference internal" href="firewalls.html">AM6 Firewall Descriptions</a></li>
 128 <li class="toctree-l3"><a class="reference internal" href="soc_devgrps.html">AM6 Device Group descriptions</a></li>
 129 <li class="toctree-l3"><a class="reference internal" href="extended_otp.html">AM65x Extended OTP Information</a></li>
 130 </ul>
 131 </li>
 132 <li class="toctree-l2"><a class="reference internal" href="../index.html#am65x-sr2">AM65x SR2</a></li>
 133 <li class="toctree-l2"><a class="reference internal" href="../index.html#am64x">AM64x</a></li>
 134 <li class="toctree-l2"><a class="reference internal" href="../index.html#j721e">J721E</a></li>
 135 </ul>
 136 </li>
 137 <li class="toctree-l1"><a class="reference internal" href="../../6_topic_user_guides/index.html">Chapter 6: Topic User Guides</a></li>
 138 </ul>
 139
 140
 141
 142         </div>
 143       </div>
 144     </nav>
 145
 146     <section data-toggle="wy-nav-shift" class="wy-nav-content-wrap">
 147
 148
 149       <nav class="wy-nav-top" role="navigation" aria-label="top navigation">
 150         <i data-toggle="wy-nav-top" class="fa fa-bars"></i>
 151         <a href="../../index.html">TISCI</a>
 152       </nav>
 153
 154
 155
 156       <div class="wy-nav-content">
 157         <div class="rst-content">
 158
 159
 160
 161
 162
 163
 164 <div role="navigation" aria-label="breadcrumbs navigation">
 165   <ul class="wy-breadcrumbs">
 166     <li><a href="../../index.html">Docs</a> &raquo;</li>
 167
 168           <li><a href="../index.html">Chapter 5: SoC Family Specific Documentation</a> &raquo;</li>
 169
 170     <li>AM6 Devices Descriptions</li>
 171       <li class="wy-breadcrumbs-aside">
 172
 173
 174
 175       </li>
 176   </ul>
 177   <hr/>
 178 </div>
 179           <div role="main" class="document" itemscope="itemscope" itemtype="http://schema.org/Article">
 180            <div itemprop="articleBody">
 181
 182   <div class="section" id="am6-devices-descriptions">
 183 <h1>AM6 Devices Descriptions<a class="headerlink" href="#am6-devices-descriptions" title="Permalink to this headline">¶</a></h1>
 184 <div class="section" id="introduction">
 185 <span id="soc-doc-am6-public-devices-desc-intro"></span><h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
 186 <p>This chapter provides information on Device IDs that are permitted in the am6
 187 SoC.  The device IDs represent SoC subsystems that can be modified via DMSC
 188 TISCI message APIs.  Some Secure, Power, and Resource Management DMSC subsystem
 189 TISCI message APIs define a device ID as a parameter allowing a user to specify
 190 management of a particular SoC subsystem.</p>
 191 </div>
 192 <div class="section" id="enumeration-of-device-ids">
 193 <span id="soc-doc-am6-public-devices-desc-device-list"></span><h2>Enumeration of Device IDs<a class="headerlink" href="#enumeration-of-device-ids" title="Permalink to this headline">¶</a></h2>
 194 <table border="1" class="docutils">
 195 <colgroup>
 196 <col width="21%" />
 197 <col width="79%" />
 198 </colgroup>
 199 <thead valign="bottom">
 200 <tr class="row-odd"><th class="head">Device ID</th>
 201 <th class="head">Device Name</th>
 202 </tr>
 203 </thead>
 204 <tbody valign="top">
 205 <tr class="row-even"><td>0</td>
 206 <td>AM6_DEV_MCU_ADC0</td>
 207 </tr>
 208 <tr class="row-odd"><td>1</td>
 209 <td>AM6_DEV_MCU_ADC1</td>
 210 </tr>
 211 <tr class="row-even"><td>2</td>
 212 <td>AM6_DEV_CAL0</td>
 213 </tr>
 214 <tr class="row-odd"><td>3</td>
 215 <td>AM6_DEV_CMPEVENT_INTRTR0</td>
 216 </tr>
 217 <tr class="row-even"><td>5</td>
 218 <td>AM6_DEV_MCU_CPSW0</td>
 219 </tr>
 220 <tr class="row-odd"><td>6</td>
 221 <td>AM6_DEV_CPT2_AGGR0</td>
 222 </tr>
 223 <tr class="row-even"><td>7</td>
 224 <td>AM6_DEV_MCU_CPT2_AGGR0</td>
 225 </tr>
 226 <tr class="row-odd"><td>8</td>
 227 <td>AM6_DEV_STM0</td>
 228 </tr>
 229 <tr class="row-even"><td>9</td>
 230 <td>AM6_DEV_DCC0</td>
 231 </tr>
 232 <tr class="row-odd"><td>10</td>
 233 <td>AM6_DEV_DCC1</td>
 234 </tr>
 235 <tr class="row-even"><td>11</td>
 236 <td>AM6_DEV_DCC2</td>
 237 </tr>
 238 <tr class="row-odd"><td>12</td>
 239 <td>AM6_DEV_DCC3</td>
 240 </tr>
 241 <tr class="row-even"><td>13</td>
 242 <td>AM6_DEV_DCC4</td>
 243 </tr>
 244 <tr class="row-odd"><td>14</td>
 245 <td>AM6_DEV_DCC5</td>
 246 </tr>
 247 <tr class="row-even"><td>15</td>
 248 <td>AM6_DEV_DCC6</td>
 249 </tr>
 250 <tr class="row-odd"><td>16</td>
 251 <td>AM6_DEV_DCC7</td>
 252 </tr>
 253 <tr class="row-even"><td>17</td>
 254 <td>AM6_DEV_MCU_DCC0</td>
 255 </tr>
 256 <tr class="row-odd"><td>18</td>
 257 <td>AM6_DEV_MCU_DCC1</td>
 258 </tr>
 259 <tr class="row-even"><td>19</td>
 260 <td>AM6_DEV_MCU_DCC2</td>
 261 </tr>
 262 <tr class="row-odd"><td>20</td>
 263 <td>AM6_DEV_DDRSS0</td>
 264 </tr>
 265 <tr class="row-even"><td>21</td>
 266 <td>AM6_DEV_DEBUGSS_WRAP0</td>
 267 </tr>
 268 <tr class="row-odd"><td>22</td>
 269 <td>AM6_DEV_WKUP_DMSC0</td>
 270 </tr>
 271 <tr class="row-even"><td>23</td>
 272 <td>AM6_DEV_TIMER0</td>
 273 </tr>
 274 <tr class="row-odd"><td>24</td>
 275 <td>AM6_DEV_TIMER1</td>
 276 </tr>
 277 <tr class="row-even"><td>25</td>
 278 <td>AM6_DEV_TIMER10</td>
 279 </tr>
 280 <tr class="row-odd"><td>26</td>
 281 <td>AM6_DEV_TIMER11</td>
 282 </tr>
 283 <tr class="row-even"><td>27</td>
 284 <td>AM6_DEV_TIMER2</td>
 285 </tr>
 286 <tr class="row-odd"><td>28</td>
 287 <td>AM6_DEV_TIMER3</td>
 288 </tr>
 289 <tr class="row-even"><td>29</td>
 290 <td>AM6_DEV_TIMER4</td>
 291 </tr>
 292 <tr class="row-odd"><td>30</td>
 293 <td>AM6_DEV_TIMER5</td>
 294 </tr>
 295 <tr class="row-even"><td>31</td>
 296 <td>AM6_DEV_TIMER6</td>
 297 </tr>
 298 <tr class="row-odd"><td>32</td>
 299 <td>AM6_DEV_TIMER7</td>
 300 </tr>
 301 <tr class="row-even"><td>33</td>
 302 <td>AM6_DEV_TIMER8</td>
 303 </tr>
 304 <tr class="row-odd"><td>34</td>
 305 <td>AM6_DEV_TIMER9</td>
 306 </tr>
 307 <tr class="row-even"><td>35</td>
 308 <td>AM6_DEV_MCU_TIMER0</td>
 309 </tr>
 310 <tr class="row-odd"><td>36</td>
 311 <td>AM6_DEV_MCU_TIMER1</td>
 312 </tr>
 313 <tr class="row-even"><td>37</td>
 314 <td>AM6_DEV_MCU_TIMER2</td>
 315 </tr>
 316 <tr class="row-odd"><td>38</td>
 317 <td>AM6_DEV_MCU_TIMER3</td>
 318 </tr>
 319 <tr class="row-even"><td>39</td>
 320 <td>AM6_DEV_ECAP0</td>
 321 </tr>
 322 <tr class="row-odd"><td>40</td>
 323 <td>AM6_DEV_EHRPWM0</td>
 324 </tr>
 325 <tr class="row-even"><td>41</td>
 326 <td>AM6_DEV_EHRPWM1</td>
 327 </tr>
 328 <tr class="row-odd"><td>42</td>
 329 <td>AM6_DEV_EHRPWM2</td>
 330 </tr>
 331 <tr class="row-even"><td>43</td>
 332 <td>AM6_DEV_EHRPWM3</td>
 333 </tr>
 334 <tr class="row-odd"><td>44</td>
 335 <td>AM6_DEV_EHRPWM4</td>
 336 </tr>
 337 <tr class="row-even"><td>45</td>
 338 <td>AM6_DEV_EHRPWM5</td>
 339 </tr>
 340 <tr class="row-odd"><td>46</td>
 341 <td>AM6_DEV_ELM0</td>
 342 </tr>
 343 <tr class="row-even"><td>47</td>
 344 <td>AM6_DEV_MMCSD0</td>
 345 </tr>
 346 <tr class="row-odd"><td>48</td>
 347 <td>AM6_DEV_MMCSD1</td>
 348 </tr>
 349 <tr class="row-even"><td>49</td>
 350 <td>AM6_DEV_EQEP0</td>
 351 </tr>
 352 <tr class="row-odd"><td>50</td>
 353 <td>AM6_DEV_EQEP1</td>
 354 </tr>
 355 <tr class="row-even"><td>51</td>
 356 <td>AM6_DEV_EQEP2</td>
 357 </tr>
 358 <tr class="row-odd"><td>52</td>
 359 <td>AM6_DEV_ESM0</td>
 360 </tr>
 361 <tr class="row-even"><td>53</td>
 362 <td>AM6_DEV_MCU_ESM0</td>
 363 </tr>
 364 <tr class="row-odd"><td>54</td>
 365 <td>AM6_DEV_WKUP_ESM0</td>
 366 </tr>
 367 <tr class="row-even"><td>56</td>
 368 <td>AM6_DEV_GIC0</td>
 369 </tr>
 370 <tr class="row-odd"><td>57</td>
 371 <td>AM6_DEV_GPIO0</td>
 372 </tr>
 373 <tr class="row-even"><td>58</td>
 374 <td>AM6_DEV_GPIO1</td>
 375 </tr>
 376 <tr class="row-odd"><td>59</td>
 377 <td>AM6_DEV_WKUP_GPIO0</td>
 378 </tr>
 379 <tr class="row-even"><td>60</td>
 380 <td>AM6_DEV_GPMC0</td>
 381 </tr>
 382 <tr class="row-odd"><td>61</td>
 383 <td>AM6_DEV_GTC0</td>
 384 </tr>
 385 <tr class="row-even"><td>62</td>
 386 <td>AM6_DEV_PRU_ICSSG0</td>
 387 </tr>
 388 <tr class="row-odd"><td>63</td>
 389 <td>AM6_DEV_PRU_ICSSG1</td>
 390 </tr>
 391 <tr class="row-even"><td>64</td>
 392 <td>AM6_DEV_PRU_ICSSG2</td>
 393 </tr>
 394 <tr class="row-odd"><td>65</td>
 395 <td>AM6_DEV_GPU0</td>
 396 </tr>
 397 <tr class="row-even"><td>66</td>
 398 <td>AM6_DEV_CCDEBUGSS0</td>
 399 </tr>
 400 <tr class="row-odd"><td>67</td>
 401 <td>AM6_DEV_DSS0</td>
 402 </tr>
 403 <tr class="row-even"><td>68</td>
 404 <td>AM6_DEV_DEBUGSS0</td>
 405 </tr>
 406 <tr class="row-odd"><td>69</td>
 407 <td>AM6_DEV_EFUSE0</td>
 408 </tr>
 409 <tr class="row-even"><td>70</td>
 410 <td>AM6_DEV_PSC0</td>
 411 </tr>
 412 <tr class="row-odd"><td>71</td>
 413 <td>AM6_DEV_MCU_DEBUGSS0</td>
 414 </tr>
 415 <tr class="row-even"><td>72</td>
 416 <td>AM6_DEV_MCU_EFUSE0</td>
 417 </tr>
 418 <tr class="row-odd"><td>73</td>
 419 <td>AM6_DEV_PBIST0</td>
 420 </tr>
 421 <tr class="row-even"><td>74</td>
 422 <td>AM6_DEV_PBIST1</td>
 423 </tr>
 424 <tr class="row-odd"><td>75</td>
 425 <td>AM6_DEV_MCU_PBIST0</td>
 426 </tr>
 427 <tr class="row-even"><td>76</td>
 428 <td>AM6_DEV_PLLCTRL0</td>
 429 </tr>
 430 <tr class="row-odd"><td>77</td>
 431 <td>AM6_DEV_WKUP_PLLCTRL0</td>
 432 </tr>
 433 <tr class="row-even"><td>78</td>
 434 <td>AM6_DEV_MCU_ROM0</td>
 435 </tr>
 436 <tr class="row-odd"><td>79</td>
 437 <td>AM6_DEV_WKUP_PSC0</td>
 438 </tr>
 439 <tr class="row-even"><td>80</td>
 440 <td>AM6_DEV_WKUP_VTM0</td>
 441 </tr>
 442 <tr class="row-odd"><td>81</td>
 443 <td>AM6_DEV_DEBUGSUSPENDRTR0</td>
 444 </tr>
 445 <tr class="row-even"><td>82</td>
 446 <td>AM6_DEV_CBASS0</td>
 447 </tr>
 448 <tr class="row-odd"><td>83</td>
 449 <td>AM6_DEV_CBASS_DEBUG0</td>
 450 </tr>
 451 <tr class="row-even"><td>84</td>
 452 <td>AM6_DEV_CBASS_FW0</td>
 453 </tr>
 454 <tr class="row-odd"><td>85</td>
 455 <td>AM6_DEV_CBASS_INFRA0</td>
 456 </tr>
 457 <tr class="row-even"><td>86</td>
 458 <td>AM6_DEV_ECC_AGGR0</td>
 459 </tr>
 460 <tr class="row-odd"><td>87</td>
 461 <td>AM6_DEV_ECC_AGGR1</td>
 462 </tr>
 463 <tr class="row-even"><td>88</td>
 464 <td>AM6_DEV_ECC_AGGR2</td>
 465 </tr>
 466 <tr class="row-odd"><td>89</td>
 467 <td>AM6_DEV_MCU_CBASS0</td>
 468 </tr>
 469 <tr class="row-even"><td>90</td>
 470 <td>AM6_DEV_MCU_CBASS_DEBUG0</td>
 471 </tr>
 472 <tr class="row-odd"><td>91</td>
 473 <td>AM6_DEV_MCU_CBASS_FW0</td>
 474 </tr>
 475 <tr class="row-even"><td>92</td>
 476 <td>AM6_DEV_MCU_ECC_AGGR0</td>
 477 </tr>
 478 <tr class="row-odd"><td>93</td>
 479 <td>AM6_DEV_MCU_ECC_AGGR1</td>
 480 </tr>
 481 <tr class="row-even"><td>94</td>
 482 <td>AM6_DEV_WKUP_CBASS0</td>
 483 </tr>
 484 <tr class="row-odd"><td>95</td>
 485 <td>AM6_DEV_WKUP_ECC_AGGR0</td>
 486 </tr>
 487 <tr class="row-even"><td>96</td>
 488 <td>AM6_DEV_WKUP_CBASS_FW0</td>
 489 </tr>
 490 <tr class="row-odd"><td>97</td>
 491 <td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
 492 </tr>
 493 <tr class="row-even"><td>98</td>
 494 <td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
 495 </tr>
 496 <tr class="row-odd"><td>99</td>
 497 <td>AM6_DEV_CTRL_MMR0</td>
 498 </tr>
 499 <tr class="row-even"><td>100</td>
 500 <td>AM6_DEV_GPIOMUX_INTRTR0</td>
 501 </tr>
 502 <tr class="row-odd"><td>101</td>
 503 <td>AM6_DEV_PLL_MMR0</td>
 504 </tr>
 505 <tr class="row-even"><td>102</td>
 506 <td>AM6_DEV_MCU_MCAN0</td>
 507 </tr>
 508 <tr class="row-odd"><td>103</td>
 509 <td>AM6_DEV_MCU_MCAN1</td>
 510 </tr>
 511 <tr class="row-even"><td>104</td>
 512 <td>AM6_DEV_MCASP0</td>
 513 </tr>
 514 <tr class="row-odd"><td>105</td>
 515 <td>AM6_DEV_MCASP1</td>
 516 </tr>
 517 <tr class="row-even"><td>106</td>
 518 <td>AM6_DEV_MCASP2</td>
 519 </tr>
 520 <tr class="row-odd"><td>107</td>
 521 <td>AM6_DEV_MCU_CTRL_MMR0</td>
 522 </tr>
 523 <tr class="row-even"><td>108</td>
 524 <td>AM6_DEV_MCU_PLL_MMR0</td>
 525 </tr>
 526 <tr class="row-odd"><td>109</td>
 527 <td>AM6_DEV_MCU_SEC_MMR0</td>
 528 </tr>
 529 <tr class="row-even"><td>110</td>
 530 <td>AM6_DEV_I2C0</td>
 531 </tr>
 532 <tr class="row-odd"><td>111</td>
 533 <td>AM6_DEV_I2C1</td>
 534 </tr>
 535 <tr class="row-even"><td>112</td>
 536 <td>AM6_DEV_I2C2</td>
 537 </tr>
 538 <tr class="row-odd"><td>113</td>
 539 <td>AM6_DEV_I2C3</td>
 540 </tr>
 541 <tr class="row-even"><td>114</td>
 542 <td>AM6_DEV_MCU_I2C0</td>
 543 </tr>
 544 <tr class="row-odd"><td>115</td>
 545 <td>AM6_DEV_WKUP_I2C0</td>
 546 </tr>
 547 <tr class="row-even"><td>116</td>
 548 <td>AM6_DEV_MCU_MSRAM0</td>
 549 </tr>
 550 <tr class="row-odd"><td>117</td>
 551 <td>AM6_DEV_DFTSS0</td>
 552 </tr>
 553 <tr class="row-even"><td>118</td>
 554 <td>AM6_DEV_NAVSS0</td>
 555 </tr>
 556 <tr class="row-odd"><td>119</td>
 557 <td>AM6_DEV_MCU_NAVSS0</td>
 558 </tr>
 559 <tr class="row-even"><td>120</td>
 560 <td>AM6_DEV_PCIE0</td>
 561 </tr>
 562 <tr class="row-odd"><td>121</td>
 563 <td>AM6_DEV_PCIE1</td>
 564 </tr>
 565 <tr class="row-even"><td>122</td>
 566 <td>AM6_DEV_PDMA_DEBUG0</td>
 567 </tr>
 568 <tr class="row-odd"><td>123</td>
 569 <td>AM6_DEV_PDMA0</td>
 570 </tr>
 571 <tr class="row-even"><td>124</td>
 572 <td>AM6_DEV_PDMA1</td>
 573 </tr>
 574 <tr class="row-odd"><td>125</td>
 575 <td>AM6_DEV_MCU_PDMA0</td>
 576 </tr>
 577 <tr class="row-even"><td>126</td>
 578 <td>AM6_DEV_MCU_PDMA1</td>
 579 </tr>
 580 <tr class="row-odd"><td>127</td>
 581 <td>AM6_DEV_MCU_PSRAM0</td>
 582 </tr>
 583 <tr class="row-even"><td>128</td>
 584 <td>AM6_DEV_PSRAMECC0</td>
 585 </tr>
 586 <tr class="row-odd"><td>129</td>
 587 <td>AM6_DEV_MCU_ARMSS0</td>
 588 </tr>
 589 <tr class="row-even"><td>130</td>
 590 <td>AM6_DEV_RTI0</td>
 591 </tr>
 592 <tr class="row-odd"><td>131</td>
 593 <td>AM6_DEV_RTI1</td>
 594 </tr>
 595 <tr class="row-even"><td>132</td>
 596 <td>AM6_DEV_RTI2</td>
 597 </tr>
 598 <tr class="row-odd"><td>133</td>
 599 <td>AM6_DEV_RTI3</td>
 600 </tr>
 601 <tr class="row-even"><td>134</td>
 602 <td>AM6_DEV_MCU_RTI0</td>
 603 </tr>
 604 <tr class="row-odd"><td>135</td>
 605 <td>AM6_DEV_MCU_RTI1</td>
 606 </tr>
 607 <tr class="row-even"><td>136</td>
 608 <td>AM6_DEV_SA2_UL0</td>
 609 </tr>
 610 <tr class="row-odd"><td>137</td>
 611 <td>AM6_DEV_MCSPI0</td>
 612 </tr>
 613 <tr class="row-even"><td>138</td>
 614 <td>AM6_DEV_MCSPI1</td>
 615 </tr>
 616 <tr class="row-odd"><td>139</td>
 617 <td>AM6_DEV_MCSPI2</td>
 618 </tr>
 619 <tr class="row-even"><td>140</td>
 620 <td>AM6_DEV_MCSPI3</td>
 621 </tr>
 622 <tr class="row-odd"><td>141</td>
 623 <td>AM6_DEV_MCSPI4</td>
 624 </tr>
 625 <tr class="row-even"><td>142</td>
 626 <td>AM6_DEV_MCU_MCSPI0</td>
 627 </tr>
 628 <tr class="row-odd"><td>143</td>
 629 <td>AM6_DEV_MCU_MCSPI1</td>
 630 </tr>
 631 <tr class="row-even"><td>144</td>
 632 <td>AM6_DEV_MCU_MCSPI2</td>
 633 </tr>
 634 <tr class="row-odd"><td>145</td>
 635 <td>AM6_DEV_TIMESYNC_INTRTR0</td>
 636 </tr>
 637 <tr class="row-even"><td>146</td>
 638 <td>AM6_DEV_UART0</td>
 639 </tr>
 640 <tr class="row-odd"><td>147</td>
 641 <td>AM6_DEV_UART1</td>
 642 </tr>
 643 <tr class="row-even"><td>148</td>
 644 <td>AM6_DEV_UART2</td>
 645 </tr>
 646 <tr class="row-odd"><td>149</td>
 647 <td>AM6_DEV_MCU_UART0</td>
 648 </tr>
 649 <tr class="row-even"><td>150</td>
 650 <td>AM6_DEV_WKUP_UART0</td>
 651 </tr>
 652 <tr class="row-odd"><td>151</td>
 653 <td>AM6_DEV_USB3SS0</td>
 654 </tr>
 655 <tr class="row-even"><td>152</td>
 656 <td>AM6_DEV_USB3SS1</td>
 657 </tr>
 658 <tr class="row-odd"><td>153</td>
 659 <td>AM6_DEV_SERDES0</td>
 660 </tr>
 661 <tr class="row-even"><td>154</td>
 662 <td>AM6_DEV_SERDES1</td>
 663 </tr>
 664 <tr class="row-odd"><td>155</td>
 665 <td>AM6_DEV_WKUP_CTRL_MMR0</td>
 666 </tr>
 667 <tr class="row-even"><td>156</td>
 668 <td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
 669 </tr>
 670 <tr class="row-odd"><td>157</td>
 671 <td>AM6_DEV_BOARD0</td>
 672 </tr>
 673 <tr class="row-even"><td>159</td>
 674 <td>AM6_DEV_MCU_ARMSS0_CPU0</td>
 675 </tr>
 676 <tr class="row-odd"><td>161</td>
 677 <td>AM6_DEV_WKUP_DMSC0_CORTEX_M3_0</td>
 678 </tr>
 679 <tr class="row-even"><td>163</td>
 680 <td>AM6_DEV_NAVSS0_CPTS0</td>
 681 </tr>
 682 <tr class="row-odd"><td>164</td>
 683 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0</td>
 684 </tr>
 685 <tr class="row-even"><td>165</td>
 686 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1</td>
 687 </tr>
 688 <tr class="row-odd"><td>166</td>
 689 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2</td>
 690 </tr>
 691 <tr class="row-even"><td>167</td>
 692 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3</td>
 693 </tr>
 694 <tr class="row-odd"><td>168</td>
 695 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4</td>
 696 </tr>
 697 <tr class="row-even"><td>169</td>
 698 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5</td>
 699 </tr>
 700 <tr class="row-odd"><td>170</td>
 701 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6</td>
 702 </tr>
 703 <tr class="row-even"><td>171</td>
 704 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7</td>
 705 </tr>
 706 <tr class="row-odd"><td>172</td>
 707 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8</td>
 708 </tr>
 709 <tr class="row-even"><td>173</td>
 710 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9</td>
 711 </tr>
 712 <tr class="row-odd"><td>174</td>
 713 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10</td>
 714 </tr>
 715 <tr class="row-even"><td>175</td>
 716 <td>AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11</td>
 717 </tr>
 718 <tr class="row-odd"><td>176</td>
 719 <td>AM6_DEV_NAVSS0_MCRC0</td>
 720 </tr>
 721 <tr class="row-even"><td>177</td>
 722 <td>AM6_DEV_NAVSS0_PVU0</td>
 723 </tr>
 724 <tr class="row-odd"><td>178</td>
 725 <td>AM6_DEV_NAVSS0_PVU1</td>
 726 </tr>
 727 <tr class="row-even"><td>179</td>
 728 <td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
 729 </tr>
 730 <tr class="row-odd"><td>180</td>
 731 <td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
 732 </tr>
 733 <tr class="row-even"><td>181</td>
 734 <td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
 735 </tr>
 736 <tr class="row-odd"><td>182</td>
 737 <td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
 738 </tr>
 739 <tr class="row-even"><td>183</td>
 740 <td>AM6_DEV_NAVSS0_TIMER_MGR0</td>
 741 </tr>
 742 <tr class="row-odd"><td>184</td>
 743 <td>AM6_DEV_NAVSS0_TIMER_MGR1</td>
 744 </tr>
 745 <tr class="row-even"><td>185</td>
 746 <td>AM6_DEV_NAVSS0_PROXY0</td>
 747 </tr>
 748 <tr class="row-odd"><td>187</td>
 749 <td>AM6_DEV_NAVSS0_RINGACC0</td>
 750 </tr>
 751 <tr class="row-even"><td>188</td>
 752 <td>AM6_DEV_NAVSS0_UDMAP0</td>
 753 </tr>
 754 <tr class="row-odd"><td>189</td>
 755 <td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
 756 </tr>
 757 <tr class="row-even"><td>190</td>
 758 <td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
 759 </tr>
 760 <tr class="row-odd"><td>191</td>
 761 <td>AM6_DEV_MCU_NAVSS0_PROXY0</td>
 762 </tr>
 763 <tr class="row-even"><td>193</td>
 764 <td>AM6_DEV_MCU_NAVSS0_MCRC0</td>
 765 </tr>
 766 <tr class="row-odd"><td>194</td>
 767 <td>AM6_DEV_MCU_NAVSS0_UDMAP0</td>
 768 </tr>
 769 <tr class="row-even"><td>195</td>
 770 <td>AM6_DEV_MCU_NAVSS0_RINGACC0</td>
 771 </tr>
 772 <tr class="row-odd"><td>196</td>
 773 <td>AM6_DEV_COMPUTE_CLUSTER_MSMC0</td>
 774 </tr>
 775 <tr class="row-even"><td>197</td>
 776 <td>AM6_DEV_COMPUTE_CLUSTER_PBIST0</td>
 777 </tr>
 778 <tr class="row-odd"><td>198</td>
 779 <td>AM6_DEV_COMPUTE_CLUSTER_CPAC0</td>
 780 </tr>
 781 <tr class="row-even"><td>199</td>
 782 <td>AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0</td>
 783 </tr>
 784 <tr class="row-odd"><td>200</td>
 785 <td>AM6_DEV_COMPUTE_CLUSTER_CPAC1</td>
 786 </tr>
 787 <tr class="row-even"><td>201</td>
 788 <td>AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1</td>
 789 </tr>
 790 <tr class="row-odd"><td>202</td>
 791 <td>AM6_DEV_COMPUTE_CLUSTER_A53_0</td>
 792 </tr>
 793 <tr class="row-even"><td>203</td>
 794 <td>AM6_DEV_COMPUTE_CLUSTER_A53_1</td>
 795 </tr>
 796 <tr class="row-odd"><td>204</td>
 797 <td>AM6_DEV_COMPUTE_CLUSTER_A53_2</td>
 798 </tr>
 799 <tr class="row-even"><td>205</td>
 800 <td>AM6_DEV_COMPUTE_CLUSTER_A53_3</td>
 801 </tr>
 802 <tr class="row-odd"><td>206</td>
 803 <td>AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4</td>
 804 </tr>
 805 <tr class="row-even"><td>207</td>
 806 <td>AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3</td>
 807 </tr>
 808 <tr class="row-odd"><td>208</td>
 809 <td>AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0</td>
 810 </tr>
 811 <tr class="row-even"><td>209</td>
 812 <td>AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3</td>
 813 </tr>
 814 <tr class="row-odd"><td>210</td>
 815 <td>AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1</td>
 816 </tr>
 817 <tr class="row-even"><td>211</td>
 818 <td>AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5</td>
 819 </tr>
 820 <tr class="row-odd"><td>212</td>
 821 <td>AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6</td>
 822 </tr>
 823 <tr class="row-even"><td>213</td>
 824 <td>AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0</td>
 825 </tr>
 826 <tr class="row-odd"><td>214</td>
 827 <td>AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2</td>
 828 </tr>
 829 <tr class="row-even"><td>215</td>
 830 <td>AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2</td>
 831 </tr>
 832 <tr class="row-odd"><td>216</td>
 833 <td>AM6_DEV_OLDI_TX_CORE_MAIN_0</td>
 834 </tr>
 835 <tr class="row-even"><td>217</td>
 836 <td>AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0</td>
 837 </tr>
 838 <tr class="row-odd"><td>218</td>
 839 <td>AM6_DEV_ICEMELTER_WKUP_0</td>
 840 </tr>
 841 <tr class="row-even"><td>219</td>
 842 <td>AM6_DEV_K3_LED_MAIN_0</td>
 843 </tr>
 844 <tr class="row-odd"><td>220</td>
 845 <td>AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU</td>
 846 </tr>
 847 <tr class="row-even"><td>221</td>
 848 <td>AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP</td>
 849 </tr>
 850 <tr class="row-odd"><td>222</td>
 851 <td>AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU</td>
 852 </tr>
 853 <tr class="row-even"><td>223</td>
 854 <td>AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN</td>
 855 </tr>
 856 <tr class="row-odd"><td>224</td>
 857 <td>AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC</td>
 858 </tr>
 859 <tr class="row-even"><td>225</td>
 860 <td>AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA</td>
 861 </tr>
 862 <tr class="row-odd"><td>226</td>
 863 <td>AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA</td>
 864 </tr>
 865 <tr class="row-even"><td>227</td>
 866 <td>AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU</td>
 867 </tr>
 868 <tr class="row-odd"><td>228</td>
 869 <td>AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN</td>
 870 </tr>
 871 <tr class="row-even"><td>229</td>
 872 <td>AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU</td>
 873 </tr>
 874 <tr class="row-odd"><td>230</td>
 875 <td>AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU</td>
 876 </tr>
 877 <tr class="row-even"><td>231</td>
 878 <td>AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0</td>
 879 </tr>
 880 <tr class="row-odd"><td>232</td>
 881 <td>AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0</td>
 882 </tr>
 883 <tr class="row-even"><td>233</td>
 884 <td>AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0</td>
 885 </tr>
 886 <tr class="row-odd"><td>234</td>
 887 <td>AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0</td>
 888 </tr>
 889 <tr class="row-even"><td>235</td>
 890 <td>AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0</td>
 891 </tr>
 892 <tr class="row-odd"><td>236</td>
 893 <td>AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU_VD</td>
 894 </tr>
 895 <tr class="row-even"><td>237</td>
 896 <td>AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA_VD</td>
 897 </tr>
 898 <tr class="row-odd"><td>238</td>
 899 <td>AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC_VD</td>
 900 </tr>
 901 <tr class="row-even"><td>239</td>
 902 <td>AM6_DEV_DUMMY_IP_LPSC_DMSC_VD</td>
 903 </tr>
 904 <tr class="row-odd"><td>240</td>
 905 <td>AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA_VD</td>
 906 </tr>
 907 <tr class="row-even"><td>241</td>
 908 <td>AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_VD</td>
 909 </tr>
 910 <tr class="row-odd"><td>242</td>
 911 <td>AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP_VD</td>
 912 </tr>
 913 <tr class="row-even"><td>243</td>
 914 <td>AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU_VD</td>
 915 </tr>
 916 <tr class="row-odd"><td>244</td>
 917 <td>AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA_VD</td>
 918 </tr>
 919 <tr class="row-even"><td>245</td>
 920 <td>AM6_DEV_MCU_ARMSS0_CPU1</td>
 921 </tr>
 922 <tr class="row-odd"><td>246</td>
 923 <td>AM6_DEV_MCU_FSS0_FSAS_0</td>
 924 </tr>
 925 <tr class="row-even"><td>247</td>
 926 <td>AM6_DEV_MCU_FSS0_HYPERBUS0</td>
 927 </tr>
 928 <tr class="row-odd"><td>248</td>
 929 <td>AM6_DEV_MCU_FSS0_OSPI_0</td>
 930 </tr>
 931 <tr class="row-even"><td>249</td>
 932 <td>AM6_DEV_MCU_FSS0_OSPI_1</td>
 933 </tr>
 934 </tbody>
 935 </table>
 936 </div>
 937 </div>
 938
 939
 940            </div>
 941           </div>
 942           <footer>
 943
 944     <div class="rst-footer-buttons" role="navigation" aria-label="footer navigation">
 945
 946         <a href="clocks.html" class="btn btn-neutral float-right" title="AM6 Clock Identifiers" accesskey="n">Next <span class="fa fa-arrow-circle-right"></span></a>
 947
 948
 949         <a href="hosts.html" class="btn btn-neutral" title="AM6 Host Descriptions" accesskey="p"><span class="fa fa-arrow-circle-left"></span> Previous</a>
 950
 951     </div>
 952
 953
 954   <hr/>
 955
 956   <div role="contentinfo">
 957     <p>
 958       <a href="http://www.ti.com/corp/docs/legal/copyright.shtml">&copy; Copyright 2016-2020</a>, Texas Instruments Incorporated. All rights reserved. <br>
 959       <a href="http://www.ti.com/corp/docs/legal/trademark/trademrk.htm">Trademarks</a> | <a href="http://www.ti.com/corp/docs/legal/privacy.shtml">Privacy policy</a> | <a href="http://www.ti.com/corp/docs/legal/termsofuse.shtml">Terms of use</a> | <a href="http://www.ti.com/lsds/ti/legal/termsofsale.page">Terms of sale</a>
 960
 961     </p>
 962   </div>
 963
 964 </footer>
 965
 966         </div>
 967       </div>
 968
 969     </section>
 970
 971   </div>
 972
 973
 974
 975
 976
 977     <script type="text/javascript">
 978         var DOCUMENTATION_OPTIONS = {
 979             URL_ROOT:'../../',
 980             VERSION:'20.05.00',
 981             COLLAPSE_INDEX:false,
 982             FILE_SUFFIX:'.html',
 983             HAS_SOURCE:  true
 984         };
 985     </script>
 986       <script type="text/javascript" src="../../_static/jquery.js"></script>
 987       <script type="text/javascript" src="../../_static/underscore.js"></script>
 988       <script type="text/javascript" src="../../_static/doctools.js"></script>
 989       <script type="text/javascript" src="../../_static/language_data.js"></script>
 990
 991     <script src="http://www.ti.com/assets/js/headerfooter/analytics.js" type="text/javascript" charset="utf-8"></script>
 992
 993
 994
 995
 996
 997     <script type="text/javascript" src="../../_static/js/theme.js"></script>
 998
 999
1000
1001
1002   <script type="text/javascript">
1003       jQuery(function () {
1004           SphinxRtdTheme.StickyNav.enable();
1005         });
1006
1007       var menuHeight = window.innerHeight;
1008
1009       var contentOffset = $(".wy-nav-content-wrap").offset();
1010       var contentHeight = $(".wy-nav-content-wrap").height();
1011       var contentBottom = contentOffset.top + contentHeight;
1012
1013       function setNavbarTop() {
1014           var scrollTop = $(window).scrollTop();
1015           var maxTop = scrollTop + menuHeight;
1016
1017           // If past the header
1018           if (scrollTop > contentOffset.top && maxTop < contentBottom) {
1019             stickyTop = scrollTop - contentOffset.top;
1020           } else if (maxTop > contentBottom) {
1021             stickyTop = scrollTop - contentOffset.top - (maxTop - contentBottom);
1022           } else {
1023             stickyTop = 0;
1024           }
1025
1026           $(".wy-nav-side").css("top", stickyTop);
1027       }
1028
1029       $(document).ready(function() {
1030         setNavbarTop();
1031         $(window).scroll(function () {
1032           setNavbarTop();
1033         });
1034
1035         $('body').on("mousewheel", function () {
1036             // Remove default behavior
1037             event.preventDefault();
1038             // Scroll without smoothing
1039             var wheelDelta = event.wheelDelta;
1040             var currentScrollPosition = window.pageYOffset;
1041             window.scrollTo(0, currentScrollPosition - wheelDelta);
1042         });
1043       });
1044   </script>
1045
1046
1047 </body>
1048 </html>