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 184 <h1>AM6 Board Configuration Resource Assignment Type Descriptions<a class="headerlink" href="#am6-board-configuration-resource-assignment-type-descriptions" title="Permalink to this headline">¶</a></h1>
 185 <div class="section" id="introduction">
 186 <h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
 187 <p>This chapter provides information of Board Configuration resource assignment
 188 type IDs that are permitted in the AM6 SoC.  The resource type IDs represent AM6
 189 resources ranges assignable to SoC processing entities (or PEs).</p>
 190 <p><strong>WARNING</strong>: System Firmware RM currently supports a maximum of 260 RM board
 191 configuration resource assignment ranges on the AM6 SoC.  Sending more
 192 entries than the maximum will result in the RM board configuration being NACK’d</p>
 193 <table border="1" class="docutils">
 194 <colgroup>
 195 <col width="20%" />
 196 <col width="8%" />
 197 <col width="23%" />
 198 <col width="8%" />
 199 <col width="11%" />
 200 <col width="14%" />
 201 <col width="15%" />
 202 </colgroup>
 203 <thead valign="bottom">
 204 <tr class="row-odd"><th class="head">Device Name</th>
 205 <th class="head">Device ID
 206 (10-bits)</th>
 207 <th class="head">Subtype Name</th>
 208 <th class="head">Subtype ID
 209 (6-bits)</th>
 210 <th class="head">Unique Type ID
 211 (16-bits)</th>
 212 <th class="head">Resource Range Start</th>
 213 <th class="head">Resource Range Number</th>
 214 </tr>
 215 </thead>
 216 <tbody valign="top">
 217 <tr class="row-even"><td>AM6_DEV_CMPEVENT_INTRTR0</td>
 218 <td>0x003</td>
 219 <td>RESASG_SUBTYPE_IR_OUTPUT</td>
 220 <td>0x00</td>
 221 <td>0x00C0</td>
 222 <td>0</td>
 223 <td>32</td>
 224 </tr>
 225 <tr class="row-odd"><td>AM6_DEV_MAIN2MCU_LVL_INTRTR0</td>
 226 <td>0x061</td>
 227 <td>RESASG_SUBTYPE_IR_OUTPUT</td>
 228 <td>0x00</td>
 229 <td>0x1840</td>
 230 <td>0</td>
 231 <td>64</td>
 232 </tr>
 233 <tr class="row-even"><td>AM6_DEV_MAIN2MCU_PLS_INTRTR0</td>
 234 <td>0x062</td>
 235 <td>RESASG_SUBTYPE_IR_OUTPUT</td>
 236 <td>0x00</td>
 237 <td>0x1880</td>
 238 <td>0</td>
 239 <td>48</td>
 240 </tr>
 241 <tr class="row-odd"><td>AM6_DEV_GPIOMUX_INTRTR0</td>
 242 <td>0x064</td>
 243 <td>RESASG_SUBTYPE_IR_OUTPUT</td>
 244 <td>0x00</td>
 245 <td>0x1900</td>
 246 <td>0</td>
 247 <td>32</td>
 248 </tr>
 249 <tr class="row-even"><td>AM6_DEV_TIMESYNC_INTRTR0</td>
 250 <td>0x091</td>
 251 <td>RESASG_SUBTYPE_IR_OUTPUT</td>
 252 <td>0x00</td>
 253 <td>0x2440</td>
 254 <td>0</td>
 255 <td>40</td>
 256 </tr>
 257 <tr class="row-odd"><td>AM6_DEV_WKUP_GPIOMUX_INTRTR0</td>
 258 <td>0x09C</td>
 259 <td>RESASG_SUBTYPE_IR_OUTPUT</td>
 260 <td>0x00</td>
 261 <td>0x2700</td>
 262 <td>0</td>
 263 <td>16</td>
 264 </tr>
 265 <tr class="row-even"><td>AM6_DEV_NAVSS0_UDMASS_INTA0</td>
 266 <td>0x0B3</td>
 267 <td>RESASG_SUBTYPE_IA_VINT</td>
 268 <td>0x0A</td>
 269 <td>0x2CCA</td>
 270 <td>16</td>
 271 <td>240</td>
 272 </tr>
 273 <tr class="row-odd"><td>&#160;</td>
 274 <td>&#160;</td>
 275 <td>RESASG_SUBTYPE_GLOBAL_EVENT_SEVT</td>
 276 <td>0x0D</td>
 277 <td>0x2CCD</td>
 278 <td>16</td>
 279 <td>4592</td>
 280 </tr>
 281 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA0</td>
 282 <td>0x0B4</td>
 283 <td>RESASG_SUBTYPE_IA_VINT</td>
 284 <td>0x0A</td>
 285 <td>0x2D0A</td>
 286 <td>0</td>
 287 <td>64</td>
 288 </tr>
 289 <tr class="row-odd"><td>&#160;</td>
 290 <td>&#160;</td>
 291 <td>RESASG_SUBTYPE_GLOBAL_EVENT_SEVT</td>
 292 <td>0x0D</td>
 293 <td>0x2D0D</td>
 294 <td>20480</td>
 295 <td>1024</td>
 296 </tr>
 297 <tr class="row-even"><td>AM6_DEV_NAVSS0_MODSS_INTA1</td>
 298 <td>0x0B5</td>
 299 <td>RESASG_SUBTYPE_IA_VINT</td>
 300 <td>0x0A</td>
 301 <td>0x2D4A</td>
 302 <td>0</td>
 303 <td>64</td>
 304 </tr>
 305 <tr class="row-odd"><td>&#160;</td>
 306 <td>&#160;</td>
 307 <td>RESASG_SUBTYPE_GLOBAL_EVENT_SEVT</td>
 308 <td>0x0D</td>
 309 <td>0x2D4D</td>
 310 <td>22528</td>
 311 <td>1024</td>
 312 </tr>
 313 <tr class="row-even"><td>AM6_DEV_NAVSS0_INTR_ROUTER_0</td>
 314 <td>0x0B6</td>
 315 <td>RESASG_SUBTYPE_IR_OUTPUT</td>
 316 <td>0x00</td>
 317 <td>0x2D80</td>
 318 <td>16</td>
 319 <td>136</td>
 320 </tr>
 321 <tr class="row-odd"><td>AM6_DEV_NAVSS0_PROXY0</td>
 322 <td>0x0B9</td>
 323 <td>RESASG_SUBTYPE_PROXY_PROXIES</td>
 324 <td>0x00</td>
 325 <td>0x2E40</td>
 326 <td>1</td>
 327 <td>63</td>
 328 </tr>
 329 <tr class="row-even"><td>AM6_DEV_NAVSS0_RINGACC0</td>
 330 <td>0x0BB</td>
 331 <td>RESASG_SUBTYPE_RA_ERROR_OES</td>
 332 <td>0x00</td>
 333 <td>0x2EC0</td>
 334 <td>0</td>
 335 <td>1</td>
 336 </tr>
 337 <tr class="row-odd"><td>&#160;</td>
 338 <td>&#160;</td>
 339 <td>RESASG_SUBTYPE_RA_GP</td>
 340 <td>0x01</td>
 341 <td>0x2EC1</td>
 342 <td>304</td>
 343 <td>464</td>
 344 </tr>
 345 <tr class="row-even"><td>&#160;</td>
 346 <td>&#160;</td>
 347 <td>RESASG_SUBTYPE_RA_UDMAP_RX</td>
 348 <td>0x02</td>
 349 <td>0x2EC2</td>
 350 <td>160</td>
 351 <td>142</td>
 352 </tr>
 353 <tr class="row-odd"><td>&#160;</td>
 354 <td>&#160;</td>
 355 <td>RESASG_SUBTYPE_RA_UDMAP_TX</td>
 356 <td>0x03</td>
 357 <td>0x2EC3</td>
 358 <td>8</td>
 359 <td>112</td>
 360 </tr>
 361 <tr class="row-even"><td>&#160;</td>
 362 <td>&#160;</td>
 363 <td>RESASG_SUBTYPE_RA_UDMAP_TX_EXT</td>
 364 <td>0x04</td>
 365 <td>0x2EC4</td>
 366 <td>120</td>
 367 <td>32</td>
 368 </tr>
 369 <tr class="row-odd"><td>&#160;</td>
 370 <td>&#160;</td>
 371 <td>RESASG_SUBTYPE_RA_UDMAP_RX_H</td>
 372 <td>0x05</td>
 373 <td>0x2EC5</td>
 374 <td>154</td>
 375 <td>6</td>
 376 </tr>
 377 <tr class="row-even"><td>&#160;</td>
 378 <td>&#160;</td>
 379 <td>RESASG_SUBTYPE_RA_UDMAP_TX_H</td>
 380 <td>0x07</td>
 381 <td>0x2EC7</td>
 382 <td>1</td>
 383 <td>7</td>
 384 </tr>
 385 <tr class="row-odd"><td>&#160;</td>
 386 <td>&#160;</td>
 387 <td>RESASG_SUBTYPE_RA_VIRTID</td>
 388 <td>0x0A</td>
 389 <td>0x2ECA</td>
 390 <td>0</td>
 391 <td>4096</td>
 392 </tr>
 393 <tr class="row-even"><td>&#160;</td>
 394 <td>&#160;</td>
 395 <td>RESASG_SUBTYPE_RA_MONITORS</td>
 396 <td>0x0B</td>
 397 <td>0x2ECB</td>
 398 <td>0</td>
 399 <td>32</td>
 400 </tr>
 401 <tr class="row-odd"><td>AM6_DEV_NAVSS0_UDMAP0</td>
 402 <td>0x0BC</td>
 403 <td>RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON</td>
 404 <td>0x00</td>
 405 <td>0x2F00</td>
 406 <td>150</td>
 407 <td>150</td>
 408 </tr>
 409 <tr class="row-even"><td>&#160;</td>
 410 <td>&#160;</td>
 411 <td>RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES</td>
 412 <td>0x01</td>
 413 <td>0x2F01</td>
 414 <td>0</td>
 415 <td>1</td>
 416 </tr>
 417 <tr class="row-odd"><td>&#160;</td>
 418 <td>&#160;</td>
 419 <td>RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER</td>
 420 <td>0x02</td>
 421 <td>0x2F02</td>
 422 <td>49152</td>
 423 <td>1024</td>
 424 </tr>
 425 <tr class="row-even"><td>&#160;</td>
 426 <td>&#160;</td>
 427 <td>RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG</td>
 428 <td>0x03</td>
 429 <td>0x2F03</td>
 430 <td>0</td>
 431 <td>1</td>
 432 </tr>
 433 <tr class="row-odd"><td>&#160;</td>
 434 <td>&#160;</td>
 435 <td>RESASG_SUBTYPE_UDMAP_RX_CHAN</td>
 436 <td>0x0A</td>
 437 <td>0x2F0A</td>
 438 <td>8</td>
 439 <td>142</td>
 440 </tr>
 441 <tr class="row-even"><td>&#160;</td>
 442 <td>&#160;</td>
 443 <td>RESASG_SUBTYPE_UDMAP_RX_HCHAN</td>
 444 <td>0x0B</td>
 445 <td>0x2F0B</td>
 446 <td>2</td>
 447 <td>6</td>
 448 </tr>
 449 <tr class="row-odd"><td>&#160;</td>
 450 <td>&#160;</td>
 451 <td>RESASG_SUBTYPE_UDMAP_TX_CHAN</td>
 452 <td>0x0D</td>
 453 <td>0x2F0D</td>
 454 <td>8</td>
 455 <td>112</td>
 456 </tr>
 457 <tr class="row-even"><td>&#160;</td>
 458 <td>&#160;</td>
 459 <td>RESASG_SUBTYPE_UDMAP_TX_ECHAN</td>
 460 <td>0x0E</td>
 461 <td>0x2F0E</td>
 462 <td>120</td>
 463 <td>32</td>
 464 </tr>
 465 <tr class="row-odd"><td>&#160;</td>
 466 <td>&#160;</td>
 467 <td>RESASG_SUBTYPE_UDMAP_TX_HCHAN</td>
 468 <td>0x0F</td>
 469 <td>0x2F0F</td>
 470 <td>1</td>
 471 <td>7</td>
 472 </tr>
 473 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_AGGR_0</td>
 474 <td>0x0BD</td>
 475 <td>RESASG_SUBTYPE_IA_VINT</td>
 476 <td>0x0A</td>
 477 <td>0x2F4A</td>
 478 <td>8</td>
 479 <td>248</td>
 480 </tr>
 481 <tr class="row-odd"><td>&#160;</td>
 482 <td>&#160;</td>
 483 <td>RESASG_SUBTYPE_GLOBAL_EVENT_SEVT</td>
 484 <td>0x0D</td>
 485 <td>0x2F4D</td>
 486 <td>16392</td>
 487 <td>1528</td>
 488 </tr>
 489 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0</td>
 490 <td>0x0BE</td>
 491 <td>RESASG_SUBTYPE_IR_OUTPUT</td>
 492 <td>0x00</td>
 493 <td>0x2F80</td>
 494 <td>4</td>
 495 <td>28</td>
 496 </tr>
 497 <tr class="row-odd"><td>&#160;</td>
 498 <td>&#160;</td>
 499 <td>&#160;</td>
 500 <td>&#160;</td>
 501 <td>&#160;</td>
 502 <td>36</td>
 503 <td>28</td>
 504 </tr>
 505 <tr class="row-even"><td>AM6_DEV_MCU_NAVSS0_PROXY0</td>
 506 <td>0x0BF</td>
 507 <td>RESASG_SUBTYPE_PROXY_PROXIES</td>
 508 <td>0x00</td>
 509 <td>0x2FC0</td>
 510 <td>0</td>
 511 <td>64</td>
 512 </tr>
 513 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_UDMAP0</td>
 514 <td>0x0C2</td>
 515 <td>RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON</td>
 516 <td>0x00</td>
 517 <td>0x3080</td>
 518 <td>48</td>
 519 <td>48</td>
 520 </tr>
 521 <tr class="row-even"><td>&#160;</td>
 522 <td>&#160;</td>
 523 <td>RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES</td>
 524 <td>0x01</td>
 525 <td>0x3081</td>
 526 <td>0</td>
 527 <td>1</td>
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 529 <tr class="row-odd"><td>&#160;</td>
 530 <td>&#160;</td>
 531 <td>RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER</td>
 532 <td>0x02</td>
 533 <td>0x3082</td>
 534 <td>56320</td>
 535 <td>256</td>
 536 </tr>
 537 <tr class="row-even"><td>&#160;</td>
 538 <td>&#160;</td>
 539 <td>RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG</td>
 540 <td>0x03</td>
 541 <td>0x3083</td>
 542 <td>0</td>
 543 <td>1</td>
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 545 <tr class="row-odd"><td>&#160;</td>
 546 <td>&#160;</td>
 547 <td>RESASG_SUBTYPE_UDMAP_RX_CHAN</td>
 548 <td>0x0A</td>
 549 <td>0x308A</td>
 550 <td>2</td>
 551 <td>46</td>
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 553 <tr class="row-even"><td>&#160;</td>
 554 <td>&#160;</td>
 555 <td>RESASG_SUBTYPE_UDMAP_RX_HCHAN</td>
 556 <td>0x0B</td>
 557 <td>0x308B</td>
 558 <td>0</td>
 559 <td>2</td>
 560 </tr>
 561 <tr class="row-odd"><td>&#160;</td>
 562 <td>&#160;</td>
 563 <td>RESASG_SUBTYPE_UDMAP_TX_CHAN</td>
 564 <td>0x0D</td>
 565 <td>0x308D</td>
 566 <td>2</td>
 567 <td>46</td>
 568 </tr>
 569 <tr class="row-even"><td>&#160;</td>
 570 <td>&#160;</td>
 571 <td>RESASG_SUBTYPE_UDMAP_TX_HCHAN</td>
 572 <td>0x0F</td>
 573 <td>0x308F</td>
 574 <td>0</td>
 575 <td>2</td>
 576 </tr>
 577 <tr class="row-odd"><td>AM6_DEV_MCU_NAVSS0_RINGACC0</td>
 578 <td>0x0C3</td>
 579 <td>RESASG_SUBTYPE_RA_ERROR_OES</td>
 580 <td>0x00</td>
 581 <td>0x30C0</td>
 582 <td>0</td>
 583 <td>1</td>
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 585 <tr class="row-even"><td>&#160;</td>
 586 <td>&#160;</td>
 587 <td>RESASG_SUBTYPE_RA_GP</td>
 588 <td>0x01</td>
 589 <td>0x30C1</td>
 590 <td>96</td>
 591 <td>160</td>
 592 </tr>
 593 <tr class="row-odd"><td>&#160;</td>
 594 <td>&#160;</td>
 595 <td>RESASG_SUBTYPE_RA_UDMAP_RX</td>
 596 <td>0x02</td>
 597 <td>0x30C2</td>
 598 <td>50</td>
 599 <td>46</td>
 600 </tr>
 601 <tr class="row-even"><td>&#160;</td>
 602 <td>&#160;</td>
 603 <td>RESASG_SUBTYPE_RA_UDMAP_TX</td>
 604 <td>0x03</td>
 605 <td>0x30C3</td>
 606 <td>2</td>
 607 <td>46</td>
 608 </tr>
 609 <tr class="row-odd"><td>&#160;</td>
 610 <td>&#160;</td>
 611 <td>RESASG_SUBTYPE_RA_UDMAP_RX_H</td>
 612 <td>0x05</td>
 613 <td>0x30C5</td>
 614 <td>48</td>
 615 <td>2</td>
 616 </tr>
 617 <tr class="row-even"><td>&#160;</td>
 618 <td>&#160;</td>
 619 <td>RESASG_SUBTYPE_RA_UDMAP_TX_H</td>
 620 <td>0x07</td>
 621 <td>0x30C7</td>
 622 <td>0</td>
 623 <td>2</td>
 624 </tr>
 625 <tr class="row-odd"><td>&#160;</td>
 626 <td>&#160;</td>
 627 <td>RESASG_SUBTYPE_RA_VIRTID</td>
 628 <td>0x0A</td>
 629 <td>0x30CA</td>
 630 <td>0</td>
 631 <td>4096</td>
 632 </tr>
 633 <tr class="row-even"><td>&#160;</td>
 634 <td>&#160;</td>
 635 <td>RESASG_SUBTYPE_RA_MONITORS</td>
 636 <td>0x0B</td>
 637 <td>0x30CB</td>
 638 <td>0</td>
 639 <td>32</td>
 640 </tr>
 641 </tbody>
 642 </table>
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