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 183   <div class="section" id="j721e-clock-identifiers">
 184 <h1>J721E Clock Identifiers<a class="headerlink" href="#j721e-clock-identifiers" title="Permalink to this headline">¶</a></h1>
 185 <div class="section" id="clock-for-j721e-device">
 186 <span id="soc-doc-j721e-public-clks-desc-intro"></span><h2>Clock for J721E Device<a class="headerlink" href="#clock-for-j721e-device" title="Permalink to this headline">¶</a></h2>
 187 <p>This chapter provides information on clock IDs that identify clocks
 188 incoming and outgoing from devices identified via
 189 <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">device IDs</span></a>
 190 in J721E SoC.</p>
 191 <p>TISCI message Power Management APIs define a device ID and clock ID as
 192 parameters allowing a user to specify granular control of clocks
 193 for a particular SoC subsystem.</p>
 194 </div>
 195 <div class="section" id="device-wise-clock-id-list-for-j721e-soc">
 196 <span id="soc-doc-j721e-public-clks-dev-list"></span><h2>Device wise clock ID list for J721E SoC<a class="headerlink" href="#device-wise-clock-id-list-for-j721e-soc" title="Permalink to this headline">¶</a></h2>
 197 <p>This is an enumerated list of clocks per device ID that can be
 198 controlled via the power management clock APIs</p>
 199 <p>The following table describes functions implemented by clocks</p>
 200 <table border="1" class="docutils">
 201 <colgroup>
 202 <col width="27%" />
 203 <col width="73%" />
 204 </colgroup>
 205 <thead valign="bottom">
 206 <tr class="row-odd"><th class="head">Function</th>
 207 <th class="head">Description</th>
 208 </tr>
 209 </thead>
 210 <tbody valign="top">
 211 <tr class="row-even"><td>Input clock</td>
 212 <td>Clock input to the SoC subsystem</td>
 213 </tr>
 214 <tr class="row-odd"><td>Output clock</td>
 215 <td>Clock output from the SoC subsystem</td>
 216 </tr>
 217 <tr class="row-even"><td>Input muxed clock</td>
 218 <td>Clock input to the SoC subsystem, but can choose one of the parent clocks as a clock source</td>
 219 </tr>
 220 <tr class="row-odd"><td>Parent input clock option to XYZ</td>
 221 <td>One of the parent clocks that can be used as a source clock to a input muxed clock</td>
 222 </tr>
 223 </tbody>
 224 </table>
 225 <p>Also note: There are devices which do not have clock information.
 226 These do have chapters in this document associated with them, however, these would be marked as:</p>
 227 <p><strong>This device has no defined clocks.</strong></p>
 228 <p>The chapters corresponding to the devices are organized alphabetically per device name for ease of readability.</p>
 229 <div class="section" id="clocks-for-a72ss0-device">
 230 <span id="soc-doc-j721e-public-clks-a72ss0"></span><h3>Clocks for A72SS0 Device<a class="headerlink" href="#clocks-for-a72ss0-device" title="Permalink to this headline">¶</a></h3>
 231 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_A72SS0</span></a> (ID = 4)</p>
 232 <p>Following is a mapping of Clocks IDs to function:</p>
 233 <table border="1" class="docutils">
 234 <colgroup>
 235 <col width="24%" />
 236 <col width="50%" />
 237 <col width="26%" />
 238 </colgroup>
 239 <thead valign="bottom">
 240 <tr class="row-odd"><th class="head">Clock ID</th>
 241 <th class="head">Name</th>
 242 <th class="head">Function</th>
 243 </tr>
 244 </thead>
 245 <tbody valign="top">
 246 <tr class="row-even"><td>0</td>
 247 <td>DEV_A72SS0_PLL_CTRL_CLK</td>
 248 <td>Input clock</td>
 249 </tr>
 250 <tr class="row-odd"><td>1</td>
 251 <td>DEV_A72SS0_MSMC_CLK</td>
 252 <td>Input clock</td>
 253 </tr>
 254 <tr class="row-even"><td>2</td>
 255 <td>DEV_A72SS0_ARM_CLK_CLK</td>
 256 <td>Input clock</td>
 257 </tr>
 258 </tbody>
 259 </table>
 260 </div>
 261 <div class="section" id="clocks-for-a72ss0-core0-device">
 262 <span id="soc-doc-j721e-public-clks-a72ss0-core0"></span><h3>Clocks for A72SS0_CORE0 Device<a class="headerlink" href="#clocks-for-a72ss0-core0-device" title="Permalink to this headline">¶</a></h3>
 263 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_A72SS0_CORE0</span></a> (ID = 202)</p>
 264 <p>Following is a mapping of Clocks IDs to function:</p>
 265 <table border="1" class="docutils">
 266 <colgroup>
 267 <col width="22%" />
 268 <col width="55%" />
 269 <col width="24%" />
 270 </colgroup>
 271 <thead valign="bottom">
 272 <tr class="row-odd"><th class="head">Clock ID</th>
 273 <th class="head">Name</th>
 274 <th class="head">Function</th>
 275 </tr>
 276 </thead>
 277 <tbody valign="top">
 278 <tr class="row-even"><td>2</td>
 279 <td>DEV_A72SS0_CORE0_ARM_CLK_CLK</td>
 280 <td>Input clock</td>
 281 </tr>
 282 </tbody>
 283 </table>
 284 </div>
 285 <div class="section" id="clocks-for-a72ss0-core1-device">
 286 <span id="soc-doc-j721e-public-clks-a72ss0-core1"></span><h3>Clocks for A72SS0_CORE1 Device<a class="headerlink" href="#clocks-for-a72ss0-core1-device" title="Permalink to this headline">¶</a></h3>
 287 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_A72SS0_CORE1</span></a> (ID = 203)</p>
 288 <p>Following is a mapping of Clocks IDs to function:</p>
 289 <table border="1" class="docutils">
 290 <colgroup>
 291 <col width="22%" />
 292 <col width="55%" />
 293 <col width="24%" />
 294 </colgroup>
 295 <thead valign="bottom">
 296 <tr class="row-odd"><th class="head">Clock ID</th>
 297 <th class="head">Name</th>
 298 <th class="head">Function</th>
 299 </tr>
 300 </thead>
 301 <tbody valign="top">
 302 <tr class="row-even"><td>0</td>
 303 <td>DEV_A72SS0_CORE1_ARM_CLK_CLK</td>
 304 <td>Input clock</td>
 305 </tr>
 306 </tbody>
 307 </table>
 308 </div>
 309 <div class="section" id="clocks-for-aasrc0-device">
 310 <span id="soc-doc-j721e-public-clks-aasrc0"></span><h3>Clocks for AASRC0 Device<a class="headerlink" href="#clocks-for-aasrc0-device" title="Permalink to this headline">¶</a></h3>
 311 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_AASRC0</span></a> (ID = 139)</p>
 312 <p>Following is a mapping of Clocks IDs to function:</p>
 313 <table border="1" class="docutils">
 314 <colgroup>
 315 <col width="10%" />
 316 <col width="50%" />
 317 <col width="40%" />
 318 </colgroup>
 319 <thead valign="bottom">
 320 <tr class="row-odd"><th class="head">Clock ID</th>
 321 <th class="head">Name</th>
 322 <th class="head">Function</th>
 323 </tr>
 324 </thead>
 325 <tbody valign="top">
 326 <tr class="row-even"><td>0</td>
 327 <td>DEV_AASRC0_SYS_CLK</td>
 328 <td>Input clock</td>
 329 </tr>
 330 <tr class="row-odd"><td>1</td>
 331 <td>DEV_AASRC0_VBUSP_CLK</td>
 332 <td>Input clock</td>
 333 </tr>
 334 <tr class="row-even"><td>2</td>
 335 <td>DEV_AASRC0_RX0_SYNC</td>
 336 <td>Input muxed clock</td>
 337 </tr>
 338 <tr class="row-odd"><td>3</td>
 339 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT</td>
 340 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 341 </tr>
 342 <tr class="row-even"><td>4</td>
 343 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT</td>
 344 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 345 </tr>
 346 <tr class="row-odd"><td>5</td>
 347 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT</td>
 348 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 349 </tr>
 350 <tr class="row-even"><td>6</td>
 351 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT</td>
 352 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 353 </tr>
 354 <tr class="row-odd"><td>7</td>
 355 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT</td>
 356 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 357 </tr>
 358 <tr class="row-even"><td>8</td>
 359 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT</td>
 360 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 361 </tr>
 362 <tr class="row-odd"><td>9</td>
 363 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT</td>
 364 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 365 </tr>
 366 <tr class="row-even"><td>10</td>
 367 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT</td>
 368 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 369 </tr>
 370 <tr class="row-odd"><td>11</td>
 371 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT</td>
 372 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 373 </tr>
 374 <tr class="row-even"><td>12</td>
 375 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT</td>
 376 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 377 </tr>
 378 <tr class="row-odd"><td>13</td>
 379 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT</td>
 380 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 381 </tr>
 382 <tr class="row-even"><td>14</td>
 383 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT</td>
 384 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 385 </tr>
 386 <tr class="row-odd"><td>15</td>
 387 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT</td>
 388 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 389 </tr>
 390 <tr class="row-even"><td>16</td>
 391 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT</td>
 392 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 393 </tr>
 394 <tr class="row-odd"><td>17</td>
 395 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT</td>
 396 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 397 </tr>
 398 <tr class="row-even"><td>18</td>
 399 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT</td>
 400 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 401 </tr>
 402 <tr class="row-odd"><td>19</td>
 403 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT</td>
 404 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 405 </tr>
 406 <tr class="row-even"><td>20</td>
 407 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT</td>
 408 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 409 </tr>
 410 <tr class="row-odd"><td>21</td>
 411 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT</td>
 412 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 413 </tr>
 414 <tr class="row-even"><td>22</td>
 415 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT</td>
 416 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 417 </tr>
 418 <tr class="row-odd"><td>23</td>
 419 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT</td>
 420 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 421 </tr>
 422 <tr class="row-even"><td>24</td>
 423 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT</td>
 424 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 425 </tr>
 426 <tr class="row-odd"><td>25</td>
 427 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT</td>
 428 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 429 </tr>
 430 <tr class="row-even"><td>26</td>
 431 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT</td>
 432 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 433 </tr>
 434 <tr class="row-odd"><td>27</td>
 435 <td>DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
 436 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 437 </tr>
 438 <tr class="row-even"><td>28</td>
 439 <td>DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
 440 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 441 </tr>
 442 <tr class="row-odd"><td>29</td>
 443 <td>DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
 444 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 445 </tr>
 446 <tr class="row-even"><td>30</td>
 447 <td>DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
 448 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 449 </tr>
 450 <tr class="row-odd"><td>31</td>
 451 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
 452 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 453 </tr>
 454 <tr class="row-even"><td>32</td>
 455 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
 456 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 457 </tr>
 458 <tr class="row-odd"><td>33</td>
 459 <td>DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK</td>
 460 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 461 </tr>
 462 <tr class="row-even"><td>34</td>
 463 <td>DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK</td>
 464 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 465 </tr>
 466 <tr class="row-odd"><td>35</td>
 467 <td>DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0</td>
 468 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 469 </tr>
 470 <tr class="row-even"><td>36</td>
 471 <td>DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1</td>
 472 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 473 </tr>
 474 <tr class="row-odd"><td>37</td>
 475 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
 476 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 477 </tr>
 478 <tr class="row-even"><td>38</td>
 479 <td>DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
 480 <td>Parent input clock option to DEV_AASRC0_RX0_SYNC</td>
 481 </tr>
 482 <tr class="row-odd"><td>39</td>
 483 <td>DEV_AASRC0_RX1_SYNC</td>
 484 <td>Input muxed clock</td>
 485 </tr>
 486 <tr class="row-even"><td>40</td>
 487 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT</td>
 488 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 489 </tr>
 490 <tr class="row-odd"><td>41</td>
 491 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT</td>
 492 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 493 </tr>
 494 <tr class="row-even"><td>42</td>
 495 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT</td>
 496 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 497 </tr>
 498 <tr class="row-odd"><td>43</td>
 499 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT</td>
 500 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 501 </tr>
 502 <tr class="row-even"><td>44</td>
 503 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT</td>
 504 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 505 </tr>
 506 <tr class="row-odd"><td>45</td>
 507 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT</td>
 508 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 509 </tr>
 510 <tr class="row-even"><td>46</td>
 511 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT</td>
 512 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 513 </tr>
 514 <tr class="row-odd"><td>47</td>
 515 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT</td>
 516 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 517 </tr>
 518 <tr class="row-even"><td>48</td>
 519 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT</td>
 520 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 521 </tr>
 522 <tr class="row-odd"><td>49</td>
 523 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT</td>
 524 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 525 </tr>
 526 <tr class="row-even"><td>50</td>
 527 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT</td>
 528 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 529 </tr>
 530 <tr class="row-odd"><td>51</td>
 531 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT</td>
 532 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 533 </tr>
 534 <tr class="row-even"><td>52</td>
 535 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT</td>
 536 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 537 </tr>
 538 <tr class="row-odd"><td>53</td>
 539 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT</td>
 540 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 541 </tr>
 542 <tr class="row-even"><td>54</td>
 543 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT</td>
 544 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 545 </tr>
 546 <tr class="row-odd"><td>55</td>
 547 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT</td>
 548 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 549 </tr>
 550 <tr class="row-even"><td>56</td>
 551 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT</td>
 552 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 553 </tr>
 554 <tr class="row-odd"><td>57</td>
 555 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT</td>
 556 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 557 </tr>
 558 <tr class="row-even"><td>58</td>
 559 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT</td>
 560 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 561 </tr>
 562 <tr class="row-odd"><td>59</td>
 563 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT</td>
 564 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 565 </tr>
 566 <tr class="row-even"><td>60</td>
 567 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT</td>
 568 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 569 </tr>
 570 <tr class="row-odd"><td>61</td>
 571 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT</td>
 572 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 573 </tr>
 574 <tr class="row-even"><td>62</td>
 575 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT</td>
 576 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 577 </tr>
 578 <tr class="row-odd"><td>63</td>
 579 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT</td>
 580 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 581 </tr>
 582 <tr class="row-even"><td>64</td>
 583 <td>DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
 584 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 585 </tr>
 586 <tr class="row-odd"><td>65</td>
 587 <td>DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
 588 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 589 </tr>
 590 <tr class="row-even"><td>66</td>
 591 <td>DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
 592 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 593 </tr>
 594 <tr class="row-odd"><td>67</td>
 595 <td>DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
 596 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 597 </tr>
 598 <tr class="row-even"><td>68</td>
 599 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
 600 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 601 </tr>
 602 <tr class="row-odd"><td>69</td>
 603 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
 604 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 605 </tr>
 606 <tr class="row-even"><td>70</td>
 607 <td>DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK</td>
 608 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 609 </tr>
 610 <tr class="row-odd"><td>71</td>
 611 <td>DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK</td>
 612 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 613 </tr>
 614 <tr class="row-even"><td>72</td>
 615 <td>DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0</td>
 616 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 617 </tr>
 618 <tr class="row-odd"><td>73</td>
 619 <td>DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1</td>
 620 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 621 </tr>
 622 <tr class="row-even"><td>74</td>
 623 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
 624 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 625 </tr>
 626 <tr class="row-odd"><td>75</td>
 627 <td>DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
 628 <td>Parent input clock option to DEV_AASRC0_RX1_SYNC</td>
 629 </tr>
 630 <tr class="row-even"><td>76</td>
 631 <td>DEV_AASRC0_RX2_SYNC</td>
 632 <td>Input muxed clock</td>
 633 </tr>
 634 <tr class="row-odd"><td>77</td>
 635 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT</td>
 636 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 637 </tr>
 638 <tr class="row-even"><td>78</td>
 639 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT</td>
 640 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 641 </tr>
 642 <tr class="row-odd"><td>79</td>
 643 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT</td>
 644 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 645 </tr>
 646 <tr class="row-even"><td>80</td>
 647 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT</td>
 648 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 649 </tr>
 650 <tr class="row-odd"><td>81</td>
 651 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT</td>
 652 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 653 </tr>
 654 <tr class="row-even"><td>82</td>
 655 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT</td>
 656 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 657 </tr>
 658 <tr class="row-odd"><td>83</td>
 659 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT</td>
 660 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 661 </tr>
 662 <tr class="row-even"><td>84</td>
 663 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT</td>
 664 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 665 </tr>
 666 <tr class="row-odd"><td>85</td>
 667 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT</td>
 668 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 669 </tr>
 670 <tr class="row-even"><td>86</td>
 671 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT</td>
 672 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 673 </tr>
 674 <tr class="row-odd"><td>87</td>
 675 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT</td>
 676 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 677 </tr>
 678 <tr class="row-even"><td>88</td>
 679 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT</td>
 680 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 681 </tr>
 682 <tr class="row-odd"><td>89</td>
 683 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT</td>
 684 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 685 </tr>
 686 <tr class="row-even"><td>90</td>
 687 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT</td>
 688 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 689 </tr>
 690 <tr class="row-odd"><td>91</td>
 691 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT</td>
 692 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 693 </tr>
 694 <tr class="row-even"><td>92</td>
 695 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT</td>
 696 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 697 </tr>
 698 <tr class="row-odd"><td>93</td>
 699 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT</td>
 700 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 701 </tr>
 702 <tr class="row-even"><td>94</td>
 703 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT</td>
 704 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 705 </tr>
 706 <tr class="row-odd"><td>95</td>
 707 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT</td>
 708 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 709 </tr>
 710 <tr class="row-even"><td>96</td>
 711 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT</td>
 712 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 713 </tr>
 714 <tr class="row-odd"><td>97</td>
 715 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT</td>
 716 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 717 </tr>
 718 <tr class="row-even"><td>98</td>
 719 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT</td>
 720 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 721 </tr>
 722 <tr class="row-odd"><td>99</td>
 723 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT</td>
 724 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 725 </tr>
 726 <tr class="row-even"><td>100</td>
 727 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT</td>
 728 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 729 </tr>
 730 <tr class="row-odd"><td>101</td>
 731 <td>DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
 732 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 733 </tr>
 734 <tr class="row-even"><td>102</td>
 735 <td>DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
 736 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 737 </tr>
 738 <tr class="row-odd"><td>103</td>
 739 <td>DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
 740 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 741 </tr>
 742 <tr class="row-even"><td>104</td>
 743 <td>DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
 744 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 745 </tr>
 746 <tr class="row-odd"><td>105</td>
 747 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
 748 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 749 </tr>
 750 <tr class="row-even"><td>106</td>
 751 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
 752 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 753 </tr>
 754 <tr class="row-odd"><td>107</td>
 755 <td>DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK</td>
 756 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 757 </tr>
 758 <tr class="row-even"><td>108</td>
 759 <td>DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK</td>
 760 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 761 </tr>
 762 <tr class="row-odd"><td>109</td>
 763 <td>DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0</td>
 764 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 765 </tr>
 766 <tr class="row-even"><td>110</td>
 767 <td>DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1</td>
 768 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 769 </tr>
 770 <tr class="row-odd"><td>111</td>
 771 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
 772 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 773 </tr>
 774 <tr class="row-even"><td>112</td>
 775 <td>DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
 776 <td>Parent input clock option to DEV_AASRC0_RX2_SYNC</td>
 777 </tr>
 778 <tr class="row-odd"><td>113</td>
 779 <td>DEV_AASRC0_RX3_SYNC</td>
 780 <td>Input muxed clock</td>
 781 </tr>
 782 <tr class="row-even"><td>114</td>
 783 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT</td>
 784 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 785 </tr>
 786 <tr class="row-odd"><td>115</td>
 787 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT</td>
 788 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 789 </tr>
 790 <tr class="row-even"><td>116</td>
 791 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT</td>
 792 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 793 </tr>
 794 <tr class="row-odd"><td>117</td>
 795 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT</td>
 796 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 797 </tr>
 798 <tr class="row-even"><td>118</td>
 799 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT</td>
 800 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 801 </tr>
 802 <tr class="row-odd"><td>119</td>
 803 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT</td>
 804 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 805 </tr>
 806 <tr class="row-even"><td>120</td>
 807 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT</td>
 808 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 809 </tr>
 810 <tr class="row-odd"><td>121</td>
 811 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT</td>
 812 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 813 </tr>
 814 <tr class="row-even"><td>122</td>
 815 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT</td>
 816 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 817 </tr>
 818 <tr class="row-odd"><td>123</td>
 819 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT</td>
 820 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 821 </tr>
 822 <tr class="row-even"><td>124</td>
 823 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT</td>
 824 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 825 </tr>
 826 <tr class="row-odd"><td>125</td>
 827 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT</td>
 828 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 829 </tr>
 830 <tr class="row-even"><td>126</td>
 831 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT</td>
 832 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 833 </tr>
 834 <tr class="row-odd"><td>127</td>
 835 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT</td>
 836 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 837 </tr>
 838 <tr class="row-even"><td>128</td>
 839 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT</td>
 840 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 841 </tr>
 842 <tr class="row-odd"><td>129</td>
 843 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT</td>
 844 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 845 </tr>
 846 <tr class="row-even"><td>130</td>
 847 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT</td>
 848 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 849 </tr>
 850 <tr class="row-odd"><td>131</td>
 851 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT</td>
 852 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 853 </tr>
 854 <tr class="row-even"><td>132</td>
 855 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT</td>
 856 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 857 </tr>
 858 <tr class="row-odd"><td>133</td>
 859 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT</td>
 860 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 861 </tr>
 862 <tr class="row-even"><td>134</td>
 863 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT</td>
 864 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 865 </tr>
 866 <tr class="row-odd"><td>135</td>
 867 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT</td>
 868 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 869 </tr>
 870 <tr class="row-even"><td>136</td>
 871 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT</td>
 872 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 873 </tr>
 874 <tr class="row-odd"><td>137</td>
 875 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT</td>
 876 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 877 </tr>
 878 <tr class="row-even"><td>138</td>
 879 <td>DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
 880 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 881 </tr>
 882 <tr class="row-odd"><td>139</td>
 883 <td>DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
 884 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 885 </tr>
 886 <tr class="row-even"><td>140</td>
 887 <td>DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
 888 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 889 </tr>
 890 <tr class="row-odd"><td>141</td>
 891 <td>DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
 892 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 893 </tr>
 894 <tr class="row-even"><td>142</td>
 895 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
 896 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 897 </tr>
 898 <tr class="row-odd"><td>143</td>
 899 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
 900 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 901 </tr>
 902 <tr class="row-even"><td>144</td>
 903 <td>DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK</td>
 904 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 905 </tr>
 906 <tr class="row-odd"><td>145</td>
 907 <td>DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK</td>
 908 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 909 </tr>
 910 <tr class="row-even"><td>146</td>
 911 <td>DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0</td>
 912 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 913 </tr>
 914 <tr class="row-odd"><td>147</td>
 915 <td>DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1</td>
 916 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 917 </tr>
 918 <tr class="row-even"><td>148</td>
 919 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
 920 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 921 </tr>
 922 <tr class="row-odd"><td>149</td>
 923 <td>DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
 924 <td>Parent input clock option to DEV_AASRC0_RX3_SYNC</td>
 925 </tr>
 926 <tr class="row-even"><td>150</td>
 927 <td>DEV_AASRC0_TX0_SYNC</td>
 928 <td>Input muxed clock</td>
 929 </tr>
 930 <tr class="row-odd"><td>151</td>
 931 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT</td>
 932 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 933 </tr>
 934 <tr class="row-even"><td>152</td>
 935 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT</td>
 936 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 937 </tr>
 938 <tr class="row-odd"><td>153</td>
 939 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0</td>
 940 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 941 </tr>
 942 <tr class="row-even"><td>154</td>
 943 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0</td>
 944 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 945 </tr>
 946 <tr class="row-odd"><td>155</td>
 947 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0</td>
 948 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 949 </tr>
 950 <tr class="row-even"><td>156</td>
 951 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0</td>
 952 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 953 </tr>
 954 <tr class="row-odd"><td>157</td>
 955 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0</td>
 956 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 957 </tr>
 958 <tr class="row-even"><td>158</td>
 959 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0</td>
 960 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 961 </tr>
 962 <tr class="row-odd"><td>159</td>
 963 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0</td>
 964 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 965 </tr>
 966 <tr class="row-even"><td>160</td>
 967 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0</td>
 968 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 969 </tr>
 970 <tr class="row-odd"><td>161</td>
 971 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT</td>
 972 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 973 </tr>
 974 <tr class="row-even"><td>162</td>
 975 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT</td>
 976 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 977 </tr>
 978 <tr class="row-odd"><td>163</td>
 979 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0</td>
 980 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 981 </tr>
 982 <tr class="row-even"><td>164</td>
 983 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0</td>
 984 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 985 </tr>
 986 <tr class="row-odd"><td>165</td>
 987 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT</td>
 988 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 989 </tr>
 990 <tr class="row-even"><td>166</td>
 991 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT</td>
 992 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 993 </tr>
 994 <tr class="row-odd"><td>167</td>
 995 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT</td>
 996 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
 997 </tr>
 998 <tr class="row-even"><td>168</td>
 999 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT</td>
1000 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1001 </tr>
1002 <tr class="row-odd"><td>169</td>
1003 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT</td>
1004 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1005 </tr>
1006 <tr class="row-even"><td>170</td>
1007 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT</td>
1008 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1009 </tr>
1010 <tr class="row-odd"><td>171</td>
1011 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT</td>
1012 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1013 </tr>
1014 <tr class="row-even"><td>172</td>
1015 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT</td>
1016 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1017 </tr>
1018 <tr class="row-odd"><td>173</td>
1019 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0</td>
1020 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1021 </tr>
1022 <tr class="row-even"><td>174</td>
1023 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0</td>
1024 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1025 </tr>
1026 <tr class="row-odd"><td>175</td>
1027 <td>DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
1028 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1029 </tr>
1030 <tr class="row-even"><td>176</td>
1031 <td>DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
1032 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1033 </tr>
1034 <tr class="row-odd"><td>177</td>
1035 <td>DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
1036 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1037 </tr>
1038 <tr class="row-even"><td>178</td>
1039 <td>DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
1040 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1041 </tr>
1042 <tr class="row-odd"><td>179</td>
1043 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
1044 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1045 </tr>
1046 <tr class="row-even"><td>180</td>
1047 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
1048 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1049 </tr>
1050 <tr class="row-odd"><td>181</td>
1051 <td>DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK</td>
1052 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1053 </tr>
1054 <tr class="row-even"><td>182</td>
1055 <td>DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK</td>
1056 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1057 </tr>
1058 <tr class="row-odd"><td>183</td>
1059 <td>DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0</td>
1060 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1061 </tr>
1062 <tr class="row-even"><td>184</td>
1063 <td>DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1</td>
1064 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1065 </tr>
1066 <tr class="row-odd"><td>185</td>
1067 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
1068 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1069 </tr>
1070 <tr class="row-even"><td>186</td>
1071 <td>DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
1072 <td>Parent input clock option to DEV_AASRC0_TX0_SYNC</td>
1073 </tr>
1074 <tr class="row-odd"><td>187</td>
1075 <td>DEV_AASRC0_TX1_SYNC</td>
1076 <td>Input muxed clock</td>
1077 </tr>
1078 <tr class="row-even"><td>188</td>
1079 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT</td>
1080 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1081 </tr>
1082 <tr class="row-odd"><td>189</td>
1083 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT</td>
1084 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1085 </tr>
1086 <tr class="row-even"><td>190</td>
1087 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0</td>
1088 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1089 </tr>
1090 <tr class="row-odd"><td>191</td>
1091 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0</td>
1092 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1093 </tr>
1094 <tr class="row-even"><td>192</td>
1095 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0</td>
1096 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1097 </tr>
1098 <tr class="row-odd"><td>193</td>
1099 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0</td>
1100 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1101 </tr>
1102 <tr class="row-even"><td>194</td>
1103 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0</td>
1104 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1105 </tr>
1106 <tr class="row-odd"><td>195</td>
1107 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0</td>
1108 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1109 </tr>
1110 <tr class="row-even"><td>196</td>
1111 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0</td>
1112 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1113 </tr>
1114 <tr class="row-odd"><td>197</td>
1115 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0</td>
1116 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1117 </tr>
1118 <tr class="row-even"><td>198</td>
1119 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT</td>
1120 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1121 </tr>
1122 <tr class="row-odd"><td>199</td>
1123 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT</td>
1124 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1125 </tr>
1126 <tr class="row-even"><td>200</td>
1127 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0</td>
1128 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1129 </tr>
1130 <tr class="row-odd"><td>201</td>
1131 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0</td>
1132 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1133 </tr>
1134 <tr class="row-even"><td>202</td>
1135 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT</td>
1136 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1137 </tr>
1138 <tr class="row-odd"><td>203</td>
1139 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT</td>
1140 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1141 </tr>
1142 <tr class="row-even"><td>204</td>
1143 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT</td>
1144 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1145 </tr>
1146 <tr class="row-odd"><td>205</td>
1147 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT</td>
1148 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1149 </tr>
1150 <tr class="row-even"><td>206</td>
1151 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT</td>
1152 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1153 </tr>
1154 <tr class="row-odd"><td>207</td>
1155 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT</td>
1156 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1157 </tr>
1158 <tr class="row-even"><td>208</td>
1159 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT</td>
1160 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1161 </tr>
1162 <tr class="row-odd"><td>209</td>
1163 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT</td>
1164 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1165 </tr>
1166 <tr class="row-even"><td>210</td>
1167 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0</td>
1168 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1169 </tr>
1170 <tr class="row-odd"><td>211</td>
1171 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0</td>
1172 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1173 </tr>
1174 <tr class="row-even"><td>212</td>
1175 <td>DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
1176 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1177 </tr>
1178 <tr class="row-odd"><td>213</td>
1179 <td>DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
1180 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1181 </tr>
1182 <tr class="row-even"><td>214</td>
1183 <td>DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
1184 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1185 </tr>
1186 <tr class="row-odd"><td>215</td>
1187 <td>DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
1188 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1189 </tr>
1190 <tr class="row-even"><td>216</td>
1191 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
1192 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1193 </tr>
1194 <tr class="row-odd"><td>217</td>
1195 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
1196 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1197 </tr>
1198 <tr class="row-even"><td>218</td>
1199 <td>DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK</td>
1200 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1201 </tr>
1202 <tr class="row-odd"><td>219</td>
1203 <td>DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK</td>
1204 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1205 </tr>
1206 <tr class="row-even"><td>220</td>
1207 <td>DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0</td>
1208 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1209 </tr>
1210 <tr class="row-odd"><td>221</td>
1211 <td>DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1</td>
1212 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1213 </tr>
1214 <tr class="row-even"><td>222</td>
1215 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
1216 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1217 </tr>
1218 <tr class="row-odd"><td>223</td>
1219 <td>DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
1220 <td>Parent input clock option to DEV_AASRC0_TX1_SYNC</td>
1221 </tr>
1222 <tr class="row-even"><td>224</td>
1223 <td>DEV_AASRC0_TX2_SYNC</td>
1224 <td>Input muxed clock</td>
1225 </tr>
1226 <tr class="row-odd"><td>225</td>
1227 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT</td>
1228 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1229 </tr>
1230 <tr class="row-even"><td>226</td>
1231 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT</td>
1232 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1233 </tr>
1234 <tr class="row-odd"><td>227</td>
1235 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0</td>
1236 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1237 </tr>
1238 <tr class="row-even"><td>228</td>
1239 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0</td>
1240 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1241 </tr>
1242 <tr class="row-odd"><td>229</td>
1243 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0</td>
1244 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1245 </tr>
1246 <tr class="row-even"><td>230</td>
1247 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0</td>
1248 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1249 </tr>
1250 <tr class="row-odd"><td>231</td>
1251 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0</td>
1252 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1253 </tr>
1254 <tr class="row-even"><td>232</td>
1255 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0</td>
1256 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1257 </tr>
1258 <tr class="row-odd"><td>233</td>
1259 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0</td>
1260 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1261 </tr>
1262 <tr class="row-even"><td>234</td>
1263 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0</td>
1264 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1265 </tr>
1266 <tr class="row-odd"><td>235</td>
1267 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT</td>
1268 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1269 </tr>
1270 <tr class="row-even"><td>236</td>
1271 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT</td>
1272 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1273 </tr>
1274 <tr class="row-odd"><td>237</td>
1275 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0</td>
1276 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1277 </tr>
1278 <tr class="row-even"><td>238</td>
1279 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0</td>
1280 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1281 </tr>
1282 <tr class="row-odd"><td>239</td>
1283 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT</td>
1284 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1285 </tr>
1286 <tr class="row-even"><td>240</td>
1287 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT</td>
1288 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1289 </tr>
1290 <tr class="row-odd"><td>241</td>
1291 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT</td>
1292 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1293 </tr>
1294 <tr class="row-even"><td>242</td>
1295 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT</td>
1296 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1297 </tr>
1298 <tr class="row-odd"><td>243</td>
1299 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT</td>
1300 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1301 </tr>
1302 <tr class="row-even"><td>244</td>
1303 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT</td>
1304 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1305 </tr>
1306 <tr class="row-odd"><td>245</td>
1307 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT</td>
1308 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1309 </tr>
1310 <tr class="row-even"><td>246</td>
1311 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT</td>
1312 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1313 </tr>
1314 <tr class="row-odd"><td>247</td>
1315 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0</td>
1316 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1317 </tr>
1318 <tr class="row-even"><td>248</td>
1319 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0</td>
1320 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1321 </tr>
1322 <tr class="row-odd"><td>249</td>
1323 <td>DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
1324 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1325 </tr>
1326 <tr class="row-even"><td>250</td>
1327 <td>DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
1328 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1329 </tr>
1330 <tr class="row-odd"><td>251</td>
1331 <td>DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
1332 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1333 </tr>
1334 <tr class="row-even"><td>252</td>
1335 <td>DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
1336 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1337 </tr>
1338 <tr class="row-odd"><td>253</td>
1339 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
1340 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1341 </tr>
1342 <tr class="row-even"><td>254</td>
1343 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
1344 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1345 </tr>
1346 <tr class="row-odd"><td>255</td>
1347 <td>DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK</td>
1348 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1349 </tr>
1350 <tr class="row-even"><td>256</td>
1351 <td>DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK</td>
1352 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1353 </tr>
1354 <tr class="row-odd"><td>257</td>
1355 <td>DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0</td>
1356 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1357 </tr>
1358 <tr class="row-even"><td>258</td>
1359 <td>DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1</td>
1360 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1361 </tr>
1362 <tr class="row-odd"><td>259</td>
1363 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
1364 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1365 </tr>
1366 <tr class="row-even"><td>260</td>
1367 <td>DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
1368 <td>Parent input clock option to DEV_AASRC0_TX2_SYNC</td>
1369 </tr>
1370 <tr class="row-odd"><td>261</td>
1371 <td>DEV_AASRC0_TX3_SYNC</td>
1372 <td>Input muxed clock</td>
1373 </tr>
1374 <tr class="row-even"><td>262</td>
1375 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT</td>
1376 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1377 </tr>
1378 <tr class="row-odd"><td>263</td>
1379 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT</td>
1380 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1381 </tr>
1382 <tr class="row-even"><td>264</td>
1383 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0</td>
1384 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1385 </tr>
1386 <tr class="row-odd"><td>265</td>
1387 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0</td>
1388 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1389 </tr>
1390 <tr class="row-even"><td>266</td>
1391 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0</td>
1392 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1393 </tr>
1394 <tr class="row-odd"><td>267</td>
1395 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0</td>
1396 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1397 </tr>
1398 <tr class="row-even"><td>268</td>
1399 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0</td>
1400 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1401 </tr>
1402 <tr class="row-odd"><td>269</td>
1403 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0</td>
1404 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1405 </tr>
1406 <tr class="row-even"><td>270</td>
1407 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0</td>
1408 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1409 </tr>
1410 <tr class="row-odd"><td>271</td>
1411 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0</td>
1412 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1413 </tr>
1414 <tr class="row-even"><td>272</td>
1415 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT</td>
1416 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1417 </tr>
1418 <tr class="row-odd"><td>273</td>
1419 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT</td>
1420 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1421 </tr>
1422 <tr class="row-even"><td>274</td>
1423 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0</td>
1424 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1425 </tr>
1426 <tr class="row-odd"><td>275</td>
1427 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0</td>
1428 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1429 </tr>
1430 <tr class="row-even"><td>276</td>
1431 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT</td>
1432 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1433 </tr>
1434 <tr class="row-odd"><td>277</td>
1435 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT</td>
1436 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1437 </tr>
1438 <tr class="row-even"><td>278</td>
1439 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT</td>
1440 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1441 </tr>
1442 <tr class="row-odd"><td>279</td>
1443 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT</td>
1444 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1445 </tr>
1446 <tr class="row-even"><td>280</td>
1447 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT</td>
1448 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1449 </tr>
1450 <tr class="row-odd"><td>281</td>
1451 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT</td>
1452 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1453 </tr>
1454 <tr class="row-even"><td>282</td>
1455 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT</td>
1456 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1457 </tr>
1458 <tr class="row-odd"><td>283</td>
1459 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT</td>
1460 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1461 </tr>
1462 <tr class="row-even"><td>284</td>
1463 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0</td>
1464 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1465 </tr>
1466 <tr class="row-odd"><td>285</td>
1467 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0</td>
1468 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1469 </tr>
1470 <tr class="row-even"><td>286</td>
1471 <td>DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
1472 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1473 </tr>
1474 <tr class="row-odd"><td>287</td>
1475 <td>DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
1476 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1477 </tr>
1478 <tr class="row-even"><td>288</td>
1479 <td>DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
1480 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1481 </tr>
1482 <tr class="row-odd"><td>289</td>
1483 <td>DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
1484 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1485 </tr>
1486 <tr class="row-even"><td>290</td>
1487 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
1488 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1489 </tr>
1490 <tr class="row-odd"><td>291</td>
1491 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
1492 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1493 </tr>
1494 <tr class="row-even"><td>292</td>
1495 <td>DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK</td>
1496 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1497 </tr>
1498 <tr class="row-odd"><td>293</td>
1499 <td>DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK</td>
1500 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1501 </tr>
1502 <tr class="row-even"><td>294</td>
1503 <td>DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0</td>
1504 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1505 </tr>
1506 <tr class="row-odd"><td>295</td>
1507 <td>DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1</td>
1508 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1509 </tr>
1510 <tr class="row-even"><td>296</td>
1511 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
1512 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1513 </tr>
1514 <tr class="row-odd"><td>297</td>
1515 <td>DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
1516 <td>Parent input clock option to DEV_AASRC0_TX3_SYNC</td>
1517 </tr>
1518 </tbody>
1519 </table>
1520 </div>
1521 <div class="section" id="clocks-for-atl0-device">
1522 <span id="soc-doc-j721e-public-clks-atl0"></span><h3>Clocks for ATL0 Device<a class="headerlink" href="#clocks-for-atl0-device" title="Permalink to this headline">¶</a></h3>
1523 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_ATL0</span></a> (ID = 2)</p>
1524 <p>Following is a mapping of Clocks IDs to function:</p>
1525 <table border="1" class="docutils">
1526 <colgroup>
1527 <col width="10%" />
1528 <col width="51%" />
1529 <col width="39%" />
1530 </colgroup>
1531 <thead valign="bottom">
1532 <tr class="row-odd"><th class="head">Clock ID</th>
1533 <th class="head">Name</th>
1534 <th class="head">Function</th>
1535 </tr>
1536 </thead>
1537 <tbody valign="top">
1538 <tr class="row-even"><td>0</td>
1539 <td>DEV_ATL0_VBUS_CLK</td>
1540 <td>Input clock</td>
1541 </tr>
1542 <tr class="row-odd"><td>1</td>
1543 <td>DEV_ATL0_ATL_CLK</td>
1544 <td>Input muxed clock</td>
1545 </tr>
1546 <tr class="row-even"><td>2</td>
1547 <td>DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK</td>
1548 <td>Parent input clock option to DEV_ATL0_ATL_CLK</td>
1549 </tr>
1550 <tr class="row-odd"><td>3</td>
1551 <td>DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
1552 <td>Parent input clock option to DEV_ATL0_ATL_CLK</td>
1553 </tr>
1554 <tr class="row-even"><td>4</td>
1555 <td>DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT1_CLK</td>
1556 <td>Parent input clock option to DEV_ATL0_ATL_CLK</td>
1557 </tr>
1558 <tr class="row-odd"><td>5</td>
1559 <td>DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK</td>
1560 <td>Parent input clock option to DEV_ATL0_ATL_CLK</td>
1561 </tr>
1562 <tr class="row-even"><td>6</td>
1563 <td>DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
1564 <td>Parent input clock option to DEV_ATL0_ATL_CLK</td>
1565 </tr>
1566 <tr class="row-odd"><td>7</td>
1567 <td>DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
1568 <td>Parent input clock option to DEV_ATL0_ATL_CLK</td>
1569 </tr>
1570 <tr class="row-even"><td>8</td>
1571 <td>DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1</td>
1572 <td>Output clock</td>
1573 </tr>
1574 <tr class="row-odd"><td>9</td>
1575 <td>DEV_ATL0_ATL_IO_PORT_ATCLK_OUT</td>
1576 <td>Output clock</td>
1577 </tr>
1578 <tr class="row-even"><td>10</td>
1579 <td>DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3</td>
1580 <td>Output clock</td>
1581 </tr>
1582 <tr class="row-odd"><td>11</td>
1583 <td>DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2</td>
1584 <td>Output clock</td>
1585 </tr>
1586 </tbody>
1587 </table>
1588 </div>
1589 <div class="section" id="clocks-for-board0-device">
1590 <span id="soc-doc-j721e-public-clks-board0"></span><h3>Clocks for BOARD0 Device<a class="headerlink" href="#clocks-for-board0-device" title="Permalink to this headline">¶</a></h3>
1591 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_BOARD0</span></a> (ID = 157)</p>
1592 <div class="admonition note">
1593 <p class="first admonition-title">Note</p>
1594 <p>BOARD0 is a special device that represents the board on which
1595 the SoC is mounted.</p>
1596 <p>Clocks that are incoming to or outgoing from the SoC are
1597 represented in this section from the <em>perspective of the board</em>.</p>
1598 <p>Function documented here implies:</p>
1599 <table border="1" class="docutils">
1600 <colgroup>
1601 <col width="15%" />
1602 <col width="85%" />
1603 </colgroup>
1604 <thead valign="bottom">
1605 <tr class="row-odd"><th class="head">Function</th>
1606 <th class="head">Description</th>
1607 </tr>
1608 </thead>
1609 <tbody valign="top">
1610 <tr class="row-even"><td>Input clock</td>
1611 <td>Clock is supplied from SoC to the board (It is an output of the SoC)</td>
1612 </tr>
1613 <tr class="row-odd"><td>Output clock</td>
1614 <td>Clock is supplied from board to the SoC (It is an output of the Board and input to the SoC)</td>
1615 </tr>
1616 </tbody>
1617 </table>
1618 <p class="last"><strong>NOTE: Clocks which can be bi-directional are listed as Output clock</strong></p>
1619 </div>
1620 <p>Following is a mapping of Clocks IDs to function:</p>
1621 <table border="1" class="docutils">
1622 <colgroup>
1623 <col width="8%" />
1624 <col width="50%" />
1625 <col width="42%" />
1626 </colgroup>
1627 <thead valign="bottom">
1628 <tr class="row-odd"><th class="head">Clock ID</th>
1629 <th class="head">Name</th>
1630 <th class="head">Function</th>
1631 </tr>
1632 </thead>
1633 <tbody valign="top">
1634 <tr class="row-even"><td>0</td>
1635 <td>DEV_BOARD0_SPI0_CLK_IN</td>
1636 <td>Input clock</td>
1637 </tr>
1638 <tr class="row-odd"><td>2</td>
1639 <td>DEV_BOARD0_SPI1_CLK_IN</td>
1640 <td>Input clock</td>
1641 </tr>
1642 <tr class="row-even"><td>4</td>
1643 <td>DEV_BOARD0_SPI2_CLK_IN</td>
1644 <td>Input clock</td>
1645 </tr>
1646 <tr class="row-odd"><td>6</td>
1647 <td>DEV_BOARD0_SPI3_CLK_IN</td>
1648 <td>Input clock</td>
1649 </tr>
1650 <tr class="row-even"><td>8</td>
1651 <td>DEV_BOARD0_SPI5_CLK_IN</td>
1652 <td>Input clock</td>
1653 </tr>
1654 <tr class="row-odd"><td>10</td>
1655 <td>DEV_BOARD0_SPI6_CLK_IN</td>
1656 <td>Input clock</td>
1657 </tr>
1658 <tr class="row-even"><td>12</td>
1659 <td>DEV_BOARD0_SPI7_CLK_IN</td>
1660 <td>Input clock</td>
1661 </tr>
1662 <tr class="row-odd"><td>14</td>
1663 <td>DEV_BOARD0_MCU_SPI0_CLK_IN</td>
1664 <td>Input clock</td>
1665 </tr>
1666 <tr class="row-even"><td>16</td>
1667 <td>DEV_BOARD0_MCU_SPI1_CLK_IN</td>
1668 <td>Input clock</td>
1669 </tr>
1670 <tr class="row-odd"><td>18</td>
1671 <td>DEV_BOARD0_MCU_OSPI0_CLK_IN</td>
1672 <td>Input clock</td>
1673 </tr>
1674 <tr class="row-even"><td>19</td>
1675 <td>DEV_BOARD0_MCU_OSPI0_LBCLKO_IN</td>
1676 <td>Input clock</td>
1677 </tr>
1678 <tr class="row-odd"><td>20</td>
1679 <td>DEV_BOARD0_MCU_OSPI0_DQS_OUT</td>
1680 <td>Output clock</td>
1681 </tr>
1682 <tr class="row-even"><td>21</td>
1683 <td>DEV_BOARD0_MCU_OSPI1_CLK_IN</td>
1684 <td>Input clock</td>
1685 </tr>
1686 <tr class="row-odd"><td>22</td>
1687 <td>DEV_BOARD0_MCU_OSPI1_LBCLKO_IN</td>
1688 <td>Input clock</td>
1689 </tr>
1690 <tr class="row-even"><td>23</td>
1691 <td>DEV_BOARD0_MCU_OSPI1_DQS_OUT</td>
1692 <td>Output clock</td>
1693 </tr>
1694 <tr class="row-odd"><td>25</td>
1695 <td>DEV_BOARD0_I2C0_SCL_OUT</td>
1696 <td>Output clock</td>
1697 </tr>
1698 <tr class="row-even"><td>27</td>
1699 <td>DEV_BOARD0_I2C1_SCL_OUT</td>
1700 <td>Output clock</td>
1701 </tr>
1702 <tr class="row-odd"><td>29</td>
1703 <td>DEV_BOARD0_I2C2_SCL_OUT</td>
1704 <td>Output clock</td>
1705 </tr>
1706 <tr class="row-even"><td>31</td>
1707 <td>DEV_BOARD0_I2C3_SCL_OUT</td>
1708 <td>Output clock</td>
1709 </tr>
1710 <tr class="row-odd"><td>33</td>
1711 <td>DEV_BOARD0_I2C4_SCL_OUT</td>
1712 <td>Output clock</td>
1713 </tr>
1714 <tr class="row-even"><td>35</td>
1715 <td>DEV_BOARD0_I2C5_SCL_OUT</td>
1716 <td>Output clock</td>
1717 </tr>
1718 <tr class="row-odd"><td>37</td>
1719 <td>DEV_BOARD0_I2C6_SCL_OUT</td>
1720 <td>Output clock</td>
1721 </tr>
1722 <tr class="row-even"><td>38</td>
1723 <td>DEV_BOARD0_MCU_I2C0_SCL_IN</td>
1724 <td>Input clock</td>
1725 </tr>
1726 <tr class="row-odd"><td>39</td>
1727 <td>DEV_BOARD0_MCU_I2C0_SCL_OUT</td>
1728 <td>Output clock</td>
1729 </tr>
1730 <tr class="row-even"><td>41</td>
1731 <td>DEV_BOARD0_MCU_I2C1_SCL_OUT</td>
1732 <td>Output clock</td>
1733 </tr>
1734 <tr class="row-odd"><td>42</td>
1735 <td>DEV_BOARD0_WKUP_I2C0_SCL_IN</td>
1736 <td>Input clock</td>
1737 </tr>
1738 <tr class="row-even"><td>43</td>
1739 <td>DEV_BOARD0_WKUP_I2C0_SCL_OUT</td>
1740 <td>Output clock</td>
1741 </tr>
1742 <tr class="row-odd"><td>44</td>
1743 <td>DEV_BOARD0_I3C0_SCL_IN</td>
1744 <td>Input clock</td>
1745 </tr>
1746 <tr class="row-even"><td>45</td>
1747 <td>DEV_BOARD0_I3C0_SCL_OUT</td>
1748 <td>Output clock</td>
1749 </tr>
1750 <tr class="row-odd"><td>46</td>
1751 <td>DEV_BOARD0_MCU_I3C0_SCL_IN</td>
1752 <td>Input clock</td>
1753 </tr>
1754 <tr class="row-even"><td>47</td>
1755 <td>DEV_BOARD0_MCU_I3C0_SCL_OUT</td>
1756 <td>Output clock</td>
1757 </tr>
1758 <tr class="row-odd"><td>48</td>
1759 <td>DEV_BOARD0_MCU_I3C1_SCL_IN</td>
1760 <td>Input clock</td>
1761 </tr>
1762 <tr class="row-even"><td>49</td>
1763 <td>DEV_BOARD0_MCU_I3C1_SCL_OUT</td>
1764 <td>Output clock</td>
1765 </tr>
1766 <tr class="row-odd"><td>50</td>
1767 <td>DEV_BOARD0_MCU_HYPERBUS0_CK_IN</td>
1768 <td>Input clock</td>
1769 </tr>
1770 <tr class="row-even"><td>51</td>
1771 <td>DEV_BOARD0_MCU_HYPERBUS0_CKN_IN</td>
1772 <td>Input clock</td>
1773 </tr>
1774 <tr class="row-odd"><td>52</td>
1775 <td>DEV_BOARD0_DSI_TXCLKP_IN</td>
1776 <td>Input clock</td>
1777 </tr>
1778 <tr class="row-even"><td>53</td>
1779 <td>DEV_BOARD0_DSI_TXCLKN_IN</td>
1780 <td>Input clock</td>
1781 </tr>
1782 <tr class="row-odd"><td>54</td>
1783 <td>DEV_BOARD0_PRG0_MDIO0_MDC_IN</td>
1784 <td>Input clock</td>
1785 </tr>
1786 <tr class="row-even"><td>55</td>
1787 <td>DEV_BOARD0_PRG0_RGMII1_TXC_IN</td>
1788 <td>Input clock</td>
1789 </tr>
1790 <tr class="row-odd"><td>56</td>
1791 <td>DEV_BOARD0_PRG0_RGMII1_TXC_OUT</td>
1792 <td>Output clock</td>
1793 </tr>
1794 <tr class="row-even"><td>57</td>
1795 <td>DEV_BOARD0_PRG0_RGMII1_RXC_OUT</td>
1796 <td>Output clock</td>
1797 </tr>
1798 <tr class="row-odd"><td>58</td>
1799 <td>DEV_BOARD0_PRG0_RGMII2_TXC_IN</td>
1800 <td>Input clock</td>
1801 </tr>
1802 <tr class="row-even"><td>59</td>
1803 <td>DEV_BOARD0_PRG0_RGMII2_TXC_OUT</td>
1804 <td>Output clock</td>
1805 </tr>
1806 <tr class="row-odd"><td>60</td>
1807 <td>DEV_BOARD0_PRG0_RGMII2_RXC_OUT</td>
1808 <td>Output clock</td>
1809 </tr>
1810 <tr class="row-even"><td>61</td>
1811 <td>DEV_BOARD0_PRG1_MDIO0_MDC_IN</td>
1812 <td>Input clock</td>
1813 </tr>
1814 <tr class="row-odd"><td>62</td>
1815 <td>DEV_BOARD0_PRG1_RGMII1_TXC_IN</td>
1816 <td>Input clock</td>
1817 </tr>
1818 <tr class="row-even"><td>63</td>
1819 <td>DEV_BOARD0_PRG1_RGMII1_TXC_OUT</td>
1820 <td>Output clock</td>
1821 </tr>
1822 <tr class="row-odd"><td>64</td>
1823 <td>DEV_BOARD0_PRG1_RGMII1_RXC_OUT</td>
1824 <td>Output clock</td>
1825 </tr>
1826 <tr class="row-even"><td>65</td>
1827 <td>DEV_BOARD0_PRG1_RGMII2_TXC_IN</td>
1828 <td>Input clock</td>
1829 </tr>
1830 <tr class="row-odd"><td>66</td>
1831 <td>DEV_BOARD0_PRG1_RGMII2_TXC_OUT</td>
1832 <td>Output clock</td>
1833 </tr>
1834 <tr class="row-even"><td>67</td>
1835 <td>DEV_BOARD0_PRG1_RGMII2_RXC_OUT</td>
1836 <td>Output clock</td>
1837 </tr>
1838 <tr class="row-odd"><td>68</td>
1839 <td>DEV_BOARD0_MDIO0_MDC_IN</td>
1840 <td>Input clock</td>
1841 </tr>
1842 <tr class="row-even"><td>70</td>
1843 <td>DEV_BOARD0_RGMII3_RXC_OUT</td>
1844 <td>Output clock</td>
1845 </tr>
1846 <tr class="row-odd"><td>72</td>
1847 <td>DEV_BOARD0_RGMII4_RXC_OUT</td>
1848 <td>Output clock</td>
1849 </tr>
1850 <tr class="row-even"><td>74</td>
1851 <td>DEV_BOARD0_RGMII5_RXC_OUT</td>
1852 <td>Output clock</td>
1853 </tr>
1854 <tr class="row-odd"><td>76</td>
1855 <td>DEV_BOARD0_RGMII6_RXC_OUT</td>
1856 <td>Output clock</td>
1857 </tr>
1858 <tr class="row-even"><td>78</td>
1859 <td>DEV_BOARD0_RGMII7_RXC_OUT</td>
1860 <td>Output clock</td>
1861 </tr>
1862 <tr class="row-odd"><td>80</td>
1863 <td>DEV_BOARD0_RGMII8_RXC_OUT</td>
1864 <td>Output clock</td>
1865 </tr>
1866 <tr class="row-even"><td>81</td>
1867 <td>DEV_BOARD0_RMII_REF_CLK_OUT</td>
1868 <td>Output clock</td>
1869 </tr>
1870 <tr class="row-odd"><td>82</td>
1871 <td>DEV_BOARD0_CPTS0_RFT_CLK_OUT</td>
1872 <td>Output clock</td>
1873 </tr>
1874 <tr class="row-even"><td>83</td>
1875 <td>DEV_BOARD0_MCU_MDIO0_MDC_IN</td>
1876 <td>Input clock</td>
1877 </tr>
1878 <tr class="row-odd"><td>84</td>
1879 <td>DEV_BOARD0_MCU_RGMII1_TXC_IN</td>
1880 <td>Input clock</td>
1881 </tr>
1882 <tr class="row-even"><td>85</td>
1883 <td>DEV_BOARD0_MCU_RGMII1_TXC_OUT</td>
1884 <td>Output clock</td>
1885 </tr>
1886 <tr class="row-odd"><td>86</td>
1887 <td>DEV_BOARD0_MCU_RGMII1_RXC_OUT</td>
1888 <td>Output clock</td>
1889 </tr>
1890 <tr class="row-even"><td>87</td>
1891 <td>DEV_BOARD0_MCU_RMII1_REF_CLK_OUT</td>
1892 <td>Output clock</td>
1893 </tr>
1894 <tr class="row-odd"><td>88</td>
1895 <td>DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT</td>
1896 <td>Output clock</td>
1897 </tr>
1898 <tr class="row-even"><td>89</td>
1899 <td>DEV_BOARD0_UFS0_REF_CLK_IN</td>
1900 <td>Input clock</td>
1901 </tr>
1902 <tr class="row-odd"><td>91</td>
1903 <td>DEV_BOARD0_DDR0_CK0_IN</td>
1904 <td>Input clock</td>
1905 </tr>
1906 <tr class="row-even"><td>92</td>
1907 <td>DEV_BOARD0_DDR0_CK0_N_IN</td>
1908 <td>Input clock</td>
1909 </tr>
1910 <tr class="row-odd"><td>99</td>
1911 <td>DEV_BOARD0_MMC0_CLK_IN</td>
1912 <td>Input clock</td>
1913 </tr>
1914 <tr class="row-even"><td>100</td>
1915 <td>DEV_BOARD0_MMC1_CLK_IN</td>
1916 <td>Input clock</td>
1917 </tr>
1918 <tr class="row-odd"><td>101</td>
1919 <td>DEV_BOARD0_MMC2_CLK_IN</td>
1920 <td>Input clock</td>
1921 </tr>
1922 <tr class="row-even"><td>102</td>
1923 <td>DEV_BOARD0_GPMC0_CLK_IN</td>
1924 <td>Input clock</td>
1925 </tr>
1926 <tr class="row-odd"><td>103</td>
1927 <td>DEV_BOARD0_GPMC0_CLK_OUT</td>
1928 <td>Output clock</td>
1929 </tr>
1930 <tr class="row-even"><td>104</td>
1931 <td>DEV_BOARD0_GPMC0_FCLK_MUX_IN</td>
1932 <td>Input clock</td>
1933 </tr>
1934 <tr class="row-odd"><td>105</td>
1935 <td>DEV_BOARD0_MLB0_MLBCLK_OUT</td>
1936 <td>Output clock</td>
1937 </tr>
1938 <tr class="row-even"><td>106</td>
1939 <td>DEV_BOARD0_MLB0_MLBCP_OUT</td>
1940 <td>Output clock</td>
1941 </tr>
1942 <tr class="row-odd"><td>108</td>
1943 <td>DEV_BOARD0_VPFE0_PCLK_OUT</td>
1944 <td>Output clock</td>
1945 </tr>
1946 <tr class="row-even"><td>109</td>
1947 <td>DEV_BOARD0_VOUT1_PCLK_IN</td>
1948 <td>Input clock</td>
1949 </tr>
1950 <tr class="row-odd"><td>110</td>
1951 <td>DEV_BOARD0_VOUT1_EXTPCLKIN_OUT</td>
1952 <td>Output clock</td>
1953 </tr>
1954 <tr class="row-even"><td>111</td>
1955 <td>DEV_BOARD0_VOUT2_PCLK_IN</td>
1956 <td>Input clock</td>
1957 </tr>
1958 <tr class="row-odd"><td>112</td>
1959 <td>DEV_BOARD0_VOUT2_EXTPCLKIN_OUT</td>
1960 <td>Output clock</td>
1961 </tr>
1962 <tr class="row-even"><td>113</td>
1963 <td>DEV_BOARD0_OBSCLK0_IN</td>
1964 <td>Input clock</td>
1965 </tr>
1966 <tr class="row-odd"><td>114</td>
1967 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK</td>
1968 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1969 </tr>
1970 <tr class="row-even"><td>115</td>
1971 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK</td>
1972 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1973 </tr>
1974 <tr class="row-odd"><td>116</td>
1975 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK</td>
1976 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1977 </tr>
1978 <tr class="row-even"><td>117</td>
1979 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK</td>
1980 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1981 </tr>
1982 <tr class="row-odd"><td>118</td>
1983 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
1984 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1985 </tr>
1986 <tr class="row-even"><td>119</td>
1987 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_5_HSDIVOUT0_CLK</td>
1988 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1989 </tr>
1990 <tr class="row-odd"><td>120</td>
1991 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK</td>
1992 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1993 </tr>
1994 <tr class="row-even"><td>126</td>
1995 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK</td>
1996 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1997 </tr>
1998 <tr class="row-odd"><td>127</td>
1999 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0</td>
2000 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2001 </tr>
2002 <tr class="row-even"><td>128</td>
2003 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK</td>
2004 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2005 </tr>
2006 <tr class="row-odd"><td>129</td>
2007 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
2008 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2009 </tr>
2010 <tr class="row-even"><td>130</td>
2011 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK</td>
2012 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2013 </tr>
2014 <tr class="row-odd"><td>131</td>
2015 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK</td>
2016 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2017 </tr>
2018 <tr class="row-even"><td>132</td>
2019 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK</td>
2020 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2021 </tr>
2022 <tr class="row-odd"><td>133</td>
2023 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK</td>
2024 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2025 </tr>
2026 <tr class="row-even"><td>137</td>
2027 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK</td>
2028 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2029 </tr>
2030 <tr class="row-odd"><td>138</td>
2031 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_24_HSDIVOUT0_CLK</td>
2032 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2033 </tr>
2034 <tr class="row-even"><td>139</td>
2035 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK</td>
2036 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2037 </tr>
2038 <tr class="row-odd"><td>140</td>
2039 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3</td>
2040 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2041 </tr>
2042 <tr class="row-even"><td>141</td>
2043 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
2044 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2045 </tr>
2046 <tr class="row-odd"><td>142</td>
2047 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
2048 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2049 </tr>
2050 <tr class="row-even"><td>143</td>
2051 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0</td>
2052 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2053 </tr>
2054 <tr class="row-odd"><td>144</td>
2055 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
2056 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2057 </tr>
2058 <tr class="row-even"><td>145</td>
2059 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
2060 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
2061 </tr>
2062 <tr class="row-odd"><td>146</td>
2063 <td>DEV_BOARD0_OBSCLK1_IN</td>
2064 <td>Input muxed clock</td>
2065 </tr>
2066 <tr class="row-even"><td>147</td>
2067 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_7_HSDIVOUT0_CLK4</td>
2068 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
2069 </tr>
2070 <tr class="row-odd"><td>148</td>
2071 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK8</td>
2072 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
2073 </tr>
2074 <tr class="row-even"><td>149</td>
2075 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_13_HSDIVOUT0_CLK4</td>
2076 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
2077 </tr>
2078 <tr class="row-odd"><td>152</td>
2079 <td>DEV_BOARD0_MCU_OBSCLK0_IN</td>
2080 <td>Input muxed clock</td>
2081 </tr>
2082 <tr class="row-even"><td>153</td>
2083 <td>DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0</td>
2084 <td>Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN</td>
2085 </tr>
2086 <tr class="row-odd"><td>154</td>
2087 <td>DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
2088 <td>Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN</td>
2089 </tr>
2090 <tr class="row-even"><td>169</td>
2091 <td>DEV_BOARD0_SYSCLKOUT0_IN</td>
2092 <td>Input clock</td>
2093 </tr>
2094 <tr class="row-odd"><td>170</td>
2095 <td>DEV_BOARD0_MCU_SYSCLKOUT0_IN</td>
2096 <td>Input clock</td>
2097 </tr>
2098 <tr class="row-even"><td>171</td>
2099 <td>DEV_BOARD0_TRC_CLK_IN</td>
2100 <td>Input clock</td>
2101 </tr>
2102 <tr class="row-odd"><td>172</td>
2103 <td>DEV_BOARD0_CLKOUT_IN</td>
2104 <td>Input muxed clock</td>
2105 </tr>
2106 <tr class="row-even"><td>173</td>
2107 <td>DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5</td>
2108 <td>Parent input clock option to DEV_BOARD0_CLKOUT_IN</td>
2109 </tr>
2110 <tr class="row-odd"><td>174</td>
2111 <td>DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10</td>
2112 <td>Parent input clock option to DEV_BOARD0_CLKOUT_IN</td>
2113 </tr>
2114 <tr class="row-even"><td>175</td>
2115 <td>DEV_BOARD0_MCU_CLKOUT0_IN</td>
2116 <td>Input muxed clock</td>
2117 </tr>
2118 <tr class="row-odd"><td>176</td>
2119 <td>DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5</td>
2120 <td>Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN</td>
2121 </tr>
2122 <tr class="row-even"><td>177</td>
2123 <td>DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10</td>
2124 <td>Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN</td>
2125 </tr>
2126 <tr class="row-odd"><td>178</td>
2127 <td>DEV_BOARD0_LED_CLK_OUT</td>
2128 <td>Output clock</td>
2129 </tr>
2130 <tr class="row-even"><td>179</td>
2131 <td>DEV_BOARD0_EXT_REFCLK1_OUT</td>
2132 <td>Output clock</td>
2133 </tr>
2134 <tr class="row-odd"><td>180</td>
2135 <td>DEV_BOARD0_MCU_EXT_REFCLK0_OUT</td>
2136 <td>Output clock</td>
2137 </tr>
2138 <tr class="row-even"><td>181</td>
2139 <td>DEV_BOARD0_HFOSC1_CLK_OUT</td>
2140 <td>Output clock</td>
2141 </tr>
2142 <tr class="row-odd"><td>182</td>
2143 <td>DEV_BOARD0_TCK_OUT</td>
2144 <td>Output clock</td>
2145 </tr>
2146 <tr class="row-even"><td>185</td>
2147 <td>DEV_BOARD0_PCIE_REFCLK0P_OUT</td>
2148 <td>Output clock</td>
2149 </tr>
2150 <tr class="row-odd"><td>186</td>
2151 <td>DEV_BOARD0_PCIE_REFCLK0N_OUT</td>
2152 <td>Output clock</td>
2153 </tr>
2154 <tr class="row-even"><td>191</td>
2155 <td>DEV_BOARD0_PCIE_REFCLK1P_OUT</td>
2156 <td>Output clock</td>
2157 </tr>
2158 <tr class="row-odd"><td>192</td>
2159 <td>DEV_BOARD0_PCIE_REFCLK1N_OUT</td>
2160 <td>Output clock</td>
2161 </tr>
2162 <tr class="row-even"><td>197</td>
2163 <td>DEV_BOARD0_PCIE_REFCLK2P_OUT</td>
2164 <td>Output clock</td>
2165 </tr>
2166 <tr class="row-odd"><td>198</td>
2167 <td>DEV_BOARD0_PCIE_REFCLK2N_OUT</td>
2168 <td>Output clock</td>
2169 </tr>
2170 <tr class="row-even"><td>201</td>
2171 <td>DEV_BOARD0_PCIE_REFCLK3P_OUT</td>
2172 <td>Output clock</td>
2173 </tr>
2174 <tr class="row-odd"><td>202</td>
2175 <td>DEV_BOARD0_PCIE_REFCLK3N_OUT</td>
2176 <td>Output clock</td>
2177 </tr>
2178 <tr class="row-even"><td>217</td>
2179 <td>DEV_BOARD0_MCASP0_ACLKR_IN</td>
2180 <td>Input clock</td>
2181 </tr>
2182 <tr class="row-odd"><td>218</td>
2183 <td>DEV_BOARD0_MCASP0_ACLKR_OUT</td>
2184 <td>Output clock</td>
2185 </tr>
2186 <tr class="row-even"><td>219</td>
2187 <td>DEV_BOARD0_MCASP0_AFSR_OUT</td>
2188 <td>Output clock</td>
2189 </tr>
2190 <tr class="row-odd"><td>220</td>
2191 <td>DEV_BOARD0_MCASP0_ACLKX_IN</td>
2192 <td>Input clock</td>
2193 </tr>
2194 <tr class="row-even"><td>221</td>
2195 <td>DEV_BOARD0_MCASP0_ACLKX_OUT</td>
2196 <td>Output clock</td>
2197 </tr>
2198 <tr class="row-odd"><td>222</td>
2199 <td>DEV_BOARD0_MCASP0_AFSX_OUT</td>
2200 <td>Output clock</td>
2201 </tr>
2202 <tr class="row-even"><td>223</td>
2203 <td>DEV_BOARD0_MCASP1_ACLKR_IN</td>
2204 <td>Input clock</td>
2205 </tr>
2206 <tr class="row-odd"><td>224</td>
2207 <td>DEV_BOARD0_MCASP1_ACLKR_OUT</td>
2208 <td>Output clock</td>
2209 </tr>
2210 <tr class="row-even"><td>225</td>
2211 <td>DEV_BOARD0_MCASP1_AFSR_OUT</td>
2212 <td>Output clock</td>
2213 </tr>
2214 <tr class="row-odd"><td>226</td>
2215 <td>DEV_BOARD0_MCASP1_ACLKX_IN</td>
2216 <td>Input clock</td>
2217 </tr>
2218 <tr class="row-even"><td>227</td>
2219 <td>DEV_BOARD0_MCASP1_ACLKX_OUT</td>
2220 <td>Output clock</td>
2221 </tr>
2222 <tr class="row-odd"><td>228</td>
2223 <td>DEV_BOARD0_MCASP1_AFSX_OUT</td>
2224 <td>Output clock</td>
2225 </tr>
2226 <tr class="row-even"><td>229</td>
2227 <td>DEV_BOARD0_MCASP2_ACLKR_IN</td>
2228 <td>Input clock</td>
2229 </tr>
2230 <tr class="row-odd"><td>230</td>
2231 <td>DEV_BOARD0_MCASP2_ACLKR_OUT</td>
2232 <td>Output clock</td>
2233 </tr>
2234 <tr class="row-even"><td>231</td>
2235 <td>DEV_BOARD0_MCASP2_AFSR_OUT</td>
2236 <td>Output clock</td>
2237 </tr>
2238 <tr class="row-odd"><td>232</td>
2239 <td>DEV_BOARD0_MCASP2_ACLKX_IN</td>
2240 <td>Input clock</td>
2241 </tr>
2242 <tr class="row-even"><td>233</td>
2243 <td>DEV_BOARD0_MCASP2_ACLKX_OUT</td>
2244 <td>Output clock</td>
2245 </tr>
2246 <tr class="row-odd"><td>234</td>
2247 <td>DEV_BOARD0_MCASP2_AFSX_OUT</td>
2248 <td>Output clock</td>
2249 </tr>
2250 <tr class="row-even"><td>235</td>
2251 <td>DEV_BOARD0_MCASP3_ACLKR_IN</td>
2252 <td>Input clock</td>
2253 </tr>
2254 <tr class="row-odd"><td>236</td>
2255 <td>DEV_BOARD0_MCASP3_ACLKR_OUT</td>
2256 <td>Output clock</td>
2257 </tr>
2258 <tr class="row-even"><td>237</td>
2259 <td>DEV_BOARD0_MCASP3_AFSR_OUT</td>
2260 <td>Output clock</td>
2261 </tr>
2262 <tr class="row-odd"><td>238</td>
2263 <td>DEV_BOARD0_MCASP3_ACLKX_IN</td>
2264 <td>Input clock</td>
2265 </tr>
2266 <tr class="row-even"><td>239</td>
2267 <td>DEV_BOARD0_MCASP3_ACLKX_OUT</td>
2268 <td>Output clock</td>
2269 </tr>
2270 <tr class="row-odd"><td>240</td>
2271 <td>DEV_BOARD0_MCASP3_AFSX_OUT</td>
2272 <td>Output clock</td>
2273 </tr>
2274 <tr class="row-even"><td>241</td>
2275 <td>DEV_BOARD0_MCASP4_ACLKR_IN</td>
2276 <td>Input clock</td>
2277 </tr>
2278 <tr class="row-odd"><td>242</td>
2279 <td>DEV_BOARD0_MCASP4_ACLKR_OUT</td>
2280 <td>Output clock</td>
2281 </tr>
2282 <tr class="row-even"><td>243</td>
2283 <td>DEV_BOARD0_MCASP4_AFSR_OUT</td>
2284 <td>Output clock</td>
2285 </tr>
2286 <tr class="row-odd"><td>244</td>
2287 <td>DEV_BOARD0_MCASP4_ACLKX_IN</td>
2288 <td>Input clock</td>
2289 </tr>
2290 <tr class="row-even"><td>245</td>
2291 <td>DEV_BOARD0_MCASP4_ACLKX_OUT</td>
2292 <td>Output clock</td>
2293 </tr>
2294 <tr class="row-odd"><td>246</td>
2295 <td>DEV_BOARD0_MCASP4_AFSX_OUT</td>
2296 <td>Output clock</td>
2297 </tr>
2298 <tr class="row-even"><td>247</td>
2299 <td>DEV_BOARD0_MCASP5_ACLKR_IN</td>
2300 <td>Input clock</td>
2301 </tr>
2302 <tr class="row-odd"><td>248</td>
2303 <td>DEV_BOARD0_MCASP5_ACLKR_OUT</td>
2304 <td>Output clock</td>
2305 </tr>
2306 <tr class="row-even"><td>249</td>
2307 <td>DEV_BOARD0_MCASP5_AFSR_OUT</td>
2308 <td>Output clock</td>
2309 </tr>
2310 <tr class="row-odd"><td>250</td>
2311 <td>DEV_BOARD0_MCASP5_ACLKX_IN</td>
2312 <td>Input clock</td>
2313 </tr>
2314 <tr class="row-even"><td>251</td>
2315 <td>DEV_BOARD0_MCASP5_ACLKX_OUT</td>
2316 <td>Output clock</td>
2317 </tr>
2318 <tr class="row-odd"><td>252</td>
2319 <td>DEV_BOARD0_MCASP5_AFSX_OUT</td>
2320 <td>Output clock</td>
2321 </tr>
2322 <tr class="row-even"><td>253</td>
2323 <td>DEV_BOARD0_MCASP6_ACLKR_IN</td>
2324 <td>Input clock</td>
2325 </tr>
2326 <tr class="row-odd"><td>254</td>
2327 <td>DEV_BOARD0_MCASP6_ACLKR_OUT</td>
2328 <td>Output clock</td>
2329 </tr>
2330 <tr class="row-even"><td>255</td>
2331 <td>DEV_BOARD0_MCASP6_AFSR_OUT</td>
2332 <td>Output clock</td>
2333 </tr>
2334 <tr class="row-odd"><td>256</td>
2335 <td>DEV_BOARD0_MCASP6_ACLKX_IN</td>
2336 <td>Input clock</td>
2337 </tr>
2338 <tr class="row-even"><td>257</td>
2339 <td>DEV_BOARD0_MCASP6_ACLKX_OUT</td>
2340 <td>Output clock</td>
2341 </tr>
2342 <tr class="row-odd"><td>258</td>
2343 <td>DEV_BOARD0_MCASP6_AFSX_OUT</td>
2344 <td>Output clock</td>
2345 </tr>
2346 <tr class="row-even"><td>259</td>
2347 <td>DEV_BOARD0_MCASP7_ACLKR_IN</td>
2348 <td>Input clock</td>
2349 </tr>
2350 <tr class="row-odd"><td>260</td>
2351 <td>DEV_BOARD0_MCASP7_ACLKR_OUT</td>
2352 <td>Output clock</td>
2353 </tr>
2354 <tr class="row-even"><td>261</td>
2355 <td>DEV_BOARD0_MCASP7_AFSR_OUT</td>
2356 <td>Output clock</td>
2357 </tr>
2358 <tr class="row-odd"><td>262</td>
2359 <td>DEV_BOARD0_MCASP7_ACLKX_IN</td>
2360 <td>Input clock</td>
2361 </tr>
2362 <tr class="row-even"><td>263</td>
2363 <td>DEV_BOARD0_MCASP7_ACLKX_OUT</td>
2364 <td>Output clock</td>
2365 </tr>
2366 <tr class="row-odd"><td>264</td>
2367 <td>DEV_BOARD0_MCASP7_AFSX_OUT</td>
2368 <td>Output clock</td>
2369 </tr>
2370 <tr class="row-even"><td>265</td>
2371 <td>DEV_BOARD0_MCASP8_ACLKR_IN</td>
2372 <td>Input clock</td>
2373 </tr>
2374 <tr class="row-odd"><td>267</td>
2375 <td>DEV_BOARD0_MCASP8_ACLKR_OUT</td>
2376 <td>Output clock</td>
2377 </tr>
2378 <tr class="row-even"><td>268</td>
2379 <td>DEV_BOARD0_MCASP8_AFSR_OUT</td>
2380 <td>Output clock</td>
2381 </tr>
2382 <tr class="row-odd"><td>269</td>
2383 <td>DEV_BOARD0_MCASP8_ACLKX_IN</td>
2384 <td>Input clock</td>
2385 </tr>
2386 <tr class="row-even"><td>270</td>
2387 <td>DEV_BOARD0_MCASP8_ACLKX_OUT</td>
2388 <td>Output clock</td>
2389 </tr>
2390 <tr class="row-odd"><td>271</td>
2391 <td>DEV_BOARD0_MCASP8_AFSX_OUT</td>
2392 <td>Output clock</td>
2393 </tr>
2394 <tr class="row-even"><td>272</td>
2395 <td>DEV_BOARD0_MCASP9_ACLKR_IN</td>
2396 <td>Input clock</td>
2397 </tr>
2398 <tr class="row-odd"><td>273</td>
2399 <td>DEV_BOARD0_MCASP9_ACLKR_OUT</td>
2400 <td>Output clock</td>
2401 </tr>
2402 <tr class="row-even"><td>274</td>
2403 <td>DEV_BOARD0_MCASP9_AFSR_OUT</td>
2404 <td>Output clock</td>
2405 </tr>
2406 <tr class="row-odd"><td>275</td>
2407 <td>DEV_BOARD0_MCASP9_ACLKX_IN</td>
2408 <td>Input clock</td>
2409 </tr>
2410 <tr class="row-even"><td>276</td>
2411 <td>DEV_BOARD0_MCASP9_ACLKX_OUT</td>
2412 <td>Output clock</td>
2413 </tr>
2414 <tr class="row-odd"><td>278</td>
2415 <td>DEV_BOARD0_MCASP9_AFSX_OUT</td>
2416 <td>Output clock</td>
2417 </tr>
2418 <tr class="row-even"><td>279</td>
2419 <td>DEV_BOARD0_MCASP10_ACLKR_IN</td>
2420 <td>Input clock</td>
2421 </tr>
2422 <tr class="row-odd"><td>280</td>
2423 <td>DEV_BOARD0_MCASP10_ACLKR_OUT</td>
2424 <td>Output clock</td>
2425 </tr>
2426 <tr class="row-even"><td>281</td>
2427 <td>DEV_BOARD0_MCASP10_AFSR_OUT</td>
2428 <td>Output clock</td>
2429 </tr>
2430 <tr class="row-odd"><td>282</td>
2431 <td>DEV_BOARD0_MCASP10_ACLKX_IN</td>
2432 <td>Input clock</td>
2433 </tr>
2434 <tr class="row-even"><td>283</td>
2435 <td>DEV_BOARD0_MCASP10_ACLKX_OUT</td>
2436 <td>Output clock</td>
2437 </tr>
2438 <tr class="row-odd"><td>284</td>
2439 <td>DEV_BOARD0_MCASP10_AFSX_OUT</td>
2440 <td>Output clock</td>
2441 </tr>
2442 <tr class="row-even"><td>285</td>
2443 <td>DEV_BOARD0_MCASP11_ACLKR_IN</td>
2444 <td>Input clock</td>
2445 </tr>
2446 <tr class="row-odd"><td>286</td>
2447 <td>DEV_BOARD0_MCASP11_ACLKR_OUT</td>
2448 <td>Output clock</td>
2449 </tr>
2450 <tr class="row-even"><td>287</td>
2451 <td>DEV_BOARD0_MCASP11_AFSR_OUT</td>
2452 <td>Output clock</td>
2453 </tr>
2454 <tr class="row-odd"><td>288</td>
2455 <td>DEV_BOARD0_MCASP11_ACLKX_IN</td>
2456 <td>Input clock</td>
2457 </tr>
2458 <tr class="row-even"><td>289</td>
2459 <td>DEV_BOARD0_MCASP11_ACLKX_OUT</td>
2460 <td>Output clock</td>
2461 </tr>
2462 <tr class="row-odd"><td>290</td>
2463 <td>DEV_BOARD0_MCASP11_AFSX_OUT</td>
2464 <td>Output clock</td>
2465 </tr>
2466 <tr class="row-even"><td>300</td>
2467 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT</td>
2468 <td>Output clock</td>
2469 </tr>
2470 <tr class="row-odd"><td>301</td>
2471 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2472 <td>Input muxed clock</td>
2473 </tr>
2474 <tr class="row-even"><td>302</td>
2475 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT</td>
2476 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2477 </tr>
2478 <tr class="row-odd"><td>303</td>
2479 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT</td>
2480 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2481 </tr>
2482 <tr class="row-even"><td>304</td>
2483 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT</td>
2484 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2485 </tr>
2486 <tr class="row-odd"><td>305</td>
2487 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT</td>
2488 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2489 </tr>
2490 <tr class="row-even"><td>306</td>
2491 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT</td>
2492 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2493 </tr>
2494 <tr class="row-odd"><td>307</td>
2495 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT</td>
2496 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2497 </tr>
2498 <tr class="row-even"><td>308</td>
2499 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT</td>
2500 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2501 </tr>
2502 <tr class="row-odd"><td>309</td>
2503 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT</td>
2504 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2505 </tr>
2506 <tr class="row-even"><td>310</td>
2507 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT</td>
2508 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2509 </tr>
2510 <tr class="row-odd"><td>311</td>
2511 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT</td>
2512 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2513 </tr>
2514 <tr class="row-even"><td>312</td>
2515 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT</td>
2516 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2517 </tr>
2518 <tr class="row-odd"><td>313</td>
2519 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT</td>
2520 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2521 </tr>
2522 <tr class="row-even"><td>314</td>
2523 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT</td>
2524 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2525 </tr>
2526 <tr class="row-odd"><td>315</td>
2527 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT</td>
2528 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2529 </tr>
2530 <tr class="row-even"><td>316</td>
2531 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT</td>
2532 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2533 </tr>
2534 <tr class="row-odd"><td>317</td>
2535 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT</td>
2536 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2537 </tr>
2538 <tr class="row-even"><td>318</td>
2539 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT</td>
2540 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2541 </tr>
2542 <tr class="row-odd"><td>319</td>
2543 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT</td>
2544 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2545 </tr>
2546 <tr class="row-even"><td>320</td>
2547 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT</td>
2548 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2549 </tr>
2550 <tr class="row-odd"><td>321</td>
2551 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT</td>
2552 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2553 </tr>
2554 <tr class="row-even"><td>322</td>
2555 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT</td>
2556 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2557 </tr>
2558 <tr class="row-odd"><td>323</td>
2559 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT</td>
2560 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2561 </tr>
2562 <tr class="row-even"><td>324</td>
2563 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT</td>
2564 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2565 </tr>
2566 <tr class="row-odd"><td>325</td>
2567 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT</td>
2568 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2569 </tr>
2570 <tr class="row-even"><td>326</td>
2571 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
2572 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2573 </tr>
2574 <tr class="row-odd"><td>327</td>
2575 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
2576 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2577 </tr>
2578 <tr class="row-even"><td>328</td>
2579 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
2580 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2581 </tr>
2582 <tr class="row-odd"><td>329</td>
2583 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
2584 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2585 </tr>
2586 <tr class="row-even"><td>330</td>
2587 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
2588 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2589 </tr>
2590 <tr class="row-odd"><td>331</td>
2591 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
2592 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2593 </tr>
2594 <tr class="row-even"><td>334</td>
2595 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
2596 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
2597 </tr>
2598 <tr class="row-odd"><td>335</td>
2599 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT</td>
2600 <td>Output clock</td>
2601 </tr>
2602 <tr class="row-even"><td>336</td>
2603 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2604 <td>Input muxed clock</td>
2605 </tr>
2606 <tr class="row-odd"><td>337</td>
2607 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT</td>
2608 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2609 </tr>
2610 <tr class="row-even"><td>338</td>
2611 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT</td>
2612 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2613 </tr>
2614 <tr class="row-odd"><td>339</td>
2615 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT</td>
2616 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2617 </tr>
2618 <tr class="row-even"><td>340</td>
2619 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT</td>
2620 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2621 </tr>
2622 <tr class="row-odd"><td>341</td>
2623 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT</td>
2624 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2625 </tr>
2626 <tr class="row-even"><td>342</td>
2627 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT</td>
2628 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2629 </tr>
2630 <tr class="row-odd"><td>343</td>
2631 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT</td>
2632 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2633 </tr>
2634 <tr class="row-even"><td>344</td>
2635 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT</td>
2636 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2637 </tr>
2638 <tr class="row-odd"><td>345</td>
2639 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT</td>
2640 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2641 </tr>
2642 <tr class="row-even"><td>346</td>
2643 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT</td>
2644 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2645 </tr>
2646 <tr class="row-odd"><td>347</td>
2647 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT</td>
2648 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2649 </tr>
2650 <tr class="row-even"><td>348</td>
2651 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT</td>
2652 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2653 </tr>
2654 <tr class="row-odd"><td>349</td>
2655 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT</td>
2656 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2657 </tr>
2658 <tr class="row-even"><td>350</td>
2659 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT</td>
2660 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2661 </tr>
2662 <tr class="row-odd"><td>351</td>
2663 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT</td>
2664 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2665 </tr>
2666 <tr class="row-even"><td>352</td>
2667 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT</td>
2668 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2669 </tr>
2670 <tr class="row-odd"><td>353</td>
2671 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT</td>
2672 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2673 </tr>
2674 <tr class="row-even"><td>354</td>
2675 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT</td>
2676 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2677 </tr>
2678 <tr class="row-odd"><td>355</td>
2679 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT</td>
2680 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2681 </tr>
2682 <tr class="row-even"><td>356</td>
2683 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT</td>
2684 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2685 </tr>
2686 <tr class="row-odd"><td>357</td>
2687 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT</td>
2688 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2689 </tr>
2690 <tr class="row-even"><td>358</td>
2691 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT</td>
2692 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2693 </tr>
2694 <tr class="row-odd"><td>359</td>
2695 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT</td>
2696 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2697 </tr>
2698 <tr class="row-even"><td>360</td>
2699 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT</td>
2700 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2701 </tr>
2702 <tr class="row-odd"><td>361</td>
2703 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
2704 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2705 </tr>
2706 <tr class="row-even"><td>362</td>
2707 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
2708 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2709 </tr>
2710 <tr class="row-odd"><td>363</td>
2711 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
2712 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2713 </tr>
2714 <tr class="row-even"><td>364</td>
2715 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
2716 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2717 </tr>
2718 <tr class="row-odd"><td>365</td>
2719 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
2720 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2721 </tr>
2722 <tr class="row-even"><td>366</td>
2723 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
2724 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2725 </tr>
2726 <tr class="row-odd"><td>369</td>
2727 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
2728 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
2729 </tr>
2730 <tr class="row-even"><td>370</td>
2731 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT</td>
2732 <td>Output clock</td>
2733 </tr>
2734 <tr class="row-odd"><td>371</td>
2735 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2736 <td>Input muxed clock</td>
2737 </tr>
2738 <tr class="row-even"><td>372</td>
2739 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT</td>
2740 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2741 </tr>
2742 <tr class="row-odd"><td>373</td>
2743 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT</td>
2744 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2745 </tr>
2746 <tr class="row-even"><td>374</td>
2747 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT</td>
2748 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2749 </tr>
2750 <tr class="row-odd"><td>375</td>
2751 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT</td>
2752 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2753 </tr>
2754 <tr class="row-even"><td>376</td>
2755 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT</td>
2756 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2757 </tr>
2758 <tr class="row-odd"><td>377</td>
2759 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT</td>
2760 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2761 </tr>
2762 <tr class="row-even"><td>378</td>
2763 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT</td>
2764 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2765 </tr>
2766 <tr class="row-odd"><td>379</td>
2767 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT</td>
2768 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2769 </tr>
2770 <tr class="row-even"><td>380</td>
2771 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT</td>
2772 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2773 </tr>
2774 <tr class="row-odd"><td>381</td>
2775 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT</td>
2776 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2777 </tr>
2778 <tr class="row-even"><td>382</td>
2779 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT</td>
2780 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2781 </tr>
2782 <tr class="row-odd"><td>383</td>
2783 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT</td>
2784 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2785 </tr>
2786 <tr class="row-even"><td>384</td>
2787 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT</td>
2788 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2789 </tr>
2790 <tr class="row-odd"><td>385</td>
2791 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT</td>
2792 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2793 </tr>
2794 <tr class="row-even"><td>386</td>
2795 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT</td>
2796 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2797 </tr>
2798 <tr class="row-odd"><td>387</td>
2799 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT</td>
2800 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2801 </tr>
2802 <tr class="row-even"><td>388</td>
2803 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT</td>
2804 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2805 </tr>
2806 <tr class="row-odd"><td>389</td>
2807 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT</td>
2808 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2809 </tr>
2810 <tr class="row-even"><td>390</td>
2811 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT</td>
2812 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2813 </tr>
2814 <tr class="row-odd"><td>391</td>
2815 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT</td>
2816 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2817 </tr>
2818 <tr class="row-even"><td>392</td>
2819 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT</td>
2820 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2821 </tr>
2822 <tr class="row-odd"><td>393</td>
2823 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT</td>
2824 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2825 </tr>
2826 <tr class="row-even"><td>394</td>
2827 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT</td>
2828 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2829 </tr>
2830 <tr class="row-odd"><td>395</td>
2831 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT</td>
2832 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2833 </tr>
2834 <tr class="row-even"><td>396</td>
2835 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
2836 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2837 </tr>
2838 <tr class="row-odd"><td>397</td>
2839 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
2840 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2841 </tr>
2842 <tr class="row-even"><td>398</td>
2843 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
2844 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2845 </tr>
2846 <tr class="row-odd"><td>399</td>
2847 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
2848 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2849 </tr>
2850 <tr class="row-even"><td>400</td>
2851 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
2852 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2853 </tr>
2854 <tr class="row-odd"><td>401</td>
2855 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
2856 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2857 </tr>
2858 <tr class="row-even"><td>404</td>
2859 <td>DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT</td>
2860 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN</td>
2861 </tr>
2862 <tr class="row-odd"><td>405</td>
2863 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_OUT</td>
2864 <td>Output clock</td>
2865 </tr>
2866 <tr class="row-even"><td>406</td>
2867 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2868 <td>Input muxed clock</td>
2869 </tr>
2870 <tr class="row-odd"><td>407</td>
2871 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT</td>
2872 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2873 </tr>
2874 <tr class="row-even"><td>408</td>
2875 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT</td>
2876 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2877 </tr>
2878 <tr class="row-odd"><td>409</td>
2879 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT</td>
2880 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2881 </tr>
2882 <tr class="row-even"><td>410</td>
2883 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT</td>
2884 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2885 </tr>
2886 <tr class="row-odd"><td>411</td>
2887 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT</td>
2888 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2889 </tr>
2890 <tr class="row-even"><td>412</td>
2891 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT</td>
2892 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2893 </tr>
2894 <tr class="row-odd"><td>413</td>
2895 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT</td>
2896 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2897 </tr>
2898 <tr class="row-even"><td>414</td>
2899 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT</td>
2900 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2901 </tr>
2902 <tr class="row-odd"><td>415</td>
2903 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT</td>
2904 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2905 </tr>
2906 <tr class="row-even"><td>416</td>
2907 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT</td>
2908 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2909 </tr>
2910 <tr class="row-odd"><td>417</td>
2911 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT</td>
2912 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2913 </tr>
2914 <tr class="row-even"><td>418</td>
2915 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT</td>
2916 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2917 </tr>
2918 <tr class="row-odd"><td>419</td>
2919 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT</td>
2920 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2921 </tr>
2922 <tr class="row-even"><td>420</td>
2923 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT</td>
2924 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2925 </tr>
2926 <tr class="row-odd"><td>421</td>
2927 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT</td>
2928 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2929 </tr>
2930 <tr class="row-even"><td>422</td>
2931 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT</td>
2932 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2933 </tr>
2934 <tr class="row-odd"><td>423</td>
2935 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT</td>
2936 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2937 </tr>
2938 <tr class="row-even"><td>424</td>
2939 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT</td>
2940 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2941 </tr>
2942 <tr class="row-odd"><td>425</td>
2943 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT</td>
2944 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2945 </tr>
2946 <tr class="row-even"><td>426</td>
2947 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT</td>
2948 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2949 </tr>
2950 <tr class="row-odd"><td>427</td>
2951 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT</td>
2952 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2953 </tr>
2954 <tr class="row-even"><td>428</td>
2955 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT</td>
2956 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2957 </tr>
2958 <tr class="row-odd"><td>429</td>
2959 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT</td>
2960 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2961 </tr>
2962 <tr class="row-even"><td>430</td>
2963 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT</td>
2964 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2965 </tr>
2966 <tr class="row-odd"><td>431</td>
2967 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
2968 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2969 </tr>
2970 <tr class="row-even"><td>432</td>
2971 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
2972 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2973 </tr>
2974 <tr class="row-odd"><td>433</td>
2975 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
2976 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2977 </tr>
2978 <tr class="row-even"><td>434</td>
2979 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
2980 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2981 </tr>
2982 <tr class="row-odd"><td>435</td>
2983 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
2984 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2985 </tr>
2986 <tr class="row-even"><td>436</td>
2987 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
2988 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2989 </tr>
2990 <tr class="row-odd"><td>439</td>
2991 <td>DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK3_OUT</td>
2992 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN</td>
2993 </tr>
2994 </tbody>
2995 </table>
2996 </div>
2997 <div class="section" id="clocks-for-c66ss0-device">
2998 <span id="soc-doc-j721e-public-clks-c66ss0"></span><h3>Clocks for C66SS0 Device<a class="headerlink" href="#clocks-for-c66ss0-device" title="Permalink to this headline">¶</a></h3>
2999 <p><strong>This device has no defined clocks.</strong></p>
3000 </div>
3001 <div class="section" id="clocks-for-c66ss0-core0-device">
3002 <span id="soc-doc-j721e-public-clks-c66ss0-core0"></span><h3>Clocks for C66SS0_CORE0 Device<a class="headerlink" href="#clocks-for-c66ss0-core0-device" title="Permalink to this headline">¶</a></h3>
3003 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_C66SS0_CORE0</span></a> (ID = 142)</p>
3004 <p>Following is a mapping of Clocks IDs to function:</p>
3005 <table border="1" class="docutils">
3006 <colgroup>
3007 <col width="19%" />
3008 <col width="58%" />
3009 <col width="23%" />
3010 </colgroup>
3011 <thead valign="bottom">
3012 <tr class="row-odd"><th class="head">Clock ID</th>
3013 <th class="head">Name</th>
3014 <th class="head">Function</th>
3015 </tr>
3016 </thead>
3017 <tbody valign="top">
3018 <tr class="row-even"><td>0</td>
3019 <td>DEV_C66SS0_CORE0_GEM_TRC_CLK</td>
3020 <td>Input clock</td>
3021 </tr>
3022 <tr class="row-odd"><td>1</td>
3023 <td>DEV_C66SS0_CORE0_GEM_CLK2_OUT_CLK</td>
3024 <td>Output clock</td>
3025 </tr>
3026 <tr class="row-even"><td>4</td>
3027 <td>DEV_C66SS0_CORE0_GEM_PBIST_ROM_CLK</td>
3028 <td>Output clock</td>
3029 </tr>
3030 <tr class="row-odd"><td>6</td>
3031 <td>DEV_C66SS0_CORE0_GEM_CLKIN_CLK</td>
3032 <td>Input clock</td>
3033 </tr>
3034 </tbody>
3035 </table>
3036 </div>
3037 <div class="section" id="clocks-for-c66ss0-introuter0-device">
3038 <span id="soc-doc-j721e-public-clks-c66ss0-introuter0"></span><h3>Clocks for C66SS0_INTROUTER0 Device<a class="headerlink" href="#clocks-for-c66ss0-introuter0-device" title="Permalink to this headline">¶</a></h3>
3039 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_C66SS0_INTROUTER0</span></a> (ID = 121)</p>
3040 <p>Following is a mapping of Clocks IDs to function:</p>
3041 <table border="1" class="docutils">
3042 <colgroup>
3043 <col width="21%" />
3044 <col width="56%" />
3045 <col width="23%" />
3046 </colgroup>
3047 <thead valign="bottom">
3048 <tr class="row-odd"><th class="head">Clock ID</th>
3049 <th class="head">Name</th>
3050 <th class="head">Function</th>
3051 </tr>
3052 </thead>
3053 <tbody valign="top">
3054 <tr class="row-even"><td>0</td>
3055 <td>DEV_C66SS0_INTROUTER0_INTR_CLK</td>
3056 <td>Input clock</td>
3057 </tr>
3058 </tbody>
3059 </table>
3060 </div>
3061 <div class="section" id="clocks-for-c66ss0-pbist0-device">
3062 <span id="soc-doc-j721e-public-clks-c66ss0-pbist0"></span><h3>Clocks for C66SS0_PBIST0 Device<a class="headerlink" href="#clocks-for-c66ss0-pbist0-device" title="Permalink to this headline">¶</a></h3>
3063 <p><strong>This device has no defined clocks.</strong></p>
3064 </div>
3065 <div class="section" id="clocks-for-c66ss1-device">
3066 <span id="soc-doc-j721e-public-clks-c66ss1"></span><h3>Clocks for C66SS1 Device<a class="headerlink" href="#clocks-for-c66ss1-device" title="Permalink to this headline">¶</a></h3>
3067 <p><strong>This device has no defined clocks.</strong></p>
3068 </div>
3069 <div class="section" id="clocks-for-c66ss1-core0-device">
3070 <span id="soc-doc-j721e-public-clks-c66ss1-core0"></span><h3>Clocks for C66SS1_CORE0 Device<a class="headerlink" href="#clocks-for-c66ss1-core0-device" title="Permalink to this headline">¶</a></h3>
3071 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_C66SS1_CORE0</span></a> (ID = 143)</p>
3072 <p>Following is a mapping of Clocks IDs to function:</p>
3073 <table border="1" class="docutils">
3074 <colgroup>
3075 <col width="19%" />
3076 <col width="58%" />
3077 <col width="23%" />
3078 </colgroup>
3079 <thead valign="bottom">
3080 <tr class="row-odd"><th class="head">Clock ID</th>
3081 <th class="head">Name</th>
3082 <th class="head">Function</th>
3083 </tr>
3084 </thead>
3085 <tbody valign="top">
3086 <tr class="row-even"><td>0</td>
3087 <td>DEV_C66SS1_CORE0_GEM_TRC_CLK</td>
3088 <td>Input clock</td>
3089 </tr>
3090 <tr class="row-odd"><td>1</td>
3091 <td>DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK</td>
3092 <td>Output clock</td>
3093 </tr>
3094 <tr class="row-even"><td>4</td>
3095 <td>DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK</td>
3096 <td>Output clock</td>
3097 </tr>
3098 <tr class="row-odd"><td>6</td>
3099 <td>DEV_C66SS1_CORE0_GEM_CLKIN_CLK</td>
3100 <td>Input clock</td>
3101 </tr>
3102 </tbody>
3103 </table>
3104 </div>
3105 <div class="section" id="clocks-for-c66ss1-introuter0-device">
3106 <span id="soc-doc-j721e-public-clks-c66ss1-introuter0"></span><h3>Clocks for C66SS1_INTROUTER0 Device<a class="headerlink" href="#clocks-for-c66ss1-introuter0-device" title="Permalink to this headline">¶</a></h3>
3107 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_C66SS1_INTROUTER0</span></a> (ID = 122)</p>
3108 <p>Following is a mapping of Clocks IDs to function:</p>
3109 <table border="1" class="docutils">
3110 <colgroup>
3111 <col width="21%" />
3112 <col width="56%" />
3113 <col width="23%" />
3114 </colgroup>
3115 <thead valign="bottom">
3116 <tr class="row-odd"><th class="head">Clock ID</th>
3117 <th class="head">Name</th>
3118 <th class="head">Function</th>
3119 </tr>
3120 </thead>
3121 <tbody valign="top">
3122 <tr class="row-even"><td>0</td>
3123 <td>DEV_C66SS1_INTROUTER0_INTR_CLK</td>
3124 <td>Input clock</td>
3125 </tr>
3126 </tbody>
3127 </table>
3128 </div>
3129 <div class="section" id="clocks-for-c66ss1-pbist0-device">
3130 <span id="soc-doc-j721e-public-clks-c66ss1-pbist0"></span><h3>Clocks for C66SS1_PBIST0 Device<a class="headerlink" href="#clocks-for-c66ss1-pbist0-device" title="Permalink to this headline">¶</a></h3>
3131 <p><strong>This device has no defined clocks.</strong></p>
3132 </div>
3133 <div class="section" id="clocks-for-c71ss0-device">
3134 <span id="soc-doc-j721e-public-clks-c71ss0"></span><h3>Clocks for C71SS0 Device<a class="headerlink" href="#clocks-for-c71ss0-device" title="Permalink to this headline">¶</a></h3>
3135 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_C71SS0</span></a> (ID = 15)</p>
3136 <p>Following is a mapping of Clocks IDs to function:</p>
3137 <table border="1" class="docutils">
3138 <colgroup>
3139 <col width="24%" />
3140 <col width="50%" />
3141 <col width="26%" />
3142 </colgroup>
3143 <thead valign="bottom">
3144 <tr class="row-odd"><th class="head">Clock ID</th>
3145 <th class="head">Name</th>
3146 <th class="head">Function</th>
3147 </tr>
3148 </thead>
3149 <tbody valign="top">
3150 <tr class="row-even"><td>0</td>
3151 <td>DEV_C71SS0_C7X_CLK</td>
3152 <td>Input clock</td>
3153 </tr>
3154 <tr class="row-odd"><td>1</td>
3155 <td>DEV_C71SS0_PLL_CTRL_CLK</td>
3156 <td>Input clock</td>
3157 </tr>
3158 </tbody>
3159 </table>
3160 </div>
3161 <div class="section" id="clocks-for-c71ss0-mma-device">
3162 <span id="soc-doc-j721e-public-clks-c71ss0-mma"></span><h3>Clocks for C71SS0_MMA Device<a class="headerlink" href="#clocks-for-c71ss0-mma-device" title="Permalink to this headline">¶</a></h3>
3163 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_C71SS0_MMA</span></a> (ID = 16)</p>
3164 <p>Following is a mapping of Clocks IDs to function:</p>
3165 <table border="1" class="docutils">
3166 <colgroup>
3167 <col width="22%" />
3168 <col width="54%" />
3169 <col width="24%" />
3170 </colgroup>
3171 <thead valign="bottom">
3172 <tr class="row-odd"><th class="head">Clock ID</th>
3173 <th class="head">Name</th>
3174 <th class="head">Function</th>
3175 </tr>
3176 </thead>
3177 <tbody valign="top">
3178 <tr class="row-even"><td>0</td>
3179 <td>DEV_C71SS0_MMA_PLL_CTRL_CLK</td>
3180 <td>Input clock</td>
3181 </tr>
3182 <tr class="row-odd"><td>1</td>
3183 <td>DEV_C71SS0_MMA_MMA_CLK</td>
3184 <td>Input clock</td>
3185 </tr>
3186 </tbody>
3187 </table>
3188 </div>
3189 <div class="section" id="clocks-for-c71x-0-pbist-vd-device">
3190 <span id="soc-doc-j721e-public-clks-c71x-0-pbist-vd"></span><h3>Clocks for C71X_0_PBIST_VD Device<a class="headerlink" href="#clocks-for-c71x-0-pbist-vd-device" title="Permalink to this headline">¶</a></h3>
3191 <p><strong>This device has no defined clocks.</strong></p>
3192 </div>
3193 <div class="section" id="clocks-for-cmpevent-intrtr0-device">
3194 <span id="soc-doc-j721e-public-clks-cmpevent-intrtr0"></span><h3>Clocks for CMPEVENT_INTRTR0 Device<a class="headerlink" href="#clocks-for-cmpevent-intrtr0-device" title="Permalink to this headline">¶</a></h3>
3195 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_CMPEVENT_INTRTR0</span></a> (ID = 123)</p>
3196 <p>Following is a mapping of Clocks IDs to function:</p>
3197 <table border="1" class="docutils">
3198 <colgroup>
3199 <col width="21%" />
3200 <col width="55%" />
3201 <col width="23%" />
3202 </colgroup>
3203 <thead valign="bottom">
3204 <tr class="row-odd"><th class="head">Clock ID</th>
3205 <th class="head">Name</th>
3206 <th class="head">Function</th>
3207 </tr>
3208 </thead>
3209 <tbody valign="top">
3210 <tr class="row-even"><td>0</td>
3211 <td>DEV_CMPEVENT_INTRTR0_INTR_CLK</td>
3212 <td>Input clock</td>
3213 </tr>
3214 </tbody>
3215 </table>
3216 </div>
3217 <div class="section" id="clocks-for-compute-cluster0-device">
3218 <span id="soc-doc-j721e-public-clks-compute-cluster0"></span><h3>Clocks for COMPUTE_CLUSTER0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-device" title="Permalink to this headline">¶</a></h3>
3219 <p><strong>This device has no defined clocks.</strong></p>
3220 </div>
3221 <div class="section" id="clocks-for-compute-cluster0-cfg-wrap-device">
3222 <span id="soc-doc-j721e-public-clks-compute-cluster0-cfg-wrap"></span><h3>Clocks for COMPUTE_CLUSTER0_CFG_WRAP Device<a class="headerlink" href="#clocks-for-compute-cluster0-cfg-wrap-device" title="Permalink to this headline">¶</a></h3>
3223 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_COMPUTE_CLUSTER0_CFG_WRAP</span></a> (ID = 5)</p>
3224 <p>Following is a mapping of Clocks IDs to function:</p>
3225 <table border="1" class="docutils">
3226 <colgroup>
3227 <col width="18%" />
3228 <col width="62%" />
3229 <col width="20%" />
3230 </colgroup>
3231 <thead valign="bottom">
3232 <tr class="row-odd"><th class="head">Clock ID</th>
3233 <th class="head">Name</th>
3234 <th class="head">Function</th>
3235 </tr>
3236 </thead>
3237 <tbody valign="top">
3238 <tr class="row-even"><td>0</td>
3239 <td>DEV_COMPUTE_CLUSTER0_CFG_WRAP_CLK4_CLK</td>
3240 <td>Input clock</td>
3241 </tr>
3242 </tbody>
3243 </table>
3244 </div>
3245 <div class="section" id="clocks-for-compute-cluster0-clec-device">
3246 <span id="soc-doc-j721e-public-clks-compute-cluster0-clec"></span><h3>Clocks for COMPUTE_CLUSTER0_CLEC Device<a class="headerlink" href="#clocks-for-compute-cluster0-clec-device" title="Permalink to this headline">¶</a></h3>
3247 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_COMPUTE_CLUSTER0_CLEC</span></a> (ID = 6)</p>
3248 <p>Following is a mapping of Clocks IDs to function:</p>
3249 <table border="1" class="docutils">
3250 <colgroup>
3251 <col width="20%" />
3252 <col width="59%" />
3253 <col width="21%" />
3254 </colgroup>
3255 <thead valign="bottom">
3256 <tr class="row-odd"><th class="head">Clock ID</th>
3257 <th class="head">Name</th>
3258 <th class="head">Function</th>
3259 </tr>
3260 </thead>
3261 <tbody valign="top">
3262 <tr class="row-even"><td>0</td>
3263 <td>DEV_COMPUTE_CLUSTER0_CLEC_CLK4_CLK</td>
3264 <td>Input clock</td>
3265 </tr>
3266 <tr class="row-odd"><td>1</td>
3267 <td>DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK</td>
3268 <td>Input clock</td>
3269 </tr>
3270 </tbody>
3271 </table>
3272 </div>
3273 <div class="section" id="clocks-for-compute-cluster0-core-core-device">
3274 <span id="soc-doc-j721e-public-clks-compute-cluster0-core-core"></span><h3>Clocks for COMPUTE_CLUSTER0_CORE_CORE Device<a class="headerlink" href="#clocks-for-compute-cluster0-core-core-device" title="Permalink to this headline">¶</a></h3>
3275 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_COMPUTE_CLUSTER0_CORE_CORE</span></a> (ID = 7)</p>
3276 <p>Following is a mapping of Clocks IDs to function:</p>
3277 <table border="1" class="docutils">
3278 <colgroup>
3279 <col width="17%" />
3280 <col width="65%" />
3281 <col width="18%" />
3282 </colgroup>
3283 <thead valign="bottom">
3284 <tr class="row-odd"><th class="head">Clock ID</th>
3285 <th class="head">Name</th>
3286 <th class="head">Function</th>
3287 </tr>
3288 </thead>
3289 <tbody valign="top">
3290 <tr class="row-even"><td>0</td>
3291 <td>DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK</td>
3292 <td>Input clock</td>
3293 </tr>
3294 <tr class="row-odd"><td>1</td>
3295 <td>DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK</td>
3296 <td>Input clock</td>
3297 </tr>
3298 </tbody>
3299 </table>
3300 </div>
3301 <div class="section" id="clocks-for-compute-cluster0-ddr32ss-emif0-ew-device">
3302 <span id="soc-doc-j721e-public-clks-compute-cluster0-ddr32ss-emif0-ew"></span><h3>Clocks for COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW Device<a class="headerlink" href="#clocks-for-compute-cluster0-ddr32ss-emif0-ew-device" title="Permalink to this headline">¶</a></h3>
3303 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW</span></a> (ID = 8)</p>
3304 <p>Following is a mapping of Clocks IDs to function:</p>
3305 <table border="1" class="docutils">
3306 <colgroup>
3307 <col width="15%" />
3308 <col width="70%" />
3309 <col width="16%" />
3310 </colgroup>
3311 <thead valign="bottom">
3312 <tr class="row-odd"><th class="head">Clock ID</th>
3313 <th class="head">Name</th>
3314 <th class="head">Function</th>
3315 </tr>
3316 </thead>
3317 <tbody valign="top">
3318 <tr class="row-even"><td>0</td>
3319 <td>DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_PLL_CTRL_CLK</td>
3320 <td>Input clock</td>
3321 </tr>
3322 <tr class="row-odd"><td>1</td>
3323 <td>DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_DDRSS_DDR_PLL_CLK</td>
3324 <td>Input clock</td>
3325 </tr>
3326 </tbody>
3327 </table>
3328 </div>
3329 <div class="section" id="clocks-for-compute-cluster0-debug-wrap-device">
3330 <span id="soc-doc-j721e-public-clks-compute-cluster0-debug-wrap"></span><h3>Clocks for COMPUTE_CLUSTER0_DEBUG_WRAP Device<a class="headerlink" href="#clocks-for-compute-cluster0-debug-wrap-device" title="Permalink to this headline">¶</a></h3>
3331 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP</span></a> (ID = 9)</p>
3332 <p>Following is a mapping of Clocks IDs to function:</p>
3333 <table border="1" class="docutils">
3334 <colgroup>
3335 <col width="17%" />
3336 <col width="65%" />
3337 <col width="18%" />
3338 </colgroup>
3339 <thead valign="bottom">
3340 <tr class="row-odd"><th class="head">Clock ID</th>
3341 <th class="head">Name</th>
3342 <th class="head">Function</th>
3343 </tr>
3344 </thead>
3345 <tbody valign="top">
3346 <tr class="row-even"><td>0</td>
3347 <td>DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK1_CLK_CLK</td>
3348 <td>Input clock</td>
3349 </tr>
3350 <tr class="row-odd"><td>1</td>
3351 <td>DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK2_CLK_CLK</td>
3352 <td>Input clock</td>
3353 </tr>
3354 </tbody>
3355 </table>
3356 </div>
3357 <div class="section" id="clocks-for-compute-cluster0-dmsc-wrap-device">
3358 <span id="soc-doc-j721e-public-clks-compute-cluster0-dmsc-wrap"></span><h3>Clocks for COMPUTE_CLUSTER0_DMSC_WRAP Device<a class="headerlink" href="#clocks-for-compute-cluster0-dmsc-wrap-device" title="Permalink to this headline">¶</a></h3>
3359 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_COMPUTE_CLUSTER0_DMSC_WRAP</span></a> (ID = 12)</p>
3360 <p>Following is a mapping of Clocks IDs to function:</p>
3361 <table border="1" class="docutils">
3362 <colgroup>
3363 <col width="17%" />
3364 <col width="64%" />
3365 <col width="19%" />
3366 </colgroup>
3367 <thead valign="bottom">
3368 <tr class="row-odd"><th class="head">Clock ID</th>
3369 <th class="head">Name</th>
3370 <th class="head">Function</th>
3371 </tr>
3372 </thead>
3373 <tbody valign="top">
3374 <tr class="row-even"><td>0</td>
3375 <td>DEV_COMPUTE_CLUSTER0_DMSC_WRAP_CLK4_CLK_CLK</td>
3376 <td>Input clock</td>
3377 </tr>
3378 </tbody>
3379 </table>
3380 </div>
3381 <div class="section" id="clocks-for-compute-cluster0-en-msmc-domain-device">
3382 <span id="soc-doc-j721e-public-clks-compute-cluster0-en-msmc-domain"></span><h3>Clocks for COMPUTE_CLUSTER0_EN_MSMC_DOMAIN Device<a class="headerlink" href="#clocks-for-compute-cluster0-en-msmc-domain-device" title="Permalink to this headline">¶</a></h3>
3383 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN</span></a> (ID = 13)</p>
3384 <p>Following is a mapping of Clocks IDs to function:</p>
3385 <table border="1" class="docutils">
3386 <colgroup>
3387 <col width="16%" />
3388 <col width="67%" />
3389 <col width="17%" />
3390 </colgroup>
3391 <thead valign="bottom">
3392 <tr class="row-odd"><th class="head">Clock ID</th>
3393 <th class="head">Name</th>
3394 <th class="head">Function</th>
3395 </tr>
3396 </thead>
3397 <tbody valign="top">
3398 <tr class="row-even"><td>0</td>
3399 <td>DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_MSMC_CLK1_CLK</td>
3400 <td>Input clock</td>
3401 </tr>
3402 </tbody>
3403 </table>
3404 </div>
3405 <div class="section" id="clocks-for-compute-cluster0-gic500ss-device">
3406 <span id="soc-doc-j721e-public-clks-compute-cluster0-gic500ss"></span><h3>Clocks for COMPUTE_CLUSTER0_GIC500SS Device<a class="headerlink" href="#clocks-for-compute-cluster0-gic500ss-device" title="Permalink to this headline">¶</a></h3>
3407 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_COMPUTE_CLUSTER0_GIC500SS</span></a> (ID = 14)</p>
3408 <p>Following is a mapping of Clocks IDs to function:</p>
3409 <table border="1" class="docutils">
3410 <colgroup>
3411 <col width="18%" />
3412 <col width="62%" />
3413 <col width="20%" />
3414 </colgroup>
3415 <thead valign="bottom">
3416 <tr class="row-odd"><th class="head">Clock ID</th>
3417 <th class="head">Name</th>
3418 <th class="head">Function</th>
3419 </tr>
3420 </thead>
3421 <tbody valign="top">
3422 <tr class="row-even"><td>0</td>
3423 <td>DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK</td>
3424 <td>Input clock</td>
3425 </tr>
3426 </tbody>
3427 </table>
3428 </div>
3429 <div class="section" id="clocks-for-compute-cluster0-pbist-wrap-device">
3430 <span id="soc-doc-j721e-public-clks-compute-cluster0-pbist-wrap"></span><h3>Clocks for COMPUTE_CLUSTER0_PBIST_WRAP Device<a class="headerlink" href="#clocks-for-compute-cluster0-pbist-wrap-device" title="Permalink to this headline">¶</a></h3>
3431 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_COMPUTE_CLUSTER0_PBIST_WRAP</span></a> (ID = 17)</p>
3432 <p>Following is a mapping of Clocks IDs to function:</p>
3433 <table border="1" class="docutils">
3434 <colgroup>
3435 <col width="16%" />
3436 <col width="67%" />
3437 <col width="17%" />
3438 </colgroup>
3439 <thead valign="bottom">
3440 <tr class="row-odd"><th class="head">Clock ID</th>
3441 <th class="head">Name</th>
3442 <th class="head">Function</th>
3443 </tr>
3444 </thead>
3445 <tbody valign="top">
3446 <tr class="row-even"><td>0</td>
3447 <td>DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVP_CLK1_CLK_CLK</td>
3448 <td>Input clock</td>
3449 </tr>
3450 <tr class="row-odd"><td>1</td>
3451 <td>DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK</td>
3452 <td>Input clock</td>
3453 </tr>
3454 <tr class="row-even"><td>2</td>
3455 <td>DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK2_CLK_CLK</td>
3456 <td>Input clock</td>
3457 </tr>
3458 </tbody>
3459 </table>
3460 </div>
3461 <div class="section" id="clocks-for-cpsw0-device">
3462 <span id="soc-doc-j721e-public-clks-cpsw0"></span><h3>Clocks for CPSW0 Device<a class="headerlink" href="#clocks-for-cpsw0-device" title="Permalink to this headline">¶</a></h3>
3463 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_CPSW0</span></a> (ID = 19)</p>
3464 <p>Following is a mapping of Clocks IDs to function:</p>
3465 <table border="1" class="docutils">
3466 <colgroup>
3467 <col width="9%" />
3468 <col width="53%" />
3469 <col width="38%" />
3470 </colgroup>
3471 <thead valign="bottom">
3472 <tr class="row-odd"><th class="head">Clock ID</th>
3473 <th class="head">Name</th>
3474 <th class="head">Function</th>
3475 </tr>
3476 </thead>
3477 <tbody valign="top">
3478 <tr class="row-even"><td>0</td>
3479 <td>DEV_CPSW0_GMII3_MT_CLK</td>
3480 <td>Input clock</td>
3481 </tr>
3482 <tr class="row-odd"><td>1</td>
3483 <td>DEV_CPSW0_SERDES6_TXFCLK</td>
3484 <td>Input clock</td>
3485 </tr>
3486 <tr class="row-even"><td>2</td>
3487 <td>DEV_CPSW0_SERDES8_TXMCLK</td>
3488 <td>Input clock</td>
3489 </tr>
3490 <tr class="row-odd"><td>3</td>
3491 <td>DEV_CPSW0_GMII2_MR_CLK</td>
3492 <td>Input clock</td>
3493 </tr>
3494 <tr class="row-even"><td>4</td>
3495 <td>DEV_CPSW0_SERDES2_TXFCLK</td>
3496 <td>Input clock</td>
3497 </tr>
3498 <tr class="row-odd"><td>5</td>
3499 <td>DEV_CPSW0_SERDES4_RXCLK</td>
3500 <td>Input clock</td>
3501 </tr>
3502 <tr class="row-even"><td>6</td>
3503 <td>DEV_CPSW0_SERDES7_TXMCLK</td>
3504 <td>Input clock</td>
3505 </tr>
3506 <tr class="row-odd"><td>7</td>
3507 <td>DEV_CPSW0_SERDES7_RXCLK</td>
3508 <td>Input clock</td>
3509 </tr>
3510 <tr class="row-even"><td>8</td>
3511 <td>DEV_CPSW0_SERDES6_REFCLK</td>
3512 <td>Input clock</td>
3513 </tr>
3514 <tr class="row-odd"><td>9</td>
3515 <td>DEV_CPSW0_SERDES5_TXFCLK</td>
3516 <td>Input clock</td>
3517 </tr>
3518 <tr class="row-even"><td>10</td>
3519 <td>DEV_CPSW0_SERDES5_RXCLK</td>
3520 <td>Input clock</td>
3521 </tr>
3522 <tr class="row-odd"><td>11</td>
3523 <td>DEV_CPSW0_GMII4_MT_CLK</td>
3524 <td>Input clock</td>
3525 </tr>
3526 <tr class="row-even"><td>12</td>
3527 <td>DEV_CPSW0_SERDES3_TXFCLK</td>
3528 <td>Input clock</td>
3529 </tr>
3530 <tr class="row-odd"><td>13</td>
3531 <td>DEV_CPSW0_SERDES2_REFCLK</td>
3532 <td>Input clock</td>
3533 </tr>
3534 <tr class="row-even"><td>14</td>
3535 <td>DEV_CPSW0_SERDES4_RXFCLK</td>
3536 <td>Input clock</td>
3537 </tr>
3538 <tr class="row-odd"><td>15</td>
3539 <td>DEV_CPSW0_SERDES6_RXFCLK</td>
3540 <td>Input clock</td>
3541 </tr>
3542 <tr class="row-even"><td>16</td>
3543 <td>DEV_CPSW0_CPTS_RFT_CLK</td>
3544 <td>Input muxed clock</td>
3545 </tr>
3546 <tr class="row-odd"><td>17</td>
3547 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
3548 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3549 </tr>
3550 <tr class="row-even"><td>18</td>
3551 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
3552 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3553 </tr>
3554 <tr class="row-odd"><td>19</td>
3555 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
3556 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3557 </tr>
3558 <tr class="row-even"><td>20</td>
3559 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
3560 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3561 </tr>
3562 <tr class="row-odd"><td>21</td>
3563 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
3564 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3565 </tr>
3566 <tr class="row-even"><td>22</td>
3567 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
3568 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3569 </tr>
3570 <tr class="row-odd"><td>23</td>
3571 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK</td>
3572 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3573 </tr>
3574 <tr class="row-even"><td>24</td>
3575 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK</td>
3576 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3577 </tr>
3578 <tr class="row-odd"><td>25</td>
3579 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK</td>
3580 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3581 </tr>
3582 <tr class="row-even"><td>26</td>
3583 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK</td>
3584 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3585 </tr>
3586 <tr class="row-odd"><td>27</td>
3587 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK</td>
3588 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3589 </tr>
3590 <tr class="row-even"><td>28</td>
3591 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK</td>
3592 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3593 </tr>
3594 <tr class="row-odd"><td>29</td>
3595 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK</td>
3596 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3597 </tr>
3598 <tr class="row-even"><td>30</td>
3599 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK</td>
3600 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3601 </tr>
3602 <tr class="row-odd"><td>31</td>
3603 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
3604 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3605 </tr>
3606 <tr class="row-even"><td>32</td>
3607 <td>DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
3608 <td>Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK</td>
3609 </tr>
3610 <tr class="row-odd"><td>33</td>
3611 <td>DEV_CPSW0_SERDES5_RXFCLK</td>
3612 <td>Input clock</td>
3613 </tr>
3614 <tr class="row-even"><td>34</td>
3615 <td>DEV_CPSW0_SERDES5_TXMCLK</td>
3616 <td>Input clock</td>
3617 </tr>
3618 <tr class="row-odd"><td>35</td>
3619 <td>DEV_CPSW0_GMII5_MT_CLK</td>
3620 <td>Input clock</td>
3621 </tr>
3622 <tr class="row-even"><td>36</td>
3623 <td>DEV_CPSW0_SERDES2_RXCLK</td>
3624 <td>Input clock</td>
3625 </tr>
3626 <tr class="row-odd"><td>37</td>
3627 <td>DEV_CPSW0_SERDES8_RXFCLK</td>
3628 <td>Input clock</td>
3629 </tr>
3630 <tr class="row-even"><td>38</td>
3631 <td>DEV_CPSW0_SERDES1_RXFCLK</td>
3632 <td>Input clock</td>
3633 </tr>
3634 <tr class="row-odd"><td>39</td>
3635 <td>DEV_CPSW0_SERDES8_RXCLK</td>
3636 <td>Input clock</td>
3637 </tr>
3638 <tr class="row-even"><td>40</td>
3639 <td>DEV_CPSW0_GMII_RFT_CLK</td>
3640 <td>Input clock</td>
3641 </tr>
3642 <tr class="row-odd"><td>41</td>
3643 <td>DEV_CPSW0_SERDES3_REFCLK</td>
3644 <td>Input clock</td>
3645 </tr>
3646 <tr class="row-even"><td>42</td>
3647 <td>DEV_CPSW0_RGMII_MHZ_250_CLK</td>
3648 <td>Input clock</td>
3649 </tr>
3650 <tr class="row-odd"><td>43</td>
3651 <td>DEV_CPSW0_SERDES7_REFCLK</td>
3652 <td>Input clock</td>
3653 </tr>
3654 <tr class="row-even"><td>44</td>
3655 <td>DEV_CPSW0_GMII6_MT_CLK</td>
3656 <td>Input clock</td>
3657 </tr>
3658 <tr class="row-odd"><td>45</td>
3659 <td>DEV_CPSW0_SERDES6_TXMCLK</td>
3660 <td>Input clock</td>
3661 </tr>
3662 <tr class="row-even"><td>46</td>
3663 <td>DEV_CPSW0_RMII_MHZ_50_CLK</td>
3664 <td>Input clock</td>
3665 </tr>
3666 <tr class="row-odd"><td>47</td>
3667 <td>DEV_CPSW0_GMII4_MR_CLK</td>
3668 <td>Input clock</td>
3669 </tr>
3670 <tr class="row-even"><td>48</td>
3671 <td>DEV_CPSW0_SERDES2_TXMCLK</td>
3672 <td>Input clock</td>
3673 </tr>
3674 <tr class="row-odd"><td>49</td>
3675 <td>DEV_CPSW0_RGMII_MHZ_50_CLK</td>
3676 <td>Input clock</td>
3677 </tr>
3678 <tr class="row-even"><td>50</td>
3679 <td>DEV_CPSW0_SERDES4_TXMCLK</td>
3680 <td>Input clock</td>
3681 </tr>
3682 <tr class="row-odd"><td>51</td>
3683 <td>DEV_CPSW0_SERDES3_RXFCLK</td>
3684 <td>Input clock</td>
3685 </tr>
3686 <tr class="row-even"><td>52</td>
3687 <td>DEV_CPSW0_GMII8_MT_CLK</td>
3688 <td>Input clock</td>
3689 </tr>
3690 <tr class="row-odd"><td>53</td>
3691 <td>DEV_CPSW0_SERDES7_TXFCLK</td>
3692 <td>Input clock</td>
3693 </tr>
3694 <tr class="row-even"><td>54</td>
3695 <td>DEV_CPSW0_GMII7_MT_CLK</td>
3696 <td>Input clock</td>
3697 </tr>
3698 <tr class="row-odd"><td>55</td>
3699 <td>DEV_CPSW0_GMII7_MR_CLK</td>
3700 <td>Input clock</td>
3701 </tr>
3702 <tr class="row-even"><td>56</td>
3703 <td>DEV_CPSW0_SERDES6_RXCLK</td>
3704 <td>Input clock</td>
3705 </tr>
3706 <tr class="row-odd"><td>57</td>
3707 <td>DEV_CPSW0_SERDES3_RXCLK</td>
3708 <td>Input clock</td>
3709 </tr>
3710 <tr class="row-even"><td>58</td>
3711 <td>DEV_CPSW0_SERDES4_REFCLK</td>
3712 <td>Input clock</td>
3713 </tr>
3714 <tr class="row-odd"><td>59</td>
3715 <td>DEV_CPSW0_SERDES1_RXCLK</td>
3716 <td>Input clock</td>
3717 </tr>
3718 <tr class="row-even"><td>60</td>
3719 <td>DEV_CPSW0_SERDES1_TXFCLK</td>
3720 <td>Input clock</td>
3721 </tr>
3722 <tr class="row-odd"><td>61</td>
3723 <td>DEV_CPSW0_GMII6_MR_CLK</td>
3724 <td>Input clock</td>
3725 </tr>
3726 <tr class="row-even"><td>62</td>
3727 <td>DEV_CPSW0_SERDES1_REFCLK</td>
3728 <td>Input clock</td>
3729 </tr>
3730 <tr class="row-odd"><td>63</td>
3731 <td>DEV_CPSW0_RGMII_MHZ_5_CLK</td>
3732 <td>Input clock</td>
3733 </tr>
3734 <tr class="row-even"><td>64</td>
3735 <td>DEV_CPSW0_SERDES5_REFCLK</td>
3736 <td>Input clock</td>
3737 </tr>
3738 <tr class="row-odd"><td>65</td>
3739 <td>DEV_CPSW0_GMII2_MT_CLK</td>
3740 <td>Input clock</td>
3741 </tr>
3742 <tr class="row-even"><td>66</td>
3743 <td>DEV_CPSW0_SERDES8_TXFCLK</td>
3744 <td>Input clock</td>
3745 </tr>
3746 <tr class="row-odd"><td>67</td>
3747 <td>DEV_CPSW0_GMII8_MR_CLK</td>
3748 <td>Input clock</td>
3749 </tr>
3750 <tr class="row-even"><td>68</td>
3751 <td>DEV_CPSW0_GMII1_MR_CLK</td>
3752 <td>Input clock</td>
3753 </tr>
3754 <tr class="row-odd"><td>69</td>
3755 <td>DEV_CPSW0_SERDES8_REFCLK</td>
3756 <td>Input clock</td>
3757 </tr>
3758 <tr class="row-even"><td>70</td>
3759 <td>DEV_CPSW0_SERDES3_TXMCLK</td>
3760 <td>Input clock</td>
3761 </tr>
3762 <tr class="row-odd"><td>71</td>
3763 <td>DEV_CPSW0_GMII3_MR_CLK</td>
3764 <td>Input clock</td>
3765 </tr>
3766 <tr class="row-even"><td>72</td>
3767 <td>DEV_CPSW0_SERDES1_TXMCLK</td>
3768 <td>Input clock</td>
3769 </tr>
3770 <tr class="row-odd"><td>73</td>
3771 <td>DEV_CPSW0_SERDES7_RXFCLK</td>
3772 <td>Input clock</td>
3773 </tr>
3774 <tr class="row-even"><td>74</td>
3775 <td>DEV_CPSW0_GMII5_MR_CLK</td>
3776 <td>Input clock</td>
3777 </tr>
3778 <tr class="row-odd"><td>75</td>
3779 <td>DEV_CPSW0_GMII1_MT_CLK</td>
3780 <td>Input clock</td>
3781 </tr>
3782 <tr class="row-even"><td>76</td>
3783 <td>DEV_CPSW0_SERDES2_RXFCLK</td>
3784 <td>Input clock</td>
3785 </tr>
3786 <tr class="row-odd"><td>77</td>
3787 <td>DEV_CPSW0_SERDES4_TXFCLK</td>
3788 <td>Input clock</td>
3789 </tr>
3790 <tr class="row-even"><td>78</td>
3791 <td>DEV_CPSW0_SERDES3_TXCLK</td>
3792 <td>Output clock</td>
3793 </tr>
3794 <tr class="row-odd"><td>79</td>
3795 <td>DEV_CPSW0_CPTS_GENF0</td>
3796 <td>Output clock</td>
3797 </tr>
3798 <tr class="row-even"><td>80</td>
3799 <td>DEV_CPSW0_SERDES5_TXCLK</td>
3800 <td>Output clock</td>
3801 </tr>
3802 <tr class="row-odd"><td>81</td>
3803 <td>DEV_CPSW0_SERDES6_TXCLK</td>
3804 <td>Output clock</td>
3805 </tr>
3806 <tr class="row-even"><td>82</td>
3807 <td>DEV_CPSW0_SERDES8_TXCLK</td>
3808 <td>Output clock</td>
3809 </tr>
3810 <tr class="row-odd"><td>83</td>
3811 <td>DEV_CPSW0_SERDES1_TXCLK</td>
3812 <td>Output clock</td>
3813 </tr>
3814 <tr class="row-even"><td>84</td>
3815 <td>DEV_CPSW0_SERDES4_TXCLK</td>
3816 <td>Output clock</td>
3817 </tr>
3818 <tr class="row-odd"><td>85</td>
3819 <td>DEV_CPSW0_SERDES2_TXCLK</td>
3820 <td>Output clock</td>
3821 </tr>
3822 <tr class="row-even"><td>86</td>
3823 <td>DEV_CPSW0_SERDES7_TXCLK</td>
3824 <td>Output clock</td>
3825 </tr>
3826 <tr class="row-odd"><td>87</td>
3827 <td>DEV_CPSW0_MDIO_MDCLK_O</td>
3828 <td>Output clock</td>
3829 </tr>
3830 <tr class="row-even"><td>89</td>
3831 <td>DEV_CPSW0_CPPI_CLK_CLK</td>
3832 <td>Input clock</td>
3833 </tr>
3834 </tbody>
3835 </table>
3836 </div>
3837 <div class="section" id="clocks-for-cpt2-aggr0-device">
3838 <span id="soc-doc-j721e-public-clks-cpt2-aggr0"></span><h3>Clocks for CPT2_AGGR0 Device<a class="headerlink" href="#clocks-for-cpt2-aggr0-device" title="Permalink to this headline">¶</a></h3>
3839 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_CPT2_AGGR0</span></a> (ID = 20)</p>
3840 <p>Following is a mapping of Clocks IDs to function:</p>
3841 <table border="1" class="docutils">
3842 <colgroup>
3843 <col width="24%" />
3844 <col width="50%" />
3845 <col width="26%" />
3846 </colgroup>
3847 <thead valign="bottom">
3848 <tr class="row-odd"><th class="head">Clock ID</th>
3849 <th class="head">Name</th>
3850 <th class="head">Function</th>
3851 </tr>
3852 </thead>
3853 <tbody valign="top">
3854 <tr class="row-even"><td>0</td>
3855 <td>DEV_CPT2_AGGR0_VCLK_CLK</td>
3856 <td>Input clock</td>
3857 </tr>
3858 </tbody>
3859 </table>
3860 </div>
3861 <div class="section" id="clocks-for-cpt2-aggr1-device">
3862 <span id="soc-doc-j721e-public-clks-cpt2-aggr1"></span><h3>Clocks for CPT2_AGGR1 Device<a class="headerlink" href="#clocks-for-cpt2-aggr1-device" title="Permalink to this headline">¶</a></h3>
3863 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_CPT2_AGGR1</span></a> (ID = 21)</p>
3864 <p>Following is a mapping of Clocks IDs to function:</p>
3865 <table border="1" class="docutils">
3866 <colgroup>
3867 <col width="24%" />
3868 <col width="50%" />
3869 <col width="26%" />
3870 </colgroup>
3871 <thead valign="bottom">
3872 <tr class="row-odd"><th class="head">Clock ID</th>
3873 <th class="head">Name</th>
3874 <th class="head">Function</th>
3875 </tr>
3876 </thead>
3877 <tbody valign="top">
3878 <tr class="row-even"><td>0</td>
3879 <td>DEV_CPT2_AGGR1_VCLK_CLK</td>
3880 <td>Input clock</td>
3881 </tr>
3882 </tbody>
3883 </table>
3884 </div>
3885 <div class="section" id="clocks-for-cpt2-aggr2-device">
3886 <span id="soc-doc-j721e-public-clks-cpt2-aggr2"></span><h3>Clocks for CPT2_AGGR2 Device<a class="headerlink" href="#clocks-for-cpt2-aggr2-device" title="Permalink to this headline">¶</a></h3>
3887 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_CPT2_AGGR2</span></a> (ID = 23)</p>
3888 <p>Following is a mapping of Clocks IDs to function:</p>
3889 <table border="1" class="docutils">
3890 <colgroup>
3891 <col width="24%" />
3892 <col width="50%" />
3893 <col width="26%" />
3894 </colgroup>
3895 <thead valign="bottom">
3896 <tr class="row-odd"><th class="head">Clock ID</th>
3897 <th class="head">Name</th>
3898 <th class="head">Function</th>
3899 </tr>
3900 </thead>
3901 <tbody valign="top">
3902 <tr class="row-even"><td>0</td>
3903 <td>DEV_CPT2_AGGR2_VCLK_CLK</td>
3904 <td>Input clock</td>
3905 </tr>
3906 </tbody>
3907 </table>
3908 </div>
3909 <div class="section" id="clocks-for-csi-psilss0-device">
3910 <span id="soc-doc-j721e-public-clks-csi-psilss0"></span><h3>Clocks for CSI_PSILSS0 Device<a class="headerlink" href="#clocks-for-csi-psilss0-device" title="Permalink to this headline">¶</a></h3>
3911 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_CSI_PSILSS0</span></a> (ID = 25)</p>
3912 <p>Following is a mapping of Clocks IDs to function:</p>
3913 <table border="1" class="docutils">
3914 <colgroup>
3915 <col width="24%" />
3916 <col width="51%" />
3917 <col width="25%" />
3918 </colgroup>
3919 <thead valign="bottom">
3920 <tr class="row-odd"><th class="head">Clock ID</th>
3921 <th class="head">Name</th>
3922 <th class="head">Function</th>
3923 </tr>
3924 </thead>
3925 <tbody valign="top">
3926 <tr class="row-even"><td>0</td>
3927 <td>DEV_CSI_PSILSS0_MAIN_CLK</td>
3928 <td>Input clock</td>
3929 </tr>
3930 </tbody>
3931 </table>
3932 </div>
3933 <div class="section" id="clocks-for-csi-rx-if0-device">
3934 <span id="soc-doc-j721e-public-clks-csi-rx-if0"></span><h3>Clocks for CSI_RX_IF0 Device<a class="headerlink" href="#clocks-for-csi-rx-if0-device" title="Permalink to this headline">¶</a></h3>
3935 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_CSI_RX_IF0</span></a> (ID = 26)</p>
3936 <p>Following is a mapping of Clocks IDs to function:</p>
3937 <table border="1" class="docutils">
3938 <colgroup>
3939 <col width="21%" />
3940 <col width="56%" />
3941 <col width="23%" />
3942 </colgroup>
3943 <thead valign="bottom">
3944 <tr class="row-odd"><th class="head">Clock ID</th>
3945 <th class="head">Name</th>
3946 <th class="head">Function</th>
3947 </tr>
3948 </thead>
3949 <tbody valign="top">
3950 <tr class="row-even"><td>0</td>
3951 <td>DEV_CSI_RX_IF0_VBUS_CLK_CLK</td>
3952 <td>Input clock</td>
3953 </tr>
3954 <tr class="row-odd"><td>1</td>
3955 <td>DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK</td>
3956 <td>Input clock</td>
3957 </tr>
3958 <tr class="row-even"><td>2</td>
3959 <td>DEV_CSI_RX_IF0_MAIN_CLK_CLK</td>
3960 <td>Input clock</td>
3961 </tr>
3962 <tr class="row-odd"><td>3</td>
3963 <td>DEV_CSI_RX_IF0_VP_CLK_CLK</td>
3964 <td>Input clock</td>
3965 </tr>
3966 </tbody>
3967 </table>
3968 </div>
3969 <div class="section" id="clocks-for-csi-rx-if1-device">
3970 <span id="soc-doc-j721e-public-clks-csi-rx-if1"></span><h3>Clocks for CSI_RX_IF1 Device<a class="headerlink" href="#clocks-for-csi-rx-if1-device" title="Permalink to this headline">¶</a></h3>
3971 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_CSI_RX_IF1</span></a> (ID = 27)</p>
3972 <p>Following is a mapping of Clocks IDs to function:</p>
3973 <table border="1" class="docutils">
3974 <colgroup>
3975 <col width="21%" />
3976 <col width="56%" />
3977 <col width="23%" />
3978 </colgroup>
3979 <thead valign="bottom">
3980 <tr class="row-odd"><th class="head">Clock ID</th>
3981 <th class="head">Name</th>
3982 <th class="head">Function</th>
3983 </tr>
3984 </thead>
3985 <tbody valign="top">
3986 <tr class="row-even"><td>0</td>
3987 <td>DEV_CSI_RX_IF1_VBUS_CLK_CLK</td>
3988 <td>Input clock</td>
3989 </tr>
3990 <tr class="row-odd"><td>1</td>
3991 <td>DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK</td>
3992 <td>Input clock</td>
3993 </tr>
3994 <tr class="row-even"><td>2</td>
3995 <td>DEV_CSI_RX_IF1_MAIN_CLK_CLK</td>
3996 <td>Input clock</td>
3997 </tr>
3998 <tr class="row-odd"><td>3</td>
3999 <td>DEV_CSI_RX_IF1_VP_CLK_CLK</td>
4000 <td>Input clock</td>
4001 </tr>
4002 </tbody>
4003 </table>
4004 </div>
4005 <div class="section" id="clocks-for-csi-tx-if0-device">
4006 <span id="soc-doc-j721e-public-clks-csi-tx-if0"></span><h3>Clocks for CSI_TX_IF0 Device<a class="headerlink" href="#clocks-for-csi-tx-if0-device" title="Permalink to this headline">¶</a></h3>
4007 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_CSI_TX_IF0</span></a> (ID = 28)</p>
4008 <p>Following is a mapping of Clocks IDs to function:</p>
4009 <table border="1" class="docutils">
4010 <colgroup>
4011 <col width="18%" />
4012 <col width="62%" />
4013 <col width="20%" />
4014 </colgroup>
4015 <thead valign="bottom">
4016 <tr class="row-odd"><th class="head">Clock ID</th>
4017 <th class="head">Name</th>
4018 <th class="head">Function</th>
4019 </tr>
4020 </thead>
4021 <tbody valign="top">
4022 <tr class="row-even"><td>0</td>
4023 <td>DEV_CSI_TX_IF0_ESC_CLK_CLK</td>
4024 <td>Input clock</td>
4025 </tr>
4026 <tr class="row-odd"><td>1</td>
4027 <td>DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK</td>
4028 <td>Input clock</td>
4029 </tr>
4030 <tr class="row-even"><td>2</td>
4031 <td>DEV_CSI_TX_IF0_VBUS_CLK_CLK</td>
4032 <td>Input clock</td>
4033 </tr>
4034 <tr class="row-odd"><td>3</td>
4035 <td>DEV_CSI_TX_IF0_MAIN_CLK_CLK</td>
4036 <td>Input clock</td>
4037 </tr>
4038 </tbody>
4039 </table>
4040 </div>
4041 <div class="section" id="clocks-for-dcc0-device">
4042 <span id="soc-doc-j721e-public-clks-dcc0"></span><h3>Clocks for DCC0 Device<a class="headerlink" href="#clocks-for-dcc0-device" title="Permalink to this headline">¶</a></h3>
4043 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC0</span></a> (ID = 30)</p>
4044 <p>Following is a mapping of Clocks IDs to function:</p>
4045 <table border="1" class="docutils">
4046 <colgroup>
4047 <col width="24%" />
4048 <col width="51%" />
4049 <col width="25%" />
4050 </colgroup>
4051 <thead valign="bottom">
4052 <tr class="row-odd"><th class="head">Clock ID</th>
4053 <th class="head">Name</th>
4054 <th class="head">Function</th>
4055 </tr>
4056 </thead>
4057 <tbody valign="top">
4058 <tr class="row-even"><td>0</td>
4059 <td>DEV_DCC0_DCC_INPUT10_CLK</td>
4060 <td>Input clock</td>
4061 </tr>
4062 <tr class="row-odd"><td>1</td>
4063 <td>DEV_DCC0_DCC_INPUT01_CLK</td>
4064 <td>Input clock</td>
4065 </tr>
4066 <tr class="row-even"><td>2</td>
4067 <td>DEV_DCC0_DCC_CLKSRC2_CLK</td>
4068 <td>Input clock</td>
4069 </tr>
4070 <tr class="row-odd"><td>3</td>
4071 <td>DEV_DCC0_DCC_CLKSRC7_CLK</td>
4072 <td>Input clock</td>
4073 </tr>
4074 <tr class="row-even"><td>4</td>
4075 <td>DEV_DCC0_DCC_CLKSRC0_CLK</td>
4076 <td>Input clock</td>
4077 </tr>
4078 <tr class="row-odd"><td>5</td>
4079 <td>DEV_DCC0_VBUS_CLK</td>
4080 <td>Input clock</td>
4081 </tr>
4082 <tr class="row-even"><td>6</td>
4083 <td>DEV_DCC0_DCC_CLKSRC4_CLK</td>
4084 <td>Input clock</td>
4085 </tr>
4086 <tr class="row-odd"><td>7</td>
4087 <td>DEV_DCC0_DCC_CLKSRC1_CLK</td>
4088 <td>Input clock</td>
4089 </tr>
4090 <tr class="row-even"><td>8</td>
4091 <td>DEV_DCC0_DCC_CLKSRC3_CLK</td>
4092 <td>Input clock</td>
4093 </tr>
4094 <tr class="row-odd"><td>9</td>
4095 <td>DEV_DCC0_DCC_INPUT00_CLK</td>
4096 <td>Input clock</td>
4097 </tr>
4098 <tr class="row-even"><td>10</td>
4099 <td>DEV_DCC0_DCC_CLKSRC5_CLK</td>
4100 <td>Input clock</td>
4101 </tr>
4102 <tr class="row-odd"><td>11</td>
4103 <td>DEV_DCC0_DCC_CLKSRC6_CLK</td>
4104 <td>Input clock</td>
4105 </tr>
4106 <tr class="row-even"><td>12</td>
4107 <td>DEV_DCC0_DCC_INPUT02_CLK</td>
4108 <td>Input clock</td>
4109 </tr>
4110 </tbody>
4111 </table>
4112 </div>
4113 <div class="section" id="clocks-for-dcc1-device">
4114 <span id="soc-doc-j721e-public-clks-dcc1"></span><h3>Clocks for DCC1 Device<a class="headerlink" href="#clocks-for-dcc1-device" title="Permalink to this headline">¶</a></h3>
4115 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC1</span></a> (ID = 31)</p>
4116 <p>Following is a mapping of Clocks IDs to function:</p>
4117 <table border="1" class="docutils">
4118 <colgroup>
4119 <col width="24%" />
4120 <col width="51%" />
4121 <col width="25%" />
4122 </colgroup>
4123 <thead valign="bottom">
4124 <tr class="row-odd"><th class="head">Clock ID</th>
4125 <th class="head">Name</th>
4126 <th class="head">Function</th>
4127 </tr>
4128 </thead>
4129 <tbody valign="top">
4130 <tr class="row-even"><td>0</td>
4131 <td>DEV_DCC1_DCC_INPUT10_CLK</td>
4132 <td>Input clock</td>
4133 </tr>
4134 <tr class="row-odd"><td>1</td>
4135 <td>DEV_DCC1_DCC_INPUT01_CLK</td>
4136 <td>Input clock</td>
4137 </tr>
4138 <tr class="row-even"><td>2</td>
4139 <td>DEV_DCC1_DCC_CLKSRC2_CLK</td>
4140 <td>Input clock</td>
4141 </tr>
4142 <tr class="row-odd"><td>3</td>
4143 <td>DEV_DCC1_DCC_CLKSRC7_CLK</td>
4144 <td>Input clock</td>
4145 </tr>
4146 <tr class="row-even"><td>4</td>
4147 <td>DEV_DCC1_DCC_CLKSRC0_CLK</td>
4148 <td>Input clock</td>
4149 </tr>
4150 <tr class="row-odd"><td>5</td>
4151 <td>DEV_DCC1_VBUS_CLK</td>
4152 <td>Input clock</td>
4153 </tr>
4154 <tr class="row-even"><td>6</td>
4155 <td>DEV_DCC1_DCC_CLKSRC4_CLK</td>
4156 <td>Input clock</td>
4157 </tr>
4158 <tr class="row-odd"><td>7</td>
4159 <td>DEV_DCC1_DCC_CLKSRC1_CLK</td>
4160 <td>Input clock</td>
4161 </tr>
4162 <tr class="row-even"><td>8</td>
4163 <td>DEV_DCC1_DCC_CLKSRC3_CLK</td>
4164 <td>Input clock</td>
4165 </tr>
4166 <tr class="row-odd"><td>9</td>
4167 <td>DEV_DCC1_DCC_INPUT00_CLK</td>
4168 <td>Input clock</td>
4169 </tr>
4170 <tr class="row-even"><td>10</td>
4171 <td>DEV_DCC1_DCC_CLKSRC5_CLK</td>
4172 <td>Input clock</td>
4173 </tr>
4174 <tr class="row-odd"><td>11</td>
4175 <td>DEV_DCC1_DCC_CLKSRC6_CLK</td>
4176 <td>Input clock</td>
4177 </tr>
4178 <tr class="row-even"><td>12</td>
4179 <td>DEV_DCC1_DCC_INPUT02_CLK</td>
4180 <td>Input clock</td>
4181 </tr>
4182 </tbody>
4183 </table>
4184 </div>
4185 <div class="section" id="clocks-for-dcc10-device">
4186 <span id="soc-doc-j721e-public-clks-dcc10"></span><h3>Clocks for DCC10 Device<a class="headerlink" href="#clocks-for-dcc10-device" title="Permalink to this headline">¶</a></h3>
4187 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC10</span></a> (ID = 41)</p>
4188 <p>Following is a mapping of Clocks IDs to function:</p>
4189 <table border="1" class="docutils">
4190 <colgroup>
4191 <col width="23%" />
4192 <col width="52%" />
4193 <col width="25%" />
4194 </colgroup>
4195 <thead valign="bottom">
4196 <tr class="row-odd"><th class="head">Clock ID</th>
4197 <th class="head">Name</th>
4198 <th class="head">Function</th>
4199 </tr>
4200 </thead>
4201 <tbody valign="top">
4202 <tr class="row-even"><td>0</td>
4203 <td>DEV_DCC10_DCC_INPUT10_CLK</td>
4204 <td>Input clock</td>
4205 </tr>
4206 <tr class="row-odd"><td>1</td>
4207 <td>DEV_DCC10_DCC_INPUT01_CLK</td>
4208 <td>Input clock</td>
4209 </tr>
4210 <tr class="row-even"><td>2</td>
4211 <td>DEV_DCC10_DCC_CLKSRC2_CLK</td>
4212 <td>Input clock</td>
4213 </tr>
4214 <tr class="row-odd"><td>3</td>
4215 <td>DEV_DCC10_DCC_CLKSRC7_CLK</td>
4216 <td>Input clock</td>
4217 </tr>
4218 <tr class="row-even"><td>4</td>
4219 <td>DEV_DCC10_DCC_CLKSRC0_CLK</td>
4220 <td>Input clock</td>
4221 </tr>
4222 <tr class="row-odd"><td>5</td>
4223 <td>DEV_DCC10_VBUS_CLK</td>
4224 <td>Input clock</td>
4225 </tr>
4226 <tr class="row-even"><td>6</td>
4227 <td>DEV_DCC10_DCC_CLKSRC4_CLK</td>
4228 <td>Input clock</td>
4229 </tr>
4230 <tr class="row-odd"><td>7</td>
4231 <td>DEV_DCC10_DCC_CLKSRC1_CLK</td>
4232 <td>Input clock</td>
4233 </tr>
4234 <tr class="row-even"><td>8</td>
4235 <td>DEV_DCC10_DCC_CLKSRC3_CLK</td>
4236 <td>Input clock</td>
4237 </tr>
4238 <tr class="row-odd"><td>9</td>
4239 <td>DEV_DCC10_DCC_INPUT00_CLK</td>
4240 <td>Input clock</td>
4241 </tr>
4242 <tr class="row-even"><td>10</td>
4243 <td>DEV_DCC10_DCC_CLKSRC5_CLK</td>
4244 <td>Input clock</td>
4245 </tr>
4246 <tr class="row-odd"><td>11</td>
4247 <td>DEV_DCC10_DCC_CLKSRC6_CLK</td>
4248 <td>Input clock</td>
4249 </tr>
4250 <tr class="row-even"><td>12</td>
4251 <td>DEV_DCC10_DCC_INPUT02_CLK</td>
4252 <td>Input clock</td>
4253 </tr>
4254 </tbody>
4255 </table>
4256 </div>
4257 <div class="section" id="clocks-for-dcc11-device">
4258 <span id="soc-doc-j721e-public-clks-dcc11"></span><h3>Clocks for DCC11 Device<a class="headerlink" href="#clocks-for-dcc11-device" title="Permalink to this headline">¶</a></h3>
4259 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC11</span></a> (ID = 42)</p>
4260 <p>Following is a mapping of Clocks IDs to function:</p>
4261 <table border="1" class="docutils">
4262 <colgroup>
4263 <col width="23%" />
4264 <col width="52%" />
4265 <col width="25%" />
4266 </colgroup>
4267 <thead valign="bottom">
4268 <tr class="row-odd"><th class="head">Clock ID</th>
4269 <th class="head">Name</th>
4270 <th class="head">Function</th>
4271 </tr>
4272 </thead>
4273 <tbody valign="top">
4274 <tr class="row-even"><td>0</td>
4275 <td>DEV_DCC11_DCC_INPUT10_CLK</td>
4276 <td>Input clock</td>
4277 </tr>
4278 <tr class="row-odd"><td>1</td>
4279 <td>DEV_DCC11_DCC_INPUT01_CLK</td>
4280 <td>Input clock</td>
4281 </tr>
4282 <tr class="row-even"><td>2</td>
4283 <td>DEV_DCC11_DCC_CLKSRC2_CLK</td>
4284 <td>Input clock</td>
4285 </tr>
4286 <tr class="row-odd"><td>3</td>
4287 <td>DEV_DCC11_DCC_CLKSRC7_CLK</td>
4288 <td>Input clock</td>
4289 </tr>
4290 <tr class="row-even"><td>4</td>
4291 <td>DEV_DCC11_DCC_CLKSRC0_CLK</td>
4292 <td>Input clock</td>
4293 </tr>
4294 <tr class="row-odd"><td>5</td>
4295 <td>DEV_DCC11_VBUS_CLK</td>
4296 <td>Input clock</td>
4297 </tr>
4298 <tr class="row-even"><td>6</td>
4299 <td>DEV_DCC11_DCC_CLKSRC4_CLK</td>
4300 <td>Input clock</td>
4301 </tr>
4302 <tr class="row-odd"><td>7</td>
4303 <td>DEV_DCC11_DCC_CLKSRC1_CLK</td>
4304 <td>Input clock</td>
4305 </tr>
4306 <tr class="row-even"><td>8</td>
4307 <td>DEV_DCC11_DCC_CLKSRC3_CLK</td>
4308 <td>Input clock</td>
4309 </tr>
4310 <tr class="row-odd"><td>9</td>
4311 <td>DEV_DCC11_DCC_INPUT00_CLK</td>
4312 <td>Input clock</td>
4313 </tr>
4314 <tr class="row-even"><td>10</td>
4315 <td>DEV_DCC11_DCC_CLKSRC5_CLK</td>
4316 <td>Input clock</td>
4317 </tr>
4318 <tr class="row-odd"><td>11</td>
4319 <td>DEV_DCC11_DCC_CLKSRC6_CLK</td>
4320 <td>Input clock</td>
4321 </tr>
4322 <tr class="row-even"><td>12</td>
4323 <td>DEV_DCC11_DCC_INPUT02_CLK</td>
4324 <td>Input clock</td>
4325 </tr>
4326 </tbody>
4327 </table>
4328 </div>
4329 <div class="section" id="clocks-for-dcc12-device">
4330 <span id="soc-doc-j721e-public-clks-dcc12"></span><h3>Clocks for DCC12 Device<a class="headerlink" href="#clocks-for-dcc12-device" title="Permalink to this headline">¶</a></h3>
4331 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC12</span></a> (ID = 43)</p>
4332 <p>Following is a mapping of Clocks IDs to function:</p>
4333 <table border="1" class="docutils">
4334 <colgroup>
4335 <col width="23%" />
4336 <col width="52%" />
4337 <col width="25%" />
4338 </colgroup>
4339 <thead valign="bottom">
4340 <tr class="row-odd"><th class="head">Clock ID</th>
4341 <th class="head">Name</th>
4342 <th class="head">Function</th>
4343 </tr>
4344 </thead>
4345 <tbody valign="top">
4346 <tr class="row-even"><td>0</td>
4347 <td>DEV_DCC12_DCC_INPUT10_CLK</td>
4348 <td>Input clock</td>
4349 </tr>
4350 <tr class="row-odd"><td>1</td>
4351 <td>DEV_DCC12_DCC_INPUT01_CLK</td>
4352 <td>Input clock</td>
4353 </tr>
4354 <tr class="row-even"><td>2</td>
4355 <td>DEV_DCC12_DCC_CLKSRC2_CLK</td>
4356 <td>Input clock</td>
4357 </tr>
4358 <tr class="row-odd"><td>3</td>
4359 <td>DEV_DCC12_DCC_CLKSRC7_CLK</td>
4360 <td>Input clock</td>
4361 </tr>
4362 <tr class="row-even"><td>4</td>
4363 <td>DEV_DCC12_DCC_CLKSRC0_CLK</td>
4364 <td>Input clock</td>
4365 </tr>
4366 <tr class="row-odd"><td>5</td>
4367 <td>DEV_DCC12_VBUS_CLK</td>
4368 <td>Input clock</td>
4369 </tr>
4370 <tr class="row-even"><td>6</td>
4371 <td>DEV_DCC12_DCC_CLKSRC4_CLK</td>
4372 <td>Input clock</td>
4373 </tr>
4374 <tr class="row-odd"><td>7</td>
4375 <td>DEV_DCC12_DCC_CLKSRC1_CLK</td>
4376 <td>Input clock</td>
4377 </tr>
4378 <tr class="row-even"><td>8</td>
4379 <td>DEV_DCC12_DCC_CLKSRC3_CLK</td>
4380 <td>Input clock</td>
4381 </tr>
4382 <tr class="row-odd"><td>9</td>
4383 <td>DEV_DCC12_DCC_INPUT00_CLK</td>
4384 <td>Input clock</td>
4385 </tr>
4386 <tr class="row-even"><td>10</td>
4387 <td>DEV_DCC12_DCC_CLKSRC5_CLK</td>
4388 <td>Input clock</td>
4389 </tr>
4390 <tr class="row-odd"><td>11</td>
4391 <td>DEV_DCC12_DCC_CLKSRC6_CLK</td>
4392 <td>Input clock</td>
4393 </tr>
4394 <tr class="row-even"><td>12</td>
4395 <td>DEV_DCC12_DCC_INPUT02_CLK</td>
4396 <td>Input clock</td>
4397 </tr>
4398 </tbody>
4399 </table>
4400 </div>
4401 <div class="section" id="clocks-for-dcc2-device">
4402 <span id="soc-doc-j721e-public-clks-dcc2"></span><h3>Clocks for DCC2 Device<a class="headerlink" href="#clocks-for-dcc2-device" title="Permalink to this headline">¶</a></h3>
4403 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC2</span></a> (ID = 32)</p>
4404 <p>Following is a mapping of Clocks IDs to function:</p>
4405 <table border="1" class="docutils">
4406 <colgroup>
4407 <col width="24%" />
4408 <col width="51%" />
4409 <col width="25%" />
4410 </colgroup>
4411 <thead valign="bottom">
4412 <tr class="row-odd"><th class="head">Clock ID</th>
4413 <th class="head">Name</th>
4414 <th class="head">Function</th>
4415 </tr>
4416 </thead>
4417 <tbody valign="top">
4418 <tr class="row-even"><td>0</td>
4419 <td>DEV_DCC2_DCC_INPUT10_CLK</td>
4420 <td>Input clock</td>
4421 </tr>
4422 <tr class="row-odd"><td>1</td>
4423 <td>DEV_DCC2_DCC_INPUT01_CLK</td>
4424 <td>Input clock</td>
4425 </tr>
4426 <tr class="row-even"><td>2</td>
4427 <td>DEV_DCC2_DCC_CLKSRC2_CLK</td>
4428 <td>Input clock</td>
4429 </tr>
4430 <tr class="row-odd"><td>3</td>
4431 <td>DEV_DCC2_DCC_CLKSRC7_CLK</td>
4432 <td>Input clock</td>
4433 </tr>
4434 <tr class="row-even"><td>4</td>
4435 <td>DEV_DCC2_DCC_CLKSRC0_CLK</td>
4436 <td>Input clock</td>
4437 </tr>
4438 <tr class="row-odd"><td>5</td>
4439 <td>DEV_DCC2_VBUS_CLK</td>
4440 <td>Input clock</td>
4441 </tr>
4442 <tr class="row-even"><td>6</td>
4443 <td>DEV_DCC2_DCC_CLKSRC4_CLK</td>
4444 <td>Input clock</td>
4445 </tr>
4446 <tr class="row-odd"><td>7</td>
4447 <td>DEV_DCC2_DCC_CLKSRC1_CLK</td>
4448 <td>Input clock</td>
4449 </tr>
4450 <tr class="row-even"><td>8</td>
4451 <td>DEV_DCC2_DCC_CLKSRC3_CLK</td>
4452 <td>Input clock</td>
4453 </tr>
4454 <tr class="row-odd"><td>9</td>
4455 <td>DEV_DCC2_DCC_INPUT00_CLK</td>
4456 <td>Input clock</td>
4457 </tr>
4458 <tr class="row-even"><td>10</td>
4459 <td>DEV_DCC2_DCC_CLKSRC5_CLK</td>
4460 <td>Input clock</td>
4461 </tr>
4462 <tr class="row-odd"><td>11</td>
4463 <td>DEV_DCC2_DCC_CLKSRC6_CLK</td>
4464 <td>Input clock</td>
4465 </tr>
4466 <tr class="row-even"><td>12</td>
4467 <td>DEV_DCC2_DCC_INPUT02_CLK</td>
4468 <td>Input clock</td>
4469 </tr>
4470 </tbody>
4471 </table>
4472 </div>
4473 <div class="section" id="clocks-for-dcc3-device">
4474 <span id="soc-doc-j721e-public-clks-dcc3"></span><h3>Clocks for DCC3 Device<a class="headerlink" href="#clocks-for-dcc3-device" title="Permalink to this headline">¶</a></h3>
4475 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC3</span></a> (ID = 33)</p>
4476 <p>Following is a mapping of Clocks IDs to function:</p>
4477 <table border="1" class="docutils">
4478 <colgroup>
4479 <col width="24%" />
4480 <col width="51%" />
4481 <col width="25%" />
4482 </colgroup>
4483 <thead valign="bottom">
4484 <tr class="row-odd"><th class="head">Clock ID</th>
4485 <th class="head">Name</th>
4486 <th class="head">Function</th>
4487 </tr>
4488 </thead>
4489 <tbody valign="top">
4490 <tr class="row-even"><td>0</td>
4491 <td>DEV_DCC3_DCC_INPUT10_CLK</td>
4492 <td>Input clock</td>
4493 </tr>
4494 <tr class="row-odd"><td>1</td>
4495 <td>DEV_DCC3_DCC_INPUT01_CLK</td>
4496 <td>Input clock</td>
4497 </tr>
4498 <tr class="row-even"><td>2</td>
4499 <td>DEV_DCC3_DCC_CLKSRC2_CLK</td>
4500 <td>Input clock</td>
4501 </tr>
4502 <tr class="row-odd"><td>3</td>
4503 <td>DEV_DCC3_DCC_CLKSRC7_CLK</td>
4504 <td>Input clock</td>
4505 </tr>
4506 <tr class="row-even"><td>4</td>
4507 <td>DEV_DCC3_DCC_CLKSRC0_CLK</td>
4508 <td>Input clock</td>
4509 </tr>
4510 <tr class="row-odd"><td>5</td>
4511 <td>DEV_DCC3_VBUS_CLK</td>
4512 <td>Input clock</td>
4513 </tr>
4514 <tr class="row-even"><td>6</td>
4515 <td>DEV_DCC3_DCC_CLKSRC4_CLK</td>
4516 <td>Input clock</td>
4517 </tr>
4518 <tr class="row-odd"><td>7</td>
4519 <td>DEV_DCC3_DCC_CLKSRC1_CLK</td>
4520 <td>Input clock</td>
4521 </tr>
4522 <tr class="row-even"><td>8</td>
4523 <td>DEV_DCC3_DCC_CLKSRC3_CLK</td>
4524 <td>Input clock</td>
4525 </tr>
4526 <tr class="row-odd"><td>9</td>
4527 <td>DEV_DCC3_DCC_INPUT00_CLK</td>
4528 <td>Input clock</td>
4529 </tr>
4530 <tr class="row-even"><td>10</td>
4531 <td>DEV_DCC3_DCC_CLKSRC5_CLK</td>
4532 <td>Input clock</td>
4533 </tr>
4534 <tr class="row-odd"><td>11</td>
4535 <td>DEV_DCC3_DCC_CLKSRC6_CLK</td>
4536 <td>Input clock</td>
4537 </tr>
4538 <tr class="row-even"><td>12</td>
4539 <td>DEV_DCC3_DCC_INPUT02_CLK</td>
4540 <td>Input clock</td>
4541 </tr>
4542 </tbody>
4543 </table>
4544 </div>
4545 <div class="section" id="clocks-for-dcc4-device">
4546 <span id="soc-doc-j721e-public-clks-dcc4"></span><h3>Clocks for DCC4 Device<a class="headerlink" href="#clocks-for-dcc4-device" title="Permalink to this headline">¶</a></h3>
4547 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC4</span></a> (ID = 34)</p>
4548 <p>Following is a mapping of Clocks IDs to function:</p>
4549 <table border="1" class="docutils">
4550 <colgroup>
4551 <col width="24%" />
4552 <col width="51%" />
4553 <col width="25%" />
4554 </colgroup>
4555 <thead valign="bottom">
4556 <tr class="row-odd"><th class="head">Clock ID</th>
4557 <th class="head">Name</th>
4558 <th class="head">Function</th>
4559 </tr>
4560 </thead>
4561 <tbody valign="top">
4562 <tr class="row-even"><td>0</td>
4563 <td>DEV_DCC4_DCC_INPUT10_CLK</td>
4564 <td>Input clock</td>
4565 </tr>
4566 <tr class="row-odd"><td>1</td>
4567 <td>DEV_DCC4_DCC_INPUT01_CLK</td>
4568 <td>Input clock</td>
4569 </tr>
4570 <tr class="row-even"><td>2</td>
4571 <td>DEV_DCC4_DCC_CLKSRC2_CLK</td>
4572 <td>Input clock</td>
4573 </tr>
4574 <tr class="row-odd"><td>3</td>
4575 <td>DEV_DCC4_DCC_CLKSRC7_CLK</td>
4576 <td>Input clock</td>
4577 </tr>
4578 <tr class="row-even"><td>4</td>
4579 <td>DEV_DCC4_DCC_CLKSRC0_CLK</td>
4580 <td>Input clock</td>
4581 </tr>
4582 <tr class="row-odd"><td>5</td>
4583 <td>DEV_DCC4_VBUS_CLK</td>
4584 <td>Input clock</td>
4585 </tr>
4586 <tr class="row-even"><td>6</td>
4587 <td>DEV_DCC4_DCC_CLKSRC4_CLK</td>
4588 <td>Input clock</td>
4589 </tr>
4590 <tr class="row-odd"><td>7</td>
4591 <td>DEV_DCC4_DCC_CLKSRC1_CLK</td>
4592 <td>Input clock</td>
4593 </tr>
4594 <tr class="row-even"><td>8</td>
4595 <td>DEV_DCC4_DCC_CLKSRC3_CLK</td>
4596 <td>Input clock</td>
4597 </tr>
4598 <tr class="row-odd"><td>9</td>
4599 <td>DEV_DCC4_DCC_INPUT00_CLK</td>
4600 <td>Input clock</td>
4601 </tr>
4602 <tr class="row-even"><td>10</td>
4603 <td>DEV_DCC4_DCC_CLKSRC5_CLK</td>
4604 <td>Input clock</td>
4605 </tr>
4606 <tr class="row-odd"><td>11</td>
4607 <td>DEV_DCC4_DCC_CLKSRC6_CLK</td>
4608 <td>Input clock</td>
4609 </tr>
4610 <tr class="row-even"><td>12</td>
4611 <td>DEV_DCC4_DCC_INPUT02_CLK</td>
4612 <td>Input clock</td>
4613 </tr>
4614 </tbody>
4615 </table>
4616 </div>
4617 <div class="section" id="clocks-for-dcc5-device">
4618 <span id="soc-doc-j721e-public-clks-dcc5"></span><h3>Clocks for DCC5 Device<a class="headerlink" href="#clocks-for-dcc5-device" title="Permalink to this headline">¶</a></h3>
4619 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC5</span></a> (ID = 36)</p>
4620 <p>Following is a mapping of Clocks IDs to function:</p>
4621 <table border="1" class="docutils">
4622 <colgroup>
4623 <col width="24%" />
4624 <col width="51%" />
4625 <col width="25%" />
4626 </colgroup>
4627 <thead valign="bottom">
4628 <tr class="row-odd"><th class="head">Clock ID</th>
4629 <th class="head">Name</th>
4630 <th class="head">Function</th>
4631 </tr>
4632 </thead>
4633 <tbody valign="top">
4634 <tr class="row-even"><td>0</td>
4635 <td>DEV_DCC5_DCC_INPUT10_CLK</td>
4636 <td>Input clock</td>
4637 </tr>
4638 <tr class="row-odd"><td>1</td>
4639 <td>DEV_DCC5_DCC_INPUT01_CLK</td>
4640 <td>Input clock</td>
4641 </tr>
4642 <tr class="row-even"><td>2</td>
4643 <td>DEV_DCC5_DCC_CLKSRC2_CLK</td>
4644 <td>Input clock</td>
4645 </tr>
4646 <tr class="row-odd"><td>3</td>
4647 <td>DEV_DCC5_DCC_CLKSRC7_CLK</td>
4648 <td>Input clock</td>
4649 </tr>
4650 <tr class="row-even"><td>4</td>
4651 <td>DEV_DCC5_DCC_CLKSRC0_CLK</td>
4652 <td>Input clock</td>
4653 </tr>
4654 <tr class="row-odd"><td>5</td>
4655 <td>DEV_DCC5_VBUS_CLK</td>
4656 <td>Input clock</td>
4657 </tr>
4658 <tr class="row-even"><td>6</td>
4659 <td>DEV_DCC5_DCC_CLKSRC4_CLK</td>
4660 <td>Input clock</td>
4661 </tr>
4662 <tr class="row-odd"><td>7</td>
4663 <td>DEV_DCC5_DCC_CLKSRC1_CLK</td>
4664 <td>Input clock</td>
4665 </tr>
4666 <tr class="row-even"><td>8</td>
4667 <td>DEV_DCC5_DCC_CLKSRC3_CLK</td>
4668 <td>Input clock</td>
4669 </tr>
4670 <tr class="row-odd"><td>9</td>
4671 <td>DEV_DCC5_DCC_INPUT00_CLK</td>
4672 <td>Input clock</td>
4673 </tr>
4674 <tr class="row-even"><td>10</td>
4675 <td>DEV_DCC5_DCC_CLKSRC5_CLK</td>
4676 <td>Input clock</td>
4677 </tr>
4678 <tr class="row-odd"><td>11</td>
4679 <td>DEV_DCC5_DCC_CLKSRC6_CLK</td>
4680 <td>Input clock</td>
4681 </tr>
4682 <tr class="row-even"><td>12</td>
4683 <td>DEV_DCC5_DCC_INPUT02_CLK</td>
4684 <td>Input clock</td>
4685 </tr>
4686 </tbody>
4687 </table>
4688 </div>
4689 <div class="section" id="clocks-for-dcc6-device">
4690 <span id="soc-doc-j721e-public-clks-dcc6"></span><h3>Clocks for DCC6 Device<a class="headerlink" href="#clocks-for-dcc6-device" title="Permalink to this headline">¶</a></h3>
4691 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC6</span></a> (ID = 37)</p>
4692 <p>Following is a mapping of Clocks IDs to function:</p>
4693 <table border="1" class="docutils">
4694 <colgroup>
4695 <col width="24%" />
4696 <col width="51%" />
4697 <col width="25%" />
4698 </colgroup>
4699 <thead valign="bottom">
4700 <tr class="row-odd"><th class="head">Clock ID</th>
4701 <th class="head">Name</th>
4702 <th class="head">Function</th>
4703 </tr>
4704 </thead>
4705 <tbody valign="top">
4706 <tr class="row-even"><td>0</td>
4707 <td>DEV_DCC6_DCC_INPUT10_CLK</td>
4708 <td>Input clock</td>
4709 </tr>
4710 <tr class="row-odd"><td>1</td>
4711 <td>DEV_DCC6_DCC_INPUT01_CLK</td>
4712 <td>Input clock</td>
4713 </tr>
4714 <tr class="row-even"><td>2</td>
4715 <td>DEV_DCC6_DCC_CLKSRC2_CLK</td>
4716 <td>Input clock</td>
4717 </tr>
4718 <tr class="row-odd"><td>3</td>
4719 <td>DEV_DCC6_DCC_CLKSRC7_CLK</td>
4720 <td>Input clock</td>
4721 </tr>
4722 <tr class="row-even"><td>4</td>
4723 <td>DEV_DCC6_DCC_CLKSRC0_CLK</td>
4724 <td>Input clock</td>
4725 </tr>
4726 <tr class="row-odd"><td>5</td>
4727 <td>DEV_DCC6_VBUS_CLK</td>
4728 <td>Input clock</td>
4729 </tr>
4730 <tr class="row-even"><td>6</td>
4731 <td>DEV_DCC6_DCC_CLKSRC4_CLK</td>
4732 <td>Input clock</td>
4733 </tr>
4734 <tr class="row-odd"><td>7</td>
4735 <td>DEV_DCC6_DCC_CLKSRC1_CLK</td>
4736 <td>Input clock</td>
4737 </tr>
4738 <tr class="row-even"><td>8</td>
4739 <td>DEV_DCC6_DCC_CLKSRC3_CLK</td>
4740 <td>Input clock</td>
4741 </tr>
4742 <tr class="row-odd"><td>9</td>
4743 <td>DEV_DCC6_DCC_INPUT00_CLK</td>
4744 <td>Input clock</td>
4745 </tr>
4746 <tr class="row-even"><td>10</td>
4747 <td>DEV_DCC6_DCC_CLKSRC5_CLK</td>
4748 <td>Input clock</td>
4749 </tr>
4750 <tr class="row-odd"><td>11</td>
4751 <td>DEV_DCC6_DCC_CLKSRC6_CLK</td>
4752 <td>Input clock</td>
4753 </tr>
4754 <tr class="row-even"><td>12</td>
4755 <td>DEV_DCC6_DCC_INPUT02_CLK</td>
4756 <td>Input clock</td>
4757 </tr>
4758 </tbody>
4759 </table>
4760 </div>
4761 <div class="section" id="clocks-for-dcc7-device">
4762 <span id="soc-doc-j721e-public-clks-dcc7"></span><h3>Clocks for DCC7 Device<a class="headerlink" href="#clocks-for-dcc7-device" title="Permalink to this headline">¶</a></h3>
4763 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC7</span></a> (ID = 38)</p>
4764 <p>Following is a mapping of Clocks IDs to function:</p>
4765 <table border="1" class="docutils">
4766 <colgroup>
4767 <col width="24%" />
4768 <col width="51%" />
4769 <col width="25%" />
4770 </colgroup>
4771 <thead valign="bottom">
4772 <tr class="row-odd"><th class="head">Clock ID</th>
4773 <th class="head">Name</th>
4774 <th class="head">Function</th>
4775 </tr>
4776 </thead>
4777 <tbody valign="top">
4778 <tr class="row-even"><td>0</td>
4779 <td>DEV_DCC7_DCC_INPUT10_CLK</td>
4780 <td>Input clock</td>
4781 </tr>
4782 <tr class="row-odd"><td>1</td>
4783 <td>DEV_DCC7_DCC_INPUT01_CLK</td>
4784 <td>Input clock</td>
4785 </tr>
4786 <tr class="row-even"><td>2</td>
4787 <td>DEV_DCC7_DCC_CLKSRC2_CLK</td>
4788 <td>Input clock</td>
4789 </tr>
4790 <tr class="row-odd"><td>3</td>
4791 <td>DEV_DCC7_DCC_CLKSRC7_CLK</td>
4792 <td>Input clock</td>
4793 </tr>
4794 <tr class="row-even"><td>4</td>
4795 <td>DEV_DCC7_DCC_CLKSRC0_CLK</td>
4796 <td>Input clock</td>
4797 </tr>
4798 <tr class="row-odd"><td>5</td>
4799 <td>DEV_DCC7_VBUS_CLK</td>
4800 <td>Input clock</td>
4801 </tr>
4802 <tr class="row-even"><td>6</td>
4803 <td>DEV_DCC7_DCC_CLKSRC4_CLK</td>
4804 <td>Input clock</td>
4805 </tr>
4806 <tr class="row-odd"><td>7</td>
4807 <td>DEV_DCC7_DCC_CLKSRC1_CLK</td>
4808 <td>Input clock</td>
4809 </tr>
4810 <tr class="row-even"><td>8</td>
4811 <td>DEV_DCC7_DCC_CLKSRC3_CLK</td>
4812 <td>Input clock</td>
4813 </tr>
4814 <tr class="row-odd"><td>9</td>
4815 <td>DEV_DCC7_DCC_INPUT00_CLK</td>
4816 <td>Input clock</td>
4817 </tr>
4818 <tr class="row-even"><td>10</td>
4819 <td>DEV_DCC7_DCC_CLKSRC5_CLK</td>
4820 <td>Input clock</td>
4821 </tr>
4822 <tr class="row-odd"><td>11</td>
4823 <td>DEV_DCC7_DCC_CLKSRC6_CLK</td>
4824 <td>Input clock</td>
4825 </tr>
4826 <tr class="row-even"><td>12</td>
4827 <td>DEV_DCC7_DCC_INPUT02_CLK</td>
4828 <td>Input clock</td>
4829 </tr>
4830 </tbody>
4831 </table>
4832 </div>
4833 <div class="section" id="clocks-for-dcc8-device">
4834 <span id="soc-doc-j721e-public-clks-dcc8"></span><h3>Clocks for DCC8 Device<a class="headerlink" href="#clocks-for-dcc8-device" title="Permalink to this headline">¶</a></h3>
4835 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC8</span></a> (ID = 39)</p>
4836 <p>Following is a mapping of Clocks IDs to function:</p>
4837 <table border="1" class="docutils">
4838 <colgroup>
4839 <col width="24%" />
4840 <col width="51%" />
4841 <col width="25%" />
4842 </colgroup>
4843 <thead valign="bottom">
4844 <tr class="row-odd"><th class="head">Clock ID</th>
4845 <th class="head">Name</th>
4846 <th class="head">Function</th>
4847 </tr>
4848 </thead>
4849 <tbody valign="top">
4850 <tr class="row-even"><td>0</td>
4851 <td>DEV_DCC8_DCC_INPUT10_CLK</td>
4852 <td>Input clock</td>
4853 </tr>
4854 <tr class="row-odd"><td>1</td>
4855 <td>DEV_DCC8_DCC_INPUT01_CLK</td>
4856 <td>Input clock</td>
4857 </tr>
4858 <tr class="row-even"><td>2</td>
4859 <td>DEV_DCC8_DCC_CLKSRC2_CLK</td>
4860 <td>Input clock</td>
4861 </tr>
4862 <tr class="row-odd"><td>3</td>
4863 <td>DEV_DCC8_DCC_CLKSRC7_CLK</td>
4864 <td>Input clock</td>
4865 </tr>
4866 <tr class="row-even"><td>4</td>
4867 <td>DEV_DCC8_DCC_CLKSRC0_CLK</td>
4868 <td>Input clock</td>
4869 </tr>
4870 <tr class="row-odd"><td>5</td>
4871 <td>DEV_DCC8_VBUS_CLK</td>
4872 <td>Input clock</td>
4873 </tr>
4874 <tr class="row-even"><td>6</td>
4875 <td>DEV_DCC8_DCC_CLKSRC4_CLK</td>
4876 <td>Input clock</td>
4877 </tr>
4878 <tr class="row-odd"><td>7</td>
4879 <td>DEV_DCC8_DCC_CLKSRC1_CLK</td>
4880 <td>Input clock</td>
4881 </tr>
4882 <tr class="row-even"><td>8</td>
4883 <td>DEV_DCC8_DCC_CLKSRC3_CLK</td>
4884 <td>Input clock</td>
4885 </tr>
4886 <tr class="row-odd"><td>9</td>
4887 <td>DEV_DCC8_DCC_INPUT00_CLK</td>
4888 <td>Input clock</td>
4889 </tr>
4890 <tr class="row-even"><td>10</td>
4891 <td>DEV_DCC8_DCC_CLKSRC5_CLK</td>
4892 <td>Input clock</td>
4893 </tr>
4894 <tr class="row-odd"><td>11</td>
4895 <td>DEV_DCC8_DCC_CLKSRC6_CLK</td>
4896 <td>Input clock</td>
4897 </tr>
4898 <tr class="row-even"><td>12</td>
4899 <td>DEV_DCC8_DCC_INPUT02_CLK</td>
4900 <td>Input clock</td>
4901 </tr>
4902 </tbody>
4903 </table>
4904 </div>
4905 <div class="section" id="clocks-for-dcc9-device">
4906 <span id="soc-doc-j721e-public-clks-dcc9"></span><h3>Clocks for DCC9 Device<a class="headerlink" href="#clocks-for-dcc9-device" title="Permalink to this headline">¶</a></h3>
4907 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DCC9</span></a> (ID = 40)</p>
4908 <p>Following is a mapping of Clocks IDs to function:</p>
4909 <table border="1" class="docutils">
4910 <colgroup>
4911 <col width="24%" />
4912 <col width="51%" />
4913 <col width="25%" />
4914 </colgroup>
4915 <thead valign="bottom">
4916 <tr class="row-odd"><th class="head">Clock ID</th>
4917 <th class="head">Name</th>
4918 <th class="head">Function</th>
4919 </tr>
4920 </thead>
4921 <tbody valign="top">
4922 <tr class="row-even"><td>0</td>
4923 <td>DEV_DCC9_DCC_INPUT10_CLK</td>
4924 <td>Input clock</td>
4925 </tr>
4926 <tr class="row-odd"><td>1</td>
4927 <td>DEV_DCC9_DCC_INPUT01_CLK</td>
4928 <td>Input clock</td>
4929 </tr>
4930 <tr class="row-even"><td>2</td>
4931 <td>DEV_DCC9_DCC_CLKSRC2_CLK</td>
4932 <td>Input clock</td>
4933 </tr>
4934 <tr class="row-odd"><td>3</td>
4935 <td>DEV_DCC9_DCC_CLKSRC7_CLK</td>
4936 <td>Input clock</td>
4937 </tr>
4938 <tr class="row-even"><td>4</td>
4939 <td>DEV_DCC9_DCC_CLKSRC0_CLK</td>
4940 <td>Input clock</td>
4941 </tr>
4942 <tr class="row-odd"><td>5</td>
4943 <td>DEV_DCC9_VBUS_CLK</td>
4944 <td>Input clock</td>
4945 </tr>
4946 <tr class="row-even"><td>6</td>
4947 <td>DEV_DCC9_DCC_CLKSRC4_CLK</td>
4948 <td>Input clock</td>
4949 </tr>
4950 <tr class="row-odd"><td>7</td>
4951 <td>DEV_DCC9_DCC_CLKSRC1_CLK</td>
4952 <td>Input clock</td>
4953 </tr>
4954 <tr class="row-even"><td>8</td>
4955 <td>DEV_DCC9_DCC_CLKSRC3_CLK</td>
4956 <td>Input clock</td>
4957 </tr>
4958 <tr class="row-odd"><td>9</td>
4959 <td>DEV_DCC9_DCC_INPUT00_CLK</td>
4960 <td>Input clock</td>
4961 </tr>
4962 <tr class="row-even"><td>10</td>
4963 <td>DEV_DCC9_DCC_CLKSRC5_CLK</td>
4964 <td>Input clock</td>
4965 </tr>
4966 <tr class="row-odd"><td>11</td>
4967 <td>DEV_DCC9_DCC_CLKSRC6_CLK</td>
4968 <td>Input clock</td>
4969 </tr>
4970 <tr class="row-even"><td>12</td>
4971 <td>DEV_DCC9_DCC_INPUT02_CLK</td>
4972 <td>Input clock</td>
4973 </tr>
4974 </tbody>
4975 </table>
4976 </div>
4977 <div class="section" id="clocks-for-ddr0-device">
4978 <span id="soc-doc-j721e-public-clks-ddr0"></span><h3>Clocks for DDR0 Device<a class="headerlink" href="#clocks-for-ddr0-device" title="Permalink to this headline">¶</a></h3>
4979 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DDR0</span></a> (ID = 47)</p>
4980 <p>Following is a mapping of Clocks IDs to function:</p>
4981 <table border="1" class="docutils">
4982 <colgroup>
4983 <col width="22%" />
4984 <col width="52%" />
4985 <col width="26%" />
4986 </colgroup>
4987 <thead valign="bottom">
4988 <tr class="row-odd"><th class="head">Clock ID</th>
4989 <th class="head">Name</th>
4990 <th class="head">Function</th>
4991 </tr>
4992 </thead>
4993 <tbody valign="top">
4994 <tr class="row-even"><td>0</td>
4995 <td>DEV_DDR0_DDRSS_VBUS_CLK</td>
4996 <td>Input clock</td>
4997 </tr>
4998 <tr class="row-odd"><td>1</td>
4999 <td>DEV_DDR0_PLL_CTRL_CLK</td>
5000 <td>Input clock</td>
5001 </tr>
5002 <tr class="row-even"><td>2</td>
5003 <td>DEV_DDR0_DDRSS_DDR_PLL_CLK</td>
5004 <td>Input clock</td>
5005 </tr>
5006 <tr class="row-odd"><td>3</td>
5007 <td>DEV_DDR0_DDRSS_CFG_CLK</td>
5008 <td>Input clock</td>
5009 </tr>
5010 <tr class="row-even"><td>4</td>
5011 <td>DEV_DDR0_DDRSS_IO_CK_N</td>
5012 <td>Output clock</td>
5013 </tr>
5014 <tr class="row-odd"><td>5</td>
5015 <td>DEV_DDR0_DDRSS_IO_CK</td>
5016 <td>Output clock</td>
5017 </tr>
5018 </tbody>
5019 </table>
5020 </div>
5021 <div class="section" id="clocks-for-debugss-wrap0-device">
5022 <span id="soc-doc-j721e-public-clks-debugss-wrap0"></span><h3>Clocks for DEBUGSS_WRAP0 Device<a class="headerlink" href="#clocks-for-debugss-wrap0-device" title="Permalink to this headline">¶</a></h3>
5023 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DEBUGSS_WRAP0</span></a> (ID = 304)</p>
5024 <p>Following is a mapping of Clocks IDs to function:</p>
5025 <table border="1" class="docutils">
5026 <colgroup>
5027 <col width="20%" />
5028 <col width="57%" />
5029 <col width="23%" />
5030 </colgroup>
5031 <thead valign="bottom">
5032 <tr class="row-odd"><th class="head">Clock ID</th>
5033 <th class="head">Name</th>
5034 <th class="head">Function</th>
5035 </tr>
5036 </thead>
5037 <tbody valign="top">
5038 <tr class="row-even"><td>5</td>
5039 <td>DEV_DEBUGSS_WRAP0_TREXPT_CLK</td>
5040 <td>Input clock</td>
5041 </tr>
5042 <tr class="row-odd"><td>9</td>
5043 <td>DEV_DEBUGSS_WRAP0_CORE_CLK</td>
5044 <td>Input clock</td>
5045 </tr>
5046 <tr class="row-even"><td>25</td>
5047 <td>DEV_DEBUGSS_WRAP0_JTAG_TCK</td>
5048 <td>Input clock</td>
5049 </tr>
5050 <tr class="row-odd"><td>32</td>
5051 <td>DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK</td>
5052 <td>Output clock</td>
5053 </tr>
5054 <tr class="row-even"><td>35</td>
5055 <td>DEV_DEBUGSS_WRAP0_ATB_CLK</td>
5056 <td>Input clock</td>
5057 </tr>
5058 </tbody>
5059 </table>
5060 </div>
5061 <div class="section" id="clocks-for-decoder0-device">
5062 <span id="soc-doc-j721e-public-clks-decoder0"></span><h3>Clocks for DECODER0 Device<a class="headerlink" href="#clocks-for-decoder0-device" title="Permalink to this headline">¶</a></h3>
5063 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DECODER0</span></a> (ID = 144)</p>
5064 <p>Following is a mapping of Clocks IDs to function:</p>
5065 <table border="1" class="docutils">
5066 <colgroup>
5067 <col width="26%" />
5068 <col width="47%" />
5069 <col width="28%" />
5070 </colgroup>
5071 <thead valign="bottom">
5072 <tr class="row-odd"><th class="head">Clock ID</th>
5073 <th class="head">Name</th>
5074 <th class="head">Function</th>
5075 </tr>
5076 </thead>
5077 <tbody valign="top">
5078 <tr class="row-even"><td>0</td>
5079 <td>DEV_DECODER0_SYS_CLK</td>
5080 <td>Input clock</td>
5081 </tr>
5082 </tbody>
5083 </table>
5084 </div>
5085 <div class="section" id="clocks-for-dmpac0-device">
5086 <span id="soc-doc-j721e-public-clks-dmpac0"></span><h3>Clocks for DMPAC0 Device<a class="headerlink" href="#clocks-for-dmpac0-device" title="Permalink to this headline">¶</a></h3>
5087 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DMPAC0</span></a> (ID = 48)</p>
5088 <p>Following is a mapping of Clocks IDs to function:</p>
5089 <table border="1" class="docutils">
5090 <colgroup>
5091 <col width="24%" />
5092 <col width="49%" />
5093 <col width="27%" />
5094 </colgroup>
5095 <thead valign="bottom">
5096 <tr class="row-odd"><th class="head">Clock ID</th>
5097 <th class="head">Name</th>
5098 <th class="head">Function</th>
5099 </tr>
5100 </thead>
5101 <tbody valign="top">
5102 <tr class="row-even"><td>0</td>
5103 <td>DEV_DMPAC0_CLK</td>
5104 <td>Input clock</td>
5105 </tr>
5106 <tr class="row-odd"><td>1</td>
5107 <td>DEV_DMPAC0_PLL_DCO_CLK</td>
5108 <td>Input clock</td>
5109 </tr>
5110 </tbody>
5111 </table>
5112 </div>
5113 <div class="section" id="clocks-for-dmpac0-sde-0-device">
5114 <span id="soc-doc-j721e-public-clks-dmpac0-sde-0"></span><h3>Clocks for DMPAC0_SDE_0 Device<a class="headerlink" href="#clocks-for-dmpac0-sde-0-device" title="Permalink to this headline">¶</a></h3>
5115 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DMPAC0_SDE_0</span></a> (ID = 305)</p>
5116 <p>Following is a mapping of Clocks IDs to function:</p>
5117 <table border="1" class="docutils">
5118 <colgroup>
5119 <col width="26%" />
5120 <col width="47%" />
5121 <col width="28%" />
5122 </colgroup>
5123 <thead valign="bottom">
5124 <tr class="row-odd"><th class="head">Clock ID</th>
5125 <th class="head">Name</th>
5126 <th class="head">Function</th>
5127 </tr>
5128 </thead>
5129 <tbody valign="top">
5130 <tr class="row-even"><td>0</td>
5131 <td>DEV_DMPAC0_SDE_0_CLK</td>
5132 <td>Input clock</td>
5133 </tr>
5134 </tbody>
5135 </table>
5136 </div>
5137 <div class="section" id="clocks-for-dphy-rx0-device">
5138 <span id="soc-doc-j721e-public-clks-dphy-rx0"></span><h3>Clocks for DPHY_RX0 Device<a class="headerlink" href="#clocks-for-dphy-rx0-device" title="Permalink to this headline">¶</a></h3>
5139 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DPHY_RX0</span></a> (ID = 147)</p>
5140 <p>Following is a mapping of Clocks IDs to function:</p>
5141 <table border="1" class="docutils">
5142 <colgroup>
5143 <col width="21%" />
5144 <col width="54%" />
5145 <col width="25%" />
5146 </colgroup>
5147 <thead valign="bottom">
5148 <tr class="row-odd"><th class="head">Clock ID</th>
5149 <th class="head">Name</th>
5150 <th class="head">Function</th>
5151 </tr>
5152 </thead>
5153 <tbody valign="top">
5154 <tr class="row-even"><td>0</td>
5155 <td>DEV_DPHY_RX0_MAIN_CLK_CLK</td>
5156 <td>Input clock</td>
5157 </tr>
5158 <tr class="row-odd"><td>1</td>
5159 <td>DEV_DPHY_RX0_PPI_RX_BYTE_CLK</td>
5160 <td>Output clock</td>
5161 </tr>
5162 </tbody>
5163 </table>
5164 </div>
5165 <div class="section" id="clocks-for-dphy-rx1-device">
5166 <span id="soc-doc-j721e-public-clks-dphy-rx1"></span><h3>Clocks for DPHY_RX1 Device<a class="headerlink" href="#clocks-for-dphy-rx1-device" title="Permalink to this headline">¶</a></h3>
5167 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DPHY_RX1</span></a> (ID = 148)</p>
5168 <p>Following is a mapping of Clocks IDs to function:</p>
5169 <table border="1" class="docutils">
5170 <colgroup>
5171 <col width="21%" />
5172 <col width="54%" />
5173 <col width="25%" />
5174 </colgroup>
5175 <thead valign="bottom">
5176 <tr class="row-odd"><th class="head">Clock ID</th>
5177 <th class="head">Name</th>
5178 <th class="head">Function</th>
5179 </tr>
5180 </thead>
5181 <tbody valign="top">
5182 <tr class="row-even"><td>0</td>
5183 <td>DEV_DPHY_RX1_MAIN_CLK_CLK</td>
5184 <td>Input clock</td>
5185 </tr>
5186 <tr class="row-odd"><td>1</td>
5187 <td>DEV_DPHY_RX1_PPI_RX_BYTE_CLK</td>
5188 <td>Output clock</td>
5189 </tr>
5190 </tbody>
5191 </table>
5192 </div>
5193 <div class="section" id="clocks-for-dphy-tx0-device">
5194 <span id="soc-doc-j721e-public-clks-dphy-tx0"></span><h3>Clocks for DPHY_TX0 Device<a class="headerlink" href="#clocks-for-dphy-tx0-device" title="Permalink to this headline">¶</a></h3>
5195 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DPHY_TX0</span></a> (ID = 296)</p>
5196 <p>Following is a mapping of Clocks IDs to function:</p>
5197 <table border="1" class="docutils">
5198 <colgroup>
5199 <col width="9%" />
5200 <col width="50%" />
5201 <col width="41%" />
5202 </colgroup>
5203 <thead valign="bottom">
5204 <tr class="row-odd"><th class="head">Clock ID</th>
5205 <th class="head">Name</th>
5206 <th class="head">Function</th>
5207 </tr>
5208 </thead>
5209 <tbody valign="top">
5210 <tr class="row-even"><td>0</td>
5211 <td>DEV_DPHY_TX0_CLK</td>
5212 <td>Input clock</td>
5213 </tr>
5214 <tr class="row-odd"><td>1</td>
5215 <td>DEV_DPHY_TX0_PSM_CLK</td>
5216 <td>Input clock</td>
5217 </tr>
5218 <tr class="row-even"><td>2</td>
5219 <td>DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK</td>
5220 <td>Input clock</td>
5221 </tr>
5222 <tr class="row-odd"><td>3</td>
5223 <td>DEV_DPHY_TX0_DPHY_REF_CLK</td>
5224 <td>Input muxed clock</td>
5225 </tr>
5226 <tr class="row-even"><td>4</td>
5227 <td>DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
5228 <td>Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK</td>
5229 </tr>
5230 <tr class="row-odd"><td>5</td>
5231 <td>DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
5232 <td>Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK</td>
5233 </tr>
5234 <tr class="row-even"><td>6</td>
5235 <td>DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
5236 <td>Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK</td>
5237 </tr>
5238 <tr class="row-odd"><td>7</td>
5239 <td>DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
5240 <td>Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK</td>
5241 </tr>
5242 <tr class="row-even"><td>8</td>
5243 <td>DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK</td>
5244 <td>Output clock</td>
5245 </tr>
5246 <tr class="row-odd"><td>9</td>
5247 <td>DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK</td>
5248 <td>Output clock</td>
5249 </tr>
5250 <tr class="row-even"><td>10</td>
5251 <td>DEV_DPHY_TX0_CK_P</td>
5252 <td>Output clock</td>
5253 </tr>
5254 <tr class="row-odd"><td>11</td>
5255 <td>DEV_DPHY_TX0_CK_M</td>
5256 <td>Output clock</td>
5257 </tr>
5258 <tr class="row-even"><td>12</td>
5259 <td>DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK</td>
5260 <td>Output clock</td>
5261 </tr>
5262 </tbody>
5263 </table>
5264 </div>
5265 <div class="section" id="clocks-for-dss0-device">
5266 <span id="soc-doc-j721e-public-clks-dss0"></span><h3>Clocks for DSS0 Device<a class="headerlink" href="#clocks-for-dss0-device" title="Permalink to this headline">¶</a></h3>
5267 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DSS0</span></a> (ID = 152)</p>
5268 <p>Following is a mapping of Clocks IDs to function:</p>
5269 <table border="1" class="docutils">
5270 <colgroup>
5271 <col width="8%" />
5272 <col width="50%" />
5273 <col width="42%" />
5274 </colgroup>
5275 <thead valign="bottom">
5276 <tr class="row-odd"><th class="head">Clock ID</th>
5277 <th class="head">Name</th>
5278 <th class="head">Function</th>
5279 </tr>
5280 </thead>
5281 <tbody valign="top">
5282 <tr class="row-even"><td>0</td>
5283 <td>DEV_DSS0_DSS_FUNC_CLK</td>
5284 <td>Input clock</td>
5285 </tr>
5286 <tr class="row-odd"><td>1</td>
5287 <td>DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK</td>
5288 <td>Input muxed clock</td>
5289 </tr>
5290 <tr class="row-even"><td>2</td>
5291 <td>DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK</td>
5292 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK</td>
5293 </tr>
5294 <tr class="row-odd"><td>3</td>
5295 <td>DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0</td>
5296 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK</td>
5297 </tr>
5298 <tr class="row-even"><td>4</td>
5299 <td>DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK</td>
5300 <td>Input muxed clock</td>
5301 </tr>
5302 <tr class="row-odd"><td>5</td>
5303 <td>DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK</td>
5304 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK</td>
5305 </tr>
5306 <tr class="row-even"><td>6</td>
5307 <td>DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0</td>
5308 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK</td>
5309 </tr>
5310 <tr class="row-odd"><td>7</td>
5311 <td>DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0</td>
5312 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK</td>
5313 </tr>
5314 <tr class="row-even"><td>8</td>
5315 <td>DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK</td>
5316 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK</td>
5317 </tr>
5318 <tr class="row-odd"><td>9</td>
5319 <td>DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK</td>
5320 <td>Input muxed clock</td>
5321 </tr>
5322 <tr class="row-even"><td>10</td>
5323 <td>DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK</td>
5324 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK</td>
5325 </tr>
5326 <tr class="row-odd"><td>11</td>
5327 <td>DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK</td>
5328 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK</td>
5329 </tr>
5330 <tr class="row-even"><td>12</td>
5331 <td>DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0</td>
5332 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK</td>
5333 </tr>
5334 <tr class="row-odd"><td>13</td>
5335 <td>DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK</td>
5336 <td>Input muxed clock</td>
5337 </tr>
5338 <tr class="row-even"><td>14</td>
5339 <td>DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK</td>
5340 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK</td>
5341 </tr>
5342 <tr class="row-odd"><td>15</td>
5343 <td>DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK</td>
5344 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK</td>
5345 </tr>
5346 <tr class="row-even"><td>16</td>
5347 <td>DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK</td>
5348 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK</td>
5349 </tr>
5350 <tr class="row-odd"><td>17</td>
5351 <td>DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0</td>
5352 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK</td>
5353 </tr>
5354 <tr class="row-even"><td>18</td>
5355 <td>DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0</td>
5356 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK</td>
5357 </tr>
5358 <tr class="row-odd"><td>23</td>
5359 <td>DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK</td>
5360 <td>Output clock</td>
5361 </tr>
5362 <tr class="row-even"><td>24</td>
5363 <td>DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK</td>
5364 <td>Output clock</td>
5365 </tr>
5366 <tr class="row-odd"><td>25</td>
5367 <td>DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK</td>
5368 <td>Output clock</td>
5369 </tr>
5370 <tr class="row-even"><td>27</td>
5371 <td>DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK</td>
5372 <td>Output clock</td>
5373 </tr>
5374 <tr class="row-odd"><td>29</td>
5375 <td>DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK</td>
5376 <td>Output clock</td>
5377 </tr>
5378 <tr class="row-even"><td>31</td>
5379 <td>DEV_DSS0_DPI0_EXT_CLKSEL</td>
5380 <td>Input muxed clock</td>
5381 </tr>
5382 <tr class="row-odd"><td>32</td>
5383 <td>DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK</td>
5384 <td>Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL</td>
5385 </tr>
5386 <tr class="row-even"><td>33</td>
5387 <td>DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT</td>
5388 <td>Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL</td>
5389 </tr>
5390 <tr class="row-odd"><td>34</td>
5391 <td>DEV_DSS0_DPI1_EXT_CLKSEL</td>
5392 <td>Input muxed clock</td>
5393 </tr>
5394 <tr class="row-even"><td>35</td>
5395 <td>DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK</td>
5396 <td>Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL</td>
5397 </tr>
5398 <tr class="row-odd"><td>36</td>
5399 <td>DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT</td>
5400 <td>Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL</td>
5401 </tr>
5402 </tbody>
5403 </table>
5404 </div>
5405 <div class="section" id="clocks-for-dss-dsi0-device">
5406 <span id="soc-doc-j721e-public-clks-dss-dsi0"></span><h3>Clocks for DSS_DSI0 Device<a class="headerlink" href="#clocks-for-dss-dsi0-device" title="Permalink to this headline">¶</a></h3>
5407 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DSS_DSI0</span></a> (ID = 150)</p>
5408 <p>Following is a mapping of Clocks IDs to function:</p>
5409 <table border="1" class="docutils">
5410 <colgroup>
5411 <col width="19%" />
5412 <col width="61%" />
5413 <col width="20%" />
5414 </colgroup>
5415 <thead valign="bottom">
5416 <tr class="row-odd"><th class="head">Clock ID</th>
5417 <th class="head">Name</th>
5418 <th class="head">Function</th>
5419 </tr>
5420 </thead>
5421 <tbody valign="top">
5422 <tr class="row-even"><td>0</td>
5423 <td>DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK</td>
5424 <td>Input clock</td>
5425 </tr>
5426 <tr class="row-odd"><td>1</td>
5427 <td>DEV_DSS_DSI0_DPI_0_CLK</td>
5428 <td>Input clock</td>
5429 </tr>
5430 <tr class="row-even"><td>2</td>
5431 <td>DEV_DSS_DSI0_PLL_CTRL_CLK</td>
5432 <td>Input clock</td>
5433 </tr>
5434 <tr class="row-odd"><td>3</td>
5435 <td>DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK</td>
5436 <td>Input clock</td>
5437 </tr>
5438 <tr class="row-even"><td>4</td>
5439 <td>DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK</td>
5440 <td>Input clock</td>
5441 </tr>
5442 <tr class="row-odd"><td>5</td>
5443 <td>DEV_DSS_DSI0_SYS_CLK</td>
5444 <td>Input clock</td>
5445 </tr>
5446 </tbody>
5447 </table>
5448 </div>
5449 <div class="section" id="clocks-for-dss-edp0-device">
5450 <span id="soc-doc-j721e-public-clks-dss-edp0"></span><h3>Clocks for DSS_EDP0 Device<a class="headerlink" href="#clocks-for-dss-edp0-device" title="Permalink to this headline">¶</a></h3>
5451 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_DSS_EDP0</span></a> (ID = 151)</p>
5452 <p>Following is a mapping of Clocks IDs to function:</p>
5453 <table border="1" class="docutils">
5454 <colgroup>
5455 <col width="22%" />
5456 <col width="53%" />
5457 <col width="25%" />
5458 </colgroup>
5459 <thead valign="bottom">
5460 <tr class="row-odd"><th class="head">Clock ID</th>
5461 <th class="head">Name</th>
5462 <th class="head">Function</th>
5463 </tr>
5464 </thead>
5465 <tbody valign="top">
5466 <tr class="row-even"><td>0</td>
5467 <td>DEV_DSS_EDP0_PHY_LN1_TXFCLK</td>
5468 <td>Input clock</td>
5469 </tr>
5470 <tr class="row-odd"><td>1</td>
5471 <td>DEV_DSS_EDP0_DPI_2_CLK</td>
5472 <td>Input clock</td>
5473 </tr>
5474 <tr class="row-even"><td>2</td>
5475 <td>DEV_DSS_EDP0_PHY_LN2_TXFCLK</td>
5476 <td>Input clock</td>
5477 </tr>
5478 <tr class="row-odd"><td>3</td>
5479 <td>DEV_DSS_EDP0_PHY_LN0_RXCLK</td>
5480 <td>Input clock</td>
5481 </tr>
5482 <tr class="row-even"><td>4</td>
5483 <td>DEV_DSS_EDP0_PHY_LN2_TXMCLK</td>
5484 <td>Input clock</td>
5485 </tr>
5486 <tr class="row-odd"><td>5</td>
5487 <td>DEV_DSS_EDP0_PHY_LN0_RXFCLK</td>
5488 <td>Input clock</td>
5489 </tr>
5490 <tr class="row-even"><td>6</td>
5491 <td>DEV_DSS_EDP0_PHY_LN0_REFCLK</td>
5492 <td>Input clock</td>
5493 </tr>
5494 <tr class="row-odd"><td>7</td>
5495 <td>DEV_DSS_EDP0_PHY_LN1_RXCLK</td>
5496 <td>Input clock</td>
5497 </tr>
5498 <tr class="row-even"><td>8</td>
5499 <td>DEV_DSS_EDP0_PHY_LN2_RXFCLK</td>
5500 <td>Input clock</td>
5501 </tr>
5502 <tr class="row-odd"><td>9</td>
5503 <td>DEV_DSS_EDP0_DPI_4_CLK</td>
5504 <td>Input clock</td>
5505 </tr>
5506 <tr class="row-even"><td>10</td>
5507 <td>DEV_DSS_EDP0_DPI_2_2X_CLK</td>
5508 <td>Input clock</td>
5509 </tr>
5510 <tr class="row-odd"><td>11</td>
5511 <td>DEV_DSS_EDP0_PHY_LN0_TXFCLK</td>
5512 <td>Input clock</td>
5513 </tr>
5514 <tr class="row-even"><td>12</td>
5515 <td>DEV_DSS_EDP0_PHY_LN2_RXCLK</td>
5516 <td>Input clock</td>
5517 </tr>
5518 <tr class="row-odd"><td>13</td>
5519 <td>DEV_DSS_EDP0_PHY_LN2_REFCLK</td>
5520 <td>Input clock</td>
5521 </tr>
5522 <tr class="row-even"><td>14</td>
5523 <td>DEV_DSS_EDP0_PHY_LN3_REFCLK</td>
5524 <td>Input clock</td>
5525 </tr>
5526 <tr class="row-odd"><td>15</td>
5527 <td>DEV_DSS_EDP0_DPI_5_CLK</td>
5528 <td>Input clock</td>
5529 </tr>
5530 <tr class="row-even"><td>16</td>
5531 <td>DEV_DSS_EDP0_PHY_LN3_RXCLK</td>
5532 <td>Input clock</td>
5533 </tr>
5534 <tr class="row-odd"><td>17</td>
5535 <td>DEV_DSS_EDP0_PHY_LN1_REFCLK</td>
5536 <td>Input clock</td>
5537 </tr>
5538 <tr class="row-even"><td>18</td>
5539 <td>DEV_DSS_EDP0_AIF_I2S_CLK</td>
5540 <td>Input clock</td>
5541 </tr>
5542 <tr class="row-odd"><td>19</td>
5543 <td>DEV_DSS_EDP0_PHY_LN3_TXFCLK</td>
5544 <td>Input clock</td>
5545 </tr>
5546 <tr class="row-even"><td>20</td>
5547 <td>DEV_DSS_EDP0_DPI_3_CLK</td>
5548 <td>Input clock</td>
5549 </tr>
5550 <tr class="row-odd"><td>21</td>
5551 <td>DEV_DSS_EDP0_PHY_LN1_RXFCLK</td>
5552 <td>Input clock</td>
5553 </tr>
5554 <tr class="row-even"><td>22</td>
5555 <td>DEV_DSS_EDP0_PHY_LN1_TXMCLK</td>
5556 <td>Input clock</td>
5557 </tr>
5558 <tr class="row-odd"><td>23</td>
5559 <td>DEV_DSS_EDP0_PLL_CTRL_CLK</td>
5560 <td>Input clock</td>
5561 </tr>
5562 <tr class="row-even"><td>24</td>
5563 <td>DEV_DSS_EDP0_PHY_LN3_TXMCLK</td>
5564 <td>Input clock</td>
5565 </tr>
5566 <tr class="row-odd"><td>25</td>
5567 <td>DEV_DSS_EDP0_PHY_LN3_RXFCLK</td>
5568 <td>Input clock</td>
5569 </tr>
5570 <tr class="row-even"><td>26</td>
5571 <td>DEV_DSS_EDP0_PHY_LN0_TXMCLK</td>
5572 <td>Input clock</td>
5573 </tr>
5574 <tr class="row-odd"><td>27</td>
5575 <td>DEV_DSS_EDP0_PHY_LN2_TXCLK</td>
5576 <td>Output clock</td>
5577 </tr>
5578 <tr class="row-even"><td>28</td>
5579 <td>DEV_DSS_EDP0_PHY_LN3_TXCLK</td>
5580 <td>Output clock</td>
5581 </tr>
5582 <tr class="row-odd"><td>29</td>
5583 <td>DEV_DSS_EDP0_PHY_LN0_TXCLK</td>
5584 <td>Output clock</td>
5585 </tr>
5586 <tr class="row-even"><td>30</td>
5587 <td>DEV_DSS_EDP0_PHY_LN1_TXCLK</td>
5588 <td>Output clock</td>
5589 </tr>
5590 <tr class="row-odd"><td>36</td>
5591 <td>DEV_DSS_EDP0_DPTX_MOD_CLK</td>
5592 <td>Input clock</td>
5593 </tr>
5594 </tbody>
5595 </table>
5596 </div>
5597 <div class="section" id="clocks-for-ecap0-device">
5598 <span id="soc-doc-j721e-public-clks-ecap0"></span><h3>Clocks for ECAP0 Device<a class="headerlink" href="#clocks-for-ecap0-device" title="Permalink to this headline">¶</a></h3>
5599 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_ECAP0</span></a> (ID = 80)</p>
5600 <p>Following is a mapping of Clocks IDs to function:</p>
5601 <table border="1" class="docutils">
5602 <colgroup>
5603 <col width="27%" />
5604 <col width="44%" />
5605 <col width="29%" />
5606 </colgroup>
5607 <thead valign="bottom">
5608 <tr class="row-odd"><th class="head">Clock ID</th>
5609 <th class="head">Name</th>
5610 <th class="head">Function</th>
5611 </tr>
5612 </thead>
5613 <tbody valign="top">
5614 <tr class="row-even"><td>0</td>
5615 <td>DEV_ECAP0_VBUS_CLK</td>
5616 <td>Input clock</td>
5617 </tr>
5618 </tbody>
5619 </table>
5620 </div>
5621 <div class="section" id="clocks-for-ecap1-device">
5622 <span id="soc-doc-j721e-public-clks-ecap1"></span><h3>Clocks for ECAP1 Device<a class="headerlink" href="#clocks-for-ecap1-device" title="Permalink to this headline">¶</a></h3>
5623 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_ECAP1</span></a> (ID = 81)</p>
5624 <p>Following is a mapping of Clocks IDs to function:</p>
5625 <table border="1" class="docutils">
5626 <colgroup>
5627 <col width="27%" />
5628 <col width="44%" />
5629 <col width="29%" />
5630 </colgroup>
5631 <thead valign="bottom">
5632 <tr class="row-odd"><th class="head">Clock ID</th>
5633 <th class="head">Name</th>
5634 <th class="head">Function</th>
5635 </tr>
5636 </thead>
5637 <tbody valign="top">
5638 <tr class="row-even"><td>0</td>
5639 <td>DEV_ECAP1_VBUS_CLK</td>
5640 <td>Input clock</td>
5641 </tr>
5642 </tbody>
5643 </table>
5644 </div>
5645 <div class="section" id="clocks-for-ecap2-device">
5646 <span id="soc-doc-j721e-public-clks-ecap2"></span><h3>Clocks for ECAP2 Device<a class="headerlink" href="#clocks-for-ecap2-device" title="Permalink to this headline">¶</a></h3>
5647 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_ECAP2</span></a> (ID = 82)</p>
5648 <p>Following is a mapping of Clocks IDs to function:</p>
5649 <table border="1" class="docutils">
5650 <colgroup>
5651 <col width="27%" />
5652 <col width="44%" />
5653 <col width="29%" />
5654 </colgroup>
5655 <thead valign="bottom">
5656 <tr class="row-odd"><th class="head">Clock ID</th>
5657 <th class="head">Name</th>
5658 <th class="head">Function</th>
5659 </tr>
5660 </thead>
5661 <tbody valign="top">
5662 <tr class="row-even"><td>0</td>
5663 <td>DEV_ECAP2_VBUS_CLK</td>
5664 <td>Input clock</td>
5665 </tr>
5666 </tbody>
5667 </table>
5668 </div>
5669 <div class="section" id="clocks-for-ehrpwm0-device">
5670 <span id="soc-doc-j721e-public-clks-ehrpwm0"></span><h3>Clocks for EHRPWM0 Device<a class="headerlink" href="#clocks-for-ehrpwm0-device" title="Permalink to this headline">¶</a></h3>
5671 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_EHRPWM0</span></a> (ID = 83)</p>
5672 <p>Following is a mapping of Clocks IDs to function:</p>
5673 <table border="1" class="docutils">
5674 <colgroup>
5675 <col width="25%" />
5676 <col width="48%" />
5677 <col width="27%" />
5678 </colgroup>
5679 <thead valign="bottom">
5680 <tr class="row-odd"><th class="head">Clock ID</th>
5681 <th class="head">Name</th>
5682 <th class="head">Function</th>
5683 </tr>
5684 </thead>
5685 <tbody valign="top">
5686 <tr class="row-even"><td>0</td>
5687 <td>DEV_EHRPWM0_VBUSP_CLK</td>
5688 <td>Input clock</td>
5689 </tr>
5690 </tbody>
5691 </table>
5692 </div>
5693 <div class="section" id="clocks-for-ehrpwm1-device">
5694 <span id="soc-doc-j721e-public-clks-ehrpwm1"></span><h3>Clocks for EHRPWM1 Device<a class="headerlink" href="#clocks-for-ehrpwm1-device" title="Permalink to this headline">¶</a></h3>
5695 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_EHRPWM1</span></a> (ID = 84)</p>
5696 <p>Following is a mapping of Clocks IDs to function:</p>
5697 <table border="1" class="docutils">
5698 <colgroup>
5699 <col width="25%" />
5700 <col width="48%" />
5701 <col width="27%" />
5702 </colgroup>
5703 <thead valign="bottom">
5704 <tr class="row-odd"><th class="head">Clock ID</th>
5705 <th class="head">Name</th>
5706 <th class="head">Function</th>
5707 </tr>
5708 </thead>
5709 <tbody valign="top">
5710 <tr class="row-even"><td>0</td>
5711 <td>DEV_EHRPWM1_VBUSP_CLK</td>
5712 <td>Input clock</td>
5713 </tr>
5714 </tbody>
5715 </table>
5716 </div>
5717 <div class="section" id="clocks-for-ehrpwm2-device">
5718 <span id="soc-doc-j721e-public-clks-ehrpwm2"></span><h3>Clocks for EHRPWM2 Device<a class="headerlink" href="#clocks-for-ehrpwm2-device" title="Permalink to this headline">¶</a></h3>
5719 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_EHRPWM2</span></a> (ID = 85)</p>
5720 <p>Following is a mapping of Clocks IDs to function:</p>
5721 <table border="1" class="docutils">
5722 <colgroup>
5723 <col width="25%" />
5724 <col width="48%" />
5725 <col width="27%" />
5726 </colgroup>
5727 <thead valign="bottom">
5728 <tr class="row-odd"><th class="head">Clock ID</th>
5729 <th class="head">Name</th>
5730 <th class="head">Function</th>
5731 </tr>
5732 </thead>
5733 <tbody valign="top">
5734 <tr class="row-even"><td>0</td>
5735 <td>DEV_EHRPWM2_VBUSP_CLK</td>
5736 <td>Input clock</td>
5737 </tr>
5738 </tbody>
5739 </table>
5740 </div>
5741 <div class="section" id="clocks-for-ehrpwm3-device">
5742 <span id="soc-doc-j721e-public-clks-ehrpwm3"></span><h3>Clocks for EHRPWM3 Device<a class="headerlink" href="#clocks-for-ehrpwm3-device" title="Permalink to this headline">¶</a></h3>
5743 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_EHRPWM3</span></a> (ID = 86)</p>
5744 <p>Following is a mapping of Clocks IDs to function:</p>
5745 <table border="1" class="docutils">
5746 <colgroup>
5747 <col width="25%" />
5748 <col width="48%" />
5749 <col width="27%" />
5750 </colgroup>
5751 <thead valign="bottom">
5752 <tr class="row-odd"><th class="head">Clock ID</th>
5753 <th class="head">Name</th>
5754 <th class="head">Function</th>
5755 </tr>
5756 </thead>
5757 <tbody valign="top">
5758 <tr class="row-even"><td>0</td>
5759 <td>DEV_EHRPWM3_VBUSP_CLK</td>
5760 <td>Input clock</td>
5761 </tr>
5762 </tbody>
5763 </table>
5764 </div>
5765 <div class="section" id="clocks-for-ehrpwm4-device">
5766 <span id="soc-doc-j721e-public-clks-ehrpwm4"></span><h3>Clocks for EHRPWM4 Device<a class="headerlink" href="#clocks-for-ehrpwm4-device" title="Permalink to this headline">¶</a></h3>
5767 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_EHRPWM4</span></a> (ID = 87)</p>
5768 <p>Following is a mapping of Clocks IDs to function:</p>
5769 <table border="1" class="docutils">
5770 <colgroup>
5771 <col width="25%" />
5772 <col width="48%" />
5773 <col width="27%" />
5774 </colgroup>
5775 <thead valign="bottom">
5776 <tr class="row-odd"><th class="head">Clock ID</th>
5777 <th class="head">Name</th>
5778 <th class="head">Function</th>
5779 </tr>
5780 </thead>
5781 <tbody valign="top">
5782 <tr class="row-even"><td>0</td>
5783 <td>DEV_EHRPWM4_VBUSP_CLK</td>
5784 <td>Input clock</td>
5785 </tr>
5786 </tbody>
5787 </table>
5788 </div>
5789 <div class="section" id="clocks-for-ehrpwm5-device">
5790 <span id="soc-doc-j721e-public-clks-ehrpwm5"></span><h3>Clocks for EHRPWM5 Device<a class="headerlink" href="#clocks-for-ehrpwm5-device" title="Permalink to this headline">¶</a></h3>
5791 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_EHRPWM5</span></a> (ID = 88)</p>
5792 <p>Following is a mapping of Clocks IDs to function:</p>
5793 <table border="1" class="docutils">
5794 <colgroup>
5795 <col width="25%" />
5796 <col width="48%" />
5797 <col width="27%" />
5798 </colgroup>
5799 <thead valign="bottom">
5800 <tr class="row-odd"><th class="head">Clock ID</th>
5801 <th class="head">Name</th>
5802 <th class="head">Function</th>
5803 </tr>
5804 </thead>
5805 <tbody valign="top">
5806 <tr class="row-even"><td>0</td>
5807 <td>DEV_EHRPWM5_VBUSP_CLK</td>
5808 <td>Input clock</td>
5809 </tr>
5810 </tbody>
5811 </table>
5812 </div>
5813 <div class="section" id="clocks-for-elm0-device">
5814 <span id="soc-doc-j721e-public-clks-elm0"></span><h3>Clocks for ELM0 Device<a class="headerlink" href="#clocks-for-elm0-device" title="Permalink to this headline">¶</a></h3>
5815 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_ELM0</span></a> (ID = 89)</p>
5816 <p>Following is a mapping of Clocks IDs to function:</p>
5817 <table border="1" class="docutils">
5818 <colgroup>
5819 <col width="27%" />
5820 <col width="44%" />
5821 <col width="29%" />
5822 </colgroup>
5823 <thead valign="bottom">
5824 <tr class="row-odd"><th class="head">Clock ID</th>
5825 <th class="head">Name</th>
5826 <th class="head">Function</th>
5827 </tr>
5828 </thead>
5829 <tbody valign="top">
5830 <tr class="row-even"><td>0</td>
5831 <td>DEV_ELM0_VBUSP_CLK</td>
5832 <td>Input clock</td>
5833 </tr>
5834 </tbody>
5835 </table>
5836 </div>
5837 <div class="section" id="clocks-for-emif-data-0-vd-device">
5838 <span id="soc-doc-j721e-public-clks-emif-data-0-vd"></span><h3>Clocks for EMIF_DATA_0_VD Device<a class="headerlink" href="#clocks-for-emif-data-0-vd-device" title="Permalink to this headline">¶</a></h3>
5839 <p><strong>This device has no defined clocks.</strong></p>
5840 </div>
5841 <div class="section" id="clocks-for-encoder0-device">
5842 <span id="soc-doc-j721e-public-clks-encoder0"></span><h3>Clocks for ENCODER0 Device<a class="headerlink" href="#clocks-for-encoder0-device" title="Permalink to this headline">¶</a></h3>
5843 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_ENCODER0</span></a> (ID = 153)</p>
5844 <p>Following is a mapping of Clocks IDs to function:</p>
5845 <table border="1" class="docutils">
5846 <colgroup>
5847 <col width="26%" />
5848 <col width="47%" />
5849 <col width="28%" />
5850 </colgroup>
5851 <thead valign="bottom">
5852 <tr class="row-odd"><th class="head">Clock ID</th>
5853 <th class="head">Name</th>
5854 <th class="head">Function</th>
5855 </tr>
5856 </thead>
5857 <tbody valign="top">
5858 <tr class="row-even"><td>0</td>
5859 <td>DEV_ENCODER0_SYS_CLK</td>
5860 <td>Input clock</td>
5861 </tr>
5862 </tbody>
5863 </table>
5864 </div>
5865 <div class="section" id="clocks-for-eqep0-device">
5866 <span id="soc-doc-j721e-public-clks-eqep0"></span><h3>Clocks for EQEP0 Device<a class="headerlink" href="#clocks-for-eqep0-device" title="Permalink to this headline">¶</a></h3>
5867 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_EQEP0</span></a> (ID = 94)</p>
5868 <p>Following is a mapping of Clocks IDs to function:</p>
5869 <table border="1" class="docutils">
5870 <colgroup>
5871 <col width="27%" />
5872 <col width="44%" />
5873 <col width="29%" />
5874 </colgroup>
5875 <thead valign="bottom">
5876 <tr class="row-odd"><th class="head">Clock ID</th>
5877 <th class="head">Name</th>
5878 <th class="head">Function</th>
5879 </tr>
5880 </thead>
5881 <tbody valign="top">
5882 <tr class="row-even"><td>0</td>
5883 <td>DEV_EQEP0_VBUS_CLK</td>
5884 <td>Input clock</td>
5885 </tr>
5886 </tbody>
5887 </table>
5888 </div>
5889 <div class="section" id="clocks-for-eqep1-device">
5890 <span id="soc-doc-j721e-public-clks-eqep1"></span><h3>Clocks for EQEP1 Device<a class="headerlink" href="#clocks-for-eqep1-device" title="Permalink to this headline">¶</a></h3>
5891 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_EQEP1</span></a> (ID = 95)</p>
5892 <p>Following is a mapping of Clocks IDs to function:</p>
5893 <table border="1" class="docutils">
5894 <colgroup>
5895 <col width="27%" />
5896 <col width="44%" />
5897 <col width="29%" />
5898 </colgroup>
5899 <thead valign="bottom">
5900 <tr class="row-odd"><th class="head">Clock ID</th>
5901 <th class="head">Name</th>
5902 <th class="head">Function</th>
5903 </tr>
5904 </thead>
5905 <tbody valign="top">
5906 <tr class="row-even"><td>0</td>
5907 <td>DEV_EQEP1_VBUS_CLK</td>
5908 <td>Input clock</td>
5909 </tr>
5910 </tbody>
5911 </table>
5912 </div>
5913 <div class="section" id="clocks-for-eqep2-device">
5914 <span id="soc-doc-j721e-public-clks-eqep2"></span><h3>Clocks for EQEP2 Device<a class="headerlink" href="#clocks-for-eqep2-device" title="Permalink to this headline">¶</a></h3>
5915 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_EQEP2</span></a> (ID = 96)</p>
5916 <p>Following is a mapping of Clocks IDs to function:</p>
5917 <table border="1" class="docutils">
5918 <colgroup>
5919 <col width="27%" />
5920 <col width="44%" />
5921 <col width="29%" />
5922 </colgroup>
5923 <thead valign="bottom">
5924 <tr class="row-odd"><th class="head">Clock ID</th>
5925 <th class="head">Name</th>
5926 <th class="head">Function</th>
5927 </tr>
5928 </thead>
5929 <tbody valign="top">
5930 <tr class="row-even"><td>0</td>
5931 <td>DEV_EQEP2_VBUS_CLK</td>
5932 <td>Input clock</td>
5933 </tr>
5934 </tbody>
5935 </table>
5936 </div>
5937 <div class="section" id="clocks-for-esm0-device">
5938 <span id="soc-doc-j721e-public-clks-esm0"></span><h3>Clocks for ESM0 Device<a class="headerlink" href="#clocks-for-esm0-device" title="Permalink to this headline">¶</a></h3>
5939 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_ESM0</span></a> (ID = 97)</p>
5940 <p>Following is a mapping of Clocks IDs to function:</p>
5941 <table border="1" class="docutils">
5942 <colgroup>
5943 <col width="31%" />
5944 <col width="36%" />
5945 <col width="33%" />
5946 </colgroup>
5947 <thead valign="bottom">
5948 <tr class="row-odd"><th class="head">Clock ID</th>
5949 <th class="head">Name</th>
5950 <th class="head">Function</th>
5951 </tr>
5952 </thead>
5953 <tbody valign="top">
5954 <tr class="row-even"><td>0</td>
5955 <td>DEV_ESM0_CLK</td>
5956 <td>Input clock</td>
5957 </tr>
5958 </tbody>
5959 </table>
5960 </div>
5961 <div class="section" id="clocks-for-gpio0-device">
5962 <span id="soc-doc-j721e-public-clks-gpio0"></span><h3>Clocks for GPIO0 Device<a class="headerlink" href="#clocks-for-gpio0-device" title="Permalink to this headline">¶</a></h3>
5963 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_GPIO0</span></a> (ID = 105)</p>
5964 <p>Following is a mapping of Clocks IDs to function:</p>
5965 <table border="1" class="docutils">
5966 <colgroup>
5967 <col width="27%" />
5968 <col width="43%" />
5969 <col width="30%" />
5970 </colgroup>
5971 <thead valign="bottom">
5972 <tr class="row-odd"><th class="head">Clock ID</th>
5973 <th class="head">Name</th>
5974 <th class="head">Function</th>
5975 </tr>
5976 </thead>
5977 <tbody valign="top">
5978 <tr class="row-even"><td>0</td>
5979 <td>DEV_GPIO0_MMR_CLK</td>
5980 <td>Input clock</td>
5981 </tr>
5982 </tbody>
5983 </table>
5984 </div>
5985 <div class="section" id="clocks-for-gpio1-device">
5986 <span id="soc-doc-j721e-public-clks-gpio1"></span><h3>Clocks for GPIO1 Device<a class="headerlink" href="#clocks-for-gpio1-device" title="Permalink to this headline">¶</a></h3>
5987 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_GPIO1</span></a> (ID = 106)</p>
5988 <p>Following is a mapping of Clocks IDs to function:</p>
5989 <table border="1" class="docutils">
5990 <colgroup>
5991 <col width="27%" />
5992 <col width="43%" />
5993 <col width="30%" />
5994 </colgroup>
5995 <thead valign="bottom">
5996 <tr class="row-odd"><th class="head">Clock ID</th>
5997 <th class="head">Name</th>
5998 <th class="head">Function</th>
5999 </tr>
6000 </thead>
6001 <tbody valign="top">
6002 <tr class="row-even"><td>0</td>
6003 <td>DEV_GPIO1_MMR_CLK</td>
6004 <td>Input clock</td>
6005 </tr>
6006 </tbody>
6007 </table>
6008 </div>
6009 <div class="section" id="clocks-for-gpio2-device">
6010 <span id="soc-doc-j721e-public-clks-gpio2"></span><h3>Clocks for GPIO2 Device<a class="headerlink" href="#clocks-for-gpio2-device" title="Permalink to this headline">¶</a></h3>
6011 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_GPIO2</span></a> (ID = 107)</p>
6012 <p>Following is a mapping of Clocks IDs to function:</p>
6013 <table border="1" class="docutils">
6014 <colgroup>
6015 <col width="27%" />
6016 <col width="43%" />
6017 <col width="30%" />
6018 </colgroup>
6019 <thead valign="bottom">
6020 <tr class="row-odd"><th class="head">Clock ID</th>
6021 <th class="head">Name</th>
6022 <th class="head">Function</th>
6023 </tr>
6024 </thead>
6025 <tbody valign="top">
6026 <tr class="row-even"><td>0</td>
6027 <td>DEV_GPIO2_MMR_CLK</td>
6028 <td>Input clock</td>
6029 </tr>
6030 </tbody>
6031 </table>
6032 </div>
6033 <div class="section" id="clocks-for-gpio3-device">
6034 <span id="soc-doc-j721e-public-clks-gpio3"></span><h3>Clocks for GPIO3 Device<a class="headerlink" href="#clocks-for-gpio3-device" title="Permalink to this headline">¶</a></h3>
6035 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_GPIO3</span></a> (ID = 108)</p>
6036 <p>Following is a mapping of Clocks IDs to function:</p>
6037 <table border="1" class="docutils">
6038 <colgroup>
6039 <col width="27%" />
6040 <col width="43%" />
6041 <col width="30%" />
6042 </colgroup>
6043 <thead valign="bottom">
6044 <tr class="row-odd"><th class="head">Clock ID</th>
6045 <th class="head">Name</th>
6046 <th class="head">Function</th>
6047 </tr>
6048 </thead>
6049 <tbody valign="top">
6050 <tr class="row-even"><td>0</td>
6051 <td>DEV_GPIO3_MMR_CLK</td>
6052 <td>Input clock</td>
6053 </tr>
6054 </tbody>
6055 </table>
6056 </div>
6057 <div class="section" id="clocks-for-gpio4-device">
6058 <span id="soc-doc-j721e-public-clks-gpio4"></span><h3>Clocks for GPIO4 Device<a class="headerlink" href="#clocks-for-gpio4-device" title="Permalink to this headline">¶</a></h3>
6059 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_GPIO4</span></a> (ID = 109)</p>
6060 <p>Following is a mapping of Clocks IDs to function:</p>
6061 <table border="1" class="docutils">
6062 <colgroup>
6063 <col width="27%" />
6064 <col width="43%" />
6065 <col width="30%" />
6066 </colgroup>
6067 <thead valign="bottom">
6068 <tr class="row-odd"><th class="head">Clock ID</th>
6069 <th class="head">Name</th>
6070 <th class="head">Function</th>
6071 </tr>
6072 </thead>
6073 <tbody valign="top">
6074 <tr class="row-even"><td>0</td>
6075 <td>DEV_GPIO4_MMR_CLK</td>
6076 <td>Input clock</td>
6077 </tr>
6078 </tbody>
6079 </table>
6080 </div>
6081 <div class="section" id="clocks-for-gpio5-device">
6082 <span id="soc-doc-j721e-public-clks-gpio5"></span><h3>Clocks for GPIO5 Device<a class="headerlink" href="#clocks-for-gpio5-device" title="Permalink to this headline">¶</a></h3>
6083 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_GPIO5</span></a> (ID = 110)</p>
6084 <p>Following is a mapping of Clocks IDs to function:</p>
6085 <table border="1" class="docutils">
6086 <colgroup>
6087 <col width="27%" />
6088 <col width="43%" />
6089 <col width="30%" />
6090 </colgroup>
6091 <thead valign="bottom">
6092 <tr class="row-odd"><th class="head">Clock ID</th>
6093 <th class="head">Name</th>
6094 <th class="head">Function</th>
6095 </tr>
6096 </thead>
6097 <tbody valign="top">
6098 <tr class="row-even"><td>0</td>
6099 <td>DEV_GPIO5_MMR_CLK</td>
6100 <td>Input clock</td>
6101 </tr>
6102 </tbody>
6103 </table>
6104 </div>
6105 <div class="section" id="clocks-for-gpio6-device">
6106 <span id="soc-doc-j721e-public-clks-gpio6"></span><h3>Clocks for GPIO6 Device<a class="headerlink" href="#clocks-for-gpio6-device" title="Permalink to this headline">¶</a></h3>
6107 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_GPIO6</span></a> (ID = 111)</p>
6108 <p>Following is a mapping of Clocks IDs to function:</p>
6109 <table border="1" class="docutils">
6110 <colgroup>
6111 <col width="27%" />
6112 <col width="43%" />
6113 <col width="30%" />
6114 </colgroup>
6115 <thead valign="bottom">
6116 <tr class="row-odd"><th class="head">Clock ID</th>
6117 <th class="head">Name</th>
6118 <th class="head">Function</th>
6119 </tr>
6120 </thead>
6121 <tbody valign="top">
6122 <tr class="row-even"><td>0</td>
6123 <td>DEV_GPIO6_MMR_CLK</td>
6124 <td>Input clock</td>
6125 </tr>
6126 </tbody>
6127 </table>
6128 </div>
6129 <div class="section" id="clocks-for-gpio7-device">
6130 <span id="soc-doc-j721e-public-clks-gpio7"></span><h3>Clocks for GPIO7 Device<a class="headerlink" href="#clocks-for-gpio7-device" title="Permalink to this headline">¶</a></h3>
6131 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_GPIO7</span></a> (ID = 112)</p>
6132 <p>Following is a mapping of Clocks IDs to function:</p>
6133 <table border="1" class="docutils">
6134 <colgroup>
6135 <col width="27%" />
6136 <col width="43%" />
6137 <col width="30%" />
6138 </colgroup>
6139 <thead valign="bottom">
6140 <tr class="row-odd"><th class="head">Clock ID</th>
6141 <th class="head">Name</th>
6142 <th class="head">Function</th>
6143 </tr>
6144 </thead>
6145 <tbody valign="top">
6146 <tr class="row-even"><td>0</td>
6147 <td>DEV_GPIO7_MMR_CLK</td>
6148 <td>Input clock</td>
6149 </tr>
6150 </tbody>
6151 </table>
6152 </div>
6153 <div class="section" id="clocks-for-gpiomux-intrtr0-device">
6154 <span id="soc-doc-j721e-public-clks-gpiomux-intrtr0"></span><h3>Clocks for GPIOMUX_INTRTR0 Device<a class="headerlink" href="#clocks-for-gpiomux-intrtr0-device" title="Permalink to this headline">¶</a></h3>
6155 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_GPIOMUX_INTRTR0</span></a> (ID = 131)</p>
6156 <p>Following is a mapping of Clocks IDs to function:</p>
6157 <table border="1" class="docutils">
6158 <colgroup>
6159 <col width="22%" />
6160 <col width="55%" />
6161 <col width="24%" />
6162 </colgroup>
6163 <thead valign="bottom">
6164 <tr class="row-odd"><th class="head">Clock ID</th>
6165 <th class="head">Name</th>
6166 <th class="head">Function</th>
6167 </tr>
6168 </thead>
6169 <tbody valign="top">
6170 <tr class="row-even"><td>0</td>
6171 <td>DEV_GPIOMUX_INTRTR0_INTR_CLK</td>
6172 <td>Input clock</td>
6173 </tr>
6174 </tbody>
6175 </table>
6176 </div>
6177 <div class="section" id="clocks-for-gpmc0-device">
6178 <span id="soc-doc-j721e-public-clks-gpmc0"></span><h3>Clocks for GPMC0 Device<a class="headerlink" href="#clocks-for-gpmc0-device" title="Permalink to this headline">¶</a></h3>
6179 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_GPMC0</span></a> (ID = 115)</p>
6180 <p>Following is a mapping of Clocks IDs to function:</p>
6181 <table border="1" class="docutils">
6182 <colgroup>
6183 <col width="9%" />
6184 <col width="53%" />
6185 <col width="37%" />
6186 </colgroup>
6187 <thead valign="bottom">
6188 <tr class="row-odd"><th class="head">Clock ID</th>
6189 <th class="head">Name</th>
6190 <th class="head">Function</th>
6191 </tr>
6192 </thead>
6193 <tbody valign="top">
6194 <tr class="row-even"><td>0</td>
6195 <td>DEV_GPMC0_PI_GPMC_RET_CLK</td>
6196 <td>Input clock</td>
6197 </tr>
6198 <tr class="row-odd"><td>1</td>
6199 <td>DEV_GPMC0_VBUSP_CLK</td>
6200 <td>Input clock</td>
6201 </tr>
6202 <tr class="row-even"><td>2</td>
6203 <td>DEV_GPMC0_FUNC_CLK</td>
6204 <td>Input muxed clock</td>
6205 </tr>
6206 <tr class="row-odd"><td>3</td>
6207 <td>DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK</td>
6208 <td>Parent input clock option to DEV_GPMC0_FUNC_CLK</td>
6209 </tr>
6210 <tr class="row-even"><td>4</td>
6211 <td>DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6</td>
6212 <td>Parent input clock option to DEV_GPMC0_FUNC_CLK</td>
6213 </tr>
6214 <tr class="row-odd"><td>5</td>
6215 <td>DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4</td>
6216 <td>Parent input clock option to DEV_GPMC0_FUNC_CLK</td>
6217 </tr>
6218 <tr class="row-even"><td>6</td>
6219 <td>DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4</td>
6220 <td>Parent input clock option to DEV_GPMC0_FUNC_CLK</td>
6221 </tr>
6222 <tr class="row-odd"><td>7</td>
6223 <td>DEV_GPMC0_PO_GPMC_DEV_CLK</td>
6224 <td>Output clock</td>
6225 </tr>
6226 </tbody>
6227 </table>
6228 </div>
6229 <div class="section" id="clocks-for-gpu0-device">
6230 <span id="soc-doc-j721e-public-clks-gpu0"></span><h3>Clocks for GPU0 Device<a class="headerlink" href="#clocks-for-gpu0-device" title="Permalink to this headline">¶</a></h3>
6231 <p><strong>This device has no defined clocks.</strong></p>
6232 </div>
6233 <div class="section" id="clocks-for-gpu0-dft-pbist-0-device">
6234 <span id="soc-doc-j721e-public-clks-gpu0-dft-pbist-0"></span><h3>Clocks for GPU0_DFT_PBIST_0 Device<a class="headerlink" href="#clocks-for-gpu0-dft-pbist-0-device" title="Permalink to this headline">¶</a></h3>
6235 <p><strong>This device has no defined clocks.</strong></p>
6236 </div>
6237 <div class="section" id="clocks-for-gpu0-gpucore-0-device">
6238 <span id="soc-doc-j721e-public-clks-gpu0-gpucore-0"></span><h3>Clocks for GPU0_GPUCORE_0 Device<a class="headerlink" href="#clocks-for-gpu0-gpucore-0-device" title="Permalink to this headline">¶</a></h3>
6239 <p><strong>This device has no defined clocks.</strong></p>
6240 </div>
6241 <div class="section" id="clocks-for-gpu0-gpu-0-device">
6242 <span id="soc-doc-j721e-public-clks-gpu0-gpu-0"></span><h3>Clocks for GPU0_GPU_0 Device<a class="headerlink" href="#clocks-for-gpu0-gpu-0-device" title="Permalink to this headline">¶</a></h3>
6243 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_GPU0_GPU_0</span></a> (ID = 125)</p>
6244 <p>Following is a mapping of Clocks IDs to function:</p>
6245 <table border="1" class="docutils">
6246 <colgroup>
6247 <col width="23%" />
6248 <col width="53%" />
6249 <col width="25%" />
6250 </colgroup>
6251 <thead valign="bottom">
6252 <tr class="row-odd"><th class="head">Clock ID</th>
6253 <th class="head">Name</th>
6254 <th class="head">Function</th>
6255 </tr>
6256 </thead>
6257 <tbody valign="top">
6258 <tr class="row-even"><td>0</td>
6259 <td>DEV_GPU0_GPU_0_GPU_PLL_CLK</td>
6260 <td>Input clock</td>
6261 </tr>
6262 </tbody>
6263 </table>
6264 </div>
6265 <div class="section" id="clocks-for-gtc0-device">
6266 <span id="soc-doc-j721e-public-clks-gtc0"></span><h3>Clocks for GTC0 Device<a class="headerlink" href="#clocks-for-gtc0-device" title="Permalink to this headline">¶</a></h3>
6267 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_GTC0</span></a> (ID = 61)</p>
6268 <p>Following is a mapping of Clocks IDs to function:</p>
6269 <table border="1" class="docutils">
6270 <colgroup>
6271 <col width="10%" />
6272 <col width="53%" />
6273 <col width="37%" />
6274 </colgroup>
6275 <thead valign="bottom">
6276 <tr class="row-odd"><th class="head">Clock ID</th>
6277 <th class="head">Name</th>
6278 <th class="head">Function</th>
6279 </tr>
6280 </thead>
6281 <tbody valign="top">
6282 <tr class="row-even"><td>0</td>
6283 <td>DEV_GTC0_VBUSP_CLK</td>
6284 <td>Input clock</td>
6285 </tr>
6286 <tr class="row-odd"><td>1</td>
6287 <td>DEV_GTC0_GTC_CLK</td>
6288 <td>Input muxed clock</td>
6289 </tr>
6290 <tr class="row-even"><td>2</td>
6291 <td>DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
6292 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6293 </tr>
6294 <tr class="row-odd"><td>3</td>
6295 <td>DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
6296 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6297 </tr>
6298 <tr class="row-even"><td>4</td>
6299 <td>DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
6300 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6301 </tr>
6302 <tr class="row-odd"><td>5</td>
6303 <td>DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
6304 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6305 </tr>
6306 <tr class="row-even"><td>6</td>
6307 <td>DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6308 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6309 </tr>
6310 <tr class="row-odd"><td>7</td>
6311 <td>DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
6312 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6313 </tr>
6314 <tr class="row-even"><td>8</td>
6315 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK</td>
6316 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6317 </tr>
6318 <tr class="row-odd"><td>9</td>
6319 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK</td>
6320 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6321 </tr>
6322 <tr class="row-even"><td>10</td>
6323 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK</td>
6324 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6325 </tr>
6326 <tr class="row-odd"><td>11</td>
6327 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK</td>
6328 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6329 </tr>
6330 <tr class="row-even"><td>12</td>
6331 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK</td>
6332 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6333 </tr>
6334 <tr class="row-odd"><td>13</td>
6335 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK</td>
6336 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6337 </tr>
6338 <tr class="row-even"><td>14</td>
6339 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK</td>
6340 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6341 </tr>
6342 <tr class="row-odd"><td>15</td>
6343 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK</td>
6344 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6345 </tr>
6346 <tr class="row-even"><td>16</td>
6347 <td>DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
6348 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6349 </tr>
6350 <tr class="row-odd"><td>17</td>
6351 <td>DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
6352 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
6353 </tr>
6354 </tbody>
6355 </table>
6356 </div>
6357 <div class="section" id="clocks-for-i2c0-device">
6358 <span id="soc-doc-j721e-public-clks-i2c0"></span><h3>Clocks for I2C0 Device<a class="headerlink" href="#clocks-for-i2c0-device" title="Permalink to this headline">¶</a></h3>
6359 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_I2C0</span></a> (ID = 187)</p>
6360 <p>Following is a mapping of Clocks IDs to function:</p>
6361 <table border="1" class="docutils">
6362 <colgroup>
6363 <col width="27%" />
6364 <col width="44%" />
6365 <col width="29%" />
6366 </colgroup>
6367 <thead valign="bottom">
6368 <tr class="row-odd"><th class="head">Clock ID</th>
6369 <th class="head">Name</th>
6370 <th class="head">Function</th>
6371 </tr>
6372 </thead>
6373 <tbody valign="top">
6374 <tr class="row-even"><td>0</td>
6375 <td>DEV_I2C0_PISYS_CLK</td>
6376 <td>Input clock</td>
6377 </tr>
6378 <tr class="row-odd"><td>1</td>
6379 <td>DEV_I2C0_PISCL</td>
6380 <td>Input clock</td>
6381 </tr>
6382 <tr class="row-even"><td>2</td>
6383 <td>DEV_I2C0_CLK</td>
6384 <td>Input clock</td>
6385 </tr>
6386 </tbody>
6387 </table>
6388 </div>
6389 <div class="section" id="clocks-for-i2c1-device">
6390 <span id="soc-doc-j721e-public-clks-i2c1"></span><h3>Clocks for I2C1 Device<a class="headerlink" href="#clocks-for-i2c1-device" title="Permalink to this headline">¶</a></h3>
6391 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_I2C1</span></a> (ID = 188)</p>
6392 <p>Following is a mapping of Clocks IDs to function:</p>
6393 <table border="1" class="docutils">
6394 <colgroup>
6395 <col width="27%" />
6396 <col width="44%" />
6397 <col width="29%" />
6398 </colgroup>
6399 <thead valign="bottom">
6400 <tr class="row-odd"><th class="head">Clock ID</th>
6401 <th class="head">Name</th>
6402 <th class="head">Function</th>
6403 </tr>
6404 </thead>
6405 <tbody valign="top">
6406 <tr class="row-even"><td>0</td>
6407 <td>DEV_I2C1_PISYS_CLK</td>
6408 <td>Input clock</td>
6409 </tr>
6410 <tr class="row-odd"><td>1</td>
6411 <td>DEV_I2C1_PISCL</td>
6412 <td>Input clock</td>
6413 </tr>
6414 <tr class="row-even"><td>2</td>
6415 <td>DEV_I2C1_CLK</td>
6416 <td>Input clock</td>
6417 </tr>
6418 </tbody>
6419 </table>
6420 </div>
6421 <div class="section" id="clocks-for-i2c2-device">
6422 <span id="soc-doc-j721e-public-clks-i2c2"></span><h3>Clocks for I2C2 Device<a class="headerlink" href="#clocks-for-i2c2-device" title="Permalink to this headline">¶</a></h3>
6423 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_I2C2</span></a> (ID = 189)</p>
6424 <p>Following is a mapping of Clocks IDs to function:</p>
6425 <table border="1" class="docutils">
6426 <colgroup>
6427 <col width="27%" />
6428 <col width="44%" />
6429 <col width="29%" />
6430 </colgroup>
6431 <thead valign="bottom">
6432 <tr class="row-odd"><th class="head">Clock ID</th>
6433 <th class="head">Name</th>
6434 <th class="head">Function</th>
6435 </tr>
6436 </thead>
6437 <tbody valign="top">
6438 <tr class="row-even"><td>0</td>
6439 <td>DEV_I2C2_PISYS_CLK</td>
6440 <td>Input clock</td>
6441 </tr>
6442 <tr class="row-odd"><td>1</td>
6443 <td>DEV_I2C2_PISCL</td>
6444 <td>Input clock</td>
6445 </tr>
6446 <tr class="row-even"><td>2</td>
6447 <td>DEV_I2C2_CLK</td>
6448 <td>Input clock</td>
6449 </tr>
6450 </tbody>
6451 </table>
6452 </div>
6453 <div class="section" id="clocks-for-i2c3-device">
6454 <span id="soc-doc-j721e-public-clks-i2c3"></span><h3>Clocks for I2C3 Device<a class="headerlink" href="#clocks-for-i2c3-device" title="Permalink to this headline">¶</a></h3>
6455 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_I2C3</span></a> (ID = 190)</p>
6456 <p>Following is a mapping of Clocks IDs to function:</p>
6457 <table border="1" class="docutils">
6458 <colgroup>
6459 <col width="27%" />
6460 <col width="44%" />
6461 <col width="29%" />
6462 </colgroup>
6463 <thead valign="bottom">
6464 <tr class="row-odd"><th class="head">Clock ID</th>
6465 <th class="head">Name</th>
6466 <th class="head">Function</th>
6467 </tr>
6468 </thead>
6469 <tbody valign="top">
6470 <tr class="row-even"><td>0</td>
6471 <td>DEV_I2C3_PISYS_CLK</td>
6472 <td>Input clock</td>
6473 </tr>
6474 <tr class="row-odd"><td>1</td>
6475 <td>DEV_I2C3_PISCL</td>
6476 <td>Input clock</td>
6477 </tr>
6478 <tr class="row-even"><td>2</td>
6479 <td>DEV_I2C3_CLK</td>
6480 <td>Input clock</td>
6481 </tr>
6482 </tbody>
6483 </table>
6484 </div>
6485 <div class="section" id="clocks-for-i2c4-device">
6486 <span id="soc-doc-j721e-public-clks-i2c4"></span><h3>Clocks for I2C4 Device<a class="headerlink" href="#clocks-for-i2c4-device" title="Permalink to this headline">¶</a></h3>
6487 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_I2C4</span></a> (ID = 191)</p>
6488 <p>Following is a mapping of Clocks IDs to function:</p>
6489 <table border="1" class="docutils">
6490 <colgroup>
6491 <col width="27%" />
6492 <col width="44%" />
6493 <col width="29%" />
6494 </colgroup>
6495 <thead valign="bottom">
6496 <tr class="row-odd"><th class="head">Clock ID</th>
6497 <th class="head">Name</th>
6498 <th class="head">Function</th>
6499 </tr>
6500 </thead>
6501 <tbody valign="top">
6502 <tr class="row-even"><td>0</td>
6503 <td>DEV_I2C4_PISYS_CLK</td>
6504 <td>Input clock</td>
6505 </tr>
6506 <tr class="row-odd"><td>1</td>
6507 <td>DEV_I2C4_PISCL</td>
6508 <td>Input clock</td>
6509 </tr>
6510 <tr class="row-even"><td>2</td>
6511 <td>DEV_I2C4_CLK</td>
6512 <td>Input clock</td>
6513 </tr>
6514 </tbody>
6515 </table>
6516 </div>
6517 <div class="section" id="clocks-for-i2c5-device">
6518 <span id="soc-doc-j721e-public-clks-i2c5"></span><h3>Clocks for I2C5 Device<a class="headerlink" href="#clocks-for-i2c5-device" title="Permalink to this headline">¶</a></h3>
6519 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_I2C5</span></a> (ID = 192)</p>
6520 <p>Following is a mapping of Clocks IDs to function:</p>
6521 <table border="1" class="docutils">
6522 <colgroup>
6523 <col width="27%" />
6524 <col width="44%" />
6525 <col width="29%" />
6526 </colgroup>
6527 <thead valign="bottom">
6528 <tr class="row-odd"><th class="head">Clock ID</th>
6529 <th class="head">Name</th>
6530 <th class="head">Function</th>
6531 </tr>
6532 </thead>
6533 <tbody valign="top">
6534 <tr class="row-even"><td>0</td>
6535 <td>DEV_I2C5_PISYS_CLK</td>
6536 <td>Input clock</td>
6537 </tr>
6538 <tr class="row-odd"><td>1</td>
6539 <td>DEV_I2C5_PISCL</td>
6540 <td>Input clock</td>
6541 </tr>
6542 <tr class="row-even"><td>2</td>
6543 <td>DEV_I2C5_CLK</td>
6544 <td>Input clock</td>
6545 </tr>
6546 </tbody>
6547 </table>
6548 </div>
6549 <div class="section" id="clocks-for-i2c6-device">
6550 <span id="soc-doc-j721e-public-clks-i2c6"></span><h3>Clocks for I2C6 Device<a class="headerlink" href="#clocks-for-i2c6-device" title="Permalink to this headline">¶</a></h3>
6551 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_I2C6</span></a> (ID = 193)</p>
6552 <p>Following is a mapping of Clocks IDs to function:</p>
6553 <table border="1" class="docutils">
6554 <colgroup>
6555 <col width="27%" />
6556 <col width="44%" />
6557 <col width="29%" />
6558 </colgroup>
6559 <thead valign="bottom">
6560 <tr class="row-odd"><th class="head">Clock ID</th>
6561 <th class="head">Name</th>
6562 <th class="head">Function</th>
6563 </tr>
6564 </thead>
6565 <tbody valign="top">
6566 <tr class="row-even"><td>0</td>
6567 <td>DEV_I2C6_PISYS_CLK</td>
6568 <td>Input clock</td>
6569 </tr>
6570 <tr class="row-odd"><td>1</td>
6571 <td>DEV_I2C6_PISCL</td>
6572 <td>Input clock</td>
6573 </tr>
6574 <tr class="row-even"><td>2</td>
6575 <td>DEV_I2C6_CLK</td>
6576 <td>Input clock</td>
6577 </tr>
6578 </tbody>
6579 </table>
6580 </div>
6581 <div class="section" id="clocks-for-i3c0-device">
6582 <span id="soc-doc-j721e-public-clks-i3c0"></span><h3>Clocks for I3C0 Device<a class="headerlink" href="#clocks-for-i3c0-device" title="Permalink to this headline">¶</a></h3>
6583 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_I3C0</span></a> (ID = 116)</p>
6584 <p>Following is a mapping of Clocks IDs to function:</p>
6585 <table border="1" class="docutils">
6586 <colgroup>
6587 <col width="24%" />
6588 <col width="47%" />
6589 <col width="29%" />
6590 </colgroup>
6591 <thead valign="bottom">
6592 <tr class="row-odd"><th class="head">Clock ID</th>
6593 <th class="head">Name</th>
6594 <th class="head">Function</th>
6595 </tr>
6596 </thead>
6597 <tbody valign="top">
6598 <tr class="row-even"><td>0</td>
6599 <td>DEV_I3C0_I3C_PCLK_CLK</td>
6600 <td>Input clock</td>
6601 </tr>
6602 <tr class="row-odd"><td>1</td>
6603 <td>DEV_I3C0_I3C_SCL_DI</td>
6604 <td>Input clock</td>
6605 </tr>
6606 <tr class="row-even"><td>2</td>
6607 <td>DEV_I3C0_I3C_SCLK_CLK</td>
6608 <td>Input clock</td>
6609 </tr>
6610 <tr class="row-odd"><td>3</td>
6611 <td>DEV_I3C0_I3C_SCL_DO</td>
6612 <td>Output clock</td>
6613 </tr>
6614 </tbody>
6615 </table>
6616 </div>
6617 <div class="section" id="clocks-for-led0-device">
6618 <span id="soc-doc-j721e-public-clks-led0"></span><h3>Clocks for LED0 Device<a class="headerlink" href="#clocks-for-led0-device" title="Permalink to this headline">¶</a></h3>
6619 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_LED0</span></a> (ID = 127)</p>
6620 <p>Following is a mapping of Clocks IDs to function:</p>
6621 <table border="1" class="docutils">
6622 <colgroup>
6623 <col width="27%" />
6624 <col width="43%" />
6625 <col width="30%" />
6626 </colgroup>
6627 <thead valign="bottom">
6628 <tr class="row-odd"><th class="head">Clock ID</th>
6629 <th class="head">Name</th>
6630 <th class="head">Function</th>
6631 </tr>
6632 </thead>
6633 <tbody valign="top">
6634 <tr class="row-even"><td>0</td>
6635 <td>DEV_LED0_LED_CLK</td>
6636 <td>Input clock</td>
6637 </tr>
6638 <tr class="row-odd"><td>1</td>
6639 <td>DEV_LED0_VBUS_CLK</td>
6640 <td>Input clock</td>
6641 </tr>
6642 </tbody>
6643 </table>
6644 </div>
6645 <div class="section" id="clocks-for-main2mcu-lvl-intrtr0-device">
6646 <span id="soc-doc-j721e-public-clks-main2mcu-lvl-intrtr0"></span><h3>Clocks for MAIN2MCU_LVL_INTRTR0 Device<a class="headerlink" href="#clocks-for-main2mcu-lvl-intrtr0-device" title="Permalink to this headline">¶</a></h3>
6647 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MAIN2MCU_LVL_INTRTR0</span></a> (ID = 128)</p>
6648 <p>Following is a mapping of Clocks IDs to function:</p>
6649 <table border="1" class="docutils">
6650 <colgroup>
6651 <col width="20%" />
6652 <col width="58%" />
6653 <col width="22%" />
6654 </colgroup>
6655 <thead valign="bottom">
6656 <tr class="row-odd"><th class="head">Clock ID</th>
6657 <th class="head">Name</th>
6658 <th class="head">Function</th>
6659 </tr>
6660 </thead>
6661 <tbody valign="top">
6662 <tr class="row-even"><td>0</td>
6663 <td>DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK</td>
6664 <td>Input clock</td>
6665 </tr>
6666 </tbody>
6667 </table>
6668 </div>
6669 <div class="section" id="clocks-for-main2mcu-pls-intrtr0-device">
6670 <span id="soc-doc-j721e-public-clks-main2mcu-pls-intrtr0"></span><h3>Clocks for MAIN2MCU_PLS_INTRTR0 Device<a class="headerlink" href="#clocks-for-main2mcu-pls-intrtr0-device" title="Permalink to this headline">¶</a></h3>
6671 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MAIN2MCU_PLS_INTRTR0</span></a> (ID = 130)</p>
6672 <p>Following is a mapping of Clocks IDs to function:</p>
6673 <table border="1" class="docutils">
6674 <colgroup>
6675 <col width="20%" />
6676 <col width="58%" />
6677 <col width="22%" />
6678 </colgroup>
6679 <thead valign="bottom">
6680 <tr class="row-odd"><th class="head">Clock ID</th>
6681 <th class="head">Name</th>
6682 <th class="head">Function</th>
6683 </tr>
6684 </thead>
6685 <tbody valign="top">
6686 <tr class="row-even"><td>0</td>
6687 <td>DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK</td>
6688 <td>Input clock</td>
6689 </tr>
6690 </tbody>
6691 </table>
6692 </div>
6693 <div class="section" id="clocks-for-main2wkupmcu-vd-device">
6694 <span id="soc-doc-j721e-public-clks-main2wkupmcu-vd"></span><h3>Clocks for MAIN2WKUPMCU_VD Device<a class="headerlink" href="#clocks-for-main2wkupmcu-vd-device" title="Permalink to this headline">¶</a></h3>
6695 <p><strong>This device has no defined clocks.</strong></p>
6696 </div>
6697 <div class="section" id="clocks-for-mcan0-device">
6698 <span id="soc-doc-j721e-public-clks-mcan0"></span><h3>Clocks for MCAN0 Device<a class="headerlink" href="#clocks-for-mcan0-device" title="Permalink to this headline">¶</a></h3>
6699 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN0</span></a> (ID = 156)</p>
6700 <p>Following is a mapping of Clocks IDs to function:</p>
6701 <table border="1" class="docutils">
6702 <colgroup>
6703 <col width="9%" />
6704 <col width="50%" />
6705 <col width="41%" />
6706 </colgroup>
6707 <thead valign="bottom">
6708 <tr class="row-odd"><th class="head">Clock ID</th>
6709 <th class="head">Name</th>
6710 <th class="head">Function</th>
6711 </tr>
6712 </thead>
6713 <tbody valign="top">
6714 <tr class="row-even"><td>0</td>
6715 <td>DEV_MCAN0_MCANSS_HCLK_CLK</td>
6716 <td>Input clock</td>
6717 </tr>
6718 <tr class="row-odd"><td>1</td>
6719 <td>DEV_MCAN0_MCANSS_CCLK_CLK</td>
6720 <td>Input muxed clock</td>
6721 </tr>
6722 <tr class="row-even"><td>2</td>
6723 <td>DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6724 <td>Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK</td>
6725 </tr>
6726 <tr class="row-odd"><td>3</td>
6727 <td>DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6728 <td>Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK</td>
6729 </tr>
6730 <tr class="row-even"><td>4</td>
6731 <td>DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6732 <td>Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK</td>
6733 </tr>
6734 <tr class="row-odd"><td>5</td>
6735 <td>DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6736 <td>Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK</td>
6737 </tr>
6738 </tbody>
6739 </table>
6740 </div>
6741 <div class="section" id="clocks-for-mcan1-device">
6742 <span id="soc-doc-j721e-public-clks-mcan1"></span><h3>Clocks for MCAN1 Device<a class="headerlink" href="#clocks-for-mcan1-device" title="Permalink to this headline">¶</a></h3>
6743 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN1</span></a> (ID = 158)</p>
6744 <p>Following is a mapping of Clocks IDs to function:</p>
6745 <table border="1" class="docutils">
6746 <colgroup>
6747 <col width="9%" />
6748 <col width="50%" />
6749 <col width="41%" />
6750 </colgroup>
6751 <thead valign="bottom">
6752 <tr class="row-odd"><th class="head">Clock ID</th>
6753 <th class="head">Name</th>
6754 <th class="head">Function</th>
6755 </tr>
6756 </thead>
6757 <tbody valign="top">
6758 <tr class="row-even"><td>0</td>
6759 <td>DEV_MCAN1_MCANSS_HCLK_CLK</td>
6760 <td>Input clock</td>
6761 </tr>
6762 <tr class="row-odd"><td>1</td>
6763 <td>DEV_MCAN1_MCANSS_CCLK_CLK</td>
6764 <td>Input muxed clock</td>
6765 </tr>
6766 <tr class="row-even"><td>2</td>
6767 <td>DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6768 <td>Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK</td>
6769 </tr>
6770 <tr class="row-odd"><td>3</td>
6771 <td>DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6772 <td>Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK</td>
6773 </tr>
6774 <tr class="row-even"><td>4</td>
6775 <td>DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6776 <td>Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK</td>
6777 </tr>
6778 <tr class="row-odd"><td>5</td>
6779 <td>DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6780 <td>Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK</td>
6781 </tr>
6782 </tbody>
6783 </table>
6784 </div>
6785 <div class="section" id="clocks-for-mcan10-device">
6786 <span id="soc-doc-j721e-public-clks-mcan10"></span><h3>Clocks for MCAN10 Device<a class="headerlink" href="#clocks-for-mcan10-device" title="Permalink to this headline">¶</a></h3>
6787 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN10</span></a> (ID = 168)</p>
6788 <p>Following is a mapping of Clocks IDs to function:</p>
6789 <table border="1" class="docutils">
6790 <colgroup>
6791 <col width="9%" />
6792 <col width="50%" />
6793 <col width="41%" />
6794 </colgroup>
6795 <thead valign="bottom">
6796 <tr class="row-odd"><th class="head">Clock ID</th>
6797 <th class="head">Name</th>
6798 <th class="head">Function</th>
6799 </tr>
6800 </thead>
6801 <tbody valign="top">
6802 <tr class="row-even"><td>0</td>
6803 <td>DEV_MCAN10_MCANSS_HCLK_CLK</td>
6804 <td>Input clock</td>
6805 </tr>
6806 <tr class="row-odd"><td>1</td>
6807 <td>DEV_MCAN10_MCANSS_CCLK_CLK</td>
6808 <td>Input muxed clock</td>
6809 </tr>
6810 <tr class="row-even"><td>2</td>
6811 <td>DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6812 <td>Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK</td>
6813 </tr>
6814 <tr class="row-odd"><td>3</td>
6815 <td>DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6816 <td>Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK</td>
6817 </tr>
6818 <tr class="row-even"><td>4</td>
6819 <td>DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6820 <td>Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK</td>
6821 </tr>
6822 <tr class="row-odd"><td>5</td>
6823 <td>DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6824 <td>Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK</td>
6825 </tr>
6826 </tbody>
6827 </table>
6828 </div>
6829 <div class="section" id="clocks-for-mcan11-device">
6830 <span id="soc-doc-j721e-public-clks-mcan11"></span><h3>Clocks for MCAN11 Device<a class="headerlink" href="#clocks-for-mcan11-device" title="Permalink to this headline">¶</a></h3>
6831 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN11</span></a> (ID = 169)</p>
6832 <p>Following is a mapping of Clocks IDs to function:</p>
6833 <table border="1" class="docutils">
6834 <colgroup>
6835 <col width="9%" />
6836 <col width="50%" />
6837 <col width="41%" />
6838 </colgroup>
6839 <thead valign="bottom">
6840 <tr class="row-odd"><th class="head">Clock ID</th>
6841 <th class="head">Name</th>
6842 <th class="head">Function</th>
6843 </tr>
6844 </thead>
6845 <tbody valign="top">
6846 <tr class="row-even"><td>0</td>
6847 <td>DEV_MCAN11_MCANSS_HCLK_CLK</td>
6848 <td>Input clock</td>
6849 </tr>
6850 <tr class="row-odd"><td>1</td>
6851 <td>DEV_MCAN11_MCANSS_CCLK_CLK</td>
6852 <td>Input muxed clock</td>
6853 </tr>
6854 <tr class="row-even"><td>2</td>
6855 <td>DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6856 <td>Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK</td>
6857 </tr>
6858 <tr class="row-odd"><td>3</td>
6859 <td>DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6860 <td>Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK</td>
6861 </tr>
6862 <tr class="row-even"><td>4</td>
6863 <td>DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6864 <td>Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK</td>
6865 </tr>
6866 <tr class="row-odd"><td>5</td>
6867 <td>DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6868 <td>Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK</td>
6869 </tr>
6870 </tbody>
6871 </table>
6872 </div>
6873 <div class="section" id="clocks-for-mcan12-device">
6874 <span id="soc-doc-j721e-public-clks-mcan12"></span><h3>Clocks for MCAN12 Device<a class="headerlink" href="#clocks-for-mcan12-device" title="Permalink to this headline">¶</a></h3>
6875 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN12</span></a> (ID = 170)</p>
6876 <p>Following is a mapping of Clocks IDs to function:</p>
6877 <table border="1" class="docutils">
6878 <colgroup>
6879 <col width="9%" />
6880 <col width="50%" />
6881 <col width="41%" />
6882 </colgroup>
6883 <thead valign="bottom">
6884 <tr class="row-odd"><th class="head">Clock ID</th>
6885 <th class="head">Name</th>
6886 <th class="head">Function</th>
6887 </tr>
6888 </thead>
6889 <tbody valign="top">
6890 <tr class="row-even"><td>0</td>
6891 <td>DEV_MCAN12_MCANSS_HCLK_CLK</td>
6892 <td>Input clock</td>
6893 </tr>
6894 <tr class="row-odd"><td>1</td>
6895 <td>DEV_MCAN12_MCANSS_CCLK_CLK</td>
6896 <td>Input muxed clock</td>
6897 </tr>
6898 <tr class="row-even"><td>2</td>
6899 <td>DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6900 <td>Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK</td>
6901 </tr>
6902 <tr class="row-odd"><td>3</td>
6903 <td>DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6904 <td>Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK</td>
6905 </tr>
6906 <tr class="row-even"><td>4</td>
6907 <td>DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6908 <td>Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK</td>
6909 </tr>
6910 <tr class="row-odd"><td>5</td>
6911 <td>DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6912 <td>Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK</td>
6913 </tr>
6914 </tbody>
6915 </table>
6916 </div>
6917 <div class="section" id="clocks-for-mcan13-device">
6918 <span id="soc-doc-j721e-public-clks-mcan13"></span><h3>Clocks for MCAN13 Device<a class="headerlink" href="#clocks-for-mcan13-device" title="Permalink to this headline">¶</a></h3>
6919 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN13</span></a> (ID = 171)</p>
6920 <p>Following is a mapping of Clocks IDs to function:</p>
6921 <table border="1" class="docutils">
6922 <colgroup>
6923 <col width="9%" />
6924 <col width="50%" />
6925 <col width="41%" />
6926 </colgroup>
6927 <thead valign="bottom">
6928 <tr class="row-odd"><th class="head">Clock ID</th>
6929 <th class="head">Name</th>
6930 <th class="head">Function</th>
6931 </tr>
6932 </thead>
6933 <tbody valign="top">
6934 <tr class="row-even"><td>0</td>
6935 <td>DEV_MCAN13_MCANSS_HCLK_CLK</td>
6936 <td>Input clock</td>
6937 </tr>
6938 <tr class="row-odd"><td>1</td>
6939 <td>DEV_MCAN13_MCANSS_CCLK_CLK</td>
6940 <td>Input muxed clock</td>
6941 </tr>
6942 <tr class="row-even"><td>2</td>
6943 <td>DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6944 <td>Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK</td>
6945 </tr>
6946 <tr class="row-odd"><td>3</td>
6947 <td>DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6948 <td>Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK</td>
6949 </tr>
6950 <tr class="row-even"><td>4</td>
6951 <td>DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6952 <td>Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK</td>
6953 </tr>
6954 <tr class="row-odd"><td>5</td>
6955 <td>DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6956 <td>Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK</td>
6957 </tr>
6958 </tbody>
6959 </table>
6960 </div>
6961 <div class="section" id="clocks-for-mcan2-device">
6962 <span id="soc-doc-j721e-public-clks-mcan2"></span><h3>Clocks for MCAN2 Device<a class="headerlink" href="#clocks-for-mcan2-device" title="Permalink to this headline">¶</a></h3>
6963 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN2</span></a> (ID = 160)</p>
6964 <p>Following is a mapping of Clocks IDs to function:</p>
6965 <table border="1" class="docutils">
6966 <colgroup>
6967 <col width="9%" />
6968 <col width="50%" />
6969 <col width="41%" />
6970 </colgroup>
6971 <thead valign="bottom">
6972 <tr class="row-odd"><th class="head">Clock ID</th>
6973 <th class="head">Name</th>
6974 <th class="head">Function</th>
6975 </tr>
6976 </thead>
6977 <tbody valign="top">
6978 <tr class="row-even"><td>0</td>
6979 <td>DEV_MCAN2_MCANSS_HCLK_CLK</td>
6980 <td>Input clock</td>
6981 </tr>
6982 <tr class="row-odd"><td>1</td>
6983 <td>DEV_MCAN2_MCANSS_CCLK_CLK</td>
6984 <td>Input muxed clock</td>
6985 </tr>
6986 <tr class="row-even"><td>2</td>
6987 <td>DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6988 <td>Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK</td>
6989 </tr>
6990 <tr class="row-odd"><td>3</td>
6991 <td>DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6992 <td>Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK</td>
6993 </tr>
6994 <tr class="row-even"><td>4</td>
6995 <td>DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6996 <td>Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK</td>
6997 </tr>
6998 <tr class="row-odd"><td>5</td>
6999 <td>DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7000 <td>Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK</td>
7001 </tr>
7002 </tbody>
7003 </table>
7004 </div>
7005 <div class="section" id="clocks-for-mcan3-device">
7006 <span id="soc-doc-j721e-public-clks-mcan3"></span><h3>Clocks for MCAN3 Device<a class="headerlink" href="#clocks-for-mcan3-device" title="Permalink to this headline">¶</a></h3>
7007 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN3</span></a> (ID = 161)</p>
7008 <p>Following is a mapping of Clocks IDs to function:</p>
7009 <table border="1" class="docutils">
7010 <colgroup>
7011 <col width="9%" />
7012 <col width="50%" />
7013 <col width="41%" />
7014 </colgroup>
7015 <thead valign="bottom">
7016 <tr class="row-odd"><th class="head">Clock ID</th>
7017 <th class="head">Name</th>
7018 <th class="head">Function</th>
7019 </tr>
7020 </thead>
7021 <tbody valign="top">
7022 <tr class="row-even"><td>0</td>
7023 <td>DEV_MCAN3_MCANSS_HCLK_CLK</td>
7024 <td>Input clock</td>
7025 </tr>
7026 <tr class="row-odd"><td>1</td>
7027 <td>DEV_MCAN3_MCANSS_CCLK_CLK</td>
7028 <td>Input muxed clock</td>
7029 </tr>
7030 <tr class="row-even"><td>2</td>
7031 <td>DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
7032 <td>Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK</td>
7033 </tr>
7034 <tr class="row-odd"><td>3</td>
7035 <td>DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
7036 <td>Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK</td>
7037 </tr>
7038 <tr class="row-even"><td>4</td>
7039 <td>DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7040 <td>Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK</td>
7041 </tr>
7042 <tr class="row-odd"><td>5</td>
7043 <td>DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7044 <td>Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK</td>
7045 </tr>
7046 </tbody>
7047 </table>
7048 </div>
7049 <div class="section" id="clocks-for-mcan4-device">
7050 <span id="soc-doc-j721e-public-clks-mcan4"></span><h3>Clocks for MCAN4 Device<a class="headerlink" href="#clocks-for-mcan4-device" title="Permalink to this headline">¶</a></h3>
7051 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN4</span></a> (ID = 162)</p>
7052 <p>Following is a mapping of Clocks IDs to function:</p>
7053 <table border="1" class="docutils">
7054 <colgroup>
7055 <col width="9%" />
7056 <col width="50%" />
7057 <col width="41%" />
7058 </colgroup>
7059 <thead valign="bottom">
7060 <tr class="row-odd"><th class="head">Clock ID</th>
7061 <th class="head">Name</th>
7062 <th class="head">Function</th>
7063 </tr>
7064 </thead>
7065 <tbody valign="top">
7066 <tr class="row-even"><td>0</td>
7067 <td>DEV_MCAN4_MCANSS_HCLK_CLK</td>
7068 <td>Input clock</td>
7069 </tr>
7070 <tr class="row-odd"><td>1</td>
7071 <td>DEV_MCAN4_MCANSS_CCLK_CLK</td>
7072 <td>Input muxed clock</td>
7073 </tr>
7074 <tr class="row-even"><td>2</td>
7075 <td>DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
7076 <td>Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK</td>
7077 </tr>
7078 <tr class="row-odd"><td>3</td>
7079 <td>DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
7080 <td>Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK</td>
7081 </tr>
7082 <tr class="row-even"><td>4</td>
7083 <td>DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7084 <td>Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK</td>
7085 </tr>
7086 <tr class="row-odd"><td>5</td>
7087 <td>DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7088 <td>Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK</td>
7089 </tr>
7090 </tbody>
7091 </table>
7092 </div>
7093 <div class="section" id="clocks-for-mcan5-device">
7094 <span id="soc-doc-j721e-public-clks-mcan5"></span><h3>Clocks for MCAN5 Device<a class="headerlink" href="#clocks-for-mcan5-device" title="Permalink to this headline">¶</a></h3>
7095 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN5</span></a> (ID = 163)</p>
7096 <p>Following is a mapping of Clocks IDs to function:</p>
7097 <table border="1" class="docutils">
7098 <colgroup>
7099 <col width="9%" />
7100 <col width="50%" />
7101 <col width="41%" />
7102 </colgroup>
7103 <thead valign="bottom">
7104 <tr class="row-odd"><th class="head">Clock ID</th>
7105 <th class="head">Name</th>
7106 <th class="head">Function</th>
7107 </tr>
7108 </thead>
7109 <tbody valign="top">
7110 <tr class="row-even"><td>0</td>
7111 <td>DEV_MCAN5_MCANSS_HCLK_CLK</td>
7112 <td>Input clock</td>
7113 </tr>
7114 <tr class="row-odd"><td>1</td>
7115 <td>DEV_MCAN5_MCANSS_CCLK_CLK</td>
7116 <td>Input muxed clock</td>
7117 </tr>
7118 <tr class="row-even"><td>2</td>
7119 <td>DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
7120 <td>Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK</td>
7121 </tr>
7122 <tr class="row-odd"><td>3</td>
7123 <td>DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
7124 <td>Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK</td>
7125 </tr>
7126 <tr class="row-even"><td>4</td>
7127 <td>DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7128 <td>Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK</td>
7129 </tr>
7130 <tr class="row-odd"><td>5</td>
7131 <td>DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7132 <td>Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK</td>
7133 </tr>
7134 </tbody>
7135 </table>
7136 </div>
7137 <div class="section" id="clocks-for-mcan6-device">
7138 <span id="soc-doc-j721e-public-clks-mcan6"></span><h3>Clocks for MCAN6 Device<a class="headerlink" href="#clocks-for-mcan6-device" title="Permalink to this headline">¶</a></h3>
7139 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN6</span></a> (ID = 164)</p>
7140 <p>Following is a mapping of Clocks IDs to function:</p>
7141 <table border="1" class="docutils">
7142 <colgroup>
7143 <col width="9%" />
7144 <col width="50%" />
7145 <col width="41%" />
7146 </colgroup>
7147 <thead valign="bottom">
7148 <tr class="row-odd"><th class="head">Clock ID</th>
7149 <th class="head">Name</th>
7150 <th class="head">Function</th>
7151 </tr>
7152 </thead>
7153 <tbody valign="top">
7154 <tr class="row-even"><td>0</td>
7155 <td>DEV_MCAN6_MCANSS_HCLK_CLK</td>
7156 <td>Input clock</td>
7157 </tr>
7158 <tr class="row-odd"><td>1</td>
7159 <td>DEV_MCAN6_MCANSS_CCLK_CLK</td>
7160 <td>Input muxed clock</td>
7161 </tr>
7162 <tr class="row-even"><td>2</td>
7163 <td>DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
7164 <td>Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK</td>
7165 </tr>
7166 <tr class="row-odd"><td>3</td>
7167 <td>DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
7168 <td>Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK</td>
7169 </tr>
7170 <tr class="row-even"><td>4</td>
7171 <td>DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7172 <td>Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK</td>
7173 </tr>
7174 <tr class="row-odd"><td>5</td>
7175 <td>DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7176 <td>Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK</td>
7177 </tr>
7178 </tbody>
7179 </table>
7180 </div>
7181 <div class="section" id="clocks-for-mcan7-device">
7182 <span id="soc-doc-j721e-public-clks-mcan7"></span><h3>Clocks for MCAN7 Device<a class="headerlink" href="#clocks-for-mcan7-device" title="Permalink to this headline">¶</a></h3>
7183 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN7</span></a> (ID = 165)</p>
7184 <p>Following is a mapping of Clocks IDs to function:</p>
7185 <table border="1" class="docutils">
7186 <colgroup>
7187 <col width="9%" />
7188 <col width="50%" />
7189 <col width="41%" />
7190 </colgroup>
7191 <thead valign="bottom">
7192 <tr class="row-odd"><th class="head">Clock ID</th>
7193 <th class="head">Name</th>
7194 <th class="head">Function</th>
7195 </tr>
7196 </thead>
7197 <tbody valign="top">
7198 <tr class="row-even"><td>0</td>
7199 <td>DEV_MCAN7_MCANSS_HCLK_CLK</td>
7200 <td>Input clock</td>
7201 </tr>
7202 <tr class="row-odd"><td>1</td>
7203 <td>DEV_MCAN7_MCANSS_CCLK_CLK</td>
7204 <td>Input muxed clock</td>
7205 </tr>
7206 <tr class="row-even"><td>2</td>
7207 <td>DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
7208 <td>Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK</td>
7209 </tr>
7210 <tr class="row-odd"><td>3</td>
7211 <td>DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
7212 <td>Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK</td>
7213 </tr>
7214 <tr class="row-even"><td>4</td>
7215 <td>DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7216 <td>Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK</td>
7217 </tr>
7218 <tr class="row-odd"><td>5</td>
7219 <td>DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7220 <td>Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK</td>
7221 </tr>
7222 </tbody>
7223 </table>
7224 </div>
7225 <div class="section" id="clocks-for-mcan8-device">
7226 <span id="soc-doc-j721e-public-clks-mcan8"></span><h3>Clocks for MCAN8 Device<a class="headerlink" href="#clocks-for-mcan8-device" title="Permalink to this headline">¶</a></h3>
7227 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN8</span></a> (ID = 166)</p>
7228 <p>Following is a mapping of Clocks IDs to function:</p>
7229 <table border="1" class="docutils">
7230 <colgroup>
7231 <col width="9%" />
7232 <col width="50%" />
7233 <col width="41%" />
7234 </colgroup>
7235 <thead valign="bottom">
7236 <tr class="row-odd"><th class="head">Clock ID</th>
7237 <th class="head">Name</th>
7238 <th class="head">Function</th>
7239 </tr>
7240 </thead>
7241 <tbody valign="top">
7242 <tr class="row-even"><td>0</td>
7243 <td>DEV_MCAN8_MCANSS_HCLK_CLK</td>
7244 <td>Input clock</td>
7245 </tr>
7246 <tr class="row-odd"><td>1</td>
7247 <td>DEV_MCAN8_MCANSS_CCLK_CLK</td>
7248 <td>Input muxed clock</td>
7249 </tr>
7250 <tr class="row-even"><td>2</td>
7251 <td>DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
7252 <td>Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK</td>
7253 </tr>
7254 <tr class="row-odd"><td>3</td>
7255 <td>DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
7256 <td>Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK</td>
7257 </tr>
7258 <tr class="row-even"><td>4</td>
7259 <td>DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7260 <td>Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK</td>
7261 </tr>
7262 <tr class="row-odd"><td>5</td>
7263 <td>DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7264 <td>Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK</td>
7265 </tr>
7266 </tbody>
7267 </table>
7268 </div>
7269 <div class="section" id="clocks-for-mcan9-device">
7270 <span id="soc-doc-j721e-public-clks-mcan9"></span><h3>Clocks for MCAN9 Device<a class="headerlink" href="#clocks-for-mcan9-device" title="Permalink to this headline">¶</a></h3>
7271 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCAN9</span></a> (ID = 167)</p>
7272 <p>Following is a mapping of Clocks IDs to function:</p>
7273 <table border="1" class="docutils">
7274 <colgroup>
7275 <col width="9%" />
7276 <col width="50%" />
7277 <col width="41%" />
7278 </colgroup>
7279 <thead valign="bottom">
7280 <tr class="row-odd"><th class="head">Clock ID</th>
7281 <th class="head">Name</th>
7282 <th class="head">Function</th>
7283 </tr>
7284 </thead>
7285 <tbody valign="top">
7286 <tr class="row-even"><td>0</td>
7287 <td>DEV_MCAN9_MCANSS_HCLK_CLK</td>
7288 <td>Input clock</td>
7289 </tr>
7290 <tr class="row-odd"><td>1</td>
7291 <td>DEV_MCAN9_MCANSS_CCLK_CLK</td>
7292 <td>Input muxed clock</td>
7293 </tr>
7294 <tr class="row-even"><td>2</td>
7295 <td>DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
7296 <td>Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK</td>
7297 </tr>
7298 <tr class="row-odd"><td>3</td>
7299 <td>DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
7300 <td>Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK</td>
7301 </tr>
7302 <tr class="row-even"><td>4</td>
7303 <td>DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7304 <td>Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK</td>
7305 </tr>
7306 <tr class="row-odd"><td>5</td>
7307 <td>DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7308 <td>Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK</td>
7309 </tr>
7310 </tbody>
7311 </table>
7312 </div>
7313 <div class="section" id="clocks-for-mcasp0-device">
7314 <span id="soc-doc-j721e-public-clks-mcasp0"></span><h3>Clocks for MCASP0 Device<a class="headerlink" href="#clocks-for-mcasp0-device" title="Permalink to this headline">¶</a></h3>
7315 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCASP0</span></a> (ID = 174)</p>
7316 <p>Following is a mapping of Clocks IDs to function:</p>
7317 <table border="1" class="docutils">
7318 <colgroup>
7319 <col width="9%" />
7320 <col width="50%" />
7321 <col width="41%" />
7322 </colgroup>
7323 <thead valign="bottom">
7324 <tr class="row-odd"><th class="head">Clock ID</th>
7325 <th class="head">Name</th>
7326 <th class="head">Function</th>
7327 </tr>
7328 </thead>
7329 <tbody valign="top">
7330 <tr class="row-even"><td>0</td>
7331 <td>DEV_MCASP0_VBUSP_CLK</td>
7332 <td>Input clock</td>
7333 </tr>
7334 <tr class="row-odd"><td>1</td>
7335 <td>DEV_MCASP0_AUX_CLK</td>
7336 <td>Input muxed clock</td>
7337 </tr>
7338 <tr class="row-even"><td>2</td>
7339 <td>DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
7340 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7341 </tr>
7342 <tr class="row-odd"><td>3</td>
7343 <td>DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
7344 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7345 </tr>
7346 <tr class="row-even"><td>4</td>
7347 <td>DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
7348 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7349 </tr>
7350 <tr class="row-odd"><td>6</td>
7351 <td>DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7352 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7353 </tr>
7354 <tr class="row-even"><td>7</td>
7355 <td>DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7356 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7357 </tr>
7358 <tr class="row-odd"><td>8</td>
7359 <td>DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7360 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7361 </tr>
7362 <tr class="row-even"><td>9</td>
7363 <td>DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7364 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7365 </tr>
7366 <tr class="row-odd"><td>10</td>
7367 <td>DEV_MCASP0_MCASP_ACLKX_POUT</td>
7368 <td>Output clock</td>
7369 </tr>
7370 <tr class="row-even"><td>11</td>
7371 <td>DEV_MCASP0_MCASP_ACLKX_PIN</td>
7372 <td>Input clock</td>
7373 </tr>
7374 <tr class="row-odd"><td>12</td>
7375 <td>DEV_MCASP0_MCASP_ACLKR_POUT</td>
7376 <td>Output clock</td>
7377 </tr>
7378 <tr class="row-even"><td>13</td>
7379 <td>DEV_MCASP0_MCASP_ACLKR_PIN</td>
7380 <td>Input clock</td>
7381 </tr>
7382 <tr class="row-odd"><td>14</td>
7383 <td>DEV_MCASP0_MCASP_AHCLKX_POUT</td>
7384 <td>Output clock</td>
7385 </tr>
7386 <tr class="row-even"><td>15</td>
7387 <td>DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7388 <td>Input muxed clock</td>
7389 </tr>
7390 <tr class="row-odd"><td>16</td>
7391 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7392 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7393 </tr>
7394 <tr class="row-even"><td>17</td>
7395 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7396 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7397 </tr>
7398 <tr class="row-odd"><td>18</td>
7399 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
7400 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7401 </tr>
7402 <tr class="row-even"><td>19</td>
7403 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
7404 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7405 </tr>
7406 <tr class="row-odd"><td>20</td>
7407 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
7408 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7409 </tr>
7410 <tr class="row-even"><td>21</td>
7411 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
7412 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7413 </tr>
7414 <tr class="row-odd"><td>22</td>
7415 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
7416 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7417 </tr>
7418 <tr class="row-even"><td>23</td>
7419 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
7420 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7421 </tr>
7422 <tr class="row-odd"><td>24</td>
7423 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7424 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7425 </tr>
7426 <tr class="row-even"><td>25</td>
7427 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7428 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7429 </tr>
7430 <tr class="row-odd"><td>26</td>
7431 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7432 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7433 </tr>
7434 <tr class="row-even"><td>27</td>
7435 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7436 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7437 </tr>
7438 <tr class="row-odd"><td>28</td>
7439 <td>DEV_MCASP0_MCASP_AHCLKR_POUT</td>
7440 <td>Output clock</td>
7441 </tr>
7442 <tr class="row-even"><td>29</td>
7443 <td>DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7444 <td>Input muxed clock</td>
7445 </tr>
7446 <tr class="row-odd"><td>30</td>
7447 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7448 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7449 </tr>
7450 <tr class="row-even"><td>31</td>
7451 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7452 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7453 </tr>
7454 <tr class="row-odd"><td>32</td>
7455 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
7456 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7457 </tr>
7458 <tr class="row-even"><td>33</td>
7459 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
7460 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7461 </tr>
7462 <tr class="row-odd"><td>34</td>
7463 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
7464 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7465 </tr>
7466 <tr class="row-even"><td>35</td>
7467 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
7468 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7469 </tr>
7470 <tr class="row-odd"><td>36</td>
7471 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
7472 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7473 </tr>
7474 <tr class="row-even"><td>37</td>
7475 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
7476 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7477 </tr>
7478 <tr class="row-odd"><td>38</td>
7479 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7480 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7481 </tr>
7482 <tr class="row-even"><td>39</td>
7483 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7484 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7485 </tr>
7486 <tr class="row-odd"><td>40</td>
7487 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7488 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7489 </tr>
7490 <tr class="row-even"><td>41</td>
7491 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7492 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7493 </tr>
7494 </tbody>
7495 </table>
7496 </div>
7497 <div class="section" id="clocks-for-mcasp1-device">
7498 <span id="soc-doc-j721e-public-clks-mcasp1"></span><h3>Clocks for MCASP1 Device<a class="headerlink" href="#clocks-for-mcasp1-device" title="Permalink to this headline">¶</a></h3>
7499 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCASP1</span></a> (ID = 175)</p>
7500 <p>Following is a mapping of Clocks IDs to function:</p>
7501 <table border="1" class="docutils">
7502 <colgroup>
7503 <col width="9%" />
7504 <col width="50%" />
7505 <col width="41%" />
7506 </colgroup>
7507 <thead valign="bottom">
7508 <tr class="row-odd"><th class="head">Clock ID</th>
7509 <th class="head">Name</th>
7510 <th class="head">Function</th>
7511 </tr>
7512 </thead>
7513 <tbody valign="top">
7514 <tr class="row-even"><td>0</td>
7515 <td>DEV_MCASP1_VBUSP_CLK</td>
7516 <td>Input clock</td>
7517 </tr>
7518 <tr class="row-odd"><td>1</td>
7519 <td>DEV_MCASP1_AUX_CLK</td>
7520 <td>Input muxed clock</td>
7521 </tr>
7522 <tr class="row-even"><td>2</td>
7523 <td>DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
7524 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7525 </tr>
7526 <tr class="row-odd"><td>3</td>
7527 <td>DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
7528 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7529 </tr>
7530 <tr class="row-even"><td>4</td>
7531 <td>DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
7532 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7533 </tr>
7534 <tr class="row-odd"><td>6</td>
7535 <td>DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7536 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7537 </tr>
7538 <tr class="row-even"><td>7</td>
7539 <td>DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7540 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7541 </tr>
7542 <tr class="row-odd"><td>8</td>
7543 <td>DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7544 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7545 </tr>
7546 <tr class="row-even"><td>9</td>
7547 <td>DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7548 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7549 </tr>
7550 <tr class="row-odd"><td>10</td>
7551 <td>DEV_MCASP1_MCASP_ACLKX_POUT</td>
7552 <td>Output clock</td>
7553 </tr>
7554 <tr class="row-even"><td>11</td>
7555 <td>DEV_MCASP1_MCASP_ACLKX_PIN</td>
7556 <td>Input clock</td>
7557 </tr>
7558 <tr class="row-odd"><td>12</td>
7559 <td>DEV_MCASP1_MCASP_ACLKR_POUT</td>
7560 <td>Output clock</td>
7561 </tr>
7562 <tr class="row-even"><td>13</td>
7563 <td>DEV_MCASP1_MCASP_ACLKR_PIN</td>
7564 <td>Input clock</td>
7565 </tr>
7566 <tr class="row-odd"><td>14</td>
7567 <td>DEV_MCASP1_MCASP_AHCLKX_POUT</td>
7568 <td>Output clock</td>
7569 </tr>
7570 <tr class="row-even"><td>15</td>
7571 <td>DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7572 <td>Input muxed clock</td>
7573 </tr>
7574 <tr class="row-odd"><td>16</td>
7575 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7576 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7577 </tr>
7578 <tr class="row-even"><td>17</td>
7579 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7580 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7581 </tr>
7582 <tr class="row-odd"><td>18</td>
7583 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
7584 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7585 </tr>
7586 <tr class="row-even"><td>19</td>
7587 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
7588 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7589 </tr>
7590 <tr class="row-odd"><td>20</td>
7591 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
7592 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7593 </tr>
7594 <tr class="row-even"><td>21</td>
7595 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
7596 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7597 </tr>
7598 <tr class="row-odd"><td>22</td>
7599 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
7600 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7601 </tr>
7602 <tr class="row-even"><td>23</td>
7603 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
7604 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7605 </tr>
7606 <tr class="row-odd"><td>24</td>
7607 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7608 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7609 </tr>
7610 <tr class="row-even"><td>25</td>
7611 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7612 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7613 </tr>
7614 <tr class="row-odd"><td>26</td>
7615 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7616 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7617 </tr>
7618 <tr class="row-even"><td>27</td>
7619 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7620 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7621 </tr>
7622 <tr class="row-odd"><td>28</td>
7623 <td>DEV_MCASP1_MCASP_AHCLKR_POUT</td>
7624 <td>Output clock</td>
7625 </tr>
7626 <tr class="row-even"><td>29</td>
7627 <td>DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7628 <td>Input muxed clock</td>
7629 </tr>
7630 <tr class="row-odd"><td>30</td>
7631 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7632 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7633 </tr>
7634 <tr class="row-even"><td>31</td>
7635 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7636 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7637 </tr>
7638 <tr class="row-odd"><td>32</td>
7639 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
7640 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7641 </tr>
7642 <tr class="row-even"><td>33</td>
7643 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
7644 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7645 </tr>
7646 <tr class="row-odd"><td>34</td>
7647 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
7648 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7649 </tr>
7650 <tr class="row-even"><td>35</td>
7651 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
7652 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7653 </tr>
7654 <tr class="row-odd"><td>36</td>
7655 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
7656 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7657 </tr>
7658 <tr class="row-even"><td>37</td>
7659 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
7660 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7661 </tr>
7662 <tr class="row-odd"><td>38</td>
7663 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7664 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7665 </tr>
7666 <tr class="row-even"><td>39</td>
7667 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7668 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7669 </tr>
7670 <tr class="row-odd"><td>40</td>
7671 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7672 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7673 </tr>
7674 <tr class="row-even"><td>41</td>
7675 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7676 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7677 </tr>
7678 </tbody>
7679 </table>
7680 </div>
7681 <div class="section" id="clocks-for-mcasp10-device">
7682 <span id="soc-doc-j721e-public-clks-mcasp10"></span><h3>Clocks for MCASP10 Device<a class="headerlink" href="#clocks-for-mcasp10-device" title="Permalink to this headline">¶</a></h3>
7683 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCASP10</span></a> (ID = 184)</p>
7684 <p>Following is a mapping of Clocks IDs to function:</p>
7685 <table border="1" class="docutils">
7686 <colgroup>
7687 <col width="8%" />
7688 <col width="50%" />
7689 <col width="41%" />
7690 </colgroup>
7691 <thead valign="bottom">
7692 <tr class="row-odd"><th class="head">Clock ID</th>
7693 <th class="head">Name</th>
7694 <th class="head">Function</th>
7695 </tr>
7696 </thead>
7697 <tbody valign="top">
7698 <tr class="row-even"><td>0</td>
7699 <td>DEV_MCASP10_VBUSP_CLK</td>
7700 <td>Input clock</td>
7701 </tr>
7702 <tr class="row-odd"><td>1</td>
7703 <td>DEV_MCASP10_AUX_CLK</td>
7704 <td>Input muxed clock</td>
7705 </tr>
7706 <tr class="row-even"><td>2</td>
7707 <td>DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
7708 <td>Parent input clock option to DEV_MCASP10_AUX_CLK</td>
7709 </tr>
7710 <tr class="row-odd"><td>3</td>
7711 <td>DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
7712 <td>Parent input clock option to DEV_MCASP10_AUX_CLK</td>
7713 </tr>
7714 <tr class="row-even"><td>4</td>
7715 <td>DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
7716 <td>Parent input clock option to DEV_MCASP10_AUX_CLK</td>
7717 </tr>
7718 <tr class="row-odd"><td>6</td>
7719 <td>DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7720 <td>Parent input clock option to DEV_MCASP10_AUX_CLK</td>
7721 </tr>
7722 <tr class="row-even"><td>7</td>
7723 <td>DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7724 <td>Parent input clock option to DEV_MCASP10_AUX_CLK</td>
7725 </tr>
7726 <tr class="row-odd"><td>8</td>
7727 <td>DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7728 <td>Parent input clock option to DEV_MCASP10_AUX_CLK</td>
7729 </tr>
7730 <tr class="row-even"><td>9</td>
7731 <td>DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7732 <td>Parent input clock option to DEV_MCASP10_AUX_CLK</td>
7733 </tr>
7734 <tr class="row-odd"><td>10</td>
7735 <td>DEV_MCASP10_MCASP_ACLKX_POUT</td>
7736 <td>Output clock</td>
7737 </tr>
7738 <tr class="row-even"><td>11</td>
7739 <td>DEV_MCASP10_MCASP_ACLKX_PIN</td>
7740 <td>Input clock</td>
7741 </tr>
7742 <tr class="row-odd"><td>12</td>
7743 <td>DEV_MCASP10_MCASP_ACLKR_POUT</td>
7744 <td>Output clock</td>
7745 </tr>
7746 <tr class="row-even"><td>13</td>
7747 <td>DEV_MCASP10_MCASP_ACLKR_PIN</td>
7748 <td>Input clock</td>
7749 </tr>
7750 <tr class="row-odd"><td>14</td>
7751 <td>DEV_MCASP10_MCASP_AHCLKX_POUT</td>
7752 <td>Output clock</td>
7753 </tr>
7754 <tr class="row-even"><td>15</td>
7755 <td>DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7756 <td>Input muxed clock</td>
7757 </tr>
7758 <tr class="row-odd"><td>16</td>
7759 <td>DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7760 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7761 </tr>
7762 <tr class="row-even"><td>17</td>
7763 <td>DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7764 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7765 </tr>
7766 <tr class="row-odd"><td>18</td>
7767 <td>DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
7768 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7769 </tr>
7770 <tr class="row-even"><td>19</td>
7771 <td>DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
7772 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7773 </tr>
7774 <tr class="row-odd"><td>20</td>
7775 <td>DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
7776 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7777 </tr>
7778 <tr class="row-even"><td>21</td>
7779 <td>DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
7780 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7781 </tr>
7782 <tr class="row-odd"><td>22</td>
7783 <td>DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
7784 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7785 </tr>
7786 <tr class="row-even"><td>23</td>
7787 <td>DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
7788 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7789 </tr>
7790 <tr class="row-odd"><td>24</td>
7791 <td>DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7792 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7793 </tr>
7794 <tr class="row-even"><td>25</td>
7795 <td>DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7796 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7797 </tr>
7798 <tr class="row-odd"><td>26</td>
7799 <td>DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7800 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7801 </tr>
7802 <tr class="row-even"><td>27</td>
7803 <td>DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7804 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN</td>
7805 </tr>
7806 <tr class="row-odd"><td>28</td>
7807 <td>DEV_MCASP10_MCASP_AHCLKR_POUT</td>
7808 <td>Output clock</td>
7809 </tr>
7810 <tr class="row-even"><td>29</td>
7811 <td>DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7812 <td>Input muxed clock</td>
7813 </tr>
7814 <tr class="row-odd"><td>30</td>
7815 <td>DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7816 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7817 </tr>
7818 <tr class="row-even"><td>31</td>
7819 <td>DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7820 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7821 </tr>
7822 <tr class="row-odd"><td>32</td>
7823 <td>DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
7824 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7825 </tr>
7826 <tr class="row-even"><td>33</td>
7827 <td>DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
7828 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7829 </tr>
7830 <tr class="row-odd"><td>34</td>
7831 <td>DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
7832 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7833 </tr>
7834 <tr class="row-even"><td>35</td>
7835 <td>DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
7836 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7837 </tr>
7838 <tr class="row-odd"><td>36</td>
7839 <td>DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
7840 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7841 </tr>
7842 <tr class="row-even"><td>37</td>
7843 <td>DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
7844 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7845 </tr>
7846 <tr class="row-odd"><td>38</td>
7847 <td>DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7848 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7849 </tr>
7850 <tr class="row-even"><td>39</td>
7851 <td>DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7852 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7853 </tr>
7854 <tr class="row-odd"><td>40</td>
7855 <td>DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7856 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7857 </tr>
7858 <tr class="row-even"><td>41</td>
7859 <td>DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7860 <td>Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN</td>
7861 </tr>
7862 </tbody>
7863 </table>
7864 </div>
7865 <div class="section" id="clocks-for-mcasp11-device">
7866 <span id="soc-doc-j721e-public-clks-mcasp11"></span><h3>Clocks for MCASP11 Device<a class="headerlink" href="#clocks-for-mcasp11-device" title="Permalink to this headline">¶</a></h3>
7867 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCASP11</span></a> (ID = 185)</p>
7868 <p>Following is a mapping of Clocks IDs to function:</p>
7869 <table border="1" class="docutils">
7870 <colgroup>
7871 <col width="8%" />
7872 <col width="50%" />
7873 <col width="41%" />
7874 </colgroup>
7875 <thead valign="bottom">
7876 <tr class="row-odd"><th class="head">Clock ID</th>
7877 <th class="head">Name</th>
7878 <th class="head">Function</th>
7879 </tr>
7880 </thead>
7881 <tbody valign="top">
7882 <tr class="row-even"><td>0</td>
7883 <td>DEV_MCASP11_VBUSP_CLK</td>
7884 <td>Input clock</td>
7885 </tr>
7886 <tr class="row-odd"><td>1</td>
7887 <td>DEV_MCASP11_AUX_CLK</td>
7888 <td>Input muxed clock</td>
7889 </tr>
7890 <tr class="row-even"><td>2</td>
7891 <td>DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
7892 <td>Parent input clock option to DEV_MCASP11_AUX_CLK</td>
7893 </tr>
7894 <tr class="row-odd"><td>3</td>
7895 <td>DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
7896 <td>Parent input clock option to DEV_MCASP11_AUX_CLK</td>
7897 </tr>
7898 <tr class="row-even"><td>4</td>
7899 <td>DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
7900 <td>Parent input clock option to DEV_MCASP11_AUX_CLK</td>
7901 </tr>
7902 <tr class="row-odd"><td>6</td>
7903 <td>DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7904 <td>Parent input clock option to DEV_MCASP11_AUX_CLK</td>
7905 </tr>
7906 <tr class="row-even"><td>7</td>
7907 <td>DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7908 <td>Parent input clock option to DEV_MCASP11_AUX_CLK</td>
7909 </tr>
7910 <tr class="row-odd"><td>8</td>
7911 <td>DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7912 <td>Parent input clock option to DEV_MCASP11_AUX_CLK</td>
7913 </tr>
7914 <tr class="row-even"><td>9</td>
7915 <td>DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7916 <td>Parent input clock option to DEV_MCASP11_AUX_CLK</td>
7917 </tr>
7918 <tr class="row-odd"><td>10</td>
7919 <td>DEV_MCASP11_MCASP_ACLKX_POUT</td>
7920 <td>Output clock</td>
7921 </tr>
7922 <tr class="row-even"><td>11</td>
7923 <td>DEV_MCASP11_MCASP_ACLKX_PIN</td>
7924 <td>Input clock</td>
7925 </tr>
7926 <tr class="row-odd"><td>12</td>
7927 <td>DEV_MCASP11_MCASP_ACLKR_POUT</td>
7928 <td>Output clock</td>
7929 </tr>
7930 <tr class="row-even"><td>13</td>
7931 <td>DEV_MCASP11_MCASP_ACLKR_PIN</td>
7932 <td>Input clock</td>
7933 </tr>
7934 <tr class="row-odd"><td>14</td>
7935 <td>DEV_MCASP11_MCASP_AHCLKX_POUT</td>
7936 <td>Output clock</td>
7937 </tr>
7938 <tr class="row-even"><td>15</td>
7939 <td>DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7940 <td>Input muxed clock</td>
7941 </tr>
7942 <tr class="row-odd"><td>16</td>
7943 <td>DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7944 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7945 </tr>
7946 <tr class="row-even"><td>17</td>
7947 <td>DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7948 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7949 </tr>
7950 <tr class="row-odd"><td>18</td>
7951 <td>DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
7952 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7953 </tr>
7954 <tr class="row-even"><td>19</td>
7955 <td>DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
7956 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7957 </tr>
7958 <tr class="row-odd"><td>20</td>
7959 <td>DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
7960 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7961 </tr>
7962 <tr class="row-even"><td>21</td>
7963 <td>DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
7964 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7965 </tr>
7966 <tr class="row-odd"><td>22</td>
7967 <td>DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
7968 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7969 </tr>
7970 <tr class="row-even"><td>23</td>
7971 <td>DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
7972 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7973 </tr>
7974 <tr class="row-odd"><td>24</td>
7975 <td>DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7976 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7977 </tr>
7978 <tr class="row-even"><td>25</td>
7979 <td>DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7980 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7981 </tr>
7982 <tr class="row-odd"><td>26</td>
7983 <td>DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7984 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7985 </tr>
7986 <tr class="row-even"><td>27</td>
7987 <td>DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7988 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN</td>
7989 </tr>
7990 <tr class="row-odd"><td>28</td>
7991 <td>DEV_MCASP11_MCASP_AHCLKR_POUT</td>
7992 <td>Output clock</td>
7993 </tr>
7994 <tr class="row-even"><td>29</td>
7995 <td>DEV_MCASP11_MCASP_AHCLKR_PIN</td>
7996 <td>Input muxed clock</td>
7997 </tr>
7998 <tr class="row-odd"><td>30</td>
7999 <td>DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
8000 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN</td>
8001 </tr>
8002 <tr class="row-even"><td>31</td>
8003 <td>DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8004 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN</td>
8005 </tr>
8006 <tr class="row-odd"><td>32</td>
8007 <td>DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
8008 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN</td>
8009 </tr>
8010 <tr class="row-even"><td>33</td>
8011 <td>DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
8012 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN</td>
8013 </tr>
8014 <tr class="row-odd"><td>34</td>
8015 <td>DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
8016 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN</td>
8017 </tr>
8018 <tr class="row-even"><td>35</td>
8019 <td>DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
8020 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN</td>
8021 </tr>
8022 <tr class="row-odd"><td>36</td>
8023 <td>DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
8024 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN</td>
8025 </tr>
8026 <tr class="row-even"><td>37</td>
8027 <td>DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
8028 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN</td>
8029 </tr>
8030 <tr class="row-odd"><td>38</td>
8031 <td>DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8032 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN</td>
8033 </tr>
8034 <tr class="row-even"><td>39</td>
8035 <td>DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8036 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN</td>
8037 </tr>
8038 <tr class="row-odd"><td>40</td>
8039 <td>DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8040 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN</td>
8041 </tr>
8042 <tr class="row-even"><td>41</td>
8043 <td>DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8044 <td>Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN</td>
8045 </tr>
8046 </tbody>
8047 </table>
8048 </div>
8049 <div class="section" id="clocks-for-mcasp2-device">
8050 <span id="soc-doc-j721e-public-clks-mcasp2"></span><h3>Clocks for MCASP2 Device<a class="headerlink" href="#clocks-for-mcasp2-device" title="Permalink to this headline">¶</a></h3>
8051 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCASP2</span></a> (ID = 176)</p>
8052 <p>Following is a mapping of Clocks IDs to function:</p>
8053 <table border="1" class="docutils">
8054 <colgroup>
8055 <col width="9%" />
8056 <col width="50%" />
8057 <col width="41%" />
8058 </colgroup>
8059 <thead valign="bottom">
8060 <tr class="row-odd"><th class="head">Clock ID</th>
8061 <th class="head">Name</th>
8062 <th class="head">Function</th>
8063 </tr>
8064 </thead>
8065 <tbody valign="top">
8066 <tr class="row-even"><td>0</td>
8067 <td>DEV_MCASP2_VBUSP_CLK</td>
8068 <td>Input clock</td>
8069 </tr>
8070 <tr class="row-odd"><td>1</td>
8071 <td>DEV_MCASP2_AUX_CLK</td>
8072 <td>Input muxed clock</td>
8073 </tr>
8074 <tr class="row-even"><td>2</td>
8075 <td>DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
8076 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
8077 </tr>
8078 <tr class="row-odd"><td>3</td>
8079 <td>DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
8080 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
8081 </tr>
8082 <tr class="row-even"><td>4</td>
8083 <td>DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
8084 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
8085 </tr>
8086 <tr class="row-odd"><td>6</td>
8087 <td>DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8088 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
8089 </tr>
8090 <tr class="row-even"><td>7</td>
8091 <td>DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8092 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
8093 </tr>
8094 <tr class="row-odd"><td>8</td>
8095 <td>DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8096 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
8097 </tr>
8098 <tr class="row-even"><td>9</td>
8099 <td>DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8100 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
8101 </tr>
8102 <tr class="row-odd"><td>10</td>
8103 <td>DEV_MCASP2_MCASP_ACLKX_POUT</td>
8104 <td>Output clock</td>
8105 </tr>
8106 <tr class="row-even"><td>11</td>
8107 <td>DEV_MCASP2_MCASP_ACLKX_PIN</td>
8108 <td>Input clock</td>
8109 </tr>
8110 <tr class="row-odd"><td>12</td>
8111 <td>DEV_MCASP2_MCASP_ACLKR_POUT</td>
8112 <td>Output clock</td>
8113 </tr>
8114 <tr class="row-even"><td>13</td>
8115 <td>DEV_MCASP2_MCASP_ACLKR_PIN</td>
8116 <td>Input clock</td>
8117 </tr>
8118 <tr class="row-odd"><td>14</td>
8119 <td>DEV_MCASP2_MCASP_AHCLKX_POUT</td>
8120 <td>Output clock</td>
8121 </tr>
8122 <tr class="row-even"><td>15</td>
8123 <td>DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8124 <td>Input muxed clock</td>
8125 </tr>
8126 <tr class="row-odd"><td>16</td>
8127 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
8128 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8129 </tr>
8130 <tr class="row-even"><td>17</td>
8131 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8132 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8133 </tr>
8134 <tr class="row-odd"><td>18</td>
8135 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
8136 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8137 </tr>
8138 <tr class="row-even"><td>19</td>
8139 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
8140 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8141 </tr>
8142 <tr class="row-odd"><td>20</td>
8143 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
8144 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8145 </tr>
8146 <tr class="row-even"><td>21</td>
8147 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
8148 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8149 </tr>
8150 <tr class="row-odd"><td>22</td>
8151 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
8152 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8153 </tr>
8154 <tr class="row-even"><td>23</td>
8155 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
8156 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8157 </tr>
8158 <tr class="row-odd"><td>24</td>
8159 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8160 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8161 </tr>
8162 <tr class="row-even"><td>25</td>
8163 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8164 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8165 </tr>
8166 <tr class="row-odd"><td>26</td>
8167 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8168 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8169 </tr>
8170 <tr class="row-even"><td>27</td>
8171 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8172 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
8173 </tr>
8174 <tr class="row-odd"><td>28</td>
8175 <td>DEV_MCASP2_MCASP_AHCLKR_POUT</td>
8176 <td>Output clock</td>
8177 </tr>
8178 <tr class="row-even"><td>29</td>
8179 <td>DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8180 <td>Input muxed clock</td>
8181 </tr>
8182 <tr class="row-odd"><td>30</td>
8183 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
8184 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8185 </tr>
8186 <tr class="row-even"><td>31</td>
8187 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8188 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8189 </tr>
8190 <tr class="row-odd"><td>32</td>
8191 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
8192 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8193 </tr>
8194 <tr class="row-even"><td>33</td>
8195 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
8196 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8197 </tr>
8198 <tr class="row-odd"><td>34</td>
8199 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
8200 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8201 </tr>
8202 <tr class="row-even"><td>35</td>
8203 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
8204 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8205 </tr>
8206 <tr class="row-odd"><td>36</td>
8207 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
8208 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8209 </tr>
8210 <tr class="row-even"><td>37</td>
8211 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
8212 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8213 </tr>
8214 <tr class="row-odd"><td>38</td>
8215 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8216 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8217 </tr>
8218 <tr class="row-even"><td>39</td>
8219 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8220 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8221 </tr>
8222 <tr class="row-odd"><td>40</td>
8223 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8224 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8225 </tr>
8226 <tr class="row-even"><td>41</td>
8227 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8228 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
8229 </tr>
8230 </tbody>
8231 </table>
8232 </div>
8233 <div class="section" id="clocks-for-mcasp3-device">
8234 <span id="soc-doc-j721e-public-clks-mcasp3"></span><h3>Clocks for MCASP3 Device<a class="headerlink" href="#clocks-for-mcasp3-device" title="Permalink to this headline">¶</a></h3>
8235 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCASP3</span></a> (ID = 177)</p>
8236 <p>Following is a mapping of Clocks IDs to function:</p>
8237 <table border="1" class="docutils">
8238 <colgroup>
8239 <col width="9%" />
8240 <col width="50%" />
8241 <col width="41%" />
8242 </colgroup>
8243 <thead valign="bottom">
8244 <tr class="row-odd"><th class="head">Clock ID</th>
8245 <th class="head">Name</th>
8246 <th class="head">Function</th>
8247 </tr>
8248 </thead>
8249 <tbody valign="top">
8250 <tr class="row-even"><td>0</td>
8251 <td>DEV_MCASP3_VBUSP_CLK</td>
8252 <td>Input clock</td>
8253 </tr>
8254 <tr class="row-odd"><td>1</td>
8255 <td>DEV_MCASP3_AUX_CLK</td>
8256 <td>Input muxed clock</td>
8257 </tr>
8258 <tr class="row-even"><td>2</td>
8259 <td>DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
8260 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
8261 </tr>
8262 <tr class="row-odd"><td>3</td>
8263 <td>DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
8264 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
8265 </tr>
8266 <tr class="row-even"><td>4</td>
8267 <td>DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
8268 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
8269 </tr>
8270 <tr class="row-odd"><td>6</td>
8271 <td>DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8272 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
8273 </tr>
8274 <tr class="row-even"><td>7</td>
8275 <td>DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8276 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
8277 </tr>
8278 <tr class="row-odd"><td>8</td>
8279 <td>DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8280 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
8281 </tr>
8282 <tr class="row-even"><td>9</td>
8283 <td>DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8284 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
8285 </tr>
8286 <tr class="row-odd"><td>10</td>
8287 <td>DEV_MCASP3_MCASP_ACLKX_POUT</td>
8288 <td>Output clock</td>
8289 </tr>
8290 <tr class="row-even"><td>11</td>
8291 <td>DEV_MCASP3_MCASP_ACLKX_PIN</td>
8292 <td>Input clock</td>
8293 </tr>
8294 <tr class="row-odd"><td>12</td>
8295 <td>DEV_MCASP3_MCASP_ACLKR_POUT</td>
8296 <td>Output clock</td>
8297 </tr>
8298 <tr class="row-even"><td>13</td>
8299 <td>DEV_MCASP3_MCASP_ACLKR_PIN</td>
8300 <td>Input clock</td>
8301 </tr>
8302 <tr class="row-odd"><td>14</td>
8303 <td>DEV_MCASP3_MCASP_AHCLKX_POUT</td>
8304 <td>Output clock</td>
8305 </tr>
8306 <tr class="row-even"><td>15</td>
8307 <td>DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8308 <td>Input muxed clock</td>
8309 </tr>
8310 <tr class="row-odd"><td>16</td>
8311 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
8312 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8313 </tr>
8314 <tr class="row-even"><td>17</td>
8315 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8316 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8317 </tr>
8318 <tr class="row-odd"><td>18</td>
8319 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
8320 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8321 </tr>
8322 <tr class="row-even"><td>19</td>
8323 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
8324 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8325 </tr>
8326 <tr class="row-odd"><td>20</td>
8327 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
8328 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8329 </tr>
8330 <tr class="row-even"><td>21</td>
8331 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
8332 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8333 </tr>
8334 <tr class="row-odd"><td>22</td>
8335 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
8336 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8337 </tr>
8338 <tr class="row-even"><td>23</td>
8339 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
8340 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8341 </tr>
8342 <tr class="row-odd"><td>24</td>
8343 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8344 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8345 </tr>
8346 <tr class="row-even"><td>25</td>
8347 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8348 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8349 </tr>
8350 <tr class="row-odd"><td>26</td>
8351 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8352 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8353 </tr>
8354 <tr class="row-even"><td>27</td>
8355 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8356 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
8357 </tr>
8358 <tr class="row-odd"><td>28</td>
8359 <td>DEV_MCASP3_MCASP_AHCLKR_POUT</td>
8360 <td>Output clock</td>
8361 </tr>
8362 <tr class="row-even"><td>29</td>
8363 <td>DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8364 <td>Input muxed clock</td>
8365 </tr>
8366 <tr class="row-odd"><td>30</td>
8367 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
8368 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8369 </tr>
8370 <tr class="row-even"><td>31</td>
8371 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8372 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8373 </tr>
8374 <tr class="row-odd"><td>32</td>
8375 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
8376 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8377 </tr>
8378 <tr class="row-even"><td>33</td>
8379 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
8380 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8381 </tr>
8382 <tr class="row-odd"><td>34</td>
8383 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
8384 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8385 </tr>
8386 <tr class="row-even"><td>35</td>
8387 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
8388 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8389 </tr>
8390 <tr class="row-odd"><td>36</td>
8391 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
8392 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8393 </tr>
8394 <tr class="row-even"><td>37</td>
8395 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
8396 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8397 </tr>
8398 <tr class="row-odd"><td>38</td>
8399 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8400 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8401 </tr>
8402 <tr class="row-even"><td>39</td>
8403 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8404 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8405 </tr>
8406 <tr class="row-odd"><td>40</td>
8407 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8408 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8409 </tr>
8410 <tr class="row-even"><td>41</td>
8411 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8412 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
8413 </tr>
8414 </tbody>
8415 </table>
8416 </div>
8417 <div class="section" id="clocks-for-mcasp4-device">
8418 <span id="soc-doc-j721e-public-clks-mcasp4"></span><h3>Clocks for MCASP4 Device<a class="headerlink" href="#clocks-for-mcasp4-device" title="Permalink to this headline">¶</a></h3>
8419 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCASP4</span></a> (ID = 178)</p>
8420 <p>Following is a mapping of Clocks IDs to function:</p>
8421 <table border="1" class="docutils">
8422 <colgroup>
8423 <col width="9%" />
8424 <col width="50%" />
8425 <col width="41%" />
8426 </colgroup>
8427 <thead valign="bottom">
8428 <tr class="row-odd"><th class="head">Clock ID</th>
8429 <th class="head">Name</th>
8430 <th class="head">Function</th>
8431 </tr>
8432 </thead>
8433 <tbody valign="top">
8434 <tr class="row-even"><td>0</td>
8435 <td>DEV_MCASP4_VBUSP_CLK</td>
8436 <td>Input clock</td>
8437 </tr>
8438 <tr class="row-odd"><td>1</td>
8439 <td>DEV_MCASP4_AUX_CLK</td>
8440 <td>Input muxed clock</td>
8441 </tr>
8442 <tr class="row-even"><td>2</td>
8443 <td>DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
8444 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
8445 </tr>
8446 <tr class="row-odd"><td>3</td>
8447 <td>DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
8448 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
8449 </tr>
8450 <tr class="row-even"><td>4</td>
8451 <td>DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
8452 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
8453 </tr>
8454 <tr class="row-odd"><td>6</td>
8455 <td>DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8456 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
8457 </tr>
8458 <tr class="row-even"><td>7</td>
8459 <td>DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8460 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
8461 </tr>
8462 <tr class="row-odd"><td>8</td>
8463 <td>DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8464 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
8465 </tr>
8466 <tr class="row-even"><td>9</td>
8467 <td>DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8468 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
8469 </tr>
8470 <tr class="row-odd"><td>10</td>
8471 <td>DEV_MCASP4_MCASP_ACLKX_POUT</td>
8472 <td>Output clock</td>
8473 </tr>
8474 <tr class="row-even"><td>11</td>
8475 <td>DEV_MCASP4_MCASP_ACLKX_PIN</td>
8476 <td>Input clock</td>
8477 </tr>
8478 <tr class="row-odd"><td>12</td>
8479 <td>DEV_MCASP4_MCASP_ACLKR_POUT</td>
8480 <td>Output clock</td>
8481 </tr>
8482 <tr class="row-even"><td>13</td>
8483 <td>DEV_MCASP4_MCASP_ACLKR_PIN</td>
8484 <td>Input clock</td>
8485 </tr>
8486 <tr class="row-odd"><td>14</td>
8487 <td>DEV_MCASP4_MCASP_AHCLKX_POUT</td>
8488 <td>Output clock</td>
8489 </tr>
8490 <tr class="row-even"><td>15</td>
8491 <td>DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8492 <td>Input muxed clock</td>
8493 </tr>
8494 <tr class="row-odd"><td>16</td>
8495 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
8496 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8497 </tr>
8498 <tr class="row-even"><td>17</td>
8499 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8500 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8501 </tr>
8502 <tr class="row-odd"><td>18</td>
8503 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
8504 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8505 </tr>
8506 <tr class="row-even"><td>19</td>
8507 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
8508 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8509 </tr>
8510 <tr class="row-odd"><td>20</td>
8511 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
8512 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8513 </tr>
8514 <tr class="row-even"><td>21</td>
8515 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
8516 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8517 </tr>
8518 <tr class="row-odd"><td>22</td>
8519 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
8520 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8521 </tr>
8522 <tr class="row-even"><td>23</td>
8523 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
8524 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8525 </tr>
8526 <tr class="row-odd"><td>24</td>
8527 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8528 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8529 </tr>
8530 <tr class="row-even"><td>25</td>
8531 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8532 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8533 </tr>
8534 <tr class="row-odd"><td>26</td>
8535 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8536 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8537 </tr>
8538 <tr class="row-even"><td>27</td>
8539 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8540 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
8541 </tr>
8542 <tr class="row-odd"><td>28</td>
8543 <td>DEV_MCASP4_MCASP_AHCLKR_POUT</td>
8544 <td>Output clock</td>
8545 </tr>
8546 <tr class="row-even"><td>29</td>
8547 <td>DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8548 <td>Input muxed clock</td>
8549 </tr>
8550 <tr class="row-odd"><td>30</td>
8551 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
8552 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8553 </tr>
8554 <tr class="row-even"><td>31</td>
8555 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8556 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8557 </tr>
8558 <tr class="row-odd"><td>32</td>
8559 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
8560 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8561 </tr>
8562 <tr class="row-even"><td>33</td>
8563 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
8564 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8565 </tr>
8566 <tr class="row-odd"><td>34</td>
8567 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
8568 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8569 </tr>
8570 <tr class="row-even"><td>35</td>
8571 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
8572 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8573 </tr>
8574 <tr class="row-odd"><td>36</td>
8575 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
8576 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8577 </tr>
8578 <tr class="row-even"><td>37</td>
8579 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
8580 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8581 </tr>
8582 <tr class="row-odd"><td>38</td>
8583 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8584 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8585 </tr>
8586 <tr class="row-even"><td>39</td>
8587 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8588 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8589 </tr>
8590 <tr class="row-odd"><td>40</td>
8591 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8592 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8593 </tr>
8594 <tr class="row-even"><td>41</td>
8595 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8596 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
8597 </tr>
8598 </tbody>
8599 </table>
8600 </div>
8601 <div class="section" id="clocks-for-mcasp5-device">
8602 <span id="soc-doc-j721e-public-clks-mcasp5"></span><h3>Clocks for MCASP5 Device<a class="headerlink" href="#clocks-for-mcasp5-device" title="Permalink to this headline">¶</a></h3>
8603 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCASP5</span></a> (ID = 179)</p>
8604 <p>Following is a mapping of Clocks IDs to function:</p>
8605 <table border="1" class="docutils">
8606 <colgroup>
8607 <col width="9%" />
8608 <col width="50%" />
8609 <col width="41%" />
8610 </colgroup>
8611 <thead valign="bottom">
8612 <tr class="row-odd"><th class="head">Clock ID</th>
8613 <th class="head">Name</th>
8614 <th class="head">Function</th>
8615 </tr>
8616 </thead>
8617 <tbody valign="top">
8618 <tr class="row-even"><td>0</td>
8619 <td>DEV_MCASP5_VBUSP_CLK</td>
8620 <td>Input clock</td>
8621 </tr>
8622 <tr class="row-odd"><td>1</td>
8623 <td>DEV_MCASP5_AUX_CLK</td>
8624 <td>Input muxed clock</td>
8625 </tr>
8626 <tr class="row-even"><td>2</td>
8627 <td>DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
8628 <td>Parent input clock option to DEV_MCASP5_AUX_CLK</td>
8629 </tr>
8630 <tr class="row-odd"><td>3</td>
8631 <td>DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
8632 <td>Parent input clock option to DEV_MCASP5_AUX_CLK</td>
8633 </tr>
8634 <tr class="row-even"><td>4</td>
8635 <td>DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
8636 <td>Parent input clock option to DEV_MCASP5_AUX_CLK</td>
8637 </tr>
8638 <tr class="row-odd"><td>6</td>
8639 <td>DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8640 <td>Parent input clock option to DEV_MCASP5_AUX_CLK</td>
8641 </tr>
8642 <tr class="row-even"><td>7</td>
8643 <td>DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8644 <td>Parent input clock option to DEV_MCASP5_AUX_CLK</td>
8645 </tr>
8646 <tr class="row-odd"><td>8</td>
8647 <td>DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8648 <td>Parent input clock option to DEV_MCASP5_AUX_CLK</td>
8649 </tr>
8650 <tr class="row-even"><td>9</td>
8651 <td>DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8652 <td>Parent input clock option to DEV_MCASP5_AUX_CLK</td>
8653 </tr>
8654 <tr class="row-odd"><td>10</td>
8655 <td>DEV_MCASP5_MCASP_ACLKX_POUT</td>
8656 <td>Output clock</td>
8657 </tr>
8658 <tr class="row-even"><td>11</td>
8659 <td>DEV_MCASP5_MCASP_ACLKX_PIN</td>
8660 <td>Input clock</td>
8661 </tr>
8662 <tr class="row-odd"><td>12</td>
8663 <td>DEV_MCASP5_MCASP_ACLKR_POUT</td>
8664 <td>Output clock</td>
8665 </tr>
8666 <tr class="row-even"><td>13</td>
8667 <td>DEV_MCASP5_MCASP_ACLKR_PIN</td>
8668 <td>Input clock</td>
8669 </tr>
8670 <tr class="row-odd"><td>14</td>
8671 <td>DEV_MCASP5_MCASP_AHCLKX_POUT</td>
8672 <td>Output clock</td>
8673 </tr>
8674 <tr class="row-even"><td>15</td>
8675 <td>DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8676 <td>Input muxed clock</td>
8677 </tr>
8678 <tr class="row-odd"><td>16</td>
8679 <td>DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
8680 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8681 </tr>
8682 <tr class="row-even"><td>17</td>
8683 <td>DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8684 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8685 </tr>
8686 <tr class="row-odd"><td>18</td>
8687 <td>DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
8688 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8689 </tr>
8690 <tr class="row-even"><td>19</td>
8691 <td>DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
8692 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8693 </tr>
8694 <tr class="row-odd"><td>20</td>
8695 <td>DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
8696 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8697 </tr>
8698 <tr class="row-even"><td>21</td>
8699 <td>DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
8700 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8701 </tr>
8702 <tr class="row-odd"><td>22</td>
8703 <td>DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
8704 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8705 </tr>
8706 <tr class="row-even"><td>23</td>
8707 <td>DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
8708 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8709 </tr>
8710 <tr class="row-odd"><td>24</td>
8711 <td>DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8712 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8713 </tr>
8714 <tr class="row-even"><td>25</td>
8715 <td>DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8716 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8717 </tr>
8718 <tr class="row-odd"><td>26</td>
8719 <td>DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8720 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8721 </tr>
8722 <tr class="row-even"><td>27</td>
8723 <td>DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8724 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN</td>
8725 </tr>
8726 <tr class="row-odd"><td>28</td>
8727 <td>DEV_MCASP5_MCASP_AHCLKR_POUT</td>
8728 <td>Output clock</td>
8729 </tr>
8730 <tr class="row-even"><td>29</td>
8731 <td>DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8732 <td>Input muxed clock</td>
8733 </tr>
8734 <tr class="row-odd"><td>30</td>
8735 <td>DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
8736 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8737 </tr>
8738 <tr class="row-even"><td>31</td>
8739 <td>DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8740 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8741 </tr>
8742 <tr class="row-odd"><td>32</td>
8743 <td>DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
8744 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8745 </tr>
8746 <tr class="row-even"><td>33</td>
8747 <td>DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
8748 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8749 </tr>
8750 <tr class="row-odd"><td>34</td>
8751 <td>DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
8752 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8753 </tr>
8754 <tr class="row-even"><td>35</td>
8755 <td>DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
8756 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8757 </tr>
8758 <tr class="row-odd"><td>36</td>
8759 <td>DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
8760 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8761 </tr>
8762 <tr class="row-even"><td>37</td>
8763 <td>DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
8764 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8765 </tr>
8766 <tr class="row-odd"><td>38</td>
8767 <td>DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8768 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8769 </tr>
8770 <tr class="row-even"><td>39</td>
8771 <td>DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8772 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8773 </tr>
8774 <tr class="row-odd"><td>40</td>
8775 <td>DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8776 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8777 </tr>
8778 <tr class="row-even"><td>41</td>
8779 <td>DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8780 <td>Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN</td>
8781 </tr>
8782 </tbody>
8783 </table>
8784 </div>
8785 <div class="section" id="clocks-for-mcasp6-device">
8786 <span id="soc-doc-j721e-public-clks-mcasp6"></span><h3>Clocks for MCASP6 Device<a class="headerlink" href="#clocks-for-mcasp6-device" title="Permalink to this headline">¶</a></h3>
8787 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCASP6</span></a> (ID = 180)</p>
8788 <p>Following is a mapping of Clocks IDs to function:</p>
8789 <table border="1" class="docutils">
8790 <colgroup>
8791 <col width="9%" />
8792 <col width="50%" />
8793 <col width="41%" />
8794 </colgroup>
8795 <thead valign="bottom">
8796 <tr class="row-odd"><th class="head">Clock ID</th>
8797 <th class="head">Name</th>
8798 <th class="head">Function</th>
8799 </tr>
8800 </thead>
8801 <tbody valign="top">
8802 <tr class="row-even"><td>0</td>
8803 <td>DEV_MCASP6_VBUSP_CLK</td>
8804 <td>Input clock</td>
8805 </tr>
8806 <tr class="row-odd"><td>1</td>
8807 <td>DEV_MCASP6_AUX_CLK</td>
8808 <td>Input muxed clock</td>
8809 </tr>
8810 <tr class="row-even"><td>2</td>
8811 <td>DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
8812 <td>Parent input clock option to DEV_MCASP6_AUX_CLK</td>
8813 </tr>
8814 <tr class="row-odd"><td>3</td>
8815 <td>DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
8816 <td>Parent input clock option to DEV_MCASP6_AUX_CLK</td>
8817 </tr>
8818 <tr class="row-even"><td>4</td>
8819 <td>DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
8820 <td>Parent input clock option to DEV_MCASP6_AUX_CLK</td>
8821 </tr>
8822 <tr class="row-odd"><td>6</td>
8823 <td>DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8824 <td>Parent input clock option to DEV_MCASP6_AUX_CLK</td>
8825 </tr>
8826 <tr class="row-even"><td>7</td>
8827 <td>DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8828 <td>Parent input clock option to DEV_MCASP6_AUX_CLK</td>
8829 </tr>
8830 <tr class="row-odd"><td>8</td>
8831 <td>DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8832 <td>Parent input clock option to DEV_MCASP6_AUX_CLK</td>
8833 </tr>
8834 <tr class="row-even"><td>9</td>
8835 <td>DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8836 <td>Parent input clock option to DEV_MCASP6_AUX_CLK</td>
8837 </tr>
8838 <tr class="row-odd"><td>10</td>
8839 <td>DEV_MCASP6_MCASP_ACLKX_POUT</td>
8840 <td>Output clock</td>
8841 </tr>
8842 <tr class="row-even"><td>11</td>
8843 <td>DEV_MCASP6_MCASP_ACLKX_PIN</td>
8844 <td>Input clock</td>
8845 </tr>
8846 <tr class="row-odd"><td>12</td>
8847 <td>DEV_MCASP6_MCASP_ACLKR_POUT</td>
8848 <td>Output clock</td>
8849 </tr>
8850 <tr class="row-even"><td>13</td>
8851 <td>DEV_MCASP6_MCASP_ACLKR_PIN</td>
8852 <td>Input clock</td>
8853 </tr>
8854 <tr class="row-odd"><td>14</td>
8855 <td>DEV_MCASP6_MCASP_AHCLKX_POUT</td>
8856 <td>Output clock</td>
8857 </tr>
8858 <tr class="row-even"><td>15</td>
8859 <td>DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8860 <td>Input muxed clock</td>
8861 </tr>
8862 <tr class="row-odd"><td>16</td>
8863 <td>DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
8864 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8865 </tr>
8866 <tr class="row-even"><td>17</td>
8867 <td>DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8868 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8869 </tr>
8870 <tr class="row-odd"><td>18</td>
8871 <td>DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
8872 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8873 </tr>
8874 <tr class="row-even"><td>19</td>
8875 <td>DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
8876 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8877 </tr>
8878 <tr class="row-odd"><td>20</td>
8879 <td>DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
8880 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8881 </tr>
8882 <tr class="row-even"><td>21</td>
8883 <td>DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
8884 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8885 </tr>
8886 <tr class="row-odd"><td>22</td>
8887 <td>DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
8888 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8889 </tr>
8890 <tr class="row-even"><td>23</td>
8891 <td>DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
8892 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8893 </tr>
8894 <tr class="row-odd"><td>24</td>
8895 <td>DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8896 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8897 </tr>
8898 <tr class="row-even"><td>25</td>
8899 <td>DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8900 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8901 </tr>
8902 <tr class="row-odd"><td>26</td>
8903 <td>DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8904 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8905 </tr>
8906 <tr class="row-even"><td>27</td>
8907 <td>DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8908 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN</td>
8909 </tr>
8910 <tr class="row-odd"><td>28</td>
8911 <td>DEV_MCASP6_MCASP_AHCLKR_POUT</td>
8912 <td>Output clock</td>
8913 </tr>
8914 <tr class="row-even"><td>29</td>
8915 <td>DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8916 <td>Input muxed clock</td>
8917 </tr>
8918 <tr class="row-odd"><td>30</td>
8919 <td>DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
8920 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8921 </tr>
8922 <tr class="row-even"><td>31</td>
8923 <td>DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8924 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8925 </tr>
8926 <tr class="row-odd"><td>32</td>
8927 <td>DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
8928 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8929 </tr>
8930 <tr class="row-even"><td>33</td>
8931 <td>DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
8932 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8933 </tr>
8934 <tr class="row-odd"><td>34</td>
8935 <td>DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
8936 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8937 </tr>
8938 <tr class="row-even"><td>35</td>
8939 <td>DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
8940 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8941 </tr>
8942 <tr class="row-odd"><td>36</td>
8943 <td>DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
8944 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8945 </tr>
8946 <tr class="row-even"><td>37</td>
8947 <td>DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
8948 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8949 </tr>
8950 <tr class="row-odd"><td>38</td>
8951 <td>DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
8952 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8953 </tr>
8954 <tr class="row-even"><td>39</td>
8955 <td>DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
8956 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8957 </tr>
8958 <tr class="row-odd"><td>40</td>
8959 <td>DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
8960 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8961 </tr>
8962 <tr class="row-even"><td>41</td>
8963 <td>DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
8964 <td>Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN</td>
8965 </tr>
8966 </tbody>
8967 </table>
8968 </div>
8969 <div class="section" id="clocks-for-mcasp7-device">
8970 <span id="soc-doc-j721e-public-clks-mcasp7"></span><h3>Clocks for MCASP7 Device<a class="headerlink" href="#clocks-for-mcasp7-device" title="Permalink to this headline">¶</a></h3>
8971 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCASP7</span></a> (ID = 181)</p>
8972 <p>Following is a mapping of Clocks IDs to function:</p>
8973 <table border="1" class="docutils">
8974 <colgroup>
8975 <col width="9%" />
8976 <col width="50%" />
8977 <col width="41%" />
8978 </colgroup>
8979 <thead valign="bottom">
8980 <tr class="row-odd"><th class="head">Clock ID</th>
8981 <th class="head">Name</th>
8982 <th class="head">Function</th>
8983 </tr>
8984 </thead>
8985 <tbody valign="top">
8986 <tr class="row-even"><td>0</td>
8987 <td>DEV_MCASP7_VBUSP_CLK</td>
8988 <td>Input clock</td>
8989 </tr>
8990 <tr class="row-odd"><td>1</td>
8991 <td>DEV_MCASP7_AUX_CLK</td>
8992 <td>Input muxed clock</td>
8993 </tr>
8994 <tr class="row-even"><td>2</td>
8995 <td>DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
8996 <td>Parent input clock option to DEV_MCASP7_AUX_CLK</td>
8997 </tr>
8998 <tr class="row-odd"><td>3</td>
8999 <td>DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
9000 <td>Parent input clock option to DEV_MCASP7_AUX_CLK</td>
9001 </tr>
9002 <tr class="row-even"><td>4</td>
9003 <td>DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
9004 <td>Parent input clock option to DEV_MCASP7_AUX_CLK</td>
9005 </tr>
9006 <tr class="row-odd"><td>6</td>
9007 <td>DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
9008 <td>Parent input clock option to DEV_MCASP7_AUX_CLK</td>
9009 </tr>
9010 <tr class="row-even"><td>7</td>
9011 <td>DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
9012 <td>Parent input clock option to DEV_MCASP7_AUX_CLK</td>
9013 </tr>
9014 <tr class="row-odd"><td>8</td>
9015 <td>DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
9016 <td>Parent input clock option to DEV_MCASP7_AUX_CLK</td>
9017 </tr>
9018 <tr class="row-even"><td>9</td>
9019 <td>DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
9020 <td>Parent input clock option to DEV_MCASP7_AUX_CLK</td>
9021 </tr>
9022 <tr class="row-odd"><td>10</td>
9023 <td>DEV_MCASP7_MCASP_ACLKX_POUT</td>
9024 <td>Output clock</td>
9025 </tr>
9026 <tr class="row-even"><td>11</td>
9027 <td>DEV_MCASP7_MCASP_ACLKX_PIN</td>
9028 <td>Input clock</td>
9029 </tr>
9030 <tr class="row-odd"><td>12</td>
9031 <td>DEV_MCASP7_MCASP_ACLKR_POUT</td>
9032 <td>Output clock</td>
9033 </tr>
9034 <tr class="row-even"><td>13</td>
9035 <td>DEV_MCASP7_MCASP_ACLKR_PIN</td>
9036 <td>Input clock</td>
9037 </tr>
9038 <tr class="row-odd"><td>14</td>
9039 <td>DEV_MCASP7_MCASP_AHCLKX_POUT</td>
9040 <td>Output clock</td>
9041 </tr>
9042 <tr class="row-even"><td>15</td>
9043 <td>DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9044 <td>Input muxed clock</td>
9045 </tr>
9046 <tr class="row-odd"><td>16</td>
9047 <td>DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
9048 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9049 </tr>
9050 <tr class="row-even"><td>17</td>
9051 <td>DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9052 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9053 </tr>
9054 <tr class="row-odd"><td>18</td>
9055 <td>DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
9056 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9057 </tr>
9058 <tr class="row-even"><td>19</td>
9059 <td>DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
9060 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9061 </tr>
9062 <tr class="row-odd"><td>20</td>
9063 <td>DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
9064 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9065 </tr>
9066 <tr class="row-even"><td>21</td>
9067 <td>DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
9068 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9069 </tr>
9070 <tr class="row-odd"><td>22</td>
9071 <td>DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
9072 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9073 </tr>
9074 <tr class="row-even"><td>23</td>
9075 <td>DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
9076 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9077 </tr>
9078 <tr class="row-odd"><td>24</td>
9079 <td>DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
9080 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9081 </tr>
9082 <tr class="row-even"><td>25</td>
9083 <td>DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
9084 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9085 </tr>
9086 <tr class="row-odd"><td>26</td>
9087 <td>DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
9088 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9089 </tr>
9090 <tr class="row-even"><td>27</td>
9091 <td>DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
9092 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN</td>
9093 </tr>
9094 <tr class="row-odd"><td>28</td>
9095 <td>DEV_MCASP7_MCASP_AHCLKR_POUT</td>
9096 <td>Output clock</td>
9097 </tr>
9098 <tr class="row-even"><td>29</td>
9099 <td>DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9100 <td>Input muxed clock</td>
9101 </tr>
9102 <tr class="row-odd"><td>30</td>
9103 <td>DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
9104 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9105 </tr>
9106 <tr class="row-even"><td>31</td>
9107 <td>DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9108 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9109 </tr>
9110 <tr class="row-odd"><td>32</td>
9111 <td>DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
9112 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9113 </tr>
9114 <tr class="row-even"><td>33</td>
9115 <td>DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
9116 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9117 </tr>
9118 <tr class="row-odd"><td>34</td>
9119 <td>DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
9120 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9121 </tr>
9122 <tr class="row-even"><td>35</td>
9123 <td>DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
9124 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9125 </tr>
9126 <tr class="row-odd"><td>36</td>
9127 <td>DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
9128 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9129 </tr>
9130 <tr class="row-even"><td>37</td>
9131 <td>DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
9132 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9133 </tr>
9134 <tr class="row-odd"><td>38</td>
9135 <td>DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
9136 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9137 </tr>
9138 <tr class="row-even"><td>39</td>
9139 <td>DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
9140 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9141 </tr>
9142 <tr class="row-odd"><td>40</td>
9143 <td>DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
9144 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9145 </tr>
9146 <tr class="row-even"><td>41</td>
9147 <td>DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
9148 <td>Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN</td>
9149 </tr>
9150 </tbody>
9151 </table>
9152 </div>
9153 <div class="section" id="clocks-for-mcasp8-device">
9154 <span id="soc-doc-j721e-public-clks-mcasp8"></span><h3>Clocks for MCASP8 Device<a class="headerlink" href="#clocks-for-mcasp8-device" title="Permalink to this headline">¶</a></h3>
9155 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCASP8</span></a> (ID = 182)</p>
9156 <p>Following is a mapping of Clocks IDs to function:</p>
9157 <table border="1" class="docutils">
9158 <colgroup>
9159 <col width="9%" />
9160 <col width="50%" />
9161 <col width="41%" />
9162 </colgroup>
9163 <thead valign="bottom">
9164 <tr class="row-odd"><th class="head">Clock ID</th>
9165 <th class="head">Name</th>
9166 <th class="head">Function</th>
9167 </tr>
9168 </thead>
9169 <tbody valign="top">
9170 <tr class="row-even"><td>0</td>
9171 <td>DEV_MCASP8_VBUSP_CLK</td>
9172 <td>Input clock</td>
9173 </tr>
9174 <tr class="row-odd"><td>1</td>
9175 <td>DEV_MCASP8_AUX_CLK</td>
9176 <td>Input muxed clock</td>
9177 </tr>
9178 <tr class="row-even"><td>2</td>
9179 <td>DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
9180 <td>Parent input clock option to DEV_MCASP8_AUX_CLK</td>
9181 </tr>
9182 <tr class="row-odd"><td>3</td>
9183 <td>DEV_MCASP8_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
9184 <td>Parent input clock option to DEV_MCASP8_AUX_CLK</td>
9185 </tr>
9186 <tr class="row-even"><td>4</td>
9187 <td>DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
9188 <td>Parent input clock option to DEV_MCASP8_AUX_CLK</td>
9189 </tr>
9190 <tr class="row-odd"><td>6</td>
9191 <td>DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
9192 <td>Parent input clock option to DEV_MCASP8_AUX_CLK</td>
9193 </tr>
9194 <tr class="row-even"><td>7</td>
9195 <td>DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
9196 <td>Parent input clock option to DEV_MCASP8_AUX_CLK</td>
9197 </tr>
9198 <tr class="row-odd"><td>8</td>
9199 <td>DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
9200 <td>Parent input clock option to DEV_MCASP8_AUX_CLK</td>
9201 </tr>
9202 <tr class="row-even"><td>9</td>
9203 <td>DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
9204 <td>Parent input clock option to DEV_MCASP8_AUX_CLK</td>
9205 </tr>
9206 <tr class="row-odd"><td>10</td>
9207 <td>DEV_MCASP8_MCASP_ACLKX_POUT</td>
9208 <td>Output clock</td>
9209 </tr>
9210 <tr class="row-even"><td>11</td>
9211 <td>DEV_MCASP8_MCASP_ACLKX_PIN</td>
9212 <td>Input clock</td>
9213 </tr>
9214 <tr class="row-odd"><td>12</td>
9215 <td>DEV_MCASP8_MCASP_ACLKR_POUT</td>
9216 <td>Output clock</td>
9217 </tr>
9218 <tr class="row-even"><td>13</td>
9219 <td>DEV_MCASP8_MCASP_ACLKR_PIN</td>
9220 <td>Input clock</td>
9221 </tr>
9222 <tr class="row-odd"><td>14</td>
9223 <td>DEV_MCASP8_MCASP_AHCLKX_POUT</td>
9224 <td>Output clock</td>
9225 </tr>
9226 <tr class="row-even"><td>15</td>
9227 <td>DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9228 <td>Input muxed clock</td>
9229 </tr>
9230 <tr class="row-odd"><td>16</td>
9231 <td>DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
9232 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9233 </tr>
9234 <tr class="row-even"><td>17</td>
9235 <td>DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9236 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9237 </tr>
9238 <tr class="row-odd"><td>18</td>
9239 <td>DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
9240 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9241 </tr>
9242 <tr class="row-even"><td>19</td>
9243 <td>DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
9244 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9245 </tr>
9246 <tr class="row-odd"><td>20</td>
9247 <td>DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
9248 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9249 </tr>
9250 <tr class="row-even"><td>21</td>
9251 <td>DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
9252 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9253 </tr>
9254 <tr class="row-odd"><td>22</td>
9255 <td>DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
9256 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9257 </tr>
9258 <tr class="row-even"><td>23</td>
9259 <td>DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
9260 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9261 </tr>
9262 <tr class="row-odd"><td>24</td>
9263 <td>DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
9264 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9265 </tr>
9266 <tr class="row-even"><td>25</td>
9267 <td>DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
9268 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9269 </tr>
9270 <tr class="row-odd"><td>26</td>
9271 <td>DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
9272 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9273 </tr>
9274 <tr class="row-even"><td>27</td>
9275 <td>DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
9276 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN</td>
9277 </tr>
9278 <tr class="row-odd"><td>28</td>
9279 <td>DEV_MCASP8_MCASP_AHCLKR_POUT</td>
9280 <td>Output clock</td>
9281 </tr>
9282 <tr class="row-even"><td>29</td>
9283 <td>DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9284 <td>Input muxed clock</td>
9285 </tr>
9286 <tr class="row-odd"><td>30</td>
9287 <td>DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
9288 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9289 </tr>
9290 <tr class="row-even"><td>31</td>
9291 <td>DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9292 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9293 </tr>
9294 <tr class="row-odd"><td>32</td>
9295 <td>DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
9296 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9297 </tr>
9298 <tr class="row-even"><td>33</td>
9299 <td>DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
9300 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9301 </tr>
9302 <tr class="row-odd"><td>34</td>
9303 <td>DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
9304 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9305 </tr>
9306 <tr class="row-even"><td>35</td>
9307 <td>DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
9308 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9309 </tr>
9310 <tr class="row-odd"><td>36</td>
9311 <td>DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
9312 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9313 </tr>
9314 <tr class="row-even"><td>37</td>
9315 <td>DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
9316 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9317 </tr>
9318 <tr class="row-odd"><td>38</td>
9319 <td>DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
9320 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9321 </tr>
9322 <tr class="row-even"><td>39</td>
9323 <td>DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
9324 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9325 </tr>
9326 <tr class="row-odd"><td>40</td>
9327 <td>DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
9328 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9329 </tr>
9330 <tr class="row-even"><td>41</td>
9331 <td>DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
9332 <td>Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN</td>
9333 </tr>
9334 </tbody>
9335 </table>
9336 </div>
9337 <div class="section" id="clocks-for-mcasp9-device">
9338 <span id="soc-doc-j721e-public-clks-mcasp9"></span><h3>Clocks for MCASP9 Device<a class="headerlink" href="#clocks-for-mcasp9-device" title="Permalink to this headline">¶</a></h3>
9339 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCASP9</span></a> (ID = 183)</p>
9340 <p>Following is a mapping of Clocks IDs to function:</p>
9341 <table border="1" class="docutils">
9342 <colgroup>
9343 <col width="9%" />
9344 <col width="50%" />
9345 <col width="41%" />
9346 </colgroup>
9347 <thead valign="bottom">
9348 <tr class="row-odd"><th class="head">Clock ID</th>
9349 <th class="head">Name</th>
9350 <th class="head">Function</th>
9351 </tr>
9352 </thead>
9353 <tbody valign="top">
9354 <tr class="row-even"><td>0</td>
9355 <td>DEV_MCASP9_VBUSP_CLK</td>
9356 <td>Input clock</td>
9357 </tr>
9358 <tr class="row-odd"><td>1</td>
9359 <td>DEV_MCASP9_AUX_CLK</td>
9360 <td>Input muxed clock</td>
9361 </tr>
9362 <tr class="row-even"><td>2</td>
9363 <td>DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
9364 <td>Parent input clock option to DEV_MCASP9_AUX_CLK</td>
9365 </tr>
9366 <tr class="row-odd"><td>3</td>
9367 <td>DEV_MCASP9_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
9368 <td>Parent input clock option to DEV_MCASP9_AUX_CLK</td>
9369 </tr>
9370 <tr class="row-even"><td>4</td>
9371 <td>DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK</td>
9372 <td>Parent input clock option to DEV_MCASP9_AUX_CLK</td>
9373 </tr>
9374 <tr class="row-odd"><td>6</td>
9375 <td>DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
9376 <td>Parent input clock option to DEV_MCASP9_AUX_CLK</td>
9377 </tr>
9378 <tr class="row-even"><td>7</td>
9379 <td>DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
9380 <td>Parent input clock option to DEV_MCASP9_AUX_CLK</td>
9381 </tr>
9382 <tr class="row-odd"><td>8</td>
9383 <td>DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
9384 <td>Parent input clock option to DEV_MCASP9_AUX_CLK</td>
9385 </tr>
9386 <tr class="row-even"><td>9</td>
9387 <td>DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
9388 <td>Parent input clock option to DEV_MCASP9_AUX_CLK</td>
9389 </tr>
9390 <tr class="row-odd"><td>10</td>
9391 <td>DEV_MCASP9_MCASP_ACLKX_POUT</td>
9392 <td>Output clock</td>
9393 </tr>
9394 <tr class="row-even"><td>11</td>
9395 <td>DEV_MCASP9_MCASP_ACLKX_PIN</td>
9396 <td>Input clock</td>
9397 </tr>
9398 <tr class="row-odd"><td>12</td>
9399 <td>DEV_MCASP9_MCASP_ACLKR_POUT</td>
9400 <td>Output clock</td>
9401 </tr>
9402 <tr class="row-even"><td>13</td>
9403 <td>DEV_MCASP9_MCASP_ACLKR_PIN</td>
9404 <td>Input clock</td>
9405 </tr>
9406 <tr class="row-odd"><td>14</td>
9407 <td>DEV_MCASP9_MCASP_AHCLKX_POUT</td>
9408 <td>Output clock</td>
9409 </tr>
9410 <tr class="row-even"><td>15</td>
9411 <td>DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9412 <td>Input muxed clock</td>
9413 </tr>
9414 <tr class="row-odd"><td>16</td>
9415 <td>DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
9416 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9417 </tr>
9418 <tr class="row-even"><td>17</td>
9419 <td>DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9420 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9421 </tr>
9422 <tr class="row-odd"><td>18</td>
9423 <td>DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
9424 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9425 </tr>
9426 <tr class="row-even"><td>19</td>
9427 <td>DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
9428 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9429 </tr>
9430 <tr class="row-odd"><td>20</td>
9431 <td>DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
9432 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9433 </tr>
9434 <tr class="row-even"><td>21</td>
9435 <td>DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
9436 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9437 </tr>
9438 <tr class="row-odd"><td>22</td>
9439 <td>DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
9440 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9441 </tr>
9442 <tr class="row-even"><td>23</td>
9443 <td>DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
9444 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9445 </tr>
9446 <tr class="row-odd"><td>24</td>
9447 <td>DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
9448 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9449 </tr>
9450 <tr class="row-even"><td>25</td>
9451 <td>DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
9452 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9453 </tr>
9454 <tr class="row-odd"><td>26</td>
9455 <td>DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
9456 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9457 </tr>
9458 <tr class="row-even"><td>27</td>
9459 <td>DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
9460 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN</td>
9461 </tr>
9462 <tr class="row-odd"><td>28</td>
9463 <td>DEV_MCASP9_MCASP_AHCLKR_POUT</td>
9464 <td>Output clock</td>
9465 </tr>
9466 <tr class="row-even"><td>29</td>
9467 <td>DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9468 <td>Input muxed clock</td>
9469 </tr>
9470 <tr class="row-odd"><td>30</td>
9471 <td>DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
9472 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9473 </tr>
9474 <tr class="row-even"><td>31</td>
9475 <td>DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9476 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9477 </tr>
9478 <tr class="row-odd"><td>32</td>
9479 <td>DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0</td>
9480 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9481 </tr>
9482 <tr class="row-even"><td>33</td>
9483 <td>DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1</td>
9484 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9485 </tr>
9486 <tr class="row-odd"><td>34</td>
9487 <td>DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2</td>
9488 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9489 </tr>
9490 <tr class="row-even"><td>35</td>
9491 <td>DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3</td>
9492 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9493 </tr>
9494 <tr class="row-odd"><td>36</td>
9495 <td>DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT</td>
9496 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9497 </tr>
9498 <tr class="row-even"><td>37</td>
9499 <td>DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2</td>
9500 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9501 </tr>
9502 <tr class="row-odd"><td>38</td>
9503 <td>DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
9504 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9505 </tr>
9506 <tr class="row-even"><td>39</td>
9507 <td>DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
9508 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9509 </tr>
9510 <tr class="row-odd"><td>40</td>
9511 <td>DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
9512 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9513 </tr>
9514 <tr class="row-even"><td>41</td>
9515 <td>DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
9516 <td>Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN</td>
9517 </tr>
9518 </tbody>
9519 </table>
9520 </div>
9521 <div class="section" id="clocks-for-mcspi0-device">
9522 <span id="soc-doc-j721e-public-clks-mcspi0"></span><h3>Clocks for MCSPI0 Device<a class="headerlink" href="#clocks-for-mcspi0-device" title="Permalink to this headline">¶</a></h3>
9523 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCSPI0</span></a> (ID = 266)</p>
9524 <p>Following is a mapping of Clocks IDs to function:</p>
9525 <table border="1" class="docutils">
9526 <colgroup>
9527 <col width="23%" />
9528 <col width="51%" />
9529 <col width="26%" />
9530 </colgroup>
9531 <thead valign="bottom">
9532 <tr class="row-odd"><th class="head">Clock ID</th>
9533 <th class="head">Name</th>
9534 <th class="head">Function</th>
9535 </tr>
9536 </thead>
9537 <tbody valign="top">
9538 <tr class="row-even"><td>0</td>
9539 <td>DEV_MCSPI0_VBUSP_CLK</td>
9540 <td>Input clock</td>
9541 </tr>
9542 <tr class="row-odd"><td>1</td>
9543 <td>DEV_MCSPI0_CLKSPIREF_CLK</td>
9544 <td>Input clock</td>
9545 </tr>
9546 <tr class="row-even"><td>2</td>
9547 <td>DEV_MCSPI0_IO_CLKSPIO_CLK</td>
9548 <td>Output clock</td>
9549 </tr>
9550 </tbody>
9551 </table>
9552 </div>
9553 <div class="section" id="clocks-for-mcspi1-device">
9554 <span id="soc-doc-j721e-public-clks-mcspi1"></span><h3>Clocks for MCSPI1 Device<a class="headerlink" href="#clocks-for-mcspi1-device" title="Permalink to this headline">¶</a></h3>
9555 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCSPI1</span></a> (ID = 267)</p>
9556 <p>Following is a mapping of Clocks IDs to function:</p>
9557 <table border="1" class="docutils">
9558 <colgroup>
9559 <col width="23%" />
9560 <col width="51%" />
9561 <col width="26%" />
9562 </colgroup>
9563 <thead valign="bottom">
9564 <tr class="row-odd"><th class="head">Clock ID</th>
9565 <th class="head">Name</th>
9566 <th class="head">Function</th>
9567 </tr>
9568 </thead>
9569 <tbody valign="top">
9570 <tr class="row-even"><td>0</td>
9571 <td>DEV_MCSPI1_VBUSP_CLK</td>
9572 <td>Input clock</td>
9573 </tr>
9574 <tr class="row-odd"><td>1</td>
9575 <td>DEV_MCSPI1_CLKSPIREF_CLK</td>
9576 <td>Input clock</td>
9577 </tr>
9578 <tr class="row-even"><td>2</td>
9579 <td>DEV_MCSPI1_IO_CLKSPIO_CLK</td>
9580 <td>Output clock</td>
9581 </tr>
9582 </tbody>
9583 </table>
9584 </div>
9585 <div class="section" id="clocks-for-mcspi2-device">
9586 <span id="soc-doc-j721e-public-clks-mcspi2"></span><h3>Clocks for MCSPI2 Device<a class="headerlink" href="#clocks-for-mcspi2-device" title="Permalink to this headline">¶</a></h3>
9587 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCSPI2</span></a> (ID = 268)</p>
9588 <p>Following is a mapping of Clocks IDs to function:</p>
9589 <table border="1" class="docutils">
9590 <colgroup>
9591 <col width="23%" />
9592 <col width="51%" />
9593 <col width="26%" />
9594 </colgroup>
9595 <thead valign="bottom">
9596 <tr class="row-odd"><th class="head">Clock ID</th>
9597 <th class="head">Name</th>
9598 <th class="head">Function</th>
9599 </tr>
9600 </thead>
9601 <tbody valign="top">
9602 <tr class="row-even"><td>0</td>
9603 <td>DEV_MCSPI2_VBUSP_CLK</td>
9604 <td>Input clock</td>
9605 </tr>
9606 <tr class="row-odd"><td>1</td>
9607 <td>DEV_MCSPI2_CLKSPIREF_CLK</td>
9608 <td>Input clock</td>
9609 </tr>
9610 <tr class="row-even"><td>2</td>
9611 <td>DEV_MCSPI2_IO_CLKSPIO_CLK</td>
9612 <td>Output clock</td>
9613 </tr>
9614 </tbody>
9615 </table>
9616 </div>
9617 <div class="section" id="clocks-for-mcspi3-device">
9618 <span id="soc-doc-j721e-public-clks-mcspi3"></span><h3>Clocks for MCSPI3 Device<a class="headerlink" href="#clocks-for-mcspi3-device" title="Permalink to this headline">¶</a></h3>
9619 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCSPI3</span></a> (ID = 269)</p>
9620 <p>Following is a mapping of Clocks IDs to function:</p>
9621 <table border="1" class="docutils">
9622 <colgroup>
9623 <col width="9%" />
9624 <col width="47%" />
9625 <col width="44%" />
9626 </colgroup>
9627 <thead valign="bottom">
9628 <tr class="row-odd"><th class="head">Clock ID</th>
9629 <th class="head">Name</th>
9630 <th class="head">Function</th>
9631 </tr>
9632 </thead>
9633 <tbody valign="top">
9634 <tr class="row-even"><td>0</td>
9635 <td>DEV_MCSPI3_VBUSP_CLK</td>
9636 <td>Input clock</td>
9637 </tr>
9638 <tr class="row-odd"><td>1</td>
9639 <td>DEV_MCSPI3_CLKSPIREF_CLK</td>
9640 <td>Input clock</td>
9641 </tr>
9642 <tr class="row-even"><td>2</td>
9643 <td>DEV_MCSPI3_IO_CLKSPII_CLK</td>
9644 <td>Input muxed clock</td>
9645 </tr>
9646 <tr class="row-odd"><td>3</td>
9647 <td>DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK</td>
9648 <td>Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK</td>
9649 </tr>
9650 <tr class="row-even"><td>4</td>
9651 <td>DEV_MCSPI3_IO_CLKSPIO_CLK</td>
9652 <td>Output clock</td>
9653 </tr>
9654 </tbody>
9655 </table>
9656 </div>
9657 <div class="section" id="clocks-for-mcspi4-device">
9658 <span id="soc-doc-j721e-public-clks-mcspi4"></span><h3>Clocks for MCSPI4 Device<a class="headerlink" href="#clocks-for-mcspi4-device" title="Permalink to this headline">¶</a></h3>
9659 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCSPI4</span></a> (ID = 270)</p>
9660 <p>Following is a mapping of Clocks IDs to function:</p>
9661 <table border="1" class="docutils">
9662 <colgroup>
9663 <col width="23%" />
9664 <col width="51%" />
9665 <col width="26%" />
9666 </colgroup>
9667 <thead valign="bottom">
9668 <tr class="row-odd"><th class="head">Clock ID</th>
9669 <th class="head">Name</th>
9670 <th class="head">Function</th>
9671 </tr>
9672 </thead>
9673 <tbody valign="top">
9674 <tr class="row-even"><td>0</td>
9675 <td>DEV_MCSPI4_VBUSP_CLK</td>
9676 <td>Input clock</td>
9677 </tr>
9678 <tr class="row-odd"><td>1</td>
9679 <td>DEV_MCSPI4_CLKSPIREF_CLK</td>
9680 <td>Input clock</td>
9681 </tr>
9682 <tr class="row-even"><td>2</td>
9683 <td>DEV_MCSPI4_IO_CLKSPII_CLK</td>
9684 <td>Input clock</td>
9685 </tr>
9686 <tr class="row-odd"><td>3</td>
9687 <td>DEV_MCSPI4_IO_CLKSPIO_CLK</td>
9688 <td>Output clock</td>
9689 </tr>
9690 </tbody>
9691 </table>
9692 </div>
9693 <div class="section" id="clocks-for-mcspi5-device">
9694 <span id="soc-doc-j721e-public-clks-mcspi5"></span><h3>Clocks for MCSPI5 Device<a class="headerlink" href="#clocks-for-mcspi5-device" title="Permalink to this headline">¶</a></h3>
9695 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCSPI5</span></a> (ID = 271)</p>
9696 <p>Following is a mapping of Clocks IDs to function:</p>
9697 <table border="1" class="docutils">
9698 <colgroup>
9699 <col width="23%" />
9700 <col width="51%" />
9701 <col width="26%" />
9702 </colgroup>
9703 <thead valign="bottom">
9704 <tr class="row-odd"><th class="head">Clock ID</th>
9705 <th class="head">Name</th>
9706 <th class="head">Function</th>
9707 </tr>
9708 </thead>
9709 <tbody valign="top">
9710 <tr class="row-even"><td>0</td>
9711 <td>DEV_MCSPI5_VBUSP_CLK</td>
9712 <td>Input clock</td>
9713 </tr>
9714 <tr class="row-odd"><td>1</td>
9715 <td>DEV_MCSPI5_CLKSPIREF_CLK</td>
9716 <td>Input clock</td>
9717 </tr>
9718 <tr class="row-even"><td>2</td>
9719 <td>DEV_MCSPI5_IO_CLKSPIO_CLK</td>
9720 <td>Output clock</td>
9721 </tr>
9722 </tbody>
9723 </table>
9724 </div>
9725 <div class="section" id="clocks-for-mcspi6-device">
9726 <span id="soc-doc-j721e-public-clks-mcspi6"></span><h3>Clocks for MCSPI6 Device<a class="headerlink" href="#clocks-for-mcspi6-device" title="Permalink to this headline">¶</a></h3>
9727 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCSPI6</span></a> (ID = 272)</p>
9728 <p>Following is a mapping of Clocks IDs to function:</p>
9729 <table border="1" class="docutils">
9730 <colgroup>
9731 <col width="23%" />
9732 <col width="51%" />
9733 <col width="26%" />
9734 </colgroup>
9735 <thead valign="bottom">
9736 <tr class="row-odd"><th class="head">Clock ID</th>
9737 <th class="head">Name</th>
9738 <th class="head">Function</th>
9739 </tr>
9740 </thead>
9741 <tbody valign="top">
9742 <tr class="row-even"><td>0</td>
9743 <td>DEV_MCSPI6_VBUSP_CLK</td>
9744 <td>Input clock</td>
9745 </tr>
9746 <tr class="row-odd"><td>1</td>
9747 <td>DEV_MCSPI6_CLKSPIREF_CLK</td>
9748 <td>Input clock</td>
9749 </tr>
9750 <tr class="row-even"><td>2</td>
9751 <td>DEV_MCSPI6_IO_CLKSPIO_CLK</td>
9752 <td>Output clock</td>
9753 </tr>
9754 </tbody>
9755 </table>
9756 </div>
9757 <div class="section" id="clocks-for-mcspi7-device">
9758 <span id="soc-doc-j721e-public-clks-mcspi7"></span><h3>Clocks for MCSPI7 Device<a class="headerlink" href="#clocks-for-mcspi7-device" title="Permalink to this headline">¶</a></h3>
9759 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCSPI7</span></a> (ID = 273)</p>
9760 <p>Following is a mapping of Clocks IDs to function:</p>
9761 <table border="1" class="docutils">
9762 <colgroup>
9763 <col width="23%" />
9764 <col width="51%" />
9765 <col width="26%" />
9766 </colgroup>
9767 <thead valign="bottom">
9768 <tr class="row-odd"><th class="head">Clock ID</th>
9769 <th class="head">Name</th>
9770 <th class="head">Function</th>
9771 </tr>
9772 </thead>
9773 <tbody valign="top">
9774 <tr class="row-even"><td>0</td>
9775 <td>DEV_MCSPI7_VBUSP_CLK</td>
9776 <td>Input clock</td>
9777 </tr>
9778 <tr class="row-odd"><td>1</td>
9779 <td>DEV_MCSPI7_CLKSPIREF_CLK</td>
9780 <td>Input clock</td>
9781 </tr>
9782 <tr class="row-even"><td>2</td>
9783 <td>DEV_MCSPI7_IO_CLKSPIO_CLK</td>
9784 <td>Output clock</td>
9785 </tr>
9786 </tbody>
9787 </table>
9788 </div>
9789 <div class="section" id="clocks-for-mcu-adc12-16ffc0-device">
9790 <span id="soc-doc-j721e-public-clks-mcu-adc12-16ffc0"></span><h3>Clocks for MCU_ADC12_16FFC0 Device<a class="headerlink" href="#clocks-for-mcu-adc12-16ffc0-device" title="Permalink to this headline">¶</a></h3>
9791 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_ADC12_16FFC0</span></a> (ID = 0)</p>
9792 <p>Following is a mapping of Clocks IDs to function:</p>
9793 <table border="1" class="docutils">
9794 <colgroup>
9795 <col width="9%" />
9796 <col width="50%" />
9797 <col width="42%" />
9798 </colgroup>
9799 <thead valign="bottom">
9800 <tr class="row-odd"><th class="head">Clock ID</th>
9801 <th class="head">Name</th>
9802 <th class="head">Function</th>
9803 </tr>
9804 </thead>
9805 <tbody valign="top">
9806 <tr class="row-even"><td>0</td>
9807 <td>DEV_MCU_ADC12_16FFC0_SYS_CLK</td>
9808 <td>Input clock</td>
9809 </tr>
9810 <tr class="row-odd"><td>1</td>
9811 <td>DEV_MCU_ADC12_16FFC0_ADC_CLK</td>
9812 <td>Input muxed clock</td>
9813 </tr>
9814 <tr class="row-even"><td>2</td>
9815 <td>DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9816 <td>Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK</td>
9817 </tr>
9818 <tr class="row-odd"><td>3</td>
9819 <td>DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK</td>
9820 <td>Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK</td>
9821 </tr>
9822 <tr class="row-even"><td>4</td>
9823 <td>DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK</td>
9824 <td>Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK</td>
9825 </tr>
9826 <tr class="row-odd"><td>5</td>
9827 <td>DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
9828 <td>Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK</td>
9829 </tr>
9830 <tr class="row-even"><td>6</td>
9831 <td>DEV_MCU_ADC12_16FFC0_VBUS_CLK</td>
9832 <td>Input clock</td>
9833 </tr>
9834 </tbody>
9835 </table>
9836 </div>
9837 <div class="section" id="clocks-for-mcu-adc12-16ffc1-device">
9838 <span id="soc-doc-j721e-public-clks-mcu-adc12-16ffc1"></span><h3>Clocks for MCU_ADC12_16FFC1 Device<a class="headerlink" href="#clocks-for-mcu-adc12-16ffc1-device" title="Permalink to this headline">¶</a></h3>
9839 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_ADC12_16FFC1</span></a> (ID = 1)</p>
9840 <p>Following is a mapping of Clocks IDs to function:</p>
9841 <table border="1" class="docutils">
9842 <colgroup>
9843 <col width="9%" />
9844 <col width="50%" />
9845 <col width="42%" />
9846 </colgroup>
9847 <thead valign="bottom">
9848 <tr class="row-odd"><th class="head">Clock ID</th>
9849 <th class="head">Name</th>
9850 <th class="head">Function</th>
9851 </tr>
9852 </thead>
9853 <tbody valign="top">
9854 <tr class="row-even"><td>0</td>
9855 <td>DEV_MCU_ADC12_16FFC1_SYS_CLK</td>
9856 <td>Input clock</td>
9857 </tr>
9858 <tr class="row-odd"><td>1</td>
9859 <td>DEV_MCU_ADC12_16FFC1_ADC_CLK</td>
9860 <td>Input muxed clock</td>
9861 </tr>
9862 <tr class="row-even"><td>2</td>
9863 <td>DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9864 <td>Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK</td>
9865 </tr>
9866 <tr class="row-odd"><td>3</td>
9867 <td>DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK</td>
9868 <td>Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK</td>
9869 </tr>
9870 <tr class="row-even"><td>4</td>
9871 <td>DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK</td>
9872 <td>Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK</td>
9873 </tr>
9874 <tr class="row-odd"><td>5</td>
9875 <td>DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
9876 <td>Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK</td>
9877 </tr>
9878 <tr class="row-even"><td>6</td>
9879 <td>DEV_MCU_ADC12_16FFC1_VBUS_CLK</td>
9880 <td>Input clock</td>
9881 </tr>
9882 </tbody>
9883 </table>
9884 </div>
9885 <div class="section" id="clocks-for-mcu-cpsw0-device">
9886 <span id="soc-doc-j721e-public-clks-mcu-cpsw0"></span><h3>Clocks for MCU_CPSW0 Device<a class="headerlink" href="#clocks-for-mcu-cpsw0-device" title="Permalink to this headline">¶</a></h3>
9887 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_CPSW0</span></a> (ID = 18)</p>
9888 <p>Following is a mapping of Clocks IDs to function:</p>
9889 <table border="1" class="docutils">
9890 <colgroup>
9891 <col width="8%" />
9892 <col width="53%" />
9893 <col width="39%" />
9894 </colgroup>
9895 <thead valign="bottom">
9896 <tr class="row-odd"><th class="head">Clock ID</th>
9897 <th class="head">Name</th>
9898 <th class="head">Function</th>
9899 </tr>
9900 </thead>
9901 <tbody valign="top">
9902 <tr class="row-even"><td>0</td>
9903 <td>DEV_MCU_CPSW0_RGMII1_RXC_I</td>
9904 <td>Input clock</td>
9905 </tr>
9906 <tr class="row-odd"><td>1</td>
9907 <td>DEV_MCU_CPSW0_RGMII_MHZ_250_CLK</td>
9908 <td>Input clock</td>
9909 </tr>
9910 <tr class="row-even"><td>2</td>
9911 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9912 <td>Input muxed clock</td>
9913 </tr>
9914 <tr class="row-odd"><td>3</td>
9915 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
9916 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9917 </tr>
9918 <tr class="row-even"><td>4</td>
9919 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
9920 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9921 </tr>
9922 <tr class="row-odd"><td>5</td>
9923 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
9924 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9925 </tr>
9926 <tr class="row-even"><td>6</td>
9927 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
9928 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9929 </tr>
9930 <tr class="row-odd"><td>7</td>
9931 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
9932 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9933 </tr>
9934 <tr class="row-even"><td>8</td>
9935 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
9936 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9937 </tr>
9938 <tr class="row-odd"><td>9</td>
9939 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK</td>
9940 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9941 </tr>
9942 <tr class="row-even"><td>10</td>
9943 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK</td>
9944 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9945 </tr>
9946 <tr class="row-odd"><td>11</td>
9947 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK</td>
9948 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9949 </tr>
9950 <tr class="row-even"><td>12</td>
9951 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK</td>
9952 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9953 </tr>
9954 <tr class="row-odd"><td>13</td>
9955 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK</td>
9956 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9957 </tr>
9958 <tr class="row-even"><td>14</td>
9959 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK</td>
9960 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9961 </tr>
9962 <tr class="row-odd"><td>15</td>
9963 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK</td>
9964 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9965 </tr>
9966 <tr class="row-even"><td>16</td>
9967 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK</td>
9968 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9969 </tr>
9970 <tr class="row-odd"><td>17</td>
9971 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
9972 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9973 </tr>
9974 <tr class="row-even"><td>18</td>
9975 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2</td>
9976 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
9977 </tr>
9978 <tr class="row-odd"><td>19</td>
9979 <td>DEV_MCU_CPSW0_GMII_RFT_CLK</td>
9980 <td>Input clock</td>
9981 </tr>
9982 <tr class="row-even"><td>20</td>
9983 <td>DEV_MCU_CPSW0_RMII_MHZ_50_CLK</td>
9984 <td>Input clock</td>
9985 </tr>
9986 <tr class="row-odd"><td>21</td>
9987 <td>DEV_MCU_CPSW0_RGMII_MHZ_50_CLK</td>
9988 <td>Input clock</td>
9989 </tr>
9990 <tr class="row-even"><td>22</td>
9991 <td>DEV_MCU_CPSW0_CPPI_CLK_CLK</td>
9992 <td>Input clock</td>
9993 </tr>
9994 <tr class="row-odd"><td>23</td>
9995 <td>DEV_MCU_CPSW0_RGMII_MHZ_5_CLK</td>
9996 <td>Input clock</td>
9997 </tr>
9998 <tr class="row-even"><td>24</td>
9999 <td>DEV_MCU_CPSW0_GMII1_MR_CLK</td>
10000 <td>Input clock</td>
10001 </tr>
10002 <tr class="row-odd"><td>25</td>
10003 <td>DEV_MCU_CPSW0_GMII1_MT_CLK</td>
10004 <td>Input clock</td>
10005 </tr>
10006 <tr class="row-even"><td>26</td>
10007 <td>DEV_MCU_CPSW0_RGMII1_TXC_I</td>
10008 <td>Input clock</td>
10009 </tr>
10010 <tr class="row-odd"><td>27</td>
10011 <td>DEV_MCU_CPSW0_RGMII1_TXC_O</td>
10012 <td>Output clock</td>
10013 </tr>
10014 <tr class="row-even"><td>28</td>
10015 <td>DEV_MCU_CPSW0_CPTS_GENF0</td>
10016 <td>Output clock</td>
10017 </tr>
10018 <tr class="row-odd"><td>29</td>
10019 <td>DEV_MCU_CPSW0_MDIO_MDCLK_O</td>
10020 <td>Output clock</td>
10021 </tr>
10022 </tbody>
10023 </table>
10024 </div>
10025 <div class="section" id="clocks-for-mcu-cpt2-aggr0-device">
10026 <span id="soc-doc-j721e-public-clks-mcu-cpt2-aggr0"></span><h3>Clocks for MCU_CPT2_AGGR0 Device<a class="headerlink" href="#clocks-for-mcu-cpt2-aggr0-device" title="Permalink to this headline">¶</a></h3>
10027 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_CPT2_AGGR0</span></a> (ID = 24)</p>
10028 <p>Following is a mapping of Clocks IDs to function:</p>
10029 <table border="1" class="docutils">
10030 <colgroup>
10031 <col width="22%" />
10032 <col width="54%" />
10033 <col width="24%" />
10034 </colgroup>
10035 <thead valign="bottom">
10036 <tr class="row-odd"><th class="head">Clock ID</th>
10037 <th class="head">Name</th>
10038 <th class="head">Function</th>
10039 </tr>
10040 </thead>
10041 <tbody valign="top">
10042 <tr class="row-even"><td>0</td>
10043 <td>DEV_MCU_CPT2_AGGR0_VCLK_CLK</td>
10044 <td>Input clock</td>
10045 </tr>
10046 </tbody>
10047 </table>
10048 </div>
10049 <div class="section" id="clocks-for-mcu-dcc0-device">
10050 <span id="soc-doc-j721e-public-clks-mcu-dcc0"></span><h3>Clocks for MCU_DCC0 Device<a class="headerlink" href="#clocks-for-mcu-dcc0-device" title="Permalink to this headline">¶</a></h3>
10051 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_DCC0</span></a> (ID = 44)</p>
10052 <p>Following is a mapping of Clocks IDs to function:</p>
10053 <table border="1" class="docutils">
10054 <colgroup>
10055 <col width="22%" />
10056 <col width="55%" />
10057 <col width="24%" />
10058 </colgroup>
10059 <thead valign="bottom">
10060 <tr class="row-odd"><th class="head">Clock ID</th>
10061 <th class="head">Name</th>
10062 <th class="head">Function</th>
10063 </tr>
10064 </thead>
10065 <tbody valign="top">
10066 <tr class="row-even"><td>0</td>
10067 <td>DEV_MCU_DCC0_DCC_INPUT10_CLK</td>
10068 <td>Input clock</td>
10069 </tr>
10070 <tr class="row-odd"><td>1</td>
10071 <td>DEV_MCU_DCC0_DCC_INPUT01_CLK</td>
10072 <td>Input clock</td>
10073 </tr>
10074 <tr class="row-even"><td>2</td>
10075 <td>DEV_MCU_DCC0_DCC_CLKSRC2_CLK</td>
10076 <td>Input clock</td>
10077 </tr>
10078 <tr class="row-odd"><td>3</td>
10079 <td>DEV_MCU_DCC0_DCC_CLKSRC7_CLK</td>
10080 <td>Input clock</td>
10081 </tr>
10082 <tr class="row-even"><td>4</td>
10083 <td>DEV_MCU_DCC0_DCC_CLKSRC0_CLK</td>
10084 <td>Input clock</td>
10085 </tr>
10086 <tr class="row-odd"><td>5</td>
10087 <td>DEV_MCU_DCC0_VBUS_CLK</td>
10088 <td>Input clock</td>
10089 </tr>
10090 <tr class="row-even"><td>6</td>
10091 <td>DEV_MCU_DCC0_DCC_CLKSRC4_CLK</td>
10092 <td>Input clock</td>
10093 </tr>
10094 <tr class="row-odd"><td>7</td>
10095 <td>DEV_MCU_DCC0_DCC_CLKSRC1_CLK</td>
10096 <td>Input clock</td>
10097 </tr>
10098 <tr class="row-even"><td>8</td>
10099 <td>DEV_MCU_DCC0_DCC_CLKSRC3_CLK</td>
10100 <td>Input clock</td>
10101 </tr>
10102 <tr class="row-odd"><td>9</td>
10103 <td>DEV_MCU_DCC0_DCC_INPUT00_CLK</td>
10104 <td>Input clock</td>
10105 </tr>
10106 <tr class="row-even"><td>10</td>
10107 <td>DEV_MCU_DCC0_DCC_CLKSRC5_CLK</td>
10108 <td>Input clock</td>
10109 </tr>
10110 <tr class="row-odd"><td>11</td>
10111 <td>DEV_MCU_DCC0_DCC_CLKSRC6_CLK</td>
10112 <td>Input clock</td>
10113 </tr>
10114 <tr class="row-even"><td>12</td>
10115 <td>DEV_MCU_DCC0_DCC_INPUT02_CLK</td>
10116 <td>Input clock</td>
10117 </tr>
10118 </tbody>
10119 </table>
10120 </div>
10121 <div class="section" id="clocks-for-mcu-dcc1-device">
10122 <span id="soc-doc-j721e-public-clks-mcu-dcc1"></span><h3>Clocks for MCU_DCC1 Device<a class="headerlink" href="#clocks-for-mcu-dcc1-device" title="Permalink to this headline">¶</a></h3>
10123 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_DCC1</span></a> (ID = 45)</p>
10124 <p>Following is a mapping of Clocks IDs to function:</p>
10125 <table border="1" class="docutils">
10126 <colgroup>
10127 <col width="22%" />
10128 <col width="55%" />
10129 <col width="24%" />
10130 </colgroup>
10131 <thead valign="bottom">
10132 <tr class="row-odd"><th class="head">Clock ID</th>
10133 <th class="head">Name</th>
10134 <th class="head">Function</th>
10135 </tr>
10136 </thead>
10137 <tbody valign="top">
10138 <tr class="row-even"><td>0</td>
10139 <td>DEV_MCU_DCC1_DCC_INPUT10_CLK</td>
10140 <td>Input clock</td>
10141 </tr>
10142 <tr class="row-odd"><td>1</td>
10143 <td>DEV_MCU_DCC1_DCC_INPUT01_CLK</td>
10144 <td>Input clock</td>
10145 </tr>
10146 <tr class="row-even"><td>2</td>
10147 <td>DEV_MCU_DCC1_DCC_CLKSRC2_CLK</td>
10148 <td>Input clock</td>
10149 </tr>
10150 <tr class="row-odd"><td>3</td>
10151 <td>DEV_MCU_DCC1_DCC_CLKSRC7_CLK</td>
10152 <td>Input clock</td>
10153 </tr>
10154 <tr class="row-even"><td>4</td>
10155 <td>DEV_MCU_DCC1_DCC_CLKSRC0_CLK</td>
10156 <td>Input clock</td>
10157 </tr>
10158 <tr class="row-odd"><td>5</td>
10159 <td>DEV_MCU_DCC1_VBUS_CLK</td>
10160 <td>Input clock</td>
10161 </tr>
10162 <tr class="row-even"><td>6</td>
10163 <td>DEV_MCU_DCC1_DCC_CLKSRC4_CLK</td>
10164 <td>Input clock</td>
10165 </tr>
10166 <tr class="row-odd"><td>7</td>
10167 <td>DEV_MCU_DCC1_DCC_CLKSRC1_CLK</td>
10168 <td>Input clock</td>
10169 </tr>
10170 <tr class="row-even"><td>8</td>
10171 <td>DEV_MCU_DCC1_DCC_CLKSRC3_CLK</td>
10172 <td>Input clock</td>
10173 </tr>
10174 <tr class="row-odd"><td>9</td>
10175 <td>DEV_MCU_DCC1_DCC_INPUT00_CLK</td>
10176 <td>Input clock</td>
10177 </tr>
10178 <tr class="row-even"><td>10</td>
10179 <td>DEV_MCU_DCC1_DCC_CLKSRC5_CLK</td>
10180 <td>Input clock</td>
10181 </tr>
10182 <tr class="row-odd"><td>11</td>
10183 <td>DEV_MCU_DCC1_DCC_CLKSRC6_CLK</td>
10184 <td>Input clock</td>
10185 </tr>
10186 <tr class="row-even"><td>12</td>
10187 <td>DEV_MCU_DCC1_DCC_INPUT02_CLK</td>
10188 <td>Input clock</td>
10189 </tr>
10190 </tbody>
10191 </table>
10192 </div>
10193 <div class="section" id="clocks-for-mcu-dcc2-device">
10194 <span id="soc-doc-j721e-public-clks-mcu-dcc2"></span><h3>Clocks for MCU_DCC2 Device<a class="headerlink" href="#clocks-for-mcu-dcc2-device" title="Permalink to this headline">¶</a></h3>
10195 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_DCC2</span></a> (ID = 46)</p>
10196 <p>Following is a mapping of Clocks IDs to function:</p>
10197 <table border="1" class="docutils">
10198 <colgroup>
10199 <col width="22%" />
10200 <col width="55%" />
10201 <col width="24%" />
10202 </colgroup>
10203 <thead valign="bottom">
10204 <tr class="row-odd"><th class="head">Clock ID</th>
10205 <th class="head">Name</th>
10206 <th class="head">Function</th>
10207 </tr>
10208 </thead>
10209 <tbody valign="top">
10210 <tr class="row-even"><td>0</td>
10211 <td>DEV_MCU_DCC2_DCC_INPUT10_CLK</td>
10212 <td>Input clock</td>
10213 </tr>
10214 <tr class="row-odd"><td>1</td>
10215 <td>DEV_MCU_DCC2_DCC_INPUT01_CLK</td>
10216 <td>Input clock</td>
10217 </tr>
10218 <tr class="row-even"><td>2</td>
10219 <td>DEV_MCU_DCC2_DCC_CLKSRC7_CLK</td>
10220 <td>Input clock</td>
10221 </tr>
10222 <tr class="row-odd"><td>3</td>
10223 <td>DEV_MCU_DCC2_DCC_CLKSRC0_CLK</td>
10224 <td>Input clock</td>
10225 </tr>
10226 <tr class="row-even"><td>4</td>
10227 <td>DEV_MCU_DCC2_VBUS_CLK</td>
10228 <td>Input clock</td>
10229 </tr>
10230 <tr class="row-odd"><td>5</td>
10231 <td>DEV_MCU_DCC2_DCC_CLKSRC4_CLK</td>
10232 <td>Input clock</td>
10233 </tr>
10234 <tr class="row-even"><td>6</td>
10235 <td>DEV_MCU_DCC2_DCC_CLKSRC1_CLK</td>
10236 <td>Input clock</td>
10237 </tr>
10238 <tr class="row-odd"><td>7</td>
10239 <td>DEV_MCU_DCC2_DCC_CLKSRC3_CLK</td>
10240 <td>Input clock</td>
10241 </tr>
10242 <tr class="row-even"><td>8</td>
10243 <td>DEV_MCU_DCC2_DCC_INPUT00_CLK</td>
10244 <td>Input clock</td>
10245 </tr>
10246 <tr class="row-odd"><td>9</td>
10247 <td>DEV_MCU_DCC2_DCC_CLKSRC6_CLK</td>
10248 <td>Input clock</td>
10249 </tr>
10250 <tr class="row-even"><td>10</td>
10251 <td>DEV_MCU_DCC2_DCC_INPUT02_CLK</td>
10252 <td>Input clock</td>
10253 </tr>
10254 </tbody>
10255 </table>
10256 </div>
10257 <div class="section" id="clocks-for-mcu-esm0-device">
10258 <span id="soc-doc-j721e-public-clks-mcu-esm0"></span><h3>Clocks for MCU_ESM0 Device<a class="headerlink" href="#clocks-for-mcu-esm0-device" title="Permalink to this headline">¶</a></h3>
10259 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_ESM0</span></a> (ID = 98)</p>
10260 <p>Following is a mapping of Clocks IDs to function:</p>
10261 <table border="1" class="docutils">
10262 <colgroup>
10263 <col width="28%" />
10264 <col width="42%" />
10265 <col width="30%" />
10266 </colgroup>
10267 <thead valign="bottom">
10268 <tr class="row-odd"><th class="head">Clock ID</th>
10269 <th class="head">Name</th>
10270 <th class="head">Function</th>
10271 </tr>
10272 </thead>
10273 <tbody valign="top">
10274 <tr class="row-even"><td>0</td>
10275 <td>DEV_MCU_ESM0_CLK</td>
10276 <td>Input clock</td>
10277 </tr>
10278 </tbody>
10279 </table>
10280 </div>
10281 <div class="section" id="clocks-for-mcu-fss0-device">
10282 <span id="soc-doc-j721e-public-clks-mcu-fss0"></span><h3>Clocks for MCU_FSS0 Device<a class="headerlink" href="#clocks-for-mcu-fss0-device" title="Permalink to this headline">¶</a></h3>
10283 <p><strong>This device has no defined clocks.</strong></p>
10284 </div>
10285 <div class="section" id="clocks-for-mcu-fss0-fsas-0-device">
10286 <span id="soc-doc-j721e-public-clks-mcu-fss0-fsas-0"></span><h3>Clocks for MCU_FSS0_FSAS_0 Device<a class="headerlink" href="#clocks-for-mcu-fss0-fsas-0-device" title="Permalink to this headline">¶</a></h3>
10287 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_FSS0_FSAS_0</span></a> (ID = 101)</p>
10288 <p>Following is a mapping of Clocks IDs to function:</p>
10289 <table border="1" class="docutils">
10290 <colgroup>
10291 <col width="24%" />
10292 <col width="51%" />
10293 <col width="25%" />
10294 </colgroup>
10295 <thead valign="bottom">
10296 <tr class="row-odd"><th class="head">Clock ID</th>
10297 <th class="head">Name</th>
10298 <th class="head">Function</th>
10299 </tr>
10300 </thead>
10301 <tbody valign="top">
10302 <tr class="row-even"><td>0</td>
10303 <td>DEV_MCU_FSS0_FSAS_0_GCLK</td>
10304 <td>Input clock</td>
10305 </tr>
10306 </tbody>
10307 </table>
10308 </div>
10309 <div class="section" id="clocks-for-mcu-fss0-hyperbus1p0-0-device">
10310 <span id="soc-doc-j721e-public-clks-mcu-fss0-hyperbus1p0-0"></span><h3>Clocks for MCU_FSS0_HYPERBUS1P0_0 Device<a class="headerlink" href="#clocks-for-mcu-fss0-hyperbus1p0-0-device" title="Permalink to this headline">¶</a></h3>
10311 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_FSS0_HYPERBUS1P0_0</span></a> (ID = 102)</p>
10312 <p>Following is a mapping of Clocks IDs to function:</p>
10313 <table border="1" class="docutils">
10314 <colgroup>
10315 <col width="17%" />
10316 <col width="64%" />
10317 <col width="19%" />
10318 </colgroup>
10319 <thead valign="bottom">
10320 <tr class="row-odd"><th class="head">Clock ID</th>
10321 <th class="head">Name</th>
10322 <th class="head">Function</th>
10323 </tr>
10324 </thead>
10325 <tbody valign="top">
10326 <tr class="row-even"><td>0</td>
10327 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK</td>
10328 <td>Input clock</td>
10329 </tr>
10330 <tr class="row-odd"><td>1</td>
10331 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK</td>
10332 <td>Input clock</td>
10333 </tr>
10334 <tr class="row-even"><td>2</td>
10335 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK</td>
10336 <td>Input clock</td>
10337 </tr>
10338 <tr class="row-odd"><td>3</td>
10339 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK</td>
10340 <td>Input clock</td>
10341 </tr>
10342 <tr class="row-even"><td>4</td>
10343 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK</td>
10344 <td>Input clock</td>
10345 </tr>
10346 <tr class="row-odd"><td>5</td>
10347 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N</td>
10348 <td>Output clock</td>
10349 </tr>
10350 <tr class="row-even"><td>6</td>
10351 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P</td>
10352 <td>Output clock</td>
10353 </tr>
10354 </tbody>
10355 </table>
10356 </div>
10357 <div class="section" id="clocks-for-mcu-fss0-ospi-0-device">
10358 <span id="soc-doc-j721e-public-clks-mcu-fss0-ospi-0"></span><h3>Clocks for MCU_FSS0_OSPI_0 Device<a class="headerlink" href="#clocks-for-mcu-fss0-ospi-0-device" title="Permalink to this headline">¶</a></h3>
10359 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_FSS0_OSPI_0</span></a> (ID = 103)</p>
10360 <p>Following is a mapping of Clocks IDs to function:</p>
10361 <table border="1" class="docutils">
10362 <colgroup>
10363 <col width="8%" />
10364 <col width="50%" />
10365 <col width="42%" />
10366 </colgroup>
10367 <thead valign="bottom">
10368 <tr class="row-odd"><th class="head">Clock ID</th>
10369 <th class="head">Name</th>
10370 <th class="head">Function</th>
10371 </tr>
10372 </thead>
10373 <tbody valign="top">
10374 <tr class="row-even"><td>0</td>
10375 <td>DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK</td>
10376 <td>Input muxed clock</td>
10377 </tr>
10378 <tr class="row-odd"><td>1</td>
10379 <td>DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK</td>
10380 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK</td>
10381 </tr>
10382 <tr class="row-even"><td>2</td>
10383 <td>DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK</td>
10384 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK</td>
10385 </tr>
10386 <tr class="row-odd"><td>3</td>
10387 <td>DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK</td>
10388 <td>Input clock</td>
10389 </tr>
10390 <tr class="row-even"><td>4</td>
10391 <td>DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK</td>
10392 <td>Input muxed clock</td>
10393 </tr>
10394 <tr class="row-odd"><td>5</td>
10395 <td>DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT</td>
10396 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK</td>
10397 </tr>
10398 <tr class="row-even"><td>6</td>
10399 <td>DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK</td>
10400 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK</td>
10401 </tr>
10402 <tr class="row-odd"><td>7</td>
10403 <td>DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK</td>
10404 <td>Input clock</td>
10405 </tr>
10406 <tr class="row-even"><td>8</td>
10407 <td>DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK</td>
10408 <td>Input clock</td>
10409 </tr>
10410 <tr class="row-odd"><td>9</td>
10411 <td>DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK</td>
10412 <td>Output clock</td>
10413 </tr>
10414 </tbody>
10415 </table>
10416 </div>
10417 <div class="section" id="clocks-for-mcu-fss0-ospi-1-device">
10418 <span id="soc-doc-j721e-public-clks-mcu-fss0-ospi-1"></span><h3>Clocks for MCU_FSS0_OSPI_1 Device<a class="headerlink" href="#clocks-for-mcu-fss0-ospi-1-device" title="Permalink to this headline">¶</a></h3>
10419 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_FSS0_OSPI_1</span></a> (ID = 104)</p>
10420 <p>Following is a mapping of Clocks IDs to function:</p>
10421 <table border="1" class="docutils">
10422 <colgroup>
10423 <col width="8%" />
10424 <col width="50%" />
10425 <col width="42%" />
10426 </colgroup>
10427 <thead valign="bottom">
10428 <tr class="row-odd"><th class="head">Clock ID</th>
10429 <th class="head">Name</th>
10430 <th class="head">Function</th>
10431 </tr>
10432 </thead>
10433 <tbody valign="top">
10434 <tr class="row-even"><td>0</td>
10435 <td>DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK</td>
10436 <td>Input muxed clock</td>
10437 </tr>
10438 <tr class="row-odd"><td>1</td>
10439 <td>DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK</td>
10440 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK</td>
10441 </tr>
10442 <tr class="row-even"><td>2</td>
10443 <td>DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK</td>
10444 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK</td>
10445 </tr>
10446 <tr class="row-odd"><td>3</td>
10447 <td>DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK</td>
10448 <td>Input clock</td>
10449 </tr>
10450 <tr class="row-even"><td>4</td>
10451 <td>DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK</td>
10452 <td>Input muxed clock</td>
10453 </tr>
10454 <tr class="row-odd"><td>5</td>
10455 <td>DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT</td>
10456 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK</td>
10457 </tr>
10458 <tr class="row-even"><td>6</td>
10459 <td>DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK</td>
10460 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK</td>
10461 </tr>
10462 <tr class="row-odd"><td>7</td>
10463 <td>DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK</td>
10464 <td>Input clock</td>
10465 </tr>
10466 <tr class="row-even"><td>8</td>
10467 <td>DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK</td>
10468 <td>Input clock</td>
10469 </tr>
10470 <tr class="row-odd"><td>9</td>
10471 <td>DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK</td>
10472 <td>Output clock</td>
10473 </tr>
10474 </tbody>
10475 </table>
10476 </div>
10477 <div class="section" id="clocks-for-mcu-i2c0-device">
10478 <span id="soc-doc-j721e-public-clks-mcu-i2c0"></span><h3>Clocks for MCU_I2C0 Device<a class="headerlink" href="#clocks-for-mcu-i2c0-device" title="Permalink to this headline">¶</a></h3>
10479 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_I2C0</span></a> (ID = 194)</p>
10480 <p>Following is a mapping of Clocks IDs to function:</p>
10481 <table border="1" class="docutils">
10482 <colgroup>
10483 <col width="24%" />
10484 <col width="48%" />
10485 <col width="28%" />
10486 </colgroup>
10487 <thead valign="bottom">
10488 <tr class="row-odd"><th class="head">Clock ID</th>
10489 <th class="head">Name</th>
10490 <th class="head">Function</th>
10491 </tr>
10492 </thead>
10493 <tbody valign="top">
10494 <tr class="row-even"><td>0</td>
10495 <td>DEV_MCU_I2C0_PISYS_CLK</td>
10496 <td>Input clock</td>
10497 </tr>
10498 <tr class="row-odd"><td>1</td>
10499 <td>DEV_MCU_I2C0_PISCL</td>
10500 <td>Input clock</td>
10501 </tr>
10502 <tr class="row-even"><td>2</td>
10503 <td>DEV_MCU_I2C0_CLK</td>
10504 <td>Input clock</td>
10505 </tr>
10506 <tr class="row-odd"><td>3</td>
10507 <td>DEV_MCU_I2C0_PORSCL</td>
10508 <td>Output clock</td>
10509 </tr>
10510 </tbody>
10511 </table>
10512 </div>
10513 <div class="section" id="clocks-for-mcu-i2c1-device">
10514 <span id="soc-doc-j721e-public-clks-mcu-i2c1"></span><h3>Clocks for MCU_I2C1 Device<a class="headerlink" href="#clocks-for-mcu-i2c1-device" title="Permalink to this headline">¶</a></h3>
10515 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_I2C1</span></a> (ID = 195)</p>
10516 <p>Following is a mapping of Clocks IDs to function:</p>
10517 <table border="1" class="docutils">
10518 <colgroup>
10519 <col width="24%" />
10520 <col width="49%" />
10521 <col width="27%" />
10522 </colgroup>
10523 <thead valign="bottom">
10524 <tr class="row-odd"><th class="head">Clock ID</th>
10525 <th class="head">Name</th>
10526 <th class="head">Function</th>
10527 </tr>
10528 </thead>
10529 <tbody valign="top">
10530 <tr class="row-even"><td>0</td>
10531 <td>DEV_MCU_I2C1_PISYS_CLK</td>
10532 <td>Input clock</td>
10533 </tr>
10534 <tr class="row-odd"><td>1</td>
10535 <td>DEV_MCU_I2C1_PISCL</td>
10536 <td>Input clock</td>
10537 </tr>
10538 <tr class="row-even"><td>2</td>
10539 <td>DEV_MCU_I2C1_CLK</td>
10540 <td>Input clock</td>
10541 </tr>
10542 </tbody>
10543 </table>
10544 </div>
10545 <div class="section" id="clocks-for-mcu-i3c0-device">
10546 <span id="soc-doc-j721e-public-clks-mcu-i3c0"></span><h3>Clocks for MCU_I3C0 Device<a class="headerlink" href="#clocks-for-mcu-i3c0-device" title="Permalink to this headline">¶</a></h3>
10547 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_I3C0</span></a> (ID = 117)</p>
10548 <p>Following is a mapping of Clocks IDs to function:</p>
10549 <table border="1" class="docutils">
10550 <colgroup>
10551 <col width="23%" />
10552 <col width="51%" />
10553 <col width="26%" />
10554 </colgroup>
10555 <thead valign="bottom">
10556 <tr class="row-odd"><th class="head">Clock ID</th>
10557 <th class="head">Name</th>
10558 <th class="head">Function</th>
10559 </tr>
10560 </thead>
10561 <tbody valign="top">
10562 <tr class="row-even"><td>0</td>
10563 <td>DEV_MCU_I3C0_I3C_PCLK_CLK</td>
10564 <td>Input clock</td>
10565 </tr>
10566 <tr class="row-odd"><td>1</td>
10567 <td>DEV_MCU_I3C0_I3C_SCL_DI</td>
10568 <td>Input clock</td>
10569 </tr>
10570 <tr class="row-even"><td>2</td>
10571 <td>DEV_MCU_I3C0_I3C_SCLK_CLK</td>
10572 <td>Input clock</td>
10573 </tr>
10574 <tr class="row-odd"><td>3</td>
10575 <td>DEV_MCU_I3C0_I3C_SCL_DO</td>
10576 <td>Output clock</td>
10577 </tr>
10578 </tbody>
10579 </table>
10580 </div>
10581 <div class="section" id="clocks-for-mcu-i3c1-device">
10582 <span id="soc-doc-j721e-public-clks-mcu-i3c1"></span><h3>Clocks for MCU_I3C1 Device<a class="headerlink" href="#clocks-for-mcu-i3c1-device" title="Permalink to this headline">¶</a></h3>
10583 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_I3C1</span></a> (ID = 118)</p>
10584 <p>Following is a mapping of Clocks IDs to function:</p>
10585 <table border="1" class="docutils">
10586 <colgroup>
10587 <col width="23%" />
10588 <col width="51%" />
10589 <col width="26%" />
10590 </colgroup>
10591 <thead valign="bottom">
10592 <tr class="row-odd"><th class="head">Clock ID</th>
10593 <th class="head">Name</th>
10594 <th class="head">Function</th>
10595 </tr>
10596 </thead>
10597 <tbody valign="top">
10598 <tr class="row-even"><td>0</td>
10599 <td>DEV_MCU_I3C1_I3C_PCLK_CLK</td>
10600 <td>Input clock</td>
10601 </tr>
10602 <tr class="row-odd"><td>1</td>
10603 <td>DEV_MCU_I3C1_I3C_SCL_DI</td>
10604 <td>Input clock</td>
10605 </tr>
10606 <tr class="row-even"><td>2</td>
10607 <td>DEV_MCU_I3C1_I3C_SCLK_CLK</td>
10608 <td>Input clock</td>
10609 </tr>
10610 <tr class="row-odd"><td>3</td>
10611 <td>DEV_MCU_I3C1_I3C_SCL_DO</td>
10612 <td>Output clock</td>
10613 </tr>
10614 </tbody>
10615 </table>
10616 </div>
10617 <div class="section" id="clocks-for-mcu-mcan0-device">
10618 <span id="soc-doc-j721e-public-clks-mcu-mcan0"></span><h3>Clocks for MCU_MCAN0 Device<a class="headerlink" href="#clocks-for-mcu-mcan0-device" title="Permalink to this headline">¶</a></h3>
10619 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_MCAN0</span></a> (ID = 172)</p>
10620 <p>Following is a mapping of Clocks IDs to function:</p>
10621 <table border="1" class="docutils">
10622 <colgroup>
10623 <col width="8%" />
10624 <col width="50%" />
10625 <col width="42%" />
10626 </colgroup>
10627 <thead valign="bottom">
10628 <tr class="row-odd"><th class="head">Clock ID</th>
10629 <th class="head">Name</th>
10630 <th class="head">Function</th>
10631 </tr>
10632 </thead>
10633 <tbody valign="top">
10634 <tr class="row-even"><td>0</td>
10635 <td>DEV_MCU_MCAN0_MCANSS_HCLK_CLK</td>
10636 <td>Input clock</td>
10637 </tr>
10638 <tr class="row-odd"><td>1</td>
10639 <td>DEV_MCU_MCAN0_MCANSS_CCLK_CLK</td>
10640 <td>Input muxed clock</td>
10641 </tr>
10642 <tr class="row-even"><td>2</td>
10643 <td>DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK</td>
10644 <td>Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK</td>
10645 </tr>
10646 <tr class="row-odd"><td>3</td>
10647 <td>DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
10648 <td>Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK</td>
10649 </tr>
10650 <tr class="row-even"><td>4</td>
10651 <td>DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK</td>
10652 <td>Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK</td>
10653 </tr>
10654 <tr class="row-odd"><td>5</td>
10655 <td>DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
10656 <td>Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK</td>
10657 </tr>
10658 </tbody>
10659 </table>
10660 </div>
10661 <div class="section" id="clocks-for-mcu-mcan1-device">
10662 <span id="soc-doc-j721e-public-clks-mcu-mcan1"></span><h3>Clocks for MCU_MCAN1 Device<a class="headerlink" href="#clocks-for-mcu-mcan1-device" title="Permalink to this headline">¶</a></h3>
10663 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_MCAN1</span></a> (ID = 173)</p>
10664 <p>Following is a mapping of Clocks IDs to function:</p>
10665 <table border="1" class="docutils">
10666 <colgroup>
10667 <col width="8%" />
10668 <col width="50%" />
10669 <col width="42%" />
10670 </colgroup>
10671 <thead valign="bottom">
10672 <tr class="row-odd"><th class="head">Clock ID</th>
10673 <th class="head">Name</th>
10674 <th class="head">Function</th>
10675 </tr>
10676 </thead>
10677 <tbody valign="top">
10678 <tr class="row-even"><td>0</td>
10679 <td>DEV_MCU_MCAN1_MCANSS_HCLK_CLK</td>
10680 <td>Input clock</td>
10681 </tr>
10682 <tr class="row-odd"><td>1</td>
10683 <td>DEV_MCU_MCAN1_MCANSS_CCLK_CLK</td>
10684 <td>Input muxed clock</td>
10685 </tr>
10686 <tr class="row-even"><td>2</td>
10687 <td>DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK</td>
10688 <td>Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK</td>
10689 </tr>
10690 <tr class="row-odd"><td>3</td>
10691 <td>DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
10692 <td>Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK</td>
10693 </tr>
10694 <tr class="row-even"><td>4</td>
10695 <td>DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK</td>
10696 <td>Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK</td>
10697 </tr>
10698 <tr class="row-odd"><td>5</td>
10699 <td>DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
10700 <td>Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK</td>
10701 </tr>
10702 </tbody>
10703 </table>
10704 </div>
10705 <div class="section" id="clocks-for-mcu-mcspi0-device">
10706 <span id="soc-doc-j721e-public-clks-mcu-mcspi0"></span><h3>Clocks for MCU_MCSPI0 Device<a class="headerlink" href="#clocks-for-mcu-mcspi0-device" title="Permalink to this headline">¶</a></h3>
10707 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_MCSPI0</span></a> (ID = 274)</p>
10708 <p>Following is a mapping of Clocks IDs to function:</p>
10709 <table border="1" class="docutils">
10710 <colgroup>
10711 <col width="21%" />
10712 <col width="54%" />
10713 <col width="25%" />
10714 </colgroup>
10715 <thead valign="bottom">
10716 <tr class="row-odd"><th class="head">Clock ID</th>
10717 <th class="head">Name</th>
10718 <th class="head">Function</th>
10719 </tr>
10720 </thead>
10721 <tbody valign="top">
10722 <tr class="row-even"><td>0</td>
10723 <td>DEV_MCU_MCSPI0_VBUSP_CLK</td>
10724 <td>Input clock</td>
10725 </tr>
10726 <tr class="row-odd"><td>1</td>
10727 <td>DEV_MCU_MCSPI0_CLKSPIREF_CLK</td>
10728 <td>Input clock</td>
10729 </tr>
10730 <tr class="row-even"><td>2</td>
10731 <td>DEV_MCU_MCSPI0_IO_CLKSPIO_CLK</td>
10732 <td>Output clock</td>
10733 </tr>
10734 </tbody>
10735 </table>
10736 </div>
10737 <div class="section" id="clocks-for-mcu-mcspi1-device">
10738 <span id="soc-doc-j721e-public-clks-mcu-mcspi1"></span><h3>Clocks for MCU_MCSPI1 Device<a class="headerlink" href="#clocks-for-mcu-mcspi1-device" title="Permalink to this headline">¶</a></h3>
10739 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_MCSPI1</span></a> (ID = 275)</p>
10740 <p>Following is a mapping of Clocks IDs to function:</p>
10741 <table border="1" class="docutils">
10742 <colgroup>
10743 <col width="9%" />
10744 <col width="47%" />
10745 <col width="44%" />
10746 </colgroup>
10747 <thead valign="bottom">
10748 <tr class="row-odd"><th class="head">Clock ID</th>
10749 <th class="head">Name</th>
10750 <th class="head">Function</th>
10751 </tr>
10752 </thead>
10753 <tbody valign="top">
10754 <tr class="row-even"><td>0</td>
10755 <td>DEV_MCU_MCSPI1_VBUSP_CLK</td>
10756 <td>Input clock</td>
10757 </tr>
10758 <tr class="row-odd"><td>1</td>
10759 <td>DEV_MCU_MCSPI1_CLKSPIREF_CLK</td>
10760 <td>Input clock</td>
10761 </tr>
10762 <tr class="row-even"><td>2</td>
10763 <td>DEV_MCU_MCSPI1_IO_CLKSPII_CLK</td>
10764 <td>Input muxed clock</td>
10765 </tr>
10766 <tr class="row-odd"><td>3</td>
10767 <td>DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK</td>
10768 <td>Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK</td>
10769 </tr>
10770 <tr class="row-even"><td>4</td>
10771 <td>DEV_MCU_MCSPI1_IO_CLKSPIO_CLK</td>
10772 <td>Output clock</td>
10773 </tr>
10774 </tbody>
10775 </table>
10776 </div>
10777 <div class="section" id="clocks-for-mcu-mcspi2-device">
10778 <span id="soc-doc-j721e-public-clks-mcu-mcspi2"></span><h3>Clocks for MCU_MCSPI2 Device<a class="headerlink" href="#clocks-for-mcu-mcspi2-device" title="Permalink to this headline">¶</a></h3>
10779 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_MCSPI2</span></a> (ID = 276)</p>
10780 <p>Following is a mapping of Clocks IDs to function:</p>
10781 <table border="1" class="docutils">
10782 <colgroup>
10783 <col width="21%" />
10784 <col width="54%" />
10785 <col width="25%" />
10786 </colgroup>
10787 <thead valign="bottom">
10788 <tr class="row-odd"><th class="head">Clock ID</th>
10789 <th class="head">Name</th>
10790 <th class="head">Function</th>
10791 </tr>
10792 </thead>
10793 <tbody valign="top">
10794 <tr class="row-even"><td>0</td>
10795 <td>DEV_MCU_MCSPI2_VBUSP_CLK</td>
10796 <td>Input clock</td>
10797 </tr>
10798 <tr class="row-odd"><td>1</td>
10799 <td>DEV_MCU_MCSPI2_CLKSPIREF_CLK</td>
10800 <td>Input clock</td>
10801 </tr>
10802 <tr class="row-even"><td>2</td>
10803 <td>DEV_MCU_MCSPI2_IO_CLKSPII_CLK</td>
10804 <td>Input clock</td>
10805 </tr>
10806 <tr class="row-odd"><td>3</td>
10807 <td>DEV_MCU_MCSPI2_IO_CLKSPIO_CLK</td>
10808 <td>Output clock</td>
10809 </tr>
10810 </tbody>
10811 </table>
10812 </div>
10813 <div class="section" id="clocks-for-mcu-navss0-device">
10814 <span id="soc-doc-j721e-public-clks-mcu-navss0"></span><h3>Clocks for MCU_NAVSS0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-device" title="Permalink to this headline">¶</a></h3>
10815 <p><strong>This device has no defined clocks.</strong></p>
10816 </div>
10817 <div class="section" id="clocks-for-mcu-navss0-intr-0-device">
10818 <span id="soc-doc-j721e-public-clks-mcu-navss0-intr-0"></span><h3>Clocks for MCU_NAVSS0_INTR_0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-intr-0-device" title="Permalink to this headline">¶</a></h3>
10819 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_NAVSS0_INTR_0</span></a> (ID = 237)</p>
10820 <p>Following is a mapping of Clocks IDs to function:</p>
10821 <table border="1" class="docutils">
10822 <colgroup>
10823 <col width="21%" />
10824 <col width="56%" />
10825 <col width="23%" />
10826 </colgroup>
10827 <thead valign="bottom">
10828 <tr class="row-odd"><th class="head">Clock ID</th>
10829 <th class="head">Name</th>
10830 <th class="head">Function</th>
10831 </tr>
10832 </thead>
10833 <tbody valign="top">
10834 <tr class="row-even"><td>0</td>
10835 <td>DEV_MCU_NAVSS0_INTR_0_INTR_CLK</td>
10836 <td>Input clock</td>
10837 </tr>
10838 </tbody>
10839 </table>
10840 </div>
10841 <div class="section" id="clocks-for-mcu-navss0-mcrc-0-device">
10842 <span id="soc-doc-j721e-public-clks-mcu-navss0-mcrc-0"></span><h3>Clocks for MCU_NAVSS0_MCRC_0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-mcrc-0-device" title="Permalink to this headline">¶</a></h3>
10843 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_NAVSS0_MCRC_0</span></a> (ID = 238)</p>
10844 <p>Following is a mapping of Clocks IDs to function:</p>
10845 <table border="1" class="docutils">
10846 <colgroup>
10847 <col width="23%" />
10848 <col width="52%" />
10849 <col width="25%" />
10850 </colgroup>
10851 <thead valign="bottom">
10852 <tr class="row-odd"><th class="head">Clock ID</th>
10853 <th class="head">Name</th>
10854 <th class="head">Function</th>
10855 </tr>
10856 </thead>
10857 <tbody valign="top">
10858 <tr class="row-even"><td>0</td>
10859 <td>DEV_MCU_NAVSS0_MCRC_0_CLK</td>
10860 <td>Input clock</td>
10861 </tr>
10862 </tbody>
10863 </table>
10864 </div>
10865 <div class="section" id="clocks-for-mcu-navss0-modss-device">
10866 <span id="soc-doc-j721e-public-clks-mcu-navss0-modss"></span><h3>Clocks for MCU_NAVSS0_MODSS Device<a class="headerlink" href="#clocks-for-mcu-navss0-modss-device" title="Permalink to this headline">¶</a></h3>
10867 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_NAVSS0_MODSS</span></a> (ID = 302)</p>
10868 <p>Following is a mapping of Clocks IDs to function:</p>
10869 <table border="1" class="docutils">
10870 <colgroup>
10871 <col width="22%" />
10872 <col width="54%" />
10873 <col width="24%" />
10874 </colgroup>
10875 <thead valign="bottom">
10876 <tr class="row-odd"><th class="head">Clock ID</th>
10877 <th class="head">Name</th>
10878 <th class="head">Function</th>
10879 </tr>
10880 </thead>
10881 <tbody valign="top">
10882 <tr class="row-even"><td>0</td>
10883 <td>DEV_MCU_NAVSS0_MODSS_VD2CLK</td>
10884 <td>Input clock</td>
10885 </tr>
10886 </tbody>
10887 </table>
10888 </div>
10889 <div class="section" id="clocks-for-mcu-navss0-proxy0-device">
10890 <span id="soc-doc-j721e-public-clks-mcu-navss0-proxy0"></span><h3>Clocks for MCU_NAVSS0_PROXY0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-proxy0-device" title="Permalink to this headline">¶</a></h3>
10891 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_NAVSS0_PROXY0</span></a> (ID = 234)</p>
10892 <p>Following is a mapping of Clocks IDs to function:</p>
10893 <table border="1" class="docutils">
10894 <colgroup>
10895 <col width="21%" />
10896 <col width="55%" />
10897 <col width="23%" />
10898 </colgroup>
10899 <thead valign="bottom">
10900 <tr class="row-odd"><th class="head">Clock ID</th>
10901 <th class="head">Name</th>
10902 <th class="head">Function</th>
10903 </tr>
10904 </thead>
10905 <tbody valign="top">
10906 <tr class="row-even"><td>0</td>
10907 <td>DEV_MCU_NAVSS0_PROXY0_CLK_CLK</td>
10908 <td>Input clock</td>
10909 </tr>
10910 </tbody>
10911 </table>
10912 </div>
10913 <div class="section" id="clocks-for-mcu-navss0-ringacc0-device">
10914 <span id="soc-doc-j721e-public-clks-mcu-navss0-ringacc0"></span><h3>Clocks for MCU_NAVSS0_RINGACC0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-ringacc0-device" title="Permalink to this headline">¶</a></h3>
10915 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_NAVSS0_RINGACC0</span></a> (ID = 235)</p>
10916 <p>Following is a mapping of Clocks IDs to function:</p>
10917 <table border="1" class="docutils">
10918 <colgroup>
10919 <col width="21%" />
10920 <col width="57%" />
10921 <col width="22%" />
10922 </colgroup>
10923 <thead valign="bottom">
10924 <tr class="row-odd"><th class="head">Clock ID</th>
10925 <th class="head">Name</th>
10926 <th class="head">Function</th>
10927 </tr>
10928 </thead>
10929 <tbody valign="top">
10930 <tr class="row-even"><td>0</td>
10931 <td>DEV_MCU_NAVSS0_RINGACC0_SYS_CLK</td>
10932 <td>Input clock</td>
10933 </tr>
10934 </tbody>
10935 </table>
10936 </div>
10937 <div class="section" id="clocks-for-mcu-navss0-udmap-0-device">
10938 <span id="soc-doc-j721e-public-clks-mcu-navss0-udmap-0"></span><h3>Clocks for MCU_NAVSS0_UDMAP_0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-udmap-0-device" title="Permalink to this headline">¶</a></h3>
10939 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_NAVSS0_UDMAP_0</span></a> (ID = 236)</p>
10940 <p>Following is a mapping of Clocks IDs to function:</p>
10941 <table border="1" class="docutils">
10942 <colgroup>
10943 <col width="21%" />
10944 <col width="56%" />
10945 <col width="23%" />
10946 </colgroup>
10947 <thead valign="bottom">
10948 <tr class="row-odd"><th class="head">Clock ID</th>
10949 <th class="head">Name</th>
10950 <th class="head">Function</th>
10951 </tr>
10952 </thead>
10953 <tbody valign="top">
10954 <tr class="row-even"><td>0</td>
10955 <td>DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK</td>
10956 <td>Input clock</td>
10957 </tr>
10958 </tbody>
10959 </table>
10960 </div>
10961 <div class="section" id="clocks-for-mcu-navss0-udmass-device">
10962 <span id="soc-doc-j721e-public-clks-mcu-navss0-udmass"></span><h3>Clocks for MCU_NAVSS0_UDMASS Device<a class="headerlink" href="#clocks-for-mcu-navss0-udmass-device" title="Permalink to this headline">¶</a></h3>
10963 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_NAVSS0_UDMASS</span></a> (ID = 303)</p>
10964 <p>Following is a mapping of Clocks IDs to function:</p>
10965 <table border="1" class="docutils">
10966 <colgroup>
10967 <col width="22%" />
10968 <col width="55%" />
10969 <col width="24%" />
10970 </colgroup>
10971 <thead valign="bottom">
10972 <tr class="row-odd"><th class="head">Clock ID</th>
10973 <th class="head">Name</th>
10974 <th class="head">Function</th>
10975 </tr>
10976 </thead>
10977 <tbody valign="top">
10978 <tr class="row-even"><td>0</td>
10979 <td>DEV_MCU_NAVSS0_UDMASS_VD2CLK</td>
10980 <td>Input clock</td>
10981 </tr>
10982 </tbody>
10983 </table>
10984 </div>
10985 <div class="section" id="clocks-for-mcu-navss0-udmass-inta-0-device">
10986 <span id="soc-doc-j721e-public-clks-mcu-navss0-udmass-inta-0"></span><h3>Clocks for MCU_NAVSS0_UDMASS_INTA_0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-udmass-inta-0-device" title="Permalink to this headline">¶</a></h3>
10987 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0</span></a> (ID = 233)</p>
10988 <p>Following is a mapping of Clocks IDs to function:</p>
10989 <table border="1" class="docutils">
10990 <colgroup>
10991 <col width="19%" />
10992 <col width="60%" />
10993 <col width="21%" />
10994 </colgroup>
10995 <thead valign="bottom">
10996 <tr class="row-odd"><th class="head">Clock ID</th>
10997 <th class="head">Name</th>
10998 <th class="head">Function</th>
10999 </tr>
11000 </thead>
11001 <tbody valign="top">
11002 <tr class="row-even"><td>0</td>
11003 <td>DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK</td>
11004 <td>Input clock</td>
11005 </tr>
11006 </tbody>
11007 </table>
11008 </div>
11009 <div class="section" id="clocks-for-mcu-pbist0-device">
11010 <span id="soc-doc-j721e-public-clks-mcu-pbist0"></span><h3>Clocks for MCU_PBIST0 Device<a class="headerlink" href="#clocks-for-mcu-pbist0-device" title="Permalink to this headline">¶</a></h3>
11011 <p><strong>This device has no defined clocks.</strong></p>
11012 </div>
11013 <div class="section" id="clocks-for-mcu-pbist1-device">
11014 <span id="soc-doc-j721e-public-clks-mcu-pbist1"></span><h3>Clocks for MCU_PBIST1 Device<a class="headerlink" href="#clocks-for-mcu-pbist1-device" title="Permalink to this headline">¶</a></h3>
11015 <p><strong>This device has no defined clocks.</strong></p>
11016 </div>
11017 <div class="section" id="clocks-for-mcu-r5fss0-device">
11018 <span id="soc-doc-j721e-public-clks-mcu-r5fss0"></span><h3>Clocks for MCU_R5FSS0 Device<a class="headerlink" href="#clocks-for-mcu-r5fss0-device" title="Permalink to this headline">¶</a></h3>
11019 <p><strong>This device has no defined clocks.</strong></p>
11020 </div>
11021 <div class="section" id="clocks-for-mcu-r5fss0-core0-device">
11022 <span id="soc-doc-j721e-public-clks-mcu-r5fss0-core0"></span><h3>Clocks for MCU_R5FSS0_CORE0 Device<a class="headerlink" href="#clocks-for-mcu-r5fss0-core0-device" title="Permalink to this headline">¶</a></h3>
11023 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_R5FSS0_CORE0</span></a> (ID = 250)</p>
11024 <p>Following is a mapping of Clocks IDs to function:</p>
11025 <table border="1" class="docutils">
11026 <colgroup>
11027 <col width="8%" />
11028 <col width="53%" />
11029 <col width="39%" />
11030 </colgroup>
11031 <thead valign="bottom">
11032 <tr class="row-odd"><th class="head">Clock ID</th>
11033 <th class="head">Name</th>
11034 <th class="head">Function</th>
11035 </tr>
11036 </thead>
11037 <tbody valign="top">
11038 <tr class="row-even"><td>0</td>
11039 <td>DEV_MCU_R5FSS0_CORE0_CPU_CLK</td>
11040 <td>Input muxed clock</td>
11041 </tr>
11042 <tr class="row-odd"><td>1</td>
11043 <td>DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK</td>
11044 <td>Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK</td>
11045 </tr>
11046 <tr class="row-even"><td>2</td>
11047 <td>DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3</td>
11048 <td>Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK</td>
11049 </tr>
11050 <tr class="row-odd"><td>3</td>
11051 <td>DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK</td>
11052 <td>Input clock</td>
11053 </tr>
11054 <tr class="row-even"><td>4</td>
11055 <td>DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE</td>
11056 <td>Input clock</td>
11057 </tr>
11058 </tbody>
11059 </table>
11060 </div>
11061 <div class="section" id="clocks-for-mcu-r5fss0-core1-device">
11062 <span id="soc-doc-j721e-public-clks-mcu-r5fss0-core1"></span><h3>Clocks for MCU_R5FSS0_CORE1 Device<a class="headerlink" href="#clocks-for-mcu-r5fss0-core1-device" title="Permalink to this headline">¶</a></h3>
11063 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_R5FSS0_CORE1</span></a> (ID = 251)</p>
11064 <p>Following is a mapping of Clocks IDs to function:</p>
11065 <table border="1" class="docutils">
11066 <colgroup>
11067 <col width="8%" />
11068 <col width="53%" />
11069 <col width="39%" />
11070 </colgroup>
11071 <thead valign="bottom">
11072 <tr class="row-odd"><th class="head">Clock ID</th>
11073 <th class="head">Name</th>
11074 <th class="head">Function</th>
11075 </tr>
11076 </thead>
11077 <tbody valign="top">
11078 <tr class="row-even"><td>0</td>
11079 <td>DEV_MCU_R5FSS0_CORE1_CPU_CLK</td>
11080 <td>Input muxed clock</td>
11081 </tr>
11082 <tr class="row-odd"><td>1</td>
11083 <td>DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK</td>
11084 <td>Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK</td>
11085 </tr>
11086 <tr class="row-even"><td>2</td>
11087 <td>DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3</td>
11088 <td>Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK</td>
11089 </tr>
11090 <tr class="row-odd"><td>3</td>
11091 <td>DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK</td>
11092 <td>Input clock</td>
11093 </tr>
11094 <tr class="row-even"><td>4</td>
11095 <td>DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE</td>
11096 <td>Input clock</td>
11097 </tr>
11098 </tbody>
11099 </table>
11100 </div>
11101 <div class="section" id="clocks-for-mcu-rti0-device">
11102 <span id="soc-doc-j721e-public-clks-mcu-rti0"></span><h3>Clocks for MCU_RTI0 Device<a class="headerlink" href="#clocks-for-mcu-rti0-device" title="Permalink to this headline">¶</a></h3>
11103 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_RTI0</span></a> (ID = 262)</p>
11104 <p>Following is a mapping of Clocks IDs to function:</p>
11105 <table border="1" class="docutils">
11106 <colgroup>
11107 <col width="9%" />
11108 <col width="53%" />
11109 <col width="38%" />
11110 </colgroup>
11111 <thead valign="bottom">
11112 <tr class="row-odd"><th class="head">Clock ID</th>
11113 <th class="head">Name</th>
11114 <th class="head">Function</th>
11115 </tr>
11116 </thead>
11117 <tbody valign="top">
11118 <tr class="row-even"><td>0</td>
11119 <td>DEV_MCU_RTI0_VBUSP_CLK</td>
11120 <td>Input clock</td>
11121 </tr>
11122 <tr class="row-odd"><td>1</td>
11123 <td>DEV_MCU_RTI0_RTI_CLK</td>
11124 <td>Input muxed clock</td>
11125 </tr>
11126 <tr class="row-even"><td>2</td>
11127 <td>DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
11128 <td>Parent input clock option to DEV_MCU_RTI0_RTI_CLK</td>
11129 </tr>
11130 <tr class="row-odd"><td>3</td>
11131 <td>DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
11132 <td>Parent input clock option to DEV_MCU_RTI0_RTI_CLK</td>
11133 </tr>
11134 <tr class="row-even"><td>4</td>
11135 <td>DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
11136 <td>Parent input clock option to DEV_MCU_RTI0_RTI_CLK</td>
11137 </tr>
11138 <tr class="row-odd"><td>5</td>
11139 <td>DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
11140 <td>Parent input clock option to DEV_MCU_RTI0_RTI_CLK</td>
11141 </tr>
11142 </tbody>
11143 </table>
11144 </div>
11145 <div class="section" id="clocks-for-mcu-rti1-device">
11146 <span id="soc-doc-j721e-public-clks-mcu-rti1"></span><h3>Clocks for MCU_RTI1 Device<a class="headerlink" href="#clocks-for-mcu-rti1-device" title="Permalink to this headline">¶</a></h3>
11147 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_RTI1</span></a> (ID = 263)</p>
11148 <p>Following is a mapping of Clocks IDs to function:</p>
11149 <table border="1" class="docutils">
11150 <colgroup>
11151 <col width="9%" />
11152 <col width="53%" />
11153 <col width="38%" />
11154 </colgroup>
11155 <thead valign="bottom">
11156 <tr class="row-odd"><th class="head">Clock ID</th>
11157 <th class="head">Name</th>
11158 <th class="head">Function</th>
11159 </tr>
11160 </thead>
11161 <tbody valign="top">
11162 <tr class="row-even"><td>0</td>
11163 <td>DEV_MCU_RTI1_VBUSP_CLK</td>
11164 <td>Input clock</td>
11165 </tr>
11166 <tr class="row-odd"><td>1</td>
11167 <td>DEV_MCU_RTI1_RTI_CLK</td>
11168 <td>Input muxed clock</td>
11169 </tr>
11170 <tr class="row-even"><td>2</td>
11171 <td>DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
11172 <td>Parent input clock option to DEV_MCU_RTI1_RTI_CLK</td>
11173 </tr>
11174 <tr class="row-odd"><td>3</td>
11175 <td>DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
11176 <td>Parent input clock option to DEV_MCU_RTI1_RTI_CLK</td>
11177 </tr>
11178 <tr class="row-even"><td>4</td>
11179 <td>DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
11180 <td>Parent input clock option to DEV_MCU_RTI1_RTI_CLK</td>
11181 </tr>
11182 <tr class="row-odd"><td>5</td>
11183 <td>DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
11184 <td>Parent input clock option to DEV_MCU_RTI1_RTI_CLK</td>
11185 </tr>
11186 </tbody>
11187 </table>
11188 </div>
11189 <div class="section" id="clocks-for-mcu-sa2-ul0-device">
11190 <span id="soc-doc-j721e-public-clks-mcu-sa2-ul0"></span><h3>Clocks for MCU_SA2_UL0 Device<a class="headerlink" href="#clocks-for-mcu-sa2-ul0-device" title="Permalink to this headline">¶</a></h3>
11191 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_SA2_UL0</span></a> (ID = 265)</p>
11192 <p>Following is a mapping of Clocks IDs to function:</p>
11193 <table border="1" class="docutils">
11194 <colgroup>
11195 <col width="23%" />
11196 <col width="53%" />
11197 <col width="25%" />
11198 </colgroup>
11199 <thead valign="bottom">
11200 <tr class="row-odd"><th class="head">Clock ID</th>
11201 <th class="head">Name</th>
11202 <th class="head">Function</th>
11203 </tr>
11204 </thead>
11205 <tbody valign="top">
11206 <tr class="row-even"><td>0</td>
11207 <td>DEV_MCU_SA2_UL0_X2_CLK</td>
11208 <td>Input clock</td>
11209 </tr>
11210 <tr class="row-odd"><td>1</td>
11211 <td>DEV_MCU_SA2_UL0_PKA_IN_CLK</td>
11212 <td>Input clock</td>
11213 </tr>
11214 <tr class="row-even"><td>2</td>
11215 <td>DEV_MCU_SA2_UL0_X1_CLK</td>
11216 <td>Input clock</td>
11217 </tr>
11218 </tbody>
11219 </table>
11220 </div>
11221 <div class="section" id="clocks-for-mcu-timer0-device">
11222 <span id="soc-doc-j721e-public-clks-mcu-timer0"></span><h3>Clocks for MCU_TIMER0 Device<a class="headerlink" href="#clocks-for-mcu-timer0-device" title="Permalink to this headline">¶</a></h3>
11223 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_TIMER0</span></a> (ID = 35)</p>
11224 <p>Following is a mapping of Clocks IDs to function:</p>
11225 <table border="1" class="docutils">
11226 <colgroup>
11227 <col width="8%" />
11228 <col width="53%" />
11229 <col width="39%" />
11230 </colgroup>
11231 <thead valign="bottom">
11232 <tr class="row-odd"><th class="head">Clock ID</th>
11233 <th class="head">Name</th>
11234 <th class="head">Function</th>
11235 </tr>
11236 </thead>
11237 <tbody valign="top">
11238 <tr class="row-even"><td>0</td>
11239 <td>DEV_MCU_TIMER0_TIMER_HCLK_CLK</td>
11240 <td>Input clock</td>
11241 </tr>
11242 <tr class="row-odd"><td>1</td>
11243 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
11244 <td>Input muxed clock</td>
11245 </tr>
11246 <tr class="row-even"><td>2</td>
11247 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
11248 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
11249 </tr>
11250 <tr class="row-odd"><td>3</td>
11251 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6</td>
11252 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
11253 </tr>
11254 <tr class="row-even"><td>4</td>
11255 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
11256 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
11257 </tr>
11258 <tr class="row-odd"><td>5</td>
11259 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK</td>
11260 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
11261 </tr>
11262 <tr class="row-even"><td>6</td>
11263 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
11264 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
11265 </tr>
11266 <tr class="row-odd"><td>7</td>
11267 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
11268 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
11269 </tr>
11270 <tr class="row-even"><td>8</td>
11271 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0</td>
11272 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
11273 </tr>
11274 <tr class="row-odd"><td>9</td>
11275 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
11276 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
11277 </tr>
11278 <tr class="row-even"><td>10</td>
11279 <td>DEV_MCU_TIMER0_TIMER_PWM</td>
11280 <td>Output clock</td>
11281 </tr>
11282 </tbody>
11283 </table>
11284 </div>
11285 <div class="section" id="clocks-for-mcu-timer1-device">
11286 <span id="soc-doc-j721e-public-clks-mcu-timer1"></span><h3>Clocks for MCU_TIMER1 Device<a class="headerlink" href="#clocks-for-mcu-timer1-device" title="Permalink to this headline">¶</a></h3>
11287 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_TIMER1</span></a> (ID = 71)</p>
11288 <p>Following is a mapping of Clocks IDs to function:</p>
11289 <table border="1" class="docutils">
11290 <colgroup>
11291 <col width="9%" />
11292 <col width="49%" />
11293 <col width="43%" />
11294 </colgroup>
11295 <thead valign="bottom">
11296 <tr class="row-odd"><th class="head">Clock ID</th>
11297 <th class="head">Name</th>
11298 <th class="head">Function</th>
11299 </tr>
11300 </thead>
11301 <tbody valign="top">
11302 <tr class="row-even"><td>0</td>
11303 <td>DEV_MCU_TIMER1_TIMER_HCLK_CLK</td>
11304 <td>Input clock</td>
11305 </tr>
11306 <tr class="row-odd"><td>1</td>
11307 <td>DEV_MCU_TIMER1_TIMER_TCLK_CLK</td>
11308 <td>Input muxed clock</td>
11309 </tr>
11310 <tr class="row-even"><td>2</td>
11311 <td>DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1</td>
11312 <td>Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK</td>
11313 </tr>
11314 <tr class="row-odd"><td>3</td>
11315 <td>DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM</td>
11316 <td>Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK</td>
11317 </tr>
11318 </tbody>
11319 </table>
11320 </div>
11321 <div class="section" id="clocks-for-mcu-timer2-device">
11322 <span id="soc-doc-j721e-public-clks-mcu-timer2"></span><h3>Clocks for MCU_TIMER2 Device<a class="headerlink" href="#clocks-for-mcu-timer2-device" title="Permalink to this headline">¶</a></h3>
11323 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_TIMER2</span></a> (ID = 72)</p>
11324 <p>Following is a mapping of Clocks IDs to function:</p>
11325 <table border="1" class="docutils">
11326 <colgroup>
11327 <col width="8%" />
11328 <col width="53%" />
11329 <col width="39%" />
11330 </colgroup>
11331 <thead valign="bottom">
11332 <tr class="row-odd"><th class="head">Clock ID</th>
11333 <th class="head">Name</th>
11334 <th class="head">Function</th>
11335 </tr>
11336 </thead>
11337 <tbody valign="top">
11338 <tr class="row-even"><td>0</td>
11339 <td>DEV_MCU_TIMER2_TIMER_HCLK_CLK</td>
11340 <td>Input clock</td>
11341 </tr>
11342 <tr class="row-odd"><td>1</td>
11343 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
11344 <td>Input muxed clock</td>
11345 </tr>
11346 <tr class="row-even"><td>2</td>
11347 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
11348 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
11349 </tr>
11350 <tr class="row-odd"><td>3</td>
11351 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6</td>
11352 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
11353 </tr>
11354 <tr class="row-even"><td>4</td>
11355 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
11356 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
11357 </tr>
11358 <tr class="row-odd"><td>5</td>
11359 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK</td>
11360 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
11361 </tr>
11362 <tr class="row-even"><td>6</td>
11363 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
11364 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
11365 </tr>
11366 <tr class="row-odd"><td>7</td>
11367 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
11368 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
11369 </tr>
11370 <tr class="row-even"><td>8</td>
11371 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0</td>
11372 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
11373 </tr>
11374 <tr class="row-odd"><td>9</td>
11375 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
11376 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
11377 </tr>
11378 <tr class="row-even"><td>10</td>
11379 <td>DEV_MCU_TIMER2_TIMER_PWM</td>
11380 <td>Output clock</td>
11381 </tr>
11382 </tbody>
11383 </table>
11384 </div>
11385 <div class="section" id="clocks-for-mcu-timer3-device">
11386 <span id="soc-doc-j721e-public-clks-mcu-timer3"></span><h3>Clocks for MCU_TIMER3 Device<a class="headerlink" href="#clocks-for-mcu-timer3-device" title="Permalink to this headline">¶</a></h3>
11387 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_TIMER3</span></a> (ID = 73)</p>
11388 <p>Following is a mapping of Clocks IDs to function:</p>
11389 <table border="1" class="docutils">
11390 <colgroup>
11391 <col width="9%" />
11392 <col width="49%" />
11393 <col width="43%" />
11394 </colgroup>
11395 <thead valign="bottom">
11396 <tr class="row-odd"><th class="head">Clock ID</th>
11397 <th class="head">Name</th>
11398 <th class="head">Function</th>
11399 </tr>
11400 </thead>
11401 <tbody valign="top">
11402 <tr class="row-even"><td>0</td>
11403 <td>DEV_MCU_TIMER3_TIMER_HCLK_CLK</td>
11404 <td>Input clock</td>
11405 </tr>
11406 <tr class="row-odd"><td>1</td>
11407 <td>DEV_MCU_TIMER3_TIMER_TCLK_CLK</td>
11408 <td>Input muxed clock</td>
11409 </tr>
11410 <tr class="row-even"><td>2</td>
11411 <td>DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3</td>
11412 <td>Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK</td>
11413 </tr>
11414 <tr class="row-odd"><td>3</td>
11415 <td>DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM</td>
11416 <td>Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK</td>
11417 </tr>
11418 </tbody>
11419 </table>
11420 </div>
11421 <div class="section" id="clocks-for-mcu-timer4-device">
11422 <span id="soc-doc-j721e-public-clks-mcu-timer4"></span><h3>Clocks for MCU_TIMER4 Device<a class="headerlink" href="#clocks-for-mcu-timer4-device" title="Permalink to this headline">¶</a></h3>
11423 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_TIMER4</span></a> (ID = 74)</p>
11424 <p>Following is a mapping of Clocks IDs to function:</p>
11425 <table border="1" class="docutils">
11426 <colgroup>
11427 <col width="8%" />
11428 <col width="53%" />
11429 <col width="39%" />
11430 </colgroup>
11431 <thead valign="bottom">
11432 <tr class="row-odd"><th class="head">Clock ID</th>
11433 <th class="head">Name</th>
11434 <th class="head">Function</th>
11435 </tr>
11436 </thead>
11437 <tbody valign="top">
11438 <tr class="row-even"><td>0</td>
11439 <td>DEV_MCU_TIMER4_TIMER_HCLK_CLK</td>
11440 <td>Input clock</td>
11441 </tr>
11442 <tr class="row-odd"><td>1</td>
11443 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
11444 <td>Input muxed clock</td>
11445 </tr>
11446 <tr class="row-even"><td>2</td>
11447 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
11448 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
11449 </tr>
11450 <tr class="row-odd"><td>3</td>
11451 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6</td>
11452 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
11453 </tr>
11454 <tr class="row-even"><td>4</td>
11455 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
11456 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
11457 </tr>
11458 <tr class="row-odd"><td>5</td>
11459 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK</td>
11460 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
11461 </tr>
11462 <tr class="row-even"><td>6</td>
11463 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
11464 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
11465 </tr>
11466 <tr class="row-odd"><td>7</td>
11467 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
11468 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
11469 </tr>
11470 <tr class="row-even"><td>8</td>
11471 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0</td>
11472 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
11473 </tr>
11474 <tr class="row-odd"><td>9</td>
11475 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
11476 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
11477 </tr>
11478 <tr class="row-even"><td>10</td>
11479 <td>DEV_MCU_TIMER4_TIMER_PWM</td>
11480 <td>Output clock</td>
11481 </tr>
11482 </tbody>
11483 </table>
11484 </div>
11485 <div class="section" id="clocks-for-mcu-timer5-device">
11486 <span id="soc-doc-j721e-public-clks-mcu-timer5"></span><h3>Clocks for MCU_TIMER5 Device<a class="headerlink" href="#clocks-for-mcu-timer5-device" title="Permalink to this headline">¶</a></h3>
11487 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_TIMER5</span></a> (ID = 75)</p>
11488 <p>Following is a mapping of Clocks IDs to function:</p>
11489 <table border="1" class="docutils">
11490 <colgroup>
11491 <col width="9%" />
11492 <col width="49%" />
11493 <col width="43%" />
11494 </colgroup>
11495 <thead valign="bottom">
11496 <tr class="row-odd"><th class="head">Clock ID</th>
11497 <th class="head">Name</th>
11498 <th class="head">Function</th>
11499 </tr>
11500 </thead>
11501 <tbody valign="top">
11502 <tr class="row-even"><td>0</td>
11503 <td>DEV_MCU_TIMER5_TIMER_HCLK_CLK</td>
11504 <td>Input clock</td>
11505 </tr>
11506 <tr class="row-odd"><td>1</td>
11507 <td>DEV_MCU_TIMER5_TIMER_TCLK_CLK</td>
11508 <td>Input muxed clock</td>
11509 </tr>
11510 <tr class="row-even"><td>2</td>
11511 <td>DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5</td>
11512 <td>Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK</td>
11513 </tr>
11514 <tr class="row-odd"><td>3</td>
11515 <td>DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM</td>
11516 <td>Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK</td>
11517 </tr>
11518 </tbody>
11519 </table>
11520 </div>
11521 <div class="section" id="clocks-for-mcu-timer6-device">
11522 <span id="soc-doc-j721e-public-clks-mcu-timer6"></span><h3>Clocks for MCU_TIMER6 Device<a class="headerlink" href="#clocks-for-mcu-timer6-device" title="Permalink to this headline">¶</a></h3>
11523 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_TIMER6</span></a> (ID = 76)</p>
11524 <p>Following is a mapping of Clocks IDs to function:</p>
11525 <table border="1" class="docutils">
11526 <colgroup>
11527 <col width="8%" />
11528 <col width="53%" />
11529 <col width="39%" />
11530 </colgroup>
11531 <thead valign="bottom">
11532 <tr class="row-odd"><th class="head">Clock ID</th>
11533 <th class="head">Name</th>
11534 <th class="head">Function</th>
11535 </tr>
11536 </thead>
11537 <tbody valign="top">
11538 <tr class="row-even"><td>0</td>
11539 <td>DEV_MCU_TIMER6_TIMER_HCLK_CLK</td>
11540 <td>Input clock</td>
11541 </tr>
11542 <tr class="row-odd"><td>1</td>
11543 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
11544 <td>Input muxed clock</td>
11545 </tr>
11546 <tr class="row-even"><td>2</td>
11547 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
11548 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
11549 </tr>
11550 <tr class="row-odd"><td>3</td>
11551 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6</td>
11552 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
11553 </tr>
11554 <tr class="row-even"><td>4</td>
11555 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
11556 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
11557 </tr>
11558 <tr class="row-odd"><td>5</td>
11559 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK</td>
11560 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
11561 </tr>
11562 <tr class="row-even"><td>6</td>
11563 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
11564 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
11565 </tr>
11566 <tr class="row-odd"><td>7</td>
11567 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
11568 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
11569 </tr>
11570 <tr class="row-even"><td>8</td>
11571 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0</td>
11572 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
11573 </tr>
11574 <tr class="row-odd"><td>9</td>
11575 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
11576 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
11577 </tr>
11578 <tr class="row-even"><td>10</td>
11579 <td>DEV_MCU_TIMER6_TIMER_PWM</td>
11580 <td>Output clock</td>
11581 </tr>
11582 </tbody>
11583 </table>
11584 </div>
11585 <div class="section" id="clocks-for-mcu-timer7-device">
11586 <span id="soc-doc-j721e-public-clks-mcu-timer7"></span><h3>Clocks for MCU_TIMER7 Device<a class="headerlink" href="#clocks-for-mcu-timer7-device" title="Permalink to this headline">¶</a></h3>
11587 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_TIMER7</span></a> (ID = 77)</p>
11588 <p>Following is a mapping of Clocks IDs to function:</p>
11589 <table border="1" class="docutils">
11590 <colgroup>
11591 <col width="9%" />
11592 <col width="49%" />
11593 <col width="43%" />
11594 </colgroup>
11595 <thead valign="bottom">
11596 <tr class="row-odd"><th class="head">Clock ID</th>
11597 <th class="head">Name</th>
11598 <th class="head">Function</th>
11599 </tr>
11600 </thead>
11601 <tbody valign="top">
11602 <tr class="row-even"><td>0</td>
11603 <td>DEV_MCU_TIMER7_TIMER_HCLK_CLK</td>
11604 <td>Input clock</td>
11605 </tr>
11606 <tr class="row-odd"><td>1</td>
11607 <td>DEV_MCU_TIMER7_TIMER_TCLK_CLK</td>
11608 <td>Input muxed clock</td>
11609 </tr>
11610 <tr class="row-even"><td>2</td>
11611 <td>DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7</td>
11612 <td>Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK</td>
11613 </tr>
11614 <tr class="row-odd"><td>3</td>
11615 <td>DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM</td>
11616 <td>Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK</td>
11617 </tr>
11618 </tbody>
11619 </table>
11620 </div>
11621 <div class="section" id="clocks-for-mcu-timer8-device">
11622 <span id="soc-doc-j721e-public-clks-mcu-timer8"></span><h3>Clocks for MCU_TIMER8 Device<a class="headerlink" href="#clocks-for-mcu-timer8-device" title="Permalink to this headline">¶</a></h3>
11623 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_TIMER8</span></a> (ID = 78)</p>
11624 <p>Following is a mapping of Clocks IDs to function:</p>
11625 <table border="1" class="docutils">
11626 <colgroup>
11627 <col width="8%" />
11628 <col width="53%" />
11629 <col width="39%" />
11630 </colgroup>
11631 <thead valign="bottom">
11632 <tr class="row-odd"><th class="head">Clock ID</th>
11633 <th class="head">Name</th>
11634 <th class="head">Function</th>
11635 </tr>
11636 </thead>
11637 <tbody valign="top">
11638 <tr class="row-even"><td>0</td>
11639 <td>DEV_MCU_TIMER8_TIMER_HCLK_CLK</td>
11640 <td>Input clock</td>
11641 </tr>
11642 <tr class="row-odd"><td>1</td>
11643 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
11644 <td>Input muxed clock</td>
11645 </tr>
11646 <tr class="row-even"><td>2</td>
11647 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
11648 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
11649 </tr>
11650 <tr class="row-odd"><td>3</td>
11651 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6</td>
11652 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
11653 </tr>
11654 <tr class="row-even"><td>4</td>
11655 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
11656 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
11657 </tr>
11658 <tr class="row-odd"><td>5</td>
11659 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK</td>
11660 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
11661 </tr>
11662 <tr class="row-even"><td>6</td>
11663 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
11664 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
11665 </tr>
11666 <tr class="row-odd"><td>7</td>
11667 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
11668 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
11669 </tr>
11670 <tr class="row-even"><td>8</td>
11671 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0</td>
11672 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
11673 </tr>
11674 <tr class="row-odd"><td>9</td>
11675 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
11676 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
11677 </tr>
11678 <tr class="row-even"><td>10</td>
11679 <td>DEV_MCU_TIMER8_TIMER_PWM</td>
11680 <td>Output clock</td>
11681 </tr>
11682 </tbody>
11683 </table>
11684 </div>
11685 <div class="section" id="clocks-for-mcu-timer9-device">
11686 <span id="soc-doc-j721e-public-clks-mcu-timer9"></span><h3>Clocks for MCU_TIMER9 Device<a class="headerlink" href="#clocks-for-mcu-timer9-device" title="Permalink to this headline">¶</a></h3>
11687 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_TIMER9</span></a> (ID = 79)</p>
11688 <p>Following is a mapping of Clocks IDs to function:</p>
11689 <table border="1" class="docutils">
11690 <colgroup>
11691 <col width="9%" />
11692 <col width="49%" />
11693 <col width="43%" />
11694 </colgroup>
11695 <thead valign="bottom">
11696 <tr class="row-odd"><th class="head">Clock ID</th>
11697 <th class="head">Name</th>
11698 <th class="head">Function</th>
11699 </tr>
11700 </thead>
11701 <tbody valign="top">
11702 <tr class="row-even"><td>0</td>
11703 <td>DEV_MCU_TIMER9_TIMER_HCLK_CLK</td>
11704 <td>Input clock</td>
11705 </tr>
11706 <tr class="row-odd"><td>1</td>
11707 <td>DEV_MCU_TIMER9_TIMER_TCLK_CLK</td>
11708 <td>Input muxed clock</td>
11709 </tr>
11710 <tr class="row-even"><td>2</td>
11711 <td>DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9</td>
11712 <td>Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK</td>
11713 </tr>
11714 <tr class="row-odd"><td>3</td>
11715 <td>DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM</td>
11716 <td>Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK</td>
11717 </tr>
11718 </tbody>
11719 </table>
11720 </div>
11721 <div class="section" id="clocks-for-mcu-uart0-device">
11722 <span id="soc-doc-j721e-public-clks-mcu-uart0"></span><h3>Clocks for MCU_UART0 Device<a class="headerlink" href="#clocks-for-mcu-uart0-device" title="Permalink to this headline">¶</a></h3>
11723 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MCU_UART0</span></a> (ID = 149)</p>
11724 <p>Following is a mapping of Clocks IDs to function:</p>
11725 <table border="1" class="docutils">
11726 <colgroup>
11727 <col width="9%" />
11728 <col width="51%" />
11729 <col width="40%" />
11730 </colgroup>
11731 <thead valign="bottom">
11732 <tr class="row-odd"><th class="head">Clock ID</th>
11733 <th class="head">Name</th>
11734 <th class="head">Function</th>
11735 </tr>
11736 </thead>
11737 <tbody valign="top">
11738 <tr class="row-even"><td>0</td>
11739 <td>DEV_MCU_UART0_FCLK_CLK</td>
11740 <td>Input muxed clock</td>
11741 </tr>
11742 <tr class="row-odd"><td>1</td>
11743 <td>DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK</td>
11744 <td>Parent input clock option to DEV_MCU_UART0_FCLK_CLK</td>
11745 </tr>
11746 <tr class="row-even"><td>2</td>
11747 <td>DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK</td>
11748 <td>Parent input clock option to DEV_MCU_UART0_FCLK_CLK</td>
11749 </tr>
11750 <tr class="row-odd"><td>3</td>
11751 <td>DEV_MCU_UART0_VBUSP_CLK</td>
11752 <td>Input clock</td>
11753 </tr>
11754 </tbody>
11755 </table>
11756 </div>
11757 <div class="section" id="clocks-for-mlb0-device">
11758 <span id="soc-doc-j721e-public-clks-mlb0"></span><h3>Clocks for MLB0 Device<a class="headerlink" href="#clocks-for-mlb0-device" title="Permalink to this headline">¶</a></h3>
11759 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MLB0</span></a> (ID = 186)</p>
11760 <p>Following is a mapping of Clocks IDs to function:</p>
11761 <table border="1" class="docutils">
11762 <colgroup>
11763 <col width="24%" />
11764 <col width="50%" />
11765 <col width="26%" />
11766 </colgroup>
11767 <thead valign="bottom">
11768 <tr class="row-odd"><th class="head">Clock ID</th>
11769 <th class="head">Name</th>
11770 <th class="head">Function</th>
11771 </tr>
11772 </thead>
11773 <tbody valign="top">
11774 <tr class="row-even"><td>0</td>
11775 <td>DEV_MLB0_MLBSS_MLB_CLK</td>
11776 <td>Input clock</td>
11777 </tr>
11778 <tr class="row-odd"><td>1</td>
11779 <td>DEV_MLB0_MLBSS_SCLK_CLK</td>
11780 <td>Input clock</td>
11781 </tr>
11782 <tr class="row-even"><td>2</td>
11783 <td>DEV_MLB0_MLBSS_HCLK_CLK</td>
11784 <td>Input clock</td>
11785 </tr>
11786 <tr class="row-odd"><td>3</td>
11787 <td>DEV_MLB0_MLBSS_PCLK_CLK</td>
11788 <td>Input clock</td>
11789 </tr>
11790 <tr class="row-even"><td>4</td>
11791 <td>DEV_MLB0_MLBSS_AMLB_CLK</td>
11792 <td>Input clock</td>
11793 </tr>
11794 </tbody>
11795 </table>
11796 </div>
11797 <div class="section" id="clocks-for-mmcsd0-device">
11798 <span id="soc-doc-j721e-public-clks-mmcsd0"></span><h3>Clocks for MMCSD0 Device<a class="headerlink" href="#clocks-for-mmcsd0-device" title="Permalink to this headline">¶</a></h3>
11799 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MMCSD0</span></a> (ID = 91)</p>
11800 <p>Following is a mapping of Clocks IDs to function:</p>
11801 <table border="1" class="docutils">
11802 <colgroup>
11803 <col width="9%" />
11804 <col width="50%" />
11805 <col width="41%" />
11806 </colgroup>
11807 <thead valign="bottom">
11808 <tr class="row-odd"><th class="head">Clock ID</th>
11809 <th class="head">Name</th>
11810 <th class="head">Function</th>
11811 </tr>
11812 </thead>
11813 <tbody valign="top">
11814 <tr class="row-even"><td>0</td>
11815 <td>DEV_MMCSD0_EMMCSS_VBUS_CLK</td>
11816 <td>Input clock</td>
11817 </tr>
11818 <tr class="row-odd"><td>1</td>
11819 <td>DEV_MMCSD0_EMMCSS_XIN_CLK</td>
11820 <td>Input muxed clock</td>
11821 </tr>
11822 <tr class="row-even"><td>2</td>
11823 <td>DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK</td>
11824 <td>Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK</td>
11825 </tr>
11826 <tr class="row-odd"><td>3</td>
11827 <td>DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK</td>
11828 <td>Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK</td>
11829 </tr>
11830 <tr class="row-even"><td>4</td>
11831 <td>DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
11832 <td>Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK</td>
11833 </tr>
11834 <tr class="row-odd"><td>5</td>
11835 <td>DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK</td>
11836 <td>Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK</td>
11837 </tr>
11838 <tr class="row-even"><td>6</td>
11839 <td>DEV_MMCSD0_EMMCSS_IO_CLK</td>
11840 <td>Output clock</td>
11841 </tr>
11842 </tbody>
11843 </table>
11844 </div>
11845 <div class="section" id="clocks-for-mmcsd1-device">
11846 <span id="soc-doc-j721e-public-clks-mmcsd1"></span><h3>Clocks for MMCSD1 Device<a class="headerlink" href="#clocks-for-mmcsd1-device" title="Permalink to this headline">¶</a></h3>
11847 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MMCSD1</span></a> (ID = 92)</p>
11848 <p>Following is a mapping of Clocks IDs to function:</p>
11849 <table border="1" class="docutils">
11850 <colgroup>
11851 <col width="9%" />
11852 <col width="50%" />
11853 <col width="41%" />
11854 </colgroup>
11855 <thead valign="bottom">
11856 <tr class="row-odd"><th class="head">Clock ID</th>
11857 <th class="head">Name</th>
11858 <th class="head">Function</th>
11859 </tr>
11860 </thead>
11861 <tbody valign="top">
11862 <tr class="row-even"><td>0</td>
11863 <td>DEV_MMCSD1_EMMCSDSS_XIN_CLK</td>
11864 <td>Input muxed clock</td>
11865 </tr>
11866 <tr class="row-odd"><td>1</td>
11867 <td>DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK</td>
11868 <td>Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK</td>
11869 </tr>
11870 <tr class="row-even"><td>2</td>
11871 <td>DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK</td>
11872 <td>Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK</td>
11873 </tr>
11874 <tr class="row-odd"><td>3</td>
11875 <td>DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
11876 <td>Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK</td>
11877 </tr>
11878 <tr class="row-even"><td>4</td>
11879 <td>DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK</td>
11880 <td>Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK</td>
11881 </tr>
11882 <tr class="row-odd"><td>5</td>
11883 <td>DEV_MMCSD1_EMMCSDSS_VBUS_CLK</td>
11884 <td>Input clock</td>
11885 </tr>
11886 <tr class="row-even"><td>6</td>
11887 <td>DEV_MMCSD1_EMMCSDSS_IO_CLK_I</td>
11888 <td>Input clock</td>
11889 </tr>
11890 <tr class="row-odd"><td>7</td>
11891 <td>DEV_MMCSD1_EMMCSDSS_IO_CLK_O</td>
11892 <td>Output clock</td>
11893 </tr>
11894 </tbody>
11895 </table>
11896 </div>
11897 <div class="section" id="clocks-for-mmcsd2-device">
11898 <span id="soc-doc-j721e-public-clks-mmcsd2"></span><h3>Clocks for MMCSD2 Device<a class="headerlink" href="#clocks-for-mmcsd2-device" title="Permalink to this headline">¶</a></h3>
11899 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_MMCSD2</span></a> (ID = 93)</p>
11900 <p>Following is a mapping of Clocks IDs to function:</p>
11901 <table border="1" class="docutils">
11902 <colgroup>
11903 <col width="9%" />
11904 <col width="50%" />
11905 <col width="41%" />
11906 </colgroup>
11907 <thead valign="bottom">
11908 <tr class="row-odd"><th class="head">Clock ID</th>
11909 <th class="head">Name</th>
11910 <th class="head">Function</th>
11911 </tr>
11912 </thead>
11913 <tbody valign="top">
11914 <tr class="row-even"><td>0</td>
11915 <td>DEV_MMCSD2_EMMCSDSS_XIN_CLK</td>
11916 <td>Input muxed clock</td>
11917 </tr>
11918 <tr class="row-odd"><td>1</td>
11919 <td>DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK</td>
11920 <td>Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK</td>
11921 </tr>
11922 <tr class="row-even"><td>2</td>
11923 <td>DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK</td>
11924 <td>Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK</td>
11925 </tr>
11926 <tr class="row-odd"><td>3</td>
11927 <td>DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
11928 <td>Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK</td>
11929 </tr>
11930 <tr class="row-even"><td>4</td>
11931 <td>DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK</td>
11932 <td>Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK</td>
11933 </tr>
11934 <tr class="row-odd"><td>5</td>
11935 <td>DEV_MMCSD2_EMMCSDSS_VBUS_CLK</td>
11936 <td>Input clock</td>
11937 </tr>
11938 <tr class="row-even"><td>6</td>
11939 <td>DEV_MMCSD2_EMMCSDSS_IO_CLK_I</td>
11940 <td>Input clock</td>
11941 </tr>
11942 <tr class="row-odd"><td>7</td>
11943 <td>DEV_MMCSD2_EMMCSDSS_IO_CLK_O</td>
11944 <td>Output clock</td>
11945 </tr>
11946 </tbody>
11947 </table>
11948 </div>
11949 <div class="section" id="clocks-for-navss0-device">
11950 <span id="soc-doc-j721e-public-clks-navss0"></span><h3>Clocks for NAVSS0 Device<a class="headerlink" href="#clocks-for-navss0-device" title="Permalink to this headline">¶</a></h3>
11951 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0</span></a> (ID = 199)</p>
11952 <p>Following is a mapping of Clocks IDs to function:</p>
11953 <table border="1" class="docutils">
11954 <colgroup>
11955 <col width="24%" />
11956 <col width="48%" />
11957 <col width="28%" />
11958 </colgroup>
11959 <thead valign="bottom">
11960 <tr class="row-odd"><th class="head">Clock ID</th>
11961 <th class="head">Name</th>
11962 <th class="head">Function</th>
11963 </tr>
11964 </thead>
11965 <tbody valign="top">
11966 <tr class="row-even"><td>0</td>
11967 <td>DEV_NAVSS0_CPTS0_GENF3</td>
11968 <td>Output clock</td>
11969 </tr>
11970 <tr class="row-odd"><td>1</td>
11971 <td>DEV_NAVSS0_CPTS0_GENF2</td>
11972 <td>Output clock</td>
11973 </tr>
11974 </tbody>
11975 </table>
11976 </div>
11977 <div class="section" id="clocks-for-navss0-cpts-0-device">
11978 <span id="soc-doc-j721e-public-clks-navss0-cpts-0"></span><h3>Clocks for NAVSS0_CPTS_0 Device<a class="headerlink" href="#clocks-for-navss0-cpts-0-device" title="Permalink to this headline">¶</a></h3>
11979 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_CPTS_0</span></a> (ID = 201)</p>
11980 <p>Following is a mapping of Clocks IDs to function:</p>
11981 <table border="1" class="docutils">
11982 <colgroup>
11983 <col width="9%" />
11984 <col width="53%" />
11985 <col width="38%" />
11986 </colgroup>
11987 <thead valign="bottom">
11988 <tr class="row-odd"><th class="head">Clock ID</th>
11989 <th class="head">Name</th>
11990 <th class="head">Function</th>
11991 </tr>
11992 </thead>
11993 <tbody valign="top">
11994 <tr class="row-even"><td>0</td>
11995 <td>DEV_NAVSS0_CPTS_0_VBUSP_GCLK</td>
11996 <td>Input clock</td>
11997 </tr>
11998 <tr class="row-odd"><td>1</td>
11999 <td>DEV_NAVSS0_CPTS_0_RCLK</td>
12000 <td>Input muxed clock</td>
12001 </tr>
12002 <tr class="row-even"><td>2</td>
12003 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
12004 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12005 </tr>
12006 <tr class="row-odd"><td>3</td>
12007 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
12008 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12009 </tr>
12010 <tr class="row-even"><td>4</td>
12011 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
12012 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12013 </tr>
12014 <tr class="row-odd"><td>5</td>
12015 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
12016 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12017 </tr>
12018 <tr class="row-even"><td>6</td>
12019 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
12020 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12021 </tr>
12022 <tr class="row-odd"><td>7</td>
12023 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
12024 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12025 </tr>
12026 <tr class="row-even"><td>8</td>
12027 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK</td>
12028 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12029 </tr>
12030 <tr class="row-odd"><td>9</td>
12031 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK</td>
12032 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12033 </tr>
12034 <tr class="row-even"><td>10</td>
12035 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK</td>
12036 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12037 </tr>
12038 <tr class="row-odd"><td>11</td>
12039 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK</td>
12040 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12041 </tr>
12042 <tr class="row-even"><td>12</td>
12043 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK</td>
12044 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12045 </tr>
12046 <tr class="row-odd"><td>13</td>
12047 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK</td>
12048 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12049 </tr>
12050 <tr class="row-even"><td>14</td>
12051 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK</td>
12052 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12053 </tr>
12054 <tr class="row-odd"><td>15</td>
12055 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK</td>
12056 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12057 </tr>
12058 <tr class="row-even"><td>16</td>
12059 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
12060 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12061 </tr>
12062 <tr class="row-odd"><td>17</td>
12063 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
12064 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
12065 </tr>
12066 <tr class="row-even"><td>18</td>
12067 <td>DEV_NAVSS0_CPTS_0_TS_GENF0</td>
12068 <td>Output clock</td>
12069 </tr>
12070 <tr class="row-odd"><td>19</td>
12071 <td>DEV_NAVSS0_CPTS_0_TS_GENF1</td>
12072 <td>Output clock</td>
12073 </tr>
12074 </tbody>
12075 </table>
12076 </div>
12077 <div class="section" id="clocks-for-navss0-dti-0-device">
12078 <span id="soc-doc-j721e-public-clks-navss0-dti-0"></span><h3>Clocks for NAVSS0_DTI_0 Device<a class="headerlink" href="#clocks-for-navss0-dti-0-device" title="Permalink to this headline">¶</a></h3>
12079 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_DTI_0</span></a> (ID = 206)</p>
12080 <p>Following is a mapping of Clocks IDs to function:</p>
12081 <table border="1" class="docutils">
12082 <colgroup>
12083 <col width="20%" />
12084 <col width="58%" />
12085 <col width="22%" />
12086 </colgroup>
12087 <thead valign="bottom">
12088 <tr class="row-odd"><th class="head">Clock ID</th>
12089 <th class="head">Name</th>
12090 <th class="head">Function</th>
12091 </tr>
12092 </thead>
12093 <tbody valign="top">
12094 <tr class="row-even"><td>0</td>
12095 <td>DEV_NAVSS0_DTI_0_CLK_CLK</td>
12096 <td>Input clock</td>
12097 </tr>
12098 <tr class="row-odd"><td>1</td>
12099 <td>DEV_NAVSS0_DTI_0_EXT0_DTI_CLK_CLK</td>
12100 <td>Input clock</td>
12101 </tr>
12102 <tr class="row-even"><td>2</td>
12103 <td>DEV_NAVSS0_DTI_0_EXT3_DTI_CLK_CLK</td>
12104 <td>Input clock</td>
12105 </tr>
12106 <tr class="row-odd"><td>3</td>
12107 <td>DEV_NAVSS0_DTI_0_EXT1_DTI_CLK_CLK</td>
12108 <td>Input clock</td>
12109 </tr>
12110 <tr class="row-even"><td>4</td>
12111 <td>DEV_NAVSS0_DTI_0_EXT2_DTI_CLK_CLK</td>
12112 <td>Input clock</td>
12113 </tr>
12114 </tbody>
12115 </table>
12116 </div>
12117 <div class="section" id="clocks-for-navss0-intr-router-0-device">
12118 <span id="soc-doc-j721e-public-clks-navss0-intr-router-0"></span><h3>Clocks for NAVSS0_INTR_ROUTER_0 Device<a class="headerlink" href="#clocks-for-navss0-intr-router-0-device" title="Permalink to this headline">¶</a></h3>
12119 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_INTR_ROUTER_0</span></a> (ID = 213)</p>
12120 <p>Following is a mapping of Clocks IDs to function:</p>
12121 <table border="1" class="docutils">
12122 <colgroup>
12123 <col width="20%" />
12124 <col width="58%" />
12125 <col width="22%" />
12126 </colgroup>
12127 <thead valign="bottom">
12128 <tr class="row-odd"><th class="head">Clock ID</th>
12129 <th class="head">Name</th>
12130 <th class="head">Function</th>
12131 </tr>
12132 </thead>
12133 <tbody valign="top">
12134 <tr class="row-even"><td>0</td>
12135 <td>DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK</td>
12136 <td>Input clock</td>
12137 </tr>
12138 </tbody>
12139 </table>
12140 </div>
12141 <div class="section" id="clocks-for-navss0-mailbox-0-device">
12142 <span id="soc-doc-j721e-public-clks-navss0-mailbox-0"></span><h3>Clocks for NAVSS0_MAILBOX_0 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-0-device" title="Permalink to this headline">¶</a></h3>
12143 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MAILBOX_0</span></a> (ID = 214)</p>
12144 <p>Following is a mapping of Clocks IDs to function:</p>
12145 <table border="1" class="docutils">
12146 <colgroup>
12147 <col width="21%" />
12148 <col width="55%" />
12149 <col width="23%" />
12150 </colgroup>
12151 <thead valign="bottom">
12152 <tr class="row-odd"><th class="head">Clock ID</th>
12153 <th class="head">Name</th>
12154 <th class="head">Function</th>
12155 </tr>
12156 </thead>
12157 <tbody valign="top">
12158 <tr class="row-even"><td>0</td>
12159 <td>DEV_NAVSS0_MAILBOX_0_VCLK_CLK</td>
12160 <td>Input clock</td>
12161 </tr>
12162 </tbody>
12163 </table>
12164 </div>
12165 <div class="section" id="clocks-for-navss0-mailbox-1-device">
12166 <span id="soc-doc-j721e-public-clks-navss0-mailbox-1"></span><h3>Clocks for NAVSS0_MAILBOX_1 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-1-device" title="Permalink to this headline">¶</a></h3>
12167 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MAILBOX_1</span></a> (ID = 215)</p>
12168 <p>Following is a mapping of Clocks IDs to function:</p>
12169 <table border="1" class="docutils">
12170 <colgroup>
12171 <col width="21%" />
12172 <col width="55%" />
12173 <col width="23%" />
12174 </colgroup>
12175 <thead valign="bottom">
12176 <tr class="row-odd"><th class="head">Clock ID</th>
12177 <th class="head">Name</th>
12178 <th class="head">Function</th>
12179 </tr>
12180 </thead>
12181 <tbody valign="top">
12182 <tr class="row-even"><td>0</td>
12183 <td>DEV_NAVSS0_MAILBOX_1_VCLK_CLK</td>
12184 <td>Input clock</td>
12185 </tr>
12186 </tbody>
12187 </table>
12188 </div>
12189 <div class="section" id="clocks-for-navss0-mailbox-10-device">
12190 <span id="soc-doc-j721e-public-clks-navss0-mailbox-10"></span><h3>Clocks for NAVSS0_MAILBOX_10 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-10-device" title="Permalink to this headline">¶</a></h3>
12191 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MAILBOX_10</span></a> (ID = 224)</p>
12192 <p>Following is a mapping of Clocks IDs to function:</p>
12193 <table border="1" class="docutils">
12194 <colgroup>
12195 <col width="21%" />
12196 <col width="56%" />
12197 <col width="23%" />
12198 </colgroup>
12199 <thead valign="bottom">
12200 <tr class="row-odd"><th class="head">Clock ID</th>
12201 <th class="head">Name</th>
12202 <th class="head">Function</th>
12203 </tr>
12204 </thead>
12205 <tbody valign="top">
12206 <tr class="row-even"><td>0</td>
12207 <td>DEV_NAVSS0_MAILBOX_10_VCLK_CLK</td>
12208 <td>Input clock</td>
12209 </tr>
12210 </tbody>
12211 </table>
12212 </div>
12213 <div class="section" id="clocks-for-navss0-mailbox-11-device">
12214 <span id="soc-doc-j721e-public-clks-navss0-mailbox-11"></span><h3>Clocks for NAVSS0_MAILBOX_11 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-11-device" title="Permalink to this headline">¶</a></h3>
12215 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MAILBOX_11</span></a> (ID = 225)</p>
12216 <p>Following is a mapping of Clocks IDs to function:</p>
12217 <table border="1" class="docutils">
12218 <colgroup>
12219 <col width="21%" />
12220 <col width="56%" />
12221 <col width="23%" />
12222 </colgroup>
12223 <thead valign="bottom">
12224 <tr class="row-odd"><th class="head">Clock ID</th>
12225 <th class="head">Name</th>
12226 <th class="head">Function</th>
12227 </tr>
12228 </thead>
12229 <tbody valign="top">
12230 <tr class="row-even"><td>0</td>
12231 <td>DEV_NAVSS0_MAILBOX_11_VCLK_CLK</td>
12232 <td>Input clock</td>
12233 </tr>
12234 </tbody>
12235 </table>
12236 </div>
12237 <div class="section" id="clocks-for-navss0-mailbox-2-device">
12238 <span id="soc-doc-j721e-public-clks-navss0-mailbox-2"></span><h3>Clocks for NAVSS0_MAILBOX_2 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-2-device" title="Permalink to this headline">¶</a></h3>
12239 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MAILBOX_2</span></a> (ID = 216)</p>
12240 <p>Following is a mapping of Clocks IDs to function:</p>
12241 <table border="1" class="docutils">
12242 <colgroup>
12243 <col width="21%" />
12244 <col width="55%" />
12245 <col width="23%" />
12246 </colgroup>
12247 <thead valign="bottom">
12248 <tr class="row-odd"><th class="head">Clock ID</th>
12249 <th class="head">Name</th>
12250 <th class="head">Function</th>
12251 </tr>
12252 </thead>
12253 <tbody valign="top">
12254 <tr class="row-even"><td>0</td>
12255 <td>DEV_NAVSS0_MAILBOX_2_VCLK_CLK</td>
12256 <td>Input clock</td>
12257 </tr>
12258 </tbody>
12259 </table>
12260 </div>
12261 <div class="section" id="clocks-for-navss0-mailbox-3-device">
12262 <span id="soc-doc-j721e-public-clks-navss0-mailbox-3"></span><h3>Clocks for NAVSS0_MAILBOX_3 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-3-device" title="Permalink to this headline">¶</a></h3>
12263 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MAILBOX_3</span></a> (ID = 217)</p>
12264 <p>Following is a mapping of Clocks IDs to function:</p>
12265 <table border="1" class="docutils">
12266 <colgroup>
12267 <col width="21%" />
12268 <col width="55%" />
12269 <col width="23%" />
12270 </colgroup>
12271 <thead valign="bottom">
12272 <tr class="row-odd"><th class="head">Clock ID</th>
12273 <th class="head">Name</th>
12274 <th class="head">Function</th>
12275 </tr>
12276 </thead>
12277 <tbody valign="top">
12278 <tr class="row-even"><td>0</td>
12279 <td>DEV_NAVSS0_MAILBOX_3_VCLK_CLK</td>
12280 <td>Input clock</td>
12281 </tr>
12282 </tbody>
12283 </table>
12284 </div>
12285 <div class="section" id="clocks-for-navss0-mailbox-4-device">
12286 <span id="soc-doc-j721e-public-clks-navss0-mailbox-4"></span><h3>Clocks for NAVSS0_MAILBOX_4 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-4-device" title="Permalink to this headline">¶</a></h3>
12287 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MAILBOX_4</span></a> (ID = 218)</p>
12288 <p>Following is a mapping of Clocks IDs to function:</p>
12289 <table border="1" class="docutils">
12290 <colgroup>
12291 <col width="21%" />
12292 <col width="55%" />
12293 <col width="23%" />
12294 </colgroup>
12295 <thead valign="bottom">
12296 <tr class="row-odd"><th class="head">Clock ID</th>
12297 <th class="head">Name</th>
12298 <th class="head">Function</th>
12299 </tr>
12300 </thead>
12301 <tbody valign="top">
12302 <tr class="row-even"><td>0</td>
12303 <td>DEV_NAVSS0_MAILBOX_4_VCLK_CLK</td>
12304 <td>Input clock</td>
12305 </tr>
12306 </tbody>
12307 </table>
12308 </div>
12309 <div class="section" id="clocks-for-navss0-mailbox-5-device">
12310 <span id="soc-doc-j721e-public-clks-navss0-mailbox-5"></span><h3>Clocks for NAVSS0_MAILBOX_5 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-5-device" title="Permalink to this headline">¶</a></h3>
12311 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MAILBOX_5</span></a> (ID = 219)</p>
12312 <p>Following is a mapping of Clocks IDs to function:</p>
12313 <table border="1" class="docutils">
12314 <colgroup>
12315 <col width="21%" />
12316 <col width="55%" />
12317 <col width="23%" />
12318 </colgroup>
12319 <thead valign="bottom">
12320 <tr class="row-odd"><th class="head">Clock ID</th>
12321 <th class="head">Name</th>
12322 <th class="head">Function</th>
12323 </tr>
12324 </thead>
12325 <tbody valign="top">
12326 <tr class="row-even"><td>0</td>
12327 <td>DEV_NAVSS0_MAILBOX_5_VCLK_CLK</td>
12328 <td>Input clock</td>
12329 </tr>
12330 </tbody>
12331 </table>
12332 </div>
12333 <div class="section" id="clocks-for-navss0-mailbox-6-device">
12334 <span id="soc-doc-j721e-public-clks-navss0-mailbox-6"></span><h3>Clocks for NAVSS0_MAILBOX_6 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-6-device" title="Permalink to this headline">¶</a></h3>
12335 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MAILBOX_6</span></a> (ID = 220)</p>
12336 <p>Following is a mapping of Clocks IDs to function:</p>
12337 <table border="1" class="docutils">
12338 <colgroup>
12339 <col width="21%" />
12340 <col width="55%" />
12341 <col width="23%" />
12342 </colgroup>
12343 <thead valign="bottom">
12344 <tr class="row-odd"><th class="head">Clock ID</th>
12345 <th class="head">Name</th>
12346 <th class="head">Function</th>
12347 </tr>
12348 </thead>
12349 <tbody valign="top">
12350 <tr class="row-even"><td>0</td>
12351 <td>DEV_NAVSS0_MAILBOX_6_VCLK_CLK</td>
12352 <td>Input clock</td>
12353 </tr>
12354 </tbody>
12355 </table>
12356 </div>
12357 <div class="section" id="clocks-for-navss0-mailbox-7-device">
12358 <span id="soc-doc-j721e-public-clks-navss0-mailbox-7"></span><h3>Clocks for NAVSS0_MAILBOX_7 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-7-device" title="Permalink to this headline">¶</a></h3>
12359 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MAILBOX_7</span></a> (ID = 221)</p>
12360 <p>Following is a mapping of Clocks IDs to function:</p>
12361 <table border="1" class="docutils">
12362 <colgroup>
12363 <col width="21%" />
12364 <col width="55%" />
12365 <col width="23%" />
12366 </colgroup>
12367 <thead valign="bottom">
12368 <tr class="row-odd"><th class="head">Clock ID</th>
12369 <th class="head">Name</th>
12370 <th class="head">Function</th>
12371 </tr>
12372 </thead>
12373 <tbody valign="top">
12374 <tr class="row-even"><td>0</td>
12375 <td>DEV_NAVSS0_MAILBOX_7_VCLK_CLK</td>
12376 <td>Input clock</td>
12377 </tr>
12378 </tbody>
12379 </table>
12380 </div>
12381 <div class="section" id="clocks-for-navss0-mailbox-8-device">
12382 <span id="soc-doc-j721e-public-clks-navss0-mailbox-8"></span><h3>Clocks for NAVSS0_MAILBOX_8 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-8-device" title="Permalink to this headline">¶</a></h3>
12383 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MAILBOX_8</span></a> (ID = 222)</p>
12384 <p>Following is a mapping of Clocks IDs to function:</p>
12385 <table border="1" class="docutils">
12386 <colgroup>
12387 <col width="21%" />
12388 <col width="55%" />
12389 <col width="23%" />
12390 </colgroup>
12391 <thead valign="bottom">
12392 <tr class="row-odd"><th class="head">Clock ID</th>
12393 <th class="head">Name</th>
12394 <th class="head">Function</th>
12395 </tr>
12396 </thead>
12397 <tbody valign="top">
12398 <tr class="row-even"><td>0</td>
12399 <td>DEV_NAVSS0_MAILBOX_8_VCLK_CLK</td>
12400 <td>Input clock</td>
12401 </tr>
12402 </tbody>
12403 </table>
12404 </div>
12405 <div class="section" id="clocks-for-navss0-mailbox-9-device">
12406 <span id="soc-doc-j721e-public-clks-navss0-mailbox-9"></span><h3>Clocks for NAVSS0_MAILBOX_9 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-9-device" title="Permalink to this headline">¶</a></h3>
12407 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MAILBOX_9</span></a> (ID = 223)</p>
12408 <p>Following is a mapping of Clocks IDs to function:</p>
12409 <table border="1" class="docutils">
12410 <colgroup>
12411 <col width="21%" />
12412 <col width="55%" />
12413 <col width="23%" />
12414 </colgroup>
12415 <thead valign="bottom">
12416 <tr class="row-odd"><th class="head">Clock ID</th>
12417 <th class="head">Name</th>
12418 <th class="head">Function</th>
12419 </tr>
12420 </thead>
12421 <tbody valign="top">
12422 <tr class="row-even"><td>0</td>
12423 <td>DEV_NAVSS0_MAILBOX_9_VCLK_CLK</td>
12424 <td>Input clock</td>
12425 </tr>
12426 </tbody>
12427 </table>
12428 </div>
12429 <div class="section" id="clocks-for-navss0-mcrc-0-device">
12430 <span id="soc-doc-j721e-public-clks-navss0-mcrc-0"></span><h3>Clocks for NAVSS0_MCRC_0 Device<a class="headerlink" href="#clocks-for-navss0-mcrc-0-device" title="Permalink to this headline">¶</a></h3>
12431 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MCRC_0</span></a> (ID = 227)</p>
12432 <p>Following is a mapping of Clocks IDs to function:</p>
12433 <table border="1" class="docutils">
12434 <colgroup>
12435 <col width="25%" />
12436 <col width="48%" />
12437 <col width="27%" />
12438 </colgroup>
12439 <thead valign="bottom">
12440 <tr class="row-odd"><th class="head">Clock ID</th>
12441 <th class="head">Name</th>
12442 <th class="head">Function</th>
12443 </tr>
12444 </thead>
12445 <tbody valign="top">
12446 <tr class="row-even"><td>0</td>
12447 <td>DEV_NAVSS0_MCRC_0_CLK</td>
12448 <td>Input clock</td>
12449 </tr>
12450 </tbody>
12451 </table>
12452 </div>
12453 <div class="section" id="clocks-for-navss0-modss-device">
12454 <span id="soc-doc-j721e-public-clks-navss0-modss"></span><h3>Clocks for NAVSS0_MODSS Device<a class="headerlink" href="#clocks-for-navss0-modss-device" title="Permalink to this headline">¶</a></h3>
12455 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MODSS</span></a> (ID = 299)</p>
12456 <p>Following is a mapping of Clocks IDs to function:</p>
12457 <table border="1" class="docutils">
12458 <colgroup>
12459 <col width="24%" />
12460 <col width="50%" />
12461 <col width="26%" />
12462 </colgroup>
12463 <thead valign="bottom">
12464 <tr class="row-odd"><th class="head">Clock ID</th>
12465 <th class="head">Name</th>
12466 <th class="head">Function</th>
12467 </tr>
12468 </thead>
12469 <tbody valign="top">
12470 <tr class="row-even"><td>0</td>
12471 <td>DEV_NAVSS0_MODSS_VD2CLK</td>
12472 <td>Input clock</td>
12473 </tr>
12474 </tbody>
12475 </table>
12476 </div>
12477 <div class="section" id="clocks-for-navss0-modss-intaggr-0-device">
12478 <span id="soc-doc-j721e-public-clks-navss0-modss-intaggr-0"></span><h3>Clocks for NAVSS0_MODSS_INTAGGR_0 Device<a class="headerlink" href="#clocks-for-navss0-modss-intaggr-0-device" title="Permalink to this headline">¶</a></h3>
12479 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MODSS_INTAGGR_0</span></a> (ID = 207)</p>
12480 <p>Following is a mapping of Clocks IDs to function:</p>
12481 <table border="1" class="docutils">
12482 <colgroup>
12483 <col width="20%" />
12484 <col width="59%" />
12485 <col width="21%" />
12486 </colgroup>
12487 <thead valign="bottom">
12488 <tr class="row-odd"><th class="head">Clock ID</th>
12489 <th class="head">Name</th>
12490 <th class="head">Function</th>
12491 </tr>
12492 </thead>
12493 <tbody valign="top">
12494 <tr class="row-even"><td>0</td>
12495 <td>DEV_NAVSS0_MODSS_INTAGGR_0_SYS_CLK</td>
12496 <td>Input clock</td>
12497 </tr>
12498 </tbody>
12499 </table>
12500 </div>
12501 <div class="section" id="clocks-for-navss0-modss-intaggr-1-device">
12502 <span id="soc-doc-j721e-public-clks-navss0-modss-intaggr-1"></span><h3>Clocks for NAVSS0_MODSS_INTAGGR_1 Device<a class="headerlink" href="#clocks-for-navss0-modss-intaggr-1-device" title="Permalink to this headline">¶</a></h3>
12503 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_MODSS_INTAGGR_1</span></a> (ID = 208)</p>
12504 <p>Following is a mapping of Clocks IDs to function:</p>
12505 <table border="1" class="docutils">
12506 <colgroup>
12507 <col width="20%" />
12508 <col width="59%" />
12509 <col width="21%" />
12510 </colgroup>
12511 <thead valign="bottom">
12512 <tr class="row-odd"><th class="head">Clock ID</th>
12513 <th class="head">Name</th>
12514 <th class="head">Function</th>
12515 </tr>
12516 </thead>
12517 <tbody valign="top">
12518 <tr class="row-even"><td>0</td>
12519 <td>DEV_NAVSS0_MODSS_INTAGGR_1_SYS_CLK</td>
12520 <td>Input clock</td>
12521 </tr>
12522 </tbody>
12523 </table>
12524 </div>
12525 <div class="section" id="clocks-for-navss0-proxy-0-device">
12526 <span id="soc-doc-j721e-public-clks-navss0-proxy-0"></span><h3>Clocks for NAVSS0_PROXY_0 Device<a class="headerlink" href="#clocks-for-navss0-proxy-0-device" title="Permalink to this headline">¶</a></h3>
12527 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_PROXY_0</span></a> (ID = 210)</p>
12528 <p>Following is a mapping of Clocks IDs to function:</p>
12529 <table border="1" class="docutils">
12530 <colgroup>
12531 <col width="23%" />
12532 <col width="53%" />
12533 <col width="25%" />
12534 </colgroup>
12535 <thead valign="bottom">
12536 <tr class="row-odd"><th class="head">Clock ID</th>
12537 <th class="head">Name</th>
12538 <th class="head">Function</th>
12539 </tr>
12540 </thead>
12541 <tbody valign="top">
12542 <tr class="row-even"><td>0</td>
12543 <td>DEV_NAVSS0_PROXY_0_CLK_CLK</td>
12544 <td>Input clock</td>
12545 </tr>
12546 </tbody>
12547 </table>
12548 </div>
12549 <div class="section" id="clocks-for-navss0-ringacc-0-device">
12550 <span id="soc-doc-j721e-public-clks-navss0-ringacc-0"></span><h3>Clocks for NAVSS0_RINGACC_0 Device<a class="headerlink" href="#clocks-for-navss0-ringacc-0-device" title="Permalink to this headline">¶</a></h3>
12551 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_RINGACC_0</span></a> (ID = 211)</p>
12552 <p>Following is a mapping of Clocks IDs to function:</p>
12553 <table border="1" class="docutils">
12554 <colgroup>
12555 <col width="22%" />
12556 <col width="55%" />
12557 <col width="24%" />
12558 </colgroup>
12559 <thead valign="bottom">
12560 <tr class="row-odd"><th class="head">Clock ID</th>
12561 <th class="head">Name</th>
12562 <th class="head">Function</th>
12563 </tr>
12564 </thead>
12565 <tbody valign="top">
12566 <tr class="row-even"><td>0</td>
12567 <td>DEV_NAVSS0_RINGACC_0_SYS_CLK</td>
12568 <td>Input clock</td>
12569 </tr>
12570 </tbody>
12571 </table>
12572 </div>
12573 <div class="section" id="clocks-for-navss0-spinlock-0-device">
12574 <span id="soc-doc-j721e-public-clks-navss0-spinlock-0"></span><h3>Clocks for NAVSS0_SPINLOCK_0 Device<a class="headerlink" href="#clocks-for-navss0-spinlock-0-device" title="Permalink to this headline">¶</a></h3>
12575 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_SPINLOCK_0</span></a> (ID = 226)</p>
12576 <p>Following is a mapping of Clocks IDs to function:</p>
12577 <table border="1" class="docutils">
12578 <colgroup>
12579 <col width="23%" />
12580 <col width="52%" />
12581 <col width="25%" />
12582 </colgroup>
12583 <thead valign="bottom">
12584 <tr class="row-odd"><th class="head">Clock ID</th>
12585 <th class="head">Name</th>
12586 <th class="head">Function</th>
12587 </tr>
12588 </thead>
12589 <tbody valign="top">
12590 <tr class="row-even"><td>0</td>
12591 <td>DEV_NAVSS0_SPINLOCK_0_CLK</td>
12592 <td>Input clock</td>
12593 </tr>
12594 </tbody>
12595 </table>
12596 </div>
12597 <div class="section" id="clocks-for-navss0-tbu-0-device">
12598 <span id="soc-doc-j721e-public-clks-navss0-tbu-0"></span><h3>Clocks for NAVSS0_TBU_0 Device<a class="headerlink" href="#clocks-for-navss0-tbu-0-device" title="Permalink to this headline">¶</a></h3>
12599 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_TBU_0</span></a> (ID = 228)</p>
12600 <p>Following is a mapping of Clocks IDs to function:</p>
12601 <table border="1" class="docutils">
12602 <colgroup>
12603 <col width="24%" />
12604 <col width="51%" />
12605 <col width="25%" />
12606 </colgroup>
12607 <thead valign="bottom">
12608 <tr class="row-odd"><th class="head">Clock ID</th>
12609 <th class="head">Name</th>
12610 <th class="head">Function</th>
12611 </tr>
12612 </thead>
12613 <tbody valign="top">
12614 <tr class="row-even"><td>0</td>
12615 <td>DEV_NAVSS0_TBU_0_CLK_CLK</td>
12616 <td>Input clock</td>
12617 </tr>
12618 </tbody>
12619 </table>
12620 </div>
12621 <div class="section" id="clocks-for-navss0-tcu-0-device">
12622 <span id="soc-doc-j721e-public-clks-navss0-tcu-0"></span><h3>Clocks for NAVSS0_TCU_0 Device<a class="headerlink" href="#clocks-for-navss0-tcu-0-device" title="Permalink to this headline">¶</a></h3>
12623 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_TCU_0</span></a> (ID = 229)</p>
12624 <p>Following is a mapping of Clocks IDs to function:</p>
12625 <table border="1" class="docutils">
12626 <colgroup>
12627 <col width="24%" />
12628 <col width="51%" />
12629 <col width="25%" />
12630 </colgroup>
12631 <thead valign="bottom">
12632 <tr class="row-odd"><th class="head">Clock ID</th>
12633 <th class="head">Name</th>
12634 <th class="head">Function</th>
12635 </tr>
12636 </thead>
12637 <tbody valign="top">
12638 <tr class="row-even"><td>0</td>
12639 <td>DEV_NAVSS0_TCU_0_CLK_CLK</td>
12640 <td>Input clock</td>
12641 </tr>
12642 </tbody>
12643 </table>
12644 </div>
12645 <div class="section" id="clocks-for-navss0-timermgr-0-device">
12646 <span id="soc-doc-j721e-public-clks-navss0-timermgr-0"></span><h3>Clocks for NAVSS0_TIMERMGR_0 Device<a class="headerlink" href="#clocks-for-navss0-timermgr-0-device" title="Permalink to this headline">¶</a></h3>
12647 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_TIMERMGR_0</span></a> (ID = 230)</p>
12648 <p>Following is a mapping of Clocks IDs to function:</p>
12649 <table border="1" class="docutils">
12650 <colgroup>
12651 <col width="20%" />
12652 <col width="59%" />
12653 <col width="21%" />
12654 </colgroup>
12655 <thead valign="bottom">
12656 <tr class="row-odd"><th class="head">Clock ID</th>
12657 <th class="head">Name</th>
12658 <th class="head">Function</th>
12659 </tr>
12660 </thead>
12661 <tbody valign="top">
12662 <tr class="row-even"><td>0</td>
12663 <td>DEV_NAVSS0_TIMERMGR_0_VCLK_CLK</td>
12664 <td>Input clock</td>
12665 </tr>
12666 <tr class="row-odd"><td>1</td>
12667 <td>DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT</td>
12668 <td>Input clock</td>
12669 </tr>
12670 </tbody>
12671 </table>
12672 </div>
12673 <div class="section" id="clocks-for-navss0-timermgr-1-device">
12674 <span id="soc-doc-j721e-public-clks-navss0-timermgr-1"></span><h3>Clocks for NAVSS0_TIMERMGR_1 Device<a class="headerlink" href="#clocks-for-navss0-timermgr-1-device" title="Permalink to this headline">¶</a></h3>
12675 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_TIMERMGR_1</span></a> (ID = 231)</p>
12676 <p>Following is a mapping of Clocks IDs to function:</p>
12677 <table border="1" class="docutils">
12678 <colgroup>
12679 <col width="20%" />
12680 <col width="59%" />
12681 <col width="21%" />
12682 </colgroup>
12683 <thead valign="bottom">
12684 <tr class="row-odd"><th class="head">Clock ID</th>
12685 <th class="head">Name</th>
12686 <th class="head">Function</th>
12687 </tr>
12688 </thead>
12689 <tbody valign="top">
12690 <tr class="row-even"><td>0</td>
12691 <td>DEV_NAVSS0_TIMERMGR_1_VCLK_CLK</td>
12692 <td>Input clock</td>
12693 </tr>
12694 <tr class="row-odd"><td>1</td>
12695 <td>DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT</td>
12696 <td>Input clock</td>
12697 </tr>
12698 </tbody>
12699 </table>
12700 </div>
12701 <div class="section" id="clocks-for-navss0-udmap-0-device">
12702 <span id="soc-doc-j721e-public-clks-navss0-udmap-0"></span><h3>Clocks for NAVSS0_UDMAP_0 Device<a class="headerlink" href="#clocks-for-navss0-udmap-0-device" title="Permalink to this headline">¶</a></h3>
12703 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_UDMAP_0</span></a> (ID = 212)</p>
12704 <p>Following is a mapping of Clocks IDs to function:</p>
12705 <table border="1" class="docutils">
12706 <colgroup>
12707 <col width="23%" />
12708 <col width="53%" />
12709 <col width="25%" />
12710 </colgroup>
12711 <thead valign="bottom">
12712 <tr class="row-odd"><th class="head">Clock ID</th>
12713 <th class="head">Name</th>
12714 <th class="head">Function</th>
12715 </tr>
12716 </thead>
12717 <tbody valign="top">
12718 <tr class="row-even"><td>0</td>
12719 <td>DEV_NAVSS0_UDMAP_0_SYS_CLK</td>
12720 <td>Input clock</td>
12721 </tr>
12722 </tbody>
12723 </table>
12724 </div>
12725 <div class="section" id="clocks-for-navss0-udmass-device">
12726 <span id="soc-doc-j721e-public-clks-navss0-udmass"></span><h3>Clocks for NAVSS0_UDMASS Device<a class="headerlink" href="#clocks-for-navss0-udmass-device" title="Permalink to this headline">¶</a></h3>
12727 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_UDMASS</span></a> (ID = 300)</p>
12728 <p>Following is a mapping of Clocks IDs to function:</p>
12729 <table border="1" class="docutils">
12730 <colgroup>
12731 <col width="24%" />
12732 <col width="51%" />
12733 <col width="25%" />
12734 </colgroup>
12735 <thead valign="bottom">
12736 <tr class="row-odd"><th class="head">Clock ID</th>
12737 <th class="head">Name</th>
12738 <th class="head">Function</th>
12739 </tr>
12740 </thead>
12741 <tbody valign="top">
12742 <tr class="row-even"><td>0</td>
12743 <td>DEV_NAVSS0_UDMASS_VD2CLK</td>
12744 <td>Input clock</td>
12745 </tr>
12746 </tbody>
12747 </table>
12748 </div>
12749 <div class="section" id="clocks-for-navss0-udmass-intaggr-0-device">
12750 <span id="soc-doc-j721e-public-clks-navss0-udmass-intaggr-0"></span><h3>Clocks for NAVSS0_UDMASS_INTAGGR_0 Device<a class="headerlink" href="#clocks-for-navss0-udmass-intaggr-0-device" title="Permalink to this headline">¶</a></h3>
12751 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_UDMASS_INTAGGR_0</span></a> (ID = 209)</p>
12752 <p>Following is a mapping of Clocks IDs to function:</p>
12753 <table border="1" class="docutils">
12754 <colgroup>
12755 <col width="19%" />
12756 <col width="60%" />
12757 <col width="21%" />
12758 </colgroup>
12759 <thead valign="bottom">
12760 <tr class="row-odd"><th class="head">Clock ID</th>
12761 <th class="head">Name</th>
12762 <th class="head">Function</th>
12763 </tr>
12764 </thead>
12765 <tbody valign="top">
12766 <tr class="row-even"><td>0</td>
12767 <td>DEV_NAVSS0_UDMASS_INTAGGR_0_SYS_CLK</td>
12768 <td>Input clock</td>
12769 </tr>
12770 </tbody>
12771 </table>
12772 </div>
12773 <div class="section" id="clocks-for-navss0-virtss-device">
12774 <span id="soc-doc-j721e-public-clks-navss0-virtss"></span><h3>Clocks for NAVSS0_VIRTSS Device<a class="headerlink" href="#clocks-for-navss0-virtss-device" title="Permalink to this headline">¶</a></h3>
12775 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_NAVSS0_VIRTSS</span></a> (ID = 301)</p>
12776 <p>Following is a mapping of Clocks IDs to function:</p>
12777 <table border="1" class="docutils">
12778 <colgroup>
12779 <col width="24%" />
12780 <col width="51%" />
12781 <col width="25%" />
12782 </colgroup>
12783 <thead valign="bottom">
12784 <tr class="row-odd"><th class="head">Clock ID</th>
12785 <th class="head">Name</th>
12786 <th class="head">Function</th>
12787 </tr>
12788 </thead>
12789 <tbody valign="top">
12790 <tr class="row-even"><td>0</td>
12791 <td>DEV_NAVSS0_VIRTSS_VD2CLK</td>
12792 <td>Input clock</td>
12793 </tr>
12794 </tbody>
12795 </table>
12796 </div>
12797 <div class="section" id="clocks-for-pbist0-device">
12798 <span id="soc-doc-j721e-public-clks-pbist0"></span><h3>Clocks for PBIST0 Device<a class="headerlink" href="#clocks-for-pbist0-device" title="Permalink to this headline">¶</a></h3>
12799 <p><strong>This device has no defined clocks.</strong></p>
12800 </div>
12801 <div class="section" id="clocks-for-pbist1-device">
12802 <span id="soc-doc-j721e-public-clks-pbist1"></span><h3>Clocks for PBIST1 Device<a class="headerlink" href="#clocks-for-pbist1-device" title="Permalink to this headline">¶</a></h3>
12803 <p><strong>This device has no defined clocks.</strong></p>
12804 </div>
12805 <div class="section" id="clocks-for-pbist10-device">
12806 <span id="soc-doc-j721e-public-clks-pbist10"></span><h3>Clocks for PBIST10 Device<a class="headerlink" href="#clocks-for-pbist10-device" title="Permalink to this headline">¶</a></h3>
12807 <p><strong>This device has no defined clocks.</strong></p>
12808 </div>
12809 <div class="section" id="clocks-for-pbist2-device">
12810 <span id="soc-doc-j721e-public-clks-pbist2"></span><h3>Clocks for PBIST2 Device<a class="headerlink" href="#clocks-for-pbist2-device" title="Permalink to this headline">¶</a></h3>
12811 <p><strong>This device has no defined clocks.</strong></p>
12812 </div>
12813 <div class="section" id="clocks-for-pbist3-device">
12814 <span id="soc-doc-j721e-public-clks-pbist3"></span><h3>Clocks for PBIST3 Device<a class="headerlink" href="#clocks-for-pbist3-device" title="Permalink to this headline">¶</a></h3>
12815 <p><strong>This device has no defined clocks.</strong></p>
12816 </div>
12817 <div class="section" id="clocks-for-pbist4-device">
12818 <span id="soc-doc-j721e-public-clks-pbist4"></span><h3>Clocks for PBIST4 Device<a class="headerlink" href="#clocks-for-pbist4-device" title="Permalink to this headline">¶</a></h3>
12819 <p><strong>This device has no defined clocks.</strong></p>
12820 </div>
12821 <div class="section" id="clocks-for-pbist5-device">
12822 <span id="soc-doc-j721e-public-clks-pbist5"></span><h3>Clocks for PBIST5 Device<a class="headerlink" href="#clocks-for-pbist5-device" title="Permalink to this headline">¶</a></h3>
12823 <p><strong>This device has no defined clocks.</strong></p>
12824 </div>
12825 <div class="section" id="clocks-for-pbist6-device">
12826 <span id="soc-doc-j721e-public-clks-pbist6"></span><h3>Clocks for PBIST6 Device<a class="headerlink" href="#clocks-for-pbist6-device" title="Permalink to this headline">¶</a></h3>
12827 <p><strong>This device has no defined clocks.</strong></p>
12828 </div>
12829 <div class="section" id="clocks-for-pbist7-device">
12830 <span id="soc-doc-j721e-public-clks-pbist7"></span><h3>Clocks for PBIST7 Device<a class="headerlink" href="#clocks-for-pbist7-device" title="Permalink to this headline">¶</a></h3>
12831 <p><strong>This device has no defined clocks.</strong></p>
12832 </div>
12833 <div class="section" id="clocks-for-pbist9-device">
12834 <span id="soc-doc-j721e-public-clks-pbist9"></span><h3>Clocks for PBIST9 Device<a class="headerlink" href="#clocks-for-pbist9-device" title="Permalink to this headline">¶</a></h3>
12835 <p><strong>This device has no defined clocks.</strong></p>
12836 </div>
12837 <div class="section" id="clocks-for-pcie0-device">
12838 <span id="soc-doc-j721e-public-clks-pcie0"></span><h3>Clocks for PCIE0 Device<a class="headerlink" href="#clocks-for-pcie0-device" title="Permalink to this headline">¶</a></h3>
12839 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_PCIE0</span></a> (ID = 239)</p>
12840 <p>Following is a mapping of Clocks IDs to function:</p>
12841 <table border="1" class="docutils">
12842 <colgroup>
12843 <col width="8%" />
12844 <col width="53%" />
12845 <col width="39%" />
12846 </colgroup>
12847 <thead valign="bottom">
12848 <tr class="row-odd"><th class="head">Clock ID</th>
12849 <th class="head">Name</th>
12850 <th class="head">Function</th>
12851 </tr>
12852 </thead>
12853 <tbody valign="top">
12854 <tr class="row-even"><td>0</td>
12855 <td>DEV_PCIE0_PCIE_LANE1_TXMCLK</td>
12856 <td>Input clock</td>
12857 </tr>
12858 <tr class="row-odd"><td>1</td>
12859 <td>DEV_PCIE0_PCIE_CBA_CLK</td>
12860 <td>Input clock</td>
12861 </tr>
12862 <tr class="row-even"><td>2</td>
12863 <td>DEV_PCIE0_PCIE_LANE1_RXCLK</td>
12864 <td>Input clock</td>
12865 </tr>
12866 <tr class="row-odd"><td>3</td>
12867 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12868 <td>Input muxed clock</td>
12869 </tr>
12870 <tr class="row-even"><td>4</td>
12871 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
12872 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12873 </tr>
12874 <tr class="row-odd"><td>5</td>
12875 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
12876 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12877 </tr>
12878 <tr class="row-even"><td>6</td>
12879 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
12880 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12881 </tr>
12882 <tr class="row-odd"><td>7</td>
12883 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
12884 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12885 </tr>
12886 <tr class="row-even"><td>8</td>
12887 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
12888 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12889 </tr>
12890 <tr class="row-odd"><td>9</td>
12891 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
12892 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12893 </tr>
12894 <tr class="row-even"><td>10</td>
12895 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK</td>
12896 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12897 </tr>
12898 <tr class="row-odd"><td>11</td>
12899 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK</td>
12900 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12901 </tr>
12902 <tr class="row-even"><td>12</td>
12903 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK</td>
12904 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12905 </tr>
12906 <tr class="row-odd"><td>13</td>
12907 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK</td>
12908 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12909 </tr>
12910 <tr class="row-even"><td>14</td>
12911 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK</td>
12912 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12913 </tr>
12914 <tr class="row-odd"><td>15</td>
12915 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK</td>
12916 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12917 </tr>
12918 <tr class="row-even"><td>16</td>
12919 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0</td>
12920 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12921 </tr>
12922 <tr class="row-odd"><td>17</td>
12923 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0</td>
12924 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12925 </tr>
12926 <tr class="row-even"><td>18</td>
12927 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
12928 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12929 </tr>
12930 <tr class="row-odd"><td>19</td>
12931 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
12932 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
12933 </tr>
12934 <tr class="row-even"><td>20</td>
12935 <td>DEV_PCIE0_PCIE_LANE1_TXFCLK</td>
12936 <td>Input clock</td>
12937 </tr>
12938 <tr class="row-odd"><td>21</td>
12939 <td>DEV_PCIE0_PCIE_LANE1_REFCLK</td>
12940 <td>Input clock</td>
12941 </tr>
12942 <tr class="row-even"><td>22</td>
12943 <td>DEV_PCIE0_PCIE_LANE0_REFCLK</td>
12944 <td>Input clock</td>
12945 </tr>
12946 <tr class="row-odd"><td>23</td>
12947 <td>DEV_PCIE0_PCIE_LANE0_TXMCLK</td>
12948 <td>Input clock</td>
12949 </tr>
12950 <tr class="row-even"><td>24</td>
12951 <td>DEV_PCIE0_PCIE_LANE0_TXFCLK</td>
12952 <td>Input clock</td>
12953 </tr>
12954 <tr class="row-odd"><td>25</td>
12955 <td>DEV_PCIE0_PCIE_PM_CLK</td>
12956 <td>Input clock</td>
12957 </tr>
12958 <tr class="row-even"><td>26</td>
12959 <td>DEV_PCIE0_PCIE_LANE0_RXFCLK</td>
12960 <td>Input clock</td>
12961 </tr>
12962 <tr class="row-odd"><td>27</td>
12963 <td>DEV_PCIE0_PCIE_LANE1_RXFCLK</td>
12964 <td>Input clock</td>
12965 </tr>
12966 <tr class="row-even"><td>28</td>
12967 <td>DEV_PCIE0_PCIE_LANE0_RXCLK</td>
12968 <td>Input clock</td>
12969 </tr>
12970 <tr class="row-odd"><td>29</td>
12971 <td>DEV_PCIE0_PCIE_LANE1_TXCLK</td>
12972 <td>Output clock</td>
12973 </tr>
12974 <tr class="row-even"><td>30</td>
12975 <td>DEV_PCIE0_PCIE_LANE0_TXCLK</td>
12976 <td>Output clock</td>
12977 </tr>
12978 </tbody>
12979 </table>
12980 </div>
12981 <div class="section" id="clocks-for-pcie1-device">
12982 <span id="soc-doc-j721e-public-clks-pcie1"></span><h3>Clocks for PCIE1 Device<a class="headerlink" href="#clocks-for-pcie1-device" title="Permalink to this headline">¶</a></h3>
12983 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_PCIE1</span></a> (ID = 240)</p>
12984 <p>Following is a mapping of Clocks IDs to function:</p>
12985 <table border="1" class="docutils">
12986 <colgroup>
12987 <col width="8%" />
12988 <col width="53%" />
12989 <col width="39%" />
12990 </colgroup>
12991 <thead valign="bottom">
12992 <tr class="row-odd"><th class="head">Clock ID</th>
12993 <th class="head">Name</th>
12994 <th class="head">Function</th>
12995 </tr>
12996 </thead>
12997 <tbody valign="top">
12998 <tr class="row-even"><td>0</td>
12999 <td>DEV_PCIE1_PCIE_LANE1_TXMCLK</td>
13000 <td>Input clock</td>
13001 </tr>
13002 <tr class="row-odd"><td>1</td>
13003 <td>DEV_PCIE1_PCIE_CBA_CLK</td>
13004 <td>Input clock</td>
13005 </tr>
13006 <tr class="row-even"><td>2</td>
13007 <td>DEV_PCIE1_PCIE_LANE1_RXCLK</td>
13008 <td>Input clock</td>
13009 </tr>
13010 <tr class="row-odd"><td>3</td>
13011 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13012 <td>Input muxed clock</td>
13013 </tr>
13014 <tr class="row-even"><td>4</td>
13015 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
13016 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13017 </tr>
13018 <tr class="row-odd"><td>5</td>
13019 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
13020 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13021 </tr>
13022 <tr class="row-even"><td>6</td>
13023 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
13024 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13025 </tr>
13026 <tr class="row-odd"><td>7</td>
13027 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
13028 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13029 </tr>
13030 <tr class="row-even"><td>8</td>
13031 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
13032 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13033 </tr>
13034 <tr class="row-odd"><td>9</td>
13035 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
13036 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13037 </tr>
13038 <tr class="row-even"><td>10</td>
13039 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK</td>
13040 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13041 </tr>
13042 <tr class="row-odd"><td>11</td>
13043 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK</td>
13044 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13045 </tr>
13046 <tr class="row-even"><td>12</td>
13047 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK</td>
13048 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13049 </tr>
13050 <tr class="row-odd"><td>13</td>
13051 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK</td>
13052 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13053 </tr>
13054 <tr class="row-even"><td>14</td>
13055 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK</td>
13056 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13057 </tr>
13058 <tr class="row-odd"><td>15</td>
13059 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK</td>
13060 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13061 </tr>
13062 <tr class="row-even"><td>16</td>
13063 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0</td>
13064 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13065 </tr>
13066 <tr class="row-odd"><td>17</td>
13067 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0</td>
13068 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13069 </tr>
13070 <tr class="row-even"><td>18</td>
13071 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
13072 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13073 </tr>
13074 <tr class="row-odd"><td>19</td>
13075 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
13076 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
13077 </tr>
13078 <tr class="row-even"><td>20</td>
13079 <td>DEV_PCIE1_PCIE_LANE1_TXFCLK</td>
13080 <td>Input clock</td>
13081 </tr>
13082 <tr class="row-odd"><td>21</td>
13083 <td>DEV_PCIE1_PCIE_LANE1_REFCLK</td>
13084 <td>Input clock</td>
13085 </tr>
13086 <tr class="row-even"><td>22</td>
13087 <td>DEV_PCIE1_PCIE_LANE0_REFCLK</td>
13088 <td>Input clock</td>
13089 </tr>
13090 <tr class="row-odd"><td>23</td>
13091 <td>DEV_PCIE1_PCIE_LANE0_TXMCLK</td>
13092 <td>Input clock</td>
13093 </tr>
13094 <tr class="row-even"><td>24</td>
13095 <td>DEV_PCIE1_PCIE_LANE0_TXFCLK</td>
13096 <td>Input clock</td>
13097 </tr>
13098 <tr class="row-odd"><td>25</td>
13099 <td>DEV_PCIE1_PCIE_PM_CLK</td>
13100 <td>Input clock</td>
13101 </tr>
13102 <tr class="row-even"><td>26</td>
13103 <td>DEV_PCIE1_PCIE_LANE0_RXFCLK</td>
13104 <td>Input clock</td>
13105 </tr>
13106 <tr class="row-odd"><td>27</td>
13107 <td>DEV_PCIE1_PCIE_LANE1_RXFCLK</td>
13108 <td>Input clock</td>
13109 </tr>
13110 <tr class="row-even"><td>28</td>
13111 <td>DEV_PCIE1_PCIE_LANE0_RXCLK</td>
13112 <td>Input clock</td>
13113 </tr>
13114 <tr class="row-odd"><td>29</td>
13115 <td>DEV_PCIE1_PCIE_LANE1_TXCLK</td>
13116 <td>Output clock</td>
13117 </tr>
13118 <tr class="row-even"><td>30</td>
13119 <td>DEV_PCIE1_PCIE_LANE0_TXCLK</td>
13120 <td>Output clock</td>
13121 </tr>
13122 </tbody>
13123 </table>
13124 </div>
13125 <div class="section" id="clocks-for-pcie2-device">
13126 <span id="soc-doc-j721e-public-clks-pcie2"></span><h3>Clocks for PCIE2 Device<a class="headerlink" href="#clocks-for-pcie2-device" title="Permalink to this headline">¶</a></h3>
13127 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_PCIE2</span></a> (ID = 241)</p>
13128 <p>Following is a mapping of Clocks IDs to function:</p>
13129 <table border="1" class="docutils">
13130 <colgroup>
13131 <col width="8%" />
13132 <col width="53%" />
13133 <col width="39%" />
13134 </colgroup>
13135 <thead valign="bottom">
13136 <tr class="row-odd"><th class="head">Clock ID</th>
13137 <th class="head">Name</th>
13138 <th class="head">Function</th>
13139 </tr>
13140 </thead>
13141 <tbody valign="top">
13142 <tr class="row-even"><td>0</td>
13143 <td>DEV_PCIE2_PCIE_LANE1_TXMCLK</td>
13144 <td>Input clock</td>
13145 </tr>
13146 <tr class="row-odd"><td>1</td>
13147 <td>DEV_PCIE2_PCIE_CBA_CLK</td>
13148 <td>Input clock</td>
13149 </tr>
13150 <tr class="row-even"><td>2</td>
13151 <td>DEV_PCIE2_PCIE_LANE1_RXCLK</td>
13152 <td>Input clock</td>
13153 </tr>
13154 <tr class="row-odd"><td>3</td>
13155 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13156 <td>Input muxed clock</td>
13157 </tr>
13158 <tr class="row-even"><td>4</td>
13159 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
13160 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13161 </tr>
13162 <tr class="row-odd"><td>5</td>
13163 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
13164 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13165 </tr>
13166 <tr class="row-even"><td>6</td>
13167 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
13168 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13169 </tr>
13170 <tr class="row-odd"><td>7</td>
13171 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
13172 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13173 </tr>
13174 <tr class="row-even"><td>8</td>
13175 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
13176 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13177 </tr>
13178 <tr class="row-odd"><td>9</td>
13179 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
13180 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13181 </tr>
13182 <tr class="row-even"><td>10</td>
13183 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK</td>
13184 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13185 </tr>
13186 <tr class="row-odd"><td>11</td>
13187 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK</td>
13188 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13189 </tr>
13190 <tr class="row-even"><td>12</td>
13191 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK</td>
13192 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13193 </tr>
13194 <tr class="row-odd"><td>13</td>
13195 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK</td>
13196 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13197 </tr>
13198 <tr class="row-even"><td>14</td>
13199 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK</td>
13200 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13201 </tr>
13202 <tr class="row-odd"><td>15</td>
13203 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK</td>
13204 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13205 </tr>
13206 <tr class="row-even"><td>16</td>
13207 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0</td>
13208 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13209 </tr>
13210 <tr class="row-odd"><td>17</td>
13211 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0</td>
13212 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13213 </tr>
13214 <tr class="row-even"><td>18</td>
13215 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
13216 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13217 </tr>
13218 <tr class="row-odd"><td>19</td>
13219 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
13220 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
13221 </tr>
13222 <tr class="row-even"><td>20</td>
13223 <td>DEV_PCIE2_PCIE_LANE1_TXFCLK</td>
13224 <td>Input clock</td>
13225 </tr>
13226 <tr class="row-odd"><td>21</td>
13227 <td>DEV_PCIE2_PCIE_LANE1_REFCLK</td>
13228 <td>Input clock</td>
13229 </tr>
13230 <tr class="row-even"><td>22</td>
13231 <td>DEV_PCIE2_PCIE_LANE0_REFCLK</td>
13232 <td>Input clock</td>
13233 </tr>
13234 <tr class="row-odd"><td>23</td>
13235 <td>DEV_PCIE2_PCIE_LANE0_TXMCLK</td>
13236 <td>Input clock</td>
13237 </tr>
13238 <tr class="row-even"><td>24</td>
13239 <td>DEV_PCIE2_PCIE_LANE0_TXFCLK</td>
13240 <td>Input clock</td>
13241 </tr>
13242 <tr class="row-odd"><td>25</td>
13243 <td>DEV_PCIE2_PCIE_PM_CLK</td>
13244 <td>Input clock</td>
13245 </tr>
13246 <tr class="row-even"><td>26</td>
13247 <td>DEV_PCIE2_PCIE_LANE0_RXFCLK</td>
13248 <td>Input clock</td>
13249 </tr>
13250 <tr class="row-odd"><td>27</td>
13251 <td>DEV_PCIE2_PCIE_LANE1_RXFCLK</td>
13252 <td>Input clock</td>
13253 </tr>
13254 <tr class="row-even"><td>28</td>
13255 <td>DEV_PCIE2_PCIE_LANE0_RXCLK</td>
13256 <td>Input clock</td>
13257 </tr>
13258 <tr class="row-odd"><td>29</td>
13259 <td>DEV_PCIE2_PCIE_LANE1_TXCLK</td>
13260 <td>Output clock</td>
13261 </tr>
13262 <tr class="row-even"><td>30</td>
13263 <td>DEV_PCIE2_PCIE_LANE0_TXCLK</td>
13264 <td>Output clock</td>
13265 </tr>
13266 </tbody>
13267 </table>
13268 </div>
13269 <div class="section" id="clocks-for-pcie3-device">
13270 <span id="soc-doc-j721e-public-clks-pcie3"></span><h3>Clocks for PCIE3 Device<a class="headerlink" href="#clocks-for-pcie3-device" title="Permalink to this headline">¶</a></h3>
13271 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_PCIE3</span></a> (ID = 242)</p>
13272 <p>Following is a mapping of Clocks IDs to function:</p>
13273 <table border="1" class="docutils">
13274 <colgroup>
13275 <col width="8%" />
13276 <col width="53%" />
13277 <col width="39%" />
13278 </colgroup>
13279 <thead valign="bottom">
13280 <tr class="row-odd"><th class="head">Clock ID</th>
13281 <th class="head">Name</th>
13282 <th class="head">Function</th>
13283 </tr>
13284 </thead>
13285 <tbody valign="top">
13286 <tr class="row-even"><td>0</td>
13287 <td>DEV_PCIE3_PCIE_LANE1_TXMCLK</td>
13288 <td>Input clock</td>
13289 </tr>
13290 <tr class="row-odd"><td>1</td>
13291 <td>DEV_PCIE3_PCIE_CBA_CLK</td>
13292 <td>Input clock</td>
13293 </tr>
13294 <tr class="row-even"><td>2</td>
13295 <td>DEV_PCIE3_PCIE_LANE1_RXCLK</td>
13296 <td>Input clock</td>
13297 </tr>
13298 <tr class="row-odd"><td>3</td>
13299 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13300 <td>Input muxed clock</td>
13301 </tr>
13302 <tr class="row-even"><td>4</td>
13303 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
13304 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13305 </tr>
13306 <tr class="row-odd"><td>5</td>
13307 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
13308 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13309 </tr>
13310 <tr class="row-even"><td>6</td>
13311 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
13312 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13313 </tr>
13314 <tr class="row-odd"><td>7</td>
13315 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
13316 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13317 </tr>
13318 <tr class="row-even"><td>8</td>
13319 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
13320 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13321 </tr>
13322 <tr class="row-odd"><td>9</td>
13323 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
13324 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13325 </tr>
13326 <tr class="row-even"><td>10</td>
13327 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK</td>
13328 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13329 </tr>
13330 <tr class="row-odd"><td>11</td>
13331 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK</td>
13332 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13333 </tr>
13334 <tr class="row-even"><td>12</td>
13335 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK</td>
13336 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13337 </tr>
13338 <tr class="row-odd"><td>13</td>
13339 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK</td>
13340 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13341 </tr>
13342 <tr class="row-even"><td>14</td>
13343 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK</td>
13344 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13345 </tr>
13346 <tr class="row-odd"><td>15</td>
13347 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK</td>
13348 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13349 </tr>
13350 <tr class="row-even"><td>16</td>
13351 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0</td>
13352 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13353 </tr>
13354 <tr class="row-odd"><td>17</td>
13355 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0</td>
13356 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13357 </tr>
13358 <tr class="row-even"><td>18</td>
13359 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
13360 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13361 </tr>
13362 <tr class="row-odd"><td>19</td>
13363 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
13364 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
13365 </tr>
13366 <tr class="row-even"><td>20</td>
13367 <td>DEV_PCIE3_PCIE_LANE1_TXFCLK</td>
13368 <td>Input clock</td>
13369 </tr>
13370 <tr class="row-odd"><td>21</td>
13371 <td>DEV_PCIE3_PCIE_LANE1_REFCLK</td>
13372 <td>Input clock</td>
13373 </tr>
13374 <tr class="row-even"><td>22</td>
13375 <td>DEV_PCIE3_PCIE_LANE0_REFCLK</td>
13376 <td>Input clock</td>
13377 </tr>
13378 <tr class="row-odd"><td>23</td>
13379 <td>DEV_PCIE3_PCIE_LANE0_TXMCLK</td>
13380 <td>Input clock</td>
13381 </tr>
13382 <tr class="row-even"><td>24</td>
13383 <td>DEV_PCIE3_PCIE_LANE0_TXFCLK</td>
13384 <td>Input clock</td>
13385 </tr>
13386 <tr class="row-odd"><td>25</td>
13387 <td>DEV_PCIE3_PCIE_PM_CLK</td>
13388 <td>Input clock</td>
13389 </tr>
13390 <tr class="row-even"><td>26</td>
13391 <td>DEV_PCIE3_PCIE_LANE0_RXFCLK</td>
13392 <td>Input clock</td>
13393 </tr>
13394 <tr class="row-odd"><td>27</td>
13395 <td>DEV_PCIE3_PCIE_LANE1_RXFCLK</td>
13396 <td>Input clock</td>
13397 </tr>
13398 <tr class="row-even"><td>28</td>
13399 <td>DEV_PCIE3_PCIE_LANE0_RXCLK</td>
13400 <td>Input clock</td>
13401 </tr>
13402 <tr class="row-odd"><td>29</td>
13403 <td>DEV_PCIE3_PCIE_LANE1_TXCLK</td>
13404 <td>Output clock</td>
13405 </tr>
13406 <tr class="row-even"><td>30</td>
13407 <td>DEV_PCIE3_PCIE_LANE0_TXCLK</td>
13408 <td>Output clock</td>
13409 </tr>
13410 </tbody>
13411 </table>
13412 </div>
13413 <div class="section" id="clocks-for-pru-icssg0-device">
13414 <span id="soc-doc-j721e-public-clks-pru-icssg0"></span><h3>Clocks for PRU_ICSSG0 Device<a class="headerlink" href="#clocks-for-pru-icssg0-device" title="Permalink to this headline">¶</a></h3>
13415 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_PRU_ICSSG0</span></a> (ID = 119)</p>
13416 <p>Following is a mapping of Clocks IDs to function:</p>
13417 <table border="1" class="docutils">
13418 <colgroup>
13419 <col width="9%" />
13420 <col width="53%" />
13421 <col width="39%" />
13422 </colgroup>
13423 <thead valign="bottom">
13424 <tr class="row-odd"><th class="head">Clock ID</th>
13425 <th class="head">Name</th>
13426 <th class="head">Function</th>
13427 </tr>
13428 </thead>
13429 <tbody valign="top">
13430 <tr class="row-even"><td>0</td>
13431 <td>DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I</td>
13432 <td>Input clock</td>
13433 </tr>
13434 <tr class="row-odd"><td>1</td>
13435 <td>DEV_PRU_ICSSG0_VCLK_CLK</td>
13436 <td>Input clock</td>
13437 </tr>
13438 <tr class="row-even"><td>2</td>
13439 <td>DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I</td>
13440 <td>Input clock</td>
13441 </tr>
13442 <tr class="row-odd"><td>3</td>
13443 <td>DEV_PRU_ICSSG0_IEP_CLK</td>
13444 <td>Input muxed clock</td>
13445 </tr>
13446 <tr class="row-even"><td>4</td>
13447 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
13448 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13449 </tr>
13450 <tr class="row-odd"><td>5</td>
13451 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
13452 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13453 </tr>
13454 <tr class="row-even"><td>6</td>
13455 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
13456 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13457 </tr>
13458 <tr class="row-odd"><td>7</td>
13459 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
13460 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13461 </tr>
13462 <tr class="row-even"><td>8</td>
13463 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
13464 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13465 </tr>
13466 <tr class="row-odd"><td>9</td>
13467 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
13468 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13469 </tr>
13470 <tr class="row-even"><td>10</td>
13471 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK</td>
13472 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13473 </tr>
13474 <tr class="row-odd"><td>11</td>
13475 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK</td>
13476 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13477 </tr>
13478 <tr class="row-even"><td>12</td>
13479 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK</td>
13480 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13481 </tr>
13482 <tr class="row-odd"><td>13</td>
13483 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK</td>
13484 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13485 </tr>
13486 <tr class="row-even"><td>14</td>
13487 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK</td>
13488 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13489 </tr>
13490 <tr class="row-odd"><td>15</td>
13491 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK</td>
13492 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13493 </tr>
13494 <tr class="row-even"><td>16</td>
13495 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK</td>
13496 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13497 </tr>
13498 <tr class="row-odd"><td>17</td>
13499 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK</td>
13500 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13501 </tr>
13502 <tr class="row-even"><td>18</td>
13503 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
13504 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13505 </tr>
13506 <tr class="row-odd"><td>19</td>
13507 <td>DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
13508 <td>Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK</td>
13509 </tr>
13510 <tr class="row-even"><td>20</td>
13511 <td>DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK</td>
13512 <td>Input clock</td>
13513 </tr>
13514 <tr class="row-odd"><td>21</td>
13515 <td>DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I</td>
13516 <td>Input clock</td>
13517 </tr>
13518 <tr class="row-even"><td>22</td>
13519 <td>DEV_PRU_ICSSG0_UCLK_CLK</td>
13520 <td>Input clock</td>
13521 </tr>
13522 <tr class="row-odd"><td>23</td>
13523 <td>DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I</td>
13524 <td>Input clock</td>
13525 </tr>
13526 <tr class="row-even"><td>24</td>
13527 <td>DEV_PRU_ICSSG0_CORE_CLK</td>
13528 <td>Input muxed clock</td>
13529 </tr>
13530 <tr class="row-odd"><td>25</td>
13531 <td>DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK</td>
13532 <td>Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK</td>
13533 </tr>
13534 <tr class="row-even"><td>26</td>
13535 <td>DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
13536 <td>Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK</td>
13537 </tr>
13538 <tr class="row-odd"><td>27</td>
13539 <td>DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK</td>
13540 <td>Input clock</td>
13541 </tr>
13542 <tr class="row-even"><td>28</td>
13543 <td>DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK</td>
13544 <td>Input clock</td>
13545 </tr>
13546 <tr class="row-odd"><td>29</td>
13547 <td>DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O</td>
13548 <td>Output clock</td>
13549 </tr>
13550 <tr class="row-even"><td>30</td>
13551 <td>DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O</td>
13552 <td>Output clock</td>
13553 </tr>
13554 <tr class="row-odd"><td>31</td>
13555 <td>DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O</td>
13556 <td>Output clock</td>
13557 </tr>
13558 </tbody>
13559 </table>
13560 </div>
13561 <div class="section" id="clocks-for-pru-icssg1-device">
13562 <span id="soc-doc-j721e-public-clks-pru-icssg1"></span><h3>Clocks for PRU_ICSSG1 Device<a class="headerlink" href="#clocks-for-pru-icssg1-device" title="Permalink to this headline">¶</a></h3>
13563 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_PRU_ICSSG1</span></a> (ID = 120)</p>
13564 <p>Following is a mapping of Clocks IDs to function:</p>
13565 <table border="1" class="docutils">
13566 <colgroup>
13567 <col width="8%" />
13568 <col width="50%" />
13569 <col width="41%" />
13570 </colgroup>
13571 <thead valign="bottom">
13572 <tr class="row-odd"><th class="head">Clock ID</th>
13573 <th class="head">Name</th>
13574 <th class="head">Function</th>
13575 </tr>
13576 </thead>
13577 <tbody valign="top">
13578 <tr class="row-even"><td>0</td>
13579 <td>DEV_PRU_ICSSG1_SERDES0_RXCLK</td>
13580 <td>Input muxed clock</td>
13581 </tr>
13582 <tr class="row-odd"><td>1</td>
13583 <td>DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXCLK</td>
13584 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK</td>
13585 </tr>
13586 <tr class="row-even"><td>2</td>
13587 <td>DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXCLK</td>
13588 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK</td>
13589 </tr>
13590 <tr class="row-odd"><td>3</td>
13591 <td>DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I</td>
13592 <td>Input clock</td>
13593 </tr>
13594 <tr class="row-even"><td>4</td>
13595 <td>DEV_PRU_ICSSG1_VCLK_CLK</td>
13596 <td>Input clock</td>
13597 </tr>
13598 <tr class="row-odd"><td>5</td>
13599 <td>DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I</td>
13600 <td>Input clock</td>
13601 </tr>
13602 <tr class="row-even"><td>6</td>
13603 <td>DEV_PRU_ICSSG1_SERDES0_RXFCLK</td>
13604 <td>Input muxed clock</td>
13605 </tr>
13606 <tr class="row-odd"><td>7</td>
13607 <td>DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXFCLK</td>
13608 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK</td>
13609 </tr>
13610 <tr class="row-even"><td>8</td>
13611 <td>DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXFCLK</td>
13612 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK</td>
13613 </tr>
13614 <tr class="row-odd"><td>9</td>
13615 <td>DEV_PRU_ICSSG1_IEP_CLK</td>
13616 <td>Input muxed clock</td>
13617 </tr>
13618 <tr class="row-even"><td>10</td>
13619 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
13620 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13621 </tr>
13622 <tr class="row-odd"><td>11</td>
13623 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
13624 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13625 </tr>
13626 <tr class="row-even"><td>12</td>
13627 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
13628 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13629 </tr>
13630 <tr class="row-odd"><td>13</td>
13631 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
13632 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13633 </tr>
13634 <tr class="row-even"><td>14</td>
13635 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
13636 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13637 </tr>
13638 <tr class="row-odd"><td>15</td>
13639 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
13640 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13641 </tr>
13642 <tr class="row-even"><td>16</td>
13643 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK</td>
13644 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13645 </tr>
13646 <tr class="row-odd"><td>17</td>
13647 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK</td>
13648 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13649 </tr>
13650 <tr class="row-even"><td>18</td>
13651 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK</td>
13652 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13653 </tr>
13654 <tr class="row-odd"><td>19</td>
13655 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK</td>
13656 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13657 </tr>
13658 <tr class="row-even"><td>20</td>
13659 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK</td>
13660 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13661 </tr>
13662 <tr class="row-odd"><td>21</td>
13663 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK</td>
13664 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13665 </tr>
13666 <tr class="row-even"><td>22</td>
13667 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK</td>
13668 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13669 </tr>
13670 <tr class="row-odd"><td>23</td>
13671 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK</td>
13672 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13673 </tr>
13674 <tr class="row-even"><td>24</td>
13675 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
13676 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13677 </tr>
13678 <tr class="row-odd"><td>25</td>
13679 <td>DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
13680 <td>Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK</td>
13681 </tr>
13682 <tr class="row-even"><td>26</td>
13683 <td>DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK</td>
13684 <td>Input clock</td>
13685 </tr>
13686 <tr class="row-odd"><td>27</td>
13687 <td>DEV_PRU_ICSSG1_SERDES0_TXMCLK</td>
13688 <td>Input muxed clock</td>
13689 </tr>
13690 <tr class="row-even"><td>28</td>
13691 <td>DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXMCLK</td>
13692 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK</td>
13693 </tr>
13694 <tr class="row-odd"><td>29</td>
13695 <td>DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXMCLK</td>
13696 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK</td>
13697 </tr>
13698 <tr class="row-even"><td>30</td>
13699 <td>DEV_PRU_ICSSG1_SERDES0_REFCLK</td>
13700 <td>Input muxed clock</td>
13701 </tr>
13702 <tr class="row-odd"><td>31</td>
13703 <td>DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_REFCLK</td>
13704 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK</td>
13705 </tr>
13706 <tr class="row-even"><td>32</td>
13707 <td>DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_REFCLK</td>
13708 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK</td>
13709 </tr>
13710 <tr class="row-odd"><td>33</td>
13711 <td>DEV_PRU_ICSSG1_SERDES1_RXFCLK</td>
13712 <td>Input muxed clock</td>
13713 </tr>
13714 <tr class="row-even"><td>34</td>
13715 <td>DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXFCLK</td>
13716 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK</td>
13717 </tr>
13718 <tr class="row-odd"><td>35</td>
13719 <td>DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXFCLK</td>
13720 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK</td>
13721 </tr>
13722 <tr class="row-even"><td>36</td>
13723 <td>DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I</td>
13724 <td>Input clock</td>
13725 </tr>
13726 <tr class="row-odd"><td>37</td>
13727 <td>DEV_PRU_ICSSG1_SERDES1_RXCLK</td>
13728 <td>Input muxed clock</td>
13729 </tr>
13730 <tr class="row-even"><td>38</td>
13731 <td>DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXCLK</td>
13732 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK</td>
13733 </tr>
13734 <tr class="row-odd"><td>39</td>
13735 <td>DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXCLK</td>
13736 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK</td>
13737 </tr>
13738 <tr class="row-even"><td>40</td>
13739 <td>DEV_PRU_ICSSG1_SERDES1_TXFCLK</td>
13740 <td>Input muxed clock</td>
13741 </tr>
13742 <tr class="row-odd"><td>41</td>
13743 <td>DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXFCLK</td>
13744 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK</td>
13745 </tr>
13746 <tr class="row-even"><td>42</td>
13747 <td>DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXFCLK</td>
13748 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK</td>
13749 </tr>
13750 <tr class="row-odd"><td>43</td>
13751 <td>DEV_PRU_ICSSG1_SERDES1_TXMCLK</td>
13752 <td>Input muxed clock</td>
13753 </tr>
13754 <tr class="row-even"><td>44</td>
13755 <td>DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXMCLK</td>
13756 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK</td>
13757 </tr>
13758 <tr class="row-odd"><td>45</td>
13759 <td>DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXMCLK</td>
13760 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK</td>
13761 </tr>
13762 <tr class="row-even"><td>46</td>
13763 <td>DEV_PRU_ICSSG1_SERDES0_TXFCLK</td>
13764 <td>Input muxed clock</td>
13765 </tr>
13766 <tr class="row-odd"><td>47</td>
13767 <td>DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXFCLK</td>
13768 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK</td>
13769 </tr>
13770 <tr class="row-even"><td>48</td>
13771 <td>DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXFCLK</td>
13772 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK</td>
13773 </tr>
13774 <tr class="row-odd"><td>49</td>
13775 <td>DEV_PRU_ICSSG1_UCLK_CLK</td>
13776 <td>Input clock</td>
13777 </tr>
13778 <tr class="row-even"><td>50</td>
13779 <td>DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I</td>
13780 <td>Input clock</td>
13781 </tr>
13782 <tr class="row-odd"><td>51</td>
13783 <td>DEV_PRU_ICSSG1_SERDES1_REFCLK</td>
13784 <td>Input muxed clock</td>
13785 </tr>
13786 <tr class="row-even"><td>52</td>
13787 <td>DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_REFCLK</td>
13788 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK</td>
13789 </tr>
13790 <tr class="row-odd"><td>53</td>
13791 <td>DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_REFCLK</td>
13792 <td>Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK</td>
13793 </tr>
13794 <tr class="row-even"><td>54</td>
13795 <td>DEV_PRU_ICSSG1_CORE_CLK</td>
13796 <td>Input muxed clock</td>
13797 </tr>
13798 <tr class="row-odd"><td>55</td>
13799 <td>DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK</td>
13800 <td>Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK</td>
13801 </tr>
13802 <tr class="row-even"><td>56</td>
13803 <td>DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
13804 <td>Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK</td>
13805 </tr>
13806 <tr class="row-odd"><td>57</td>
13807 <td>DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK</td>
13808 <td>Input clock</td>
13809 </tr>
13810 <tr class="row-even"><td>58</td>
13811 <td>DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK</td>
13812 <td>Input clock</td>
13813 </tr>
13814 <tr class="row-odd"><td>59</td>
13815 <td>DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O</td>
13816 <td>Output clock</td>
13817 </tr>
13818 <tr class="row-even"><td>60</td>
13819 <td>DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O</td>
13820 <td>Output clock</td>
13821 </tr>
13822 <tr class="row-odd"><td>61</td>
13823 <td>DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O</td>
13824 <td>Output clock</td>
13825 </tr>
13826 <tr class="row-even"><td>62</td>
13827 <td>DEV_PRU_ICSSG1_SERDES0_TXCLK</td>
13828 <td>Output clock</td>
13829 </tr>
13830 <tr class="row-odd"><td>63</td>
13831 <td>DEV_PRU_ICSSG1_SERDES1_TXCLK</td>
13832 <td>Output clock</td>
13833 </tr>
13834 </tbody>
13835 </table>
13836 </div>
13837 <div class="section" id="clocks-for-psc0-device">
13838 <span id="soc-doc-j721e-public-clks-psc0"></span><h3>Clocks for PSC0 Device<a class="headerlink" href="#clocks-for-psc0-device" title="Permalink to this headline">¶</a></h3>
13839 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_PSC0</span></a> (ID = 133)</p>
13840 <p>Following is a mapping of Clocks IDs to function:</p>
13841 <table border="1" class="docutils">
13842 <colgroup>
13843 <col width="27%" />
13844 <col width="43%" />
13845 <col width="30%" />
13846 </colgroup>
13847 <thead valign="bottom">
13848 <tr class="row-odd"><th class="head">Clock ID</th>
13849 <th class="head">Name</th>
13850 <th class="head">Function</th>
13851 </tr>
13852 </thead>
13853 <tbody valign="top">
13854 <tr class="row-even"><td>0</td>
13855 <td>DEV_PSC0_SLOW_CLK</td>
13856 <td>Input clock</td>
13857 </tr>
13858 <tr class="row-odd"><td>1</td>
13859 <td>DEV_PSC0_CLK</td>
13860 <td>Input clock</td>
13861 </tr>
13862 </tbody>
13863 </table>
13864 </div>
13865 <div class="section" id="clocks-for-r5fss0-device">
13866 <span id="soc-doc-j721e-public-clks-r5fss0"></span><h3>Clocks for R5FSS0 Device<a class="headerlink" href="#clocks-for-r5fss0-device" title="Permalink to this headline">¶</a></h3>
13867 <p><strong>This device has no defined clocks.</strong></p>
13868 </div>
13869 <div class="section" id="clocks-for-r5fss0-core0-device">
13870 <span id="soc-doc-j721e-public-clks-r5fss0-core0"></span><h3>Clocks for R5FSS0_CORE0 Device<a class="headerlink" href="#clocks-for-r5fss0-core0-device" title="Permalink to this headline">¶</a></h3>
13871 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_R5FSS0_CORE0</span></a> (ID = 245)</p>
13872 <p>Following is a mapping of Clocks IDs to function:</p>
13873 <table border="1" class="docutils">
13874 <colgroup>
13875 <col width="20%" />
13876 <col width="58%" />
13877 <col width="22%" />
13878 </colgroup>
13879 <thead valign="bottom">
13880 <tr class="row-odd"><th class="head">Clock ID</th>
13881 <th class="head">Name</th>
13882 <th class="head">Function</th>
13883 </tr>
13884 </thead>
13885 <tbody valign="top">
13886 <tr class="row-even"><td>0</td>
13887 <td>DEV_R5FSS0_CORE0_CPU_CLK</td>
13888 <td>Input clock</td>
13889 </tr>
13890 <tr class="row-odd"><td>1</td>
13891 <td>DEV_R5FSS0_CORE0_INTERFACE_CLK</td>
13892 <td>Input clock</td>
13893 </tr>
13894 <tr class="row-even"><td>2</td>
13895 <td>DEV_R5FSS0_CORE0_INTERFACE_PHASE</td>
13896 <td>Input clock</td>
13897 </tr>
13898 </tbody>
13899 </table>
13900 </div>
13901 <div class="section" id="clocks-for-r5fss0-core1-device">
13902 <span id="soc-doc-j721e-public-clks-r5fss0-core1"></span><h3>Clocks for R5FSS0_CORE1 Device<a class="headerlink" href="#clocks-for-r5fss0-core1-device" title="Permalink to this headline">¶</a></h3>
13903 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_R5FSS0_CORE1</span></a> (ID = 246)</p>
13904 <p>Following is a mapping of Clocks IDs to function:</p>
13905 <table border="1" class="docutils">
13906 <colgroup>
13907 <col width="20%" />
13908 <col width="58%" />
13909 <col width="22%" />
13910 </colgroup>
13911 <thead valign="bottom">
13912 <tr class="row-odd"><th class="head">Clock ID</th>
13913 <th class="head">Name</th>
13914 <th class="head">Function</th>
13915 </tr>
13916 </thead>
13917 <tbody valign="top">
13918 <tr class="row-even"><td>0</td>
13919 <td>DEV_R5FSS0_CORE1_CPU_CLK</td>
13920 <td>Input clock</td>
13921 </tr>
13922 <tr class="row-odd"><td>1</td>
13923 <td>DEV_R5FSS0_CORE1_INTERFACE_CLK</td>
13924 <td>Input clock</td>
13925 </tr>
13926 <tr class="row-even"><td>2</td>
13927 <td>DEV_R5FSS0_CORE1_INTERFACE_PHASE</td>
13928 <td>Input clock</td>
13929 </tr>
13930 </tbody>
13931 </table>
13932 </div>
13933 <div class="section" id="clocks-for-r5fss0-introuter0-device">
13934 <span id="soc-doc-j721e-public-clks-r5fss0-introuter0"></span><h3>Clocks for R5FSS0_INTROUTER0 Device<a class="headerlink" href="#clocks-for-r5fss0-introuter0-device" title="Permalink to this headline">¶</a></h3>
13935 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_R5FSS0_INTROUTER0</span></a> (ID = 134)</p>
13936 <p>Following is a mapping of Clocks IDs to function:</p>
13937 <table border="1" class="docutils">
13938 <colgroup>
13939 <col width="21%" />
13940 <col width="56%" />
13941 <col width="23%" />
13942 </colgroup>
13943 <thead valign="bottom">
13944 <tr class="row-odd"><th class="head">Clock ID</th>
13945 <th class="head">Name</th>
13946 <th class="head">Function</th>
13947 </tr>
13948 </thead>
13949 <tbody valign="top">
13950 <tr class="row-even"><td>0</td>
13951 <td>DEV_R5FSS0_INTROUTER0_INTR_CLK</td>
13952 <td>Input clock</td>
13953 </tr>
13954 </tbody>
13955 </table>
13956 </div>
13957 <div class="section" id="clocks-for-r5fss1-device">
13958 <span id="soc-doc-j721e-public-clks-r5fss1"></span><h3>Clocks for R5FSS1 Device<a class="headerlink" href="#clocks-for-r5fss1-device" title="Permalink to this headline">¶</a></h3>
13959 <p><strong>This device has no defined clocks.</strong></p>
13960 </div>
13961 <div class="section" id="clocks-for-r5fss1-core0-device">
13962 <span id="soc-doc-j721e-public-clks-r5fss1-core0"></span><h3>Clocks for R5FSS1_CORE0 Device<a class="headerlink" href="#clocks-for-r5fss1-core0-device" title="Permalink to this headline">¶</a></h3>
13963 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_R5FSS1_CORE0</span></a> (ID = 247)</p>
13964 <p>Following is a mapping of Clocks IDs to function:</p>
13965 <table border="1" class="docutils">
13966 <colgroup>
13967 <col width="20%" />
13968 <col width="58%" />
13969 <col width="22%" />
13970 </colgroup>
13971 <thead valign="bottom">
13972 <tr class="row-odd"><th class="head">Clock ID</th>
13973 <th class="head">Name</th>
13974 <th class="head">Function</th>
13975 </tr>
13976 </thead>
13977 <tbody valign="top">
13978 <tr class="row-even"><td>0</td>
13979 <td>DEV_R5FSS1_CORE0_CPU_CLK</td>
13980 <td>Input clock</td>
13981 </tr>
13982 <tr class="row-odd"><td>1</td>
13983 <td>DEV_R5FSS1_CORE0_INTERFACE_CLK</td>
13984 <td>Input clock</td>
13985 </tr>
13986 <tr class="row-even"><td>2</td>
13987 <td>DEV_R5FSS1_CORE0_INTERFACE_PHASE</td>
13988 <td>Input clock</td>
13989 </tr>
13990 </tbody>
13991 </table>
13992 </div>
13993 <div class="section" id="clocks-for-r5fss1-core1-device">
13994 <span id="soc-doc-j721e-public-clks-r5fss1-core1"></span><h3>Clocks for R5FSS1_CORE1 Device<a class="headerlink" href="#clocks-for-r5fss1-core1-device" title="Permalink to this headline">¶</a></h3>
13995 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_R5FSS1_CORE1</span></a> (ID = 248)</p>
13996 <p>Following is a mapping of Clocks IDs to function:</p>
13997 <table border="1" class="docutils">
13998 <colgroup>
13999 <col width="20%" />
14000 <col width="58%" />
14001 <col width="22%" />
14002 </colgroup>
14003 <thead valign="bottom">
14004 <tr class="row-odd"><th class="head">Clock ID</th>
14005 <th class="head">Name</th>
14006 <th class="head">Function</th>
14007 </tr>
14008 </thead>
14009 <tbody valign="top">
14010 <tr class="row-even"><td>0</td>
14011 <td>DEV_R5FSS1_CORE1_CPU_CLK</td>
14012 <td>Input clock</td>
14013 </tr>
14014 <tr class="row-odd"><td>1</td>
14015 <td>DEV_R5FSS1_CORE1_INTERFACE_CLK</td>
14016 <td>Input clock</td>
14017 </tr>
14018 <tr class="row-even"><td>2</td>
14019 <td>DEV_R5FSS1_CORE1_INTERFACE_PHASE</td>
14020 <td>Input clock</td>
14021 </tr>
14022 </tbody>
14023 </table>
14024 </div>
14025 <div class="section" id="clocks-for-r5fss1-introuter0-device">
14026 <span id="soc-doc-j721e-public-clks-r5fss1-introuter0"></span><h3>Clocks for R5FSS1_INTROUTER0 Device<a class="headerlink" href="#clocks-for-r5fss1-introuter0-device" title="Permalink to this headline">¶</a></h3>
14027 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_R5FSS1_INTROUTER0</span></a> (ID = 135)</p>
14028 <p>Following is a mapping of Clocks IDs to function:</p>
14029 <table border="1" class="docutils">
14030 <colgroup>
14031 <col width="21%" />
14032 <col width="56%" />
14033 <col width="23%" />
14034 </colgroup>
14035 <thead valign="bottom">
14036 <tr class="row-odd"><th class="head">Clock ID</th>
14037 <th class="head">Name</th>
14038 <th class="head">Function</th>
14039 </tr>
14040 </thead>
14041 <tbody valign="top">
14042 <tr class="row-even"><td>0</td>
14043 <td>DEV_R5FSS1_INTROUTER0_INTR_CLK</td>
14044 <td>Input clock</td>
14045 </tr>
14046 </tbody>
14047 </table>
14048 </div>
14049 <div class="section" id="clocks-for-rti0-device">
14050 <span id="soc-doc-j721e-public-clks-rti0"></span><h3>Clocks for RTI0 Device<a class="headerlink" href="#clocks-for-rti0-device" title="Permalink to this headline">¶</a></h3>
14051 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_RTI0</span></a> (ID = 252)</p>
14052 <p>Following is a mapping of Clocks IDs to function:</p>
14053 <table border="1" class="docutils">
14054 <colgroup>
14055 <col width="9%" />
14056 <col width="54%" />
14057 <col width="37%" />
14058 </colgroup>
14059 <thead valign="bottom">
14060 <tr class="row-odd"><th class="head">Clock ID</th>
14061 <th class="head">Name</th>
14062 <th class="head">Function</th>
14063 </tr>
14064 </thead>
14065 <tbody valign="top">
14066 <tr class="row-even"><td>0</td>
14067 <td>DEV_RTI0_VBUSP_CLK</td>
14068 <td>Input clock</td>
14069 </tr>
14070 <tr class="row-odd"><td>1</td>
14071 <td>DEV_RTI0_RTI_CLK</td>
14072 <td>Input muxed clock</td>
14073 </tr>
14074 <tr class="row-even"><td>2</td>
14075 <td>DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14076 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
14077 </tr>
14078 <tr class="row-odd"><td>3</td>
14079 <td>DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
14080 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
14081 </tr>
14082 <tr class="row-even"><td>4</td>
14083 <td>DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
14084 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
14085 </tr>
14086 <tr class="row-odd"><td>5</td>
14087 <td>DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
14088 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
14089 </tr>
14090 <tr class="row-even"><td>6</td>
14091 <td>DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14092 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
14093 </tr>
14094 <tr class="row-odd"><td>7</td>
14095 <td>DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
14096 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
14097 </tr>
14098 <tr class="row-even"><td>8</td>
14099 <td>DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
14100 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
14101 </tr>
14102 <tr class="row-odd"><td>9</td>
14103 <td>DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
14104 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
14105 </tr>
14106 </tbody>
14107 </table>
14108 </div>
14109 <div class="section" id="clocks-for-rti1-device">
14110 <span id="soc-doc-j721e-public-clks-rti1"></span><h3>Clocks for RTI1 Device<a class="headerlink" href="#clocks-for-rti1-device" title="Permalink to this headline">¶</a></h3>
14111 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_RTI1</span></a> (ID = 253)</p>
14112 <p>Following is a mapping of Clocks IDs to function:</p>
14113 <table border="1" class="docutils">
14114 <colgroup>
14115 <col width="9%" />
14116 <col width="54%" />
14117 <col width="37%" />
14118 </colgroup>
14119 <thead valign="bottom">
14120 <tr class="row-odd"><th class="head">Clock ID</th>
14121 <th class="head">Name</th>
14122 <th class="head">Function</th>
14123 </tr>
14124 </thead>
14125 <tbody valign="top">
14126 <tr class="row-even"><td>0</td>
14127 <td>DEV_RTI1_VBUSP_CLK</td>
14128 <td>Input clock</td>
14129 </tr>
14130 <tr class="row-odd"><td>1</td>
14131 <td>DEV_RTI1_RTI_CLK</td>
14132 <td>Input muxed clock</td>
14133 </tr>
14134 <tr class="row-even"><td>2</td>
14135 <td>DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14136 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
14137 </tr>
14138 <tr class="row-odd"><td>3</td>
14139 <td>DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
14140 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
14141 </tr>
14142 <tr class="row-even"><td>4</td>
14143 <td>DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
14144 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
14145 </tr>
14146 <tr class="row-odd"><td>5</td>
14147 <td>DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
14148 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
14149 </tr>
14150 <tr class="row-even"><td>6</td>
14151 <td>DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14152 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
14153 </tr>
14154 <tr class="row-odd"><td>7</td>
14155 <td>DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
14156 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
14157 </tr>
14158 <tr class="row-even"><td>8</td>
14159 <td>DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
14160 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
14161 </tr>
14162 <tr class="row-odd"><td>9</td>
14163 <td>DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
14164 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
14165 </tr>
14166 </tbody>
14167 </table>
14168 </div>
14169 <div class="section" id="clocks-for-rti15-device">
14170 <span id="soc-doc-j721e-public-clks-rti15"></span><h3>Clocks for RTI15 Device<a class="headerlink" href="#clocks-for-rti15-device" title="Permalink to this headline">¶</a></h3>
14171 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_RTI15</span></a> (ID = 257)</p>
14172 <p>Following is a mapping of Clocks IDs to function:</p>
14173 <table border="1" class="docutils">
14174 <colgroup>
14175 <col width="9%" />
14176 <col width="53%" />
14177 <col width="37%" />
14178 </colgroup>
14179 <thead valign="bottom">
14180 <tr class="row-odd"><th class="head">Clock ID</th>
14181 <th class="head">Name</th>
14182 <th class="head">Function</th>
14183 </tr>
14184 </thead>
14185 <tbody valign="top">
14186 <tr class="row-even"><td>0</td>
14187 <td>DEV_RTI15_VBUSP_CLK</td>
14188 <td>Input clock</td>
14189 </tr>
14190 <tr class="row-odd"><td>1</td>
14191 <td>DEV_RTI15_RTI_CLK</td>
14192 <td>Input muxed clock</td>
14193 </tr>
14194 <tr class="row-even"><td>2</td>
14195 <td>DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14196 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
14197 </tr>
14198 <tr class="row-odd"><td>3</td>
14199 <td>DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
14200 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
14201 </tr>
14202 <tr class="row-even"><td>4</td>
14203 <td>DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
14204 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
14205 </tr>
14206 <tr class="row-odd"><td>5</td>
14207 <td>DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
14208 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
14209 </tr>
14210 <tr class="row-even"><td>6</td>
14211 <td>DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14212 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
14213 </tr>
14214 <tr class="row-odd"><td>7</td>
14215 <td>DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
14216 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
14217 </tr>
14218 <tr class="row-even"><td>8</td>
14219 <td>DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
14220 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
14221 </tr>
14222 <tr class="row-odd"><td>9</td>
14223 <td>DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
14224 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
14225 </tr>
14226 </tbody>
14227 </table>
14228 </div>
14229 <div class="section" id="clocks-for-rti16-device">
14230 <span id="soc-doc-j721e-public-clks-rti16"></span><h3>Clocks for RTI16 Device<a class="headerlink" href="#clocks-for-rti16-device" title="Permalink to this headline">¶</a></h3>
14231 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_RTI16</span></a> (ID = 256)</p>
14232 <p>Following is a mapping of Clocks IDs to function:</p>
14233 <table border="1" class="docutils">
14234 <colgroup>
14235 <col width="9%" />
14236 <col width="53%" />
14237 <col width="37%" />
14238 </colgroup>
14239 <thead valign="bottom">
14240 <tr class="row-odd"><th class="head">Clock ID</th>
14241 <th class="head">Name</th>
14242 <th class="head">Function</th>
14243 </tr>
14244 </thead>
14245 <tbody valign="top">
14246 <tr class="row-even"><td>0</td>
14247 <td>DEV_RTI16_VBUSP_CLK</td>
14248 <td>Input clock</td>
14249 </tr>
14250 <tr class="row-odd"><td>1</td>
14251 <td>DEV_RTI16_RTI_CLK</td>
14252 <td>Input muxed clock</td>
14253 </tr>
14254 <tr class="row-even"><td>2</td>
14255 <td>DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14256 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
14257 </tr>
14258 <tr class="row-odd"><td>3</td>
14259 <td>DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
14260 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
14261 </tr>
14262 <tr class="row-even"><td>4</td>
14263 <td>DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
14264 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
14265 </tr>
14266 <tr class="row-odd"><td>5</td>
14267 <td>DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
14268 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
14269 </tr>
14270 <tr class="row-even"><td>6</td>
14271 <td>DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14272 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
14273 </tr>
14274 <tr class="row-odd"><td>7</td>
14275 <td>DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
14276 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
14277 </tr>
14278 <tr class="row-even"><td>8</td>
14279 <td>DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
14280 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
14281 </tr>
14282 <tr class="row-odd"><td>9</td>
14283 <td>DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
14284 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
14285 </tr>
14286 </tbody>
14287 </table>
14288 </div>
14289 <div class="section" id="clocks-for-rti24-device">
14290 <span id="soc-doc-j721e-public-clks-rti24"></span><h3>Clocks for RTI24 Device<a class="headerlink" href="#clocks-for-rti24-device" title="Permalink to this headline">¶</a></h3>
14291 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_RTI24</span></a> (ID = 254)</p>
14292 <p>Following is a mapping of Clocks IDs to function:</p>
14293 <table border="1" class="docutils">
14294 <colgroup>
14295 <col width="9%" />
14296 <col width="53%" />
14297 <col width="37%" />
14298 </colgroup>
14299 <thead valign="bottom">
14300 <tr class="row-odd"><th class="head">Clock ID</th>
14301 <th class="head">Name</th>
14302 <th class="head">Function</th>
14303 </tr>
14304 </thead>
14305 <tbody valign="top">
14306 <tr class="row-even"><td>0</td>
14307 <td>DEV_RTI24_VBUSP_CLK</td>
14308 <td>Input clock</td>
14309 </tr>
14310 <tr class="row-odd"><td>1</td>
14311 <td>DEV_RTI24_RTI_CLK</td>
14312 <td>Input muxed clock</td>
14313 </tr>
14314 <tr class="row-even"><td>2</td>
14315 <td>DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14316 <td>Parent input clock option to DEV_RTI24_RTI_CLK</td>
14317 </tr>
14318 <tr class="row-odd"><td>3</td>
14319 <td>DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
14320 <td>Parent input clock option to DEV_RTI24_RTI_CLK</td>
14321 </tr>
14322 <tr class="row-even"><td>4</td>
14323 <td>DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
14324 <td>Parent input clock option to DEV_RTI24_RTI_CLK</td>
14325 </tr>
14326 <tr class="row-odd"><td>5</td>
14327 <td>DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
14328 <td>Parent input clock option to DEV_RTI24_RTI_CLK</td>
14329 </tr>
14330 <tr class="row-even"><td>6</td>
14331 <td>DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14332 <td>Parent input clock option to DEV_RTI24_RTI_CLK</td>
14333 </tr>
14334 <tr class="row-odd"><td>7</td>
14335 <td>DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
14336 <td>Parent input clock option to DEV_RTI24_RTI_CLK</td>
14337 </tr>
14338 <tr class="row-even"><td>8</td>
14339 <td>DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
14340 <td>Parent input clock option to DEV_RTI24_RTI_CLK</td>
14341 </tr>
14342 <tr class="row-odd"><td>9</td>
14343 <td>DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
14344 <td>Parent input clock option to DEV_RTI24_RTI_CLK</td>
14345 </tr>
14346 </tbody>
14347 </table>
14348 </div>
14349 <div class="section" id="clocks-for-rti25-device">
14350 <span id="soc-doc-j721e-public-clks-rti25"></span><h3>Clocks for RTI25 Device<a class="headerlink" href="#clocks-for-rti25-device" title="Permalink to this headline">¶</a></h3>
14351 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_RTI25</span></a> (ID = 255)</p>
14352 <p>Following is a mapping of Clocks IDs to function:</p>
14353 <table border="1" class="docutils">
14354 <colgroup>
14355 <col width="9%" />
14356 <col width="53%" />
14357 <col width="37%" />
14358 </colgroup>
14359 <thead valign="bottom">
14360 <tr class="row-odd"><th class="head">Clock ID</th>
14361 <th class="head">Name</th>
14362 <th class="head">Function</th>
14363 </tr>
14364 </thead>
14365 <tbody valign="top">
14366 <tr class="row-even"><td>0</td>
14367 <td>DEV_RTI25_VBUSP_CLK</td>
14368 <td>Input clock</td>
14369 </tr>
14370 <tr class="row-odd"><td>1</td>
14371 <td>DEV_RTI25_RTI_CLK</td>
14372 <td>Input muxed clock</td>
14373 </tr>
14374 <tr class="row-even"><td>2</td>
14375 <td>DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14376 <td>Parent input clock option to DEV_RTI25_RTI_CLK</td>
14377 </tr>
14378 <tr class="row-odd"><td>3</td>
14379 <td>DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
14380 <td>Parent input clock option to DEV_RTI25_RTI_CLK</td>
14381 </tr>
14382 <tr class="row-even"><td>4</td>
14383 <td>DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
14384 <td>Parent input clock option to DEV_RTI25_RTI_CLK</td>
14385 </tr>
14386 <tr class="row-odd"><td>5</td>
14387 <td>DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
14388 <td>Parent input clock option to DEV_RTI25_RTI_CLK</td>
14389 </tr>
14390 <tr class="row-even"><td>6</td>
14391 <td>DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14392 <td>Parent input clock option to DEV_RTI25_RTI_CLK</td>
14393 </tr>
14394 <tr class="row-odd"><td>7</td>
14395 <td>DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
14396 <td>Parent input clock option to DEV_RTI25_RTI_CLK</td>
14397 </tr>
14398 <tr class="row-even"><td>8</td>
14399 <td>DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
14400 <td>Parent input clock option to DEV_RTI25_RTI_CLK</td>
14401 </tr>
14402 <tr class="row-odd"><td>9</td>
14403 <td>DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
14404 <td>Parent input clock option to DEV_RTI25_RTI_CLK</td>
14405 </tr>
14406 </tbody>
14407 </table>
14408 </div>
14409 <div class="section" id="clocks-for-rti28-device">
14410 <span id="soc-doc-j721e-public-clks-rti28"></span><h3>Clocks for RTI28 Device<a class="headerlink" href="#clocks-for-rti28-device" title="Permalink to this headline">¶</a></h3>
14411 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_RTI28</span></a> (ID = 258)</p>
14412 <p>Following is a mapping of Clocks IDs to function:</p>
14413 <table border="1" class="docutils">
14414 <colgroup>
14415 <col width="9%" />
14416 <col width="53%" />
14417 <col width="37%" />
14418 </colgroup>
14419 <thead valign="bottom">
14420 <tr class="row-odd"><th class="head">Clock ID</th>
14421 <th class="head">Name</th>
14422 <th class="head">Function</th>
14423 </tr>
14424 </thead>
14425 <tbody valign="top">
14426 <tr class="row-even"><td>0</td>
14427 <td>DEV_RTI28_VBUSP_CLK</td>
14428 <td>Input clock</td>
14429 </tr>
14430 <tr class="row-odd"><td>1</td>
14431 <td>DEV_RTI28_RTI_CLK</td>
14432 <td>Input muxed clock</td>
14433 </tr>
14434 <tr class="row-even"><td>2</td>
14435 <td>DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14436 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
14437 </tr>
14438 <tr class="row-odd"><td>3</td>
14439 <td>DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
14440 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
14441 </tr>
14442 <tr class="row-even"><td>4</td>
14443 <td>DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
14444 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
14445 </tr>
14446 <tr class="row-odd"><td>5</td>
14447 <td>DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
14448 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
14449 </tr>
14450 <tr class="row-even"><td>6</td>
14451 <td>DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14452 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
14453 </tr>
14454 <tr class="row-odd"><td>7</td>
14455 <td>DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
14456 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
14457 </tr>
14458 <tr class="row-even"><td>8</td>
14459 <td>DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
14460 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
14461 </tr>
14462 <tr class="row-odd"><td>9</td>
14463 <td>DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
14464 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
14465 </tr>
14466 </tbody>
14467 </table>
14468 </div>
14469 <div class="section" id="clocks-for-rti29-device">
14470 <span id="soc-doc-j721e-public-clks-rti29"></span><h3>Clocks for RTI29 Device<a class="headerlink" href="#clocks-for-rti29-device" title="Permalink to this headline">¶</a></h3>
14471 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_RTI29</span></a> (ID = 259)</p>
14472 <p>Following is a mapping of Clocks IDs to function:</p>
14473 <table border="1" class="docutils">
14474 <colgroup>
14475 <col width="9%" />
14476 <col width="53%" />
14477 <col width="37%" />
14478 </colgroup>
14479 <thead valign="bottom">
14480 <tr class="row-odd"><th class="head">Clock ID</th>
14481 <th class="head">Name</th>
14482 <th class="head">Function</th>
14483 </tr>
14484 </thead>
14485 <tbody valign="top">
14486 <tr class="row-even"><td>0</td>
14487 <td>DEV_RTI29_VBUSP_CLK</td>
14488 <td>Input clock</td>
14489 </tr>
14490 <tr class="row-odd"><td>1</td>
14491 <td>DEV_RTI29_RTI_CLK</td>
14492 <td>Input muxed clock</td>
14493 </tr>
14494 <tr class="row-even"><td>2</td>
14495 <td>DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14496 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
14497 </tr>
14498 <tr class="row-odd"><td>3</td>
14499 <td>DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
14500 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
14501 </tr>
14502 <tr class="row-even"><td>4</td>
14503 <td>DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
14504 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
14505 </tr>
14506 <tr class="row-odd"><td>5</td>
14507 <td>DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
14508 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
14509 </tr>
14510 <tr class="row-even"><td>6</td>
14511 <td>DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14512 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
14513 </tr>
14514 <tr class="row-odd"><td>7</td>
14515 <td>DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
14516 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
14517 </tr>
14518 <tr class="row-even"><td>8</td>
14519 <td>DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
14520 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
14521 </tr>
14522 <tr class="row-odd"><td>9</td>
14523 <td>DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
14524 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
14525 </tr>
14526 </tbody>
14527 </table>
14528 </div>
14529 <div class="section" id="clocks-for-rti30-device">
14530 <span id="soc-doc-j721e-public-clks-rti30"></span><h3>Clocks for RTI30 Device<a class="headerlink" href="#clocks-for-rti30-device" title="Permalink to this headline">¶</a></h3>
14531 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_RTI30</span></a> (ID = 260)</p>
14532 <p>Following is a mapping of Clocks IDs to function:</p>
14533 <table border="1" class="docutils">
14534 <colgroup>
14535 <col width="9%" />
14536 <col width="53%" />
14537 <col width="37%" />
14538 </colgroup>
14539 <thead valign="bottom">
14540 <tr class="row-odd"><th class="head">Clock ID</th>
14541 <th class="head">Name</th>
14542 <th class="head">Function</th>
14543 </tr>
14544 </thead>
14545 <tbody valign="top">
14546 <tr class="row-even"><td>0</td>
14547 <td>DEV_RTI30_VBUSP_CLK</td>
14548 <td>Input clock</td>
14549 </tr>
14550 <tr class="row-odd"><td>1</td>
14551 <td>DEV_RTI30_RTI_CLK</td>
14552 <td>Input muxed clock</td>
14553 </tr>
14554 <tr class="row-even"><td>2</td>
14555 <td>DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14556 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
14557 </tr>
14558 <tr class="row-odd"><td>3</td>
14559 <td>DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
14560 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
14561 </tr>
14562 <tr class="row-even"><td>4</td>
14563 <td>DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
14564 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
14565 </tr>
14566 <tr class="row-odd"><td>5</td>
14567 <td>DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
14568 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
14569 </tr>
14570 <tr class="row-even"><td>6</td>
14571 <td>DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14572 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
14573 </tr>
14574 <tr class="row-odd"><td>7</td>
14575 <td>DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
14576 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
14577 </tr>
14578 <tr class="row-even"><td>8</td>
14579 <td>DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
14580 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
14581 </tr>
14582 <tr class="row-odd"><td>9</td>
14583 <td>DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
14584 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
14585 </tr>
14586 </tbody>
14587 </table>
14588 </div>
14589 <div class="section" id="clocks-for-rti31-device">
14590 <span id="soc-doc-j721e-public-clks-rti31"></span><h3>Clocks for RTI31 Device<a class="headerlink" href="#clocks-for-rti31-device" title="Permalink to this headline">¶</a></h3>
14591 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_RTI31</span></a> (ID = 261)</p>
14592 <p>Following is a mapping of Clocks IDs to function:</p>
14593 <table border="1" class="docutils">
14594 <colgroup>
14595 <col width="9%" />
14596 <col width="53%" />
14597 <col width="37%" />
14598 </colgroup>
14599 <thead valign="bottom">
14600 <tr class="row-odd"><th class="head">Clock ID</th>
14601 <th class="head">Name</th>
14602 <th class="head">Function</th>
14603 </tr>
14604 </thead>
14605 <tbody valign="top">
14606 <tr class="row-even"><td>0</td>
14607 <td>DEV_RTI31_VBUSP_CLK</td>
14608 <td>Input clock</td>
14609 </tr>
14610 <tr class="row-odd"><td>1</td>
14611 <td>DEV_RTI31_RTI_CLK</td>
14612 <td>Input muxed clock</td>
14613 </tr>
14614 <tr class="row-even"><td>2</td>
14615 <td>DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14616 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
14617 </tr>
14618 <tr class="row-odd"><td>3</td>
14619 <td>DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
14620 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
14621 </tr>
14622 <tr class="row-even"><td>4</td>
14623 <td>DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
14624 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
14625 </tr>
14626 <tr class="row-odd"><td>5</td>
14627 <td>DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
14628 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
14629 </tr>
14630 <tr class="row-even"><td>6</td>
14631 <td>DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14632 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
14633 </tr>
14634 <tr class="row-odd"><td>7</td>
14635 <td>DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
14636 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
14637 </tr>
14638 <tr class="row-even"><td>8</td>
14639 <td>DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
14640 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
14641 </tr>
14642 <tr class="row-odd"><td>9</td>
14643 <td>DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
14644 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
14645 </tr>
14646 </tbody>
14647 </table>
14648 </div>
14649 <div class="section" id="clocks-for-sa2-ul0-device">
14650 <span id="soc-doc-j721e-public-clks-sa2-ul0"></span><h3>Clocks for SA2_UL0 Device<a class="headerlink" href="#clocks-for-sa2-ul0-device" title="Permalink to this headline">¶</a></h3>
14651 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_SA2_UL0</span></a> (ID = 264)</p>
14652 <p>Following is a mapping of Clocks IDs to function:</p>
14653 <table border="1" class="docutils">
14654 <colgroup>
14655 <col width="24%" />
14656 <col width="49%" />
14657 <col width="27%" />
14658 </colgroup>
14659 <thead valign="bottom">
14660 <tr class="row-odd"><th class="head">Clock ID</th>
14661 <th class="head">Name</th>
14662 <th class="head">Function</th>
14663 </tr>
14664 </thead>
14665 <tbody valign="top">
14666 <tr class="row-even"><td>0</td>
14667 <td>DEV_SA2_UL0_X2_CLK</td>
14668 <td>Input clock</td>
14669 </tr>
14670 <tr class="row-odd"><td>1</td>
14671 <td>DEV_SA2_UL0_PKA_IN_CLK</td>
14672 <td>Input clock</td>
14673 </tr>
14674 <tr class="row-even"><td>2</td>
14675 <td>DEV_SA2_UL0_X1_CLK</td>
14676 <td>Input clock</td>
14677 </tr>
14678 </tbody>
14679 </table>
14680 </div>
14681 <div class="section" id="clocks-for-serdes-10g0-device">
14682 <span id="soc-doc-j721e-public-clks-serdes-10g0"></span><h3>Clocks for SERDES_10G0 Device<a class="headerlink" href="#clocks-for-serdes-10g0-device" title="Permalink to this headline">¶</a></h3>
14683 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_SERDES_10G0</span></a> (ID = 297)</p>
14684 <p>Following is a mapping of Clocks IDs to function:</p>
14685 <table border="1" class="docutils">
14686 <colgroup>
14687 <col width="8%" />
14688 <col width="50%" />
14689 <col width="42%" />
14690 </colgroup>
14691 <thead valign="bottom">
14692 <tr class="row-odd"><th class="head">Clock ID</th>
14693 <th class="head">Name</th>
14694 <th class="head">Function</th>
14695 </tr>
14696 </thead>
14697 <tbody valign="top">
14698 <tr class="row-even"><td>0</td>
14699 <td>DEV_SERDES_10G0_IP1_LN3_TXCLK</td>
14700 <td>Input clock</td>
14701 </tr>
14702 <tr class="row-odd"><td>1</td>
14703 <td>DEV_SERDES_10G0_CLK</td>
14704 <td>Input clock</td>
14705 </tr>
14706 <tr class="row-even"><td>2</td>
14707 <td>DEV_SERDES_10G0_IP3_LN2_TXCLK</td>
14708 <td>Input clock</td>
14709 </tr>
14710 <tr class="row-odd"><td>3</td>
14711 <td>DEV_SERDES_10G0_IP1_LN2_TXCLK</td>
14712 <td>Input clock</td>
14713 </tr>
14714 <tr class="row-even"><td>4</td>
14715 <td>DEV_SERDES_10G0_IP1_LN0_TXCLK</td>
14716 <td>Input clock</td>
14717 </tr>
14718 <tr class="row-odd"><td>5</td>
14719 <td>DEV_SERDES_10G0_IP3_LN1_TXCLK</td>
14720 <td>Input clock</td>
14721 </tr>
14722 <tr class="row-even"><td>6</td>
14723 <td>DEV_SERDES_10G0_IP3_LN3_TXCLK</td>
14724 <td>Input clock</td>
14725 </tr>
14726 <tr class="row-odd"><td>7</td>
14727 <td>DEV_SERDES_10G0_IP3_LN0_TXCLK</td>
14728 <td>Input clock</td>
14729 </tr>
14730 <tr class="row-even"><td>8</td>
14731 <td>DEV_SERDES_10G0_IP1_LN1_TXCLK</td>
14732 <td>Input clock</td>
14733 </tr>
14734 <tr class="row-odd"><td>9</td>
14735 <td>DEV_SERDES_10G0_CORE_REF_CLK</td>
14736 <td>Input muxed clock</td>
14737 </tr>
14738 <tr class="row-even"><td>10</td>
14739 <td>DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14740 <td>Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK</td>
14741 </tr>
14742 <tr class="row-odd"><td>11</td>
14743 <td>DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14744 <td>Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK</td>
14745 </tr>
14746 <tr class="row-even"><td>12</td>
14747 <td>DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
14748 <td>Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK</td>
14749 </tr>
14750 <tr class="row-odd"><td>13</td>
14751 <td>DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
14752 <td>Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK</td>
14753 </tr>
14754 <tr class="row-even"><td>14</td>
14755 <td>DEV_SERDES_10G0_IP1_LN1_REFCLK</td>
14756 <td>Output clock</td>
14757 </tr>
14758 <tr class="row-odd"><td>15</td>
14759 <td>DEV_SERDES_10G0_IP1_LN2_RXCLK</td>
14760 <td>Output clock</td>
14761 </tr>
14762 <tr class="row-even"><td>16</td>
14763 <td>DEV_SERDES_10G0_IP3_LN1_TXFCLK</td>
14764 <td>Output clock</td>
14765 </tr>
14766 <tr class="row-odd"><td>17</td>
14767 <td>DEV_SERDES_10G0_IP1_LN0_RXFCLK</td>
14768 <td>Output clock</td>
14769 </tr>
14770 <tr class="row-even"><td>18</td>
14771 <td>DEV_SERDES_10G0_IP1_LN3_RXCLK</td>
14772 <td>Output clock</td>
14773 </tr>
14774 <tr class="row-odd"><td>19</td>
14775 <td>DEV_SERDES_10G0_IP3_LN3_RXCLK</td>
14776 <td>Output clock</td>
14777 </tr>
14778 <tr class="row-even"><td>20</td>
14779 <td>DEV_SERDES_10G0_IP3_LN1_TXMCLK</td>
14780 <td>Output clock</td>
14781 </tr>
14782 <tr class="row-odd"><td>21</td>
14783 <td>DEV_SERDES_10G0_IP3_LN3_RXFCLK</td>
14784 <td>Output clock</td>
14785 </tr>
14786 <tr class="row-even"><td>22</td>
14787 <td>DEV_SERDES_10G0_IP3_LN3_REFCLK</td>
14788 <td>Output clock</td>
14789 </tr>
14790 <tr class="row-odd"><td>23</td>
14791 <td>DEV_SERDES_10G0_IP3_LN2_RXCLK</td>
14792 <td>Output clock</td>
14793 </tr>
14794 <tr class="row-even"><td>24</td>
14795 <td>DEV_SERDES_10G0_IP1_LN0_TXFCLK</td>
14796 <td>Output clock</td>
14797 </tr>
14798 <tr class="row-odd"><td>25</td>
14799 <td>DEV_SERDES_10G0_IP3_LN3_TXMCLK</td>
14800 <td>Output clock</td>
14801 </tr>
14802 <tr class="row-even"><td>26</td>
14803 <td>DEV_SERDES_10G0_IP3_LN1_RXFCLK</td>
14804 <td>Output clock</td>
14805 </tr>
14806 <tr class="row-odd"><td>27</td>
14807 <td>DEV_SERDES_10G0_IP3_LN0_RXFCLK</td>
14808 <td>Output clock</td>
14809 </tr>
14810 <tr class="row-even"><td>28</td>
14811 <td>DEV_SERDES_10G0_IP1_LN1_TXMCLK</td>
14812 <td>Output clock</td>
14813 </tr>
14814 <tr class="row-odd"><td>29</td>
14815 <td>DEV_SERDES_10G0_IP1_LN1_RXFCLK</td>
14816 <td>Output clock</td>
14817 </tr>
14818 <tr class="row-even"><td>30</td>
14819 <td>DEV_SERDES_10G0_IP3_LN3_TXFCLK</td>
14820 <td>Output clock</td>
14821 </tr>
14822 <tr class="row-odd"><td>31</td>
14823 <td>DEV_SERDES_10G0_IP1_LN3_TXFCLK</td>
14824 <td>Output clock</td>
14825 </tr>
14826 <tr class="row-even"><td>32</td>
14827 <td>DEV_SERDES_10G0_IP1_LN3_TXMCLK</td>
14828 <td>Output clock</td>
14829 </tr>
14830 <tr class="row-odd"><td>33</td>
14831 <td>DEV_SERDES_10G0_IP3_LN1_REFCLK</td>
14832 <td>Output clock</td>
14833 </tr>
14834 <tr class="row-even"><td>34</td>
14835 <td>DEV_SERDES_10G0_IP3_LN0_REFCLK</td>
14836 <td>Output clock</td>
14837 </tr>
14838 <tr class="row-odd"><td>35</td>
14839 <td>DEV_SERDES_10G0_IP1_LN3_REFCLK</td>
14840 <td>Output clock</td>
14841 </tr>
14842 <tr class="row-even"><td>36</td>
14843 <td>DEV_SERDES_10G0_IP3_LN0_RXCLK</td>
14844 <td>Output clock</td>
14845 </tr>
14846 <tr class="row-odd"><td>37</td>
14847 <td>DEV_SERDES_10G0_IP3_LN2_REFCLK</td>
14848 <td>Output clock</td>
14849 </tr>
14850 <tr class="row-even"><td>38</td>
14851 <td>DEV_SERDES_10G0_IP1_LN0_RXCLK</td>
14852 <td>Output clock</td>
14853 </tr>
14854 <tr class="row-odd"><td>39</td>
14855 <td>DEV_SERDES_10G0_IP1_LN0_REFCLK</td>
14856 <td>Output clock</td>
14857 </tr>
14858 <tr class="row-even"><td>40</td>
14859 <td>DEV_SERDES_10G0_IP1_LN2_RXFCLK</td>
14860 <td>Output clock</td>
14861 </tr>
14862 <tr class="row-odd"><td>41</td>
14863 <td>DEV_SERDES_10G0_IP1_LN1_TXFCLK</td>
14864 <td>Output clock</td>
14865 </tr>
14866 <tr class="row-even"><td>42</td>
14867 <td>DEV_SERDES_10G0_IP3_LN0_TXFCLK</td>
14868 <td>Output clock</td>
14869 </tr>
14870 <tr class="row-odd"><td>43</td>
14871 <td>DEV_SERDES_10G0_REF_OUT_CLK</td>
14872 <td>Output clock</td>
14873 </tr>
14874 <tr class="row-even"><td>44</td>
14875 <td>DEV_SERDES_10G0_IP3_LN1_RXCLK</td>
14876 <td>Output clock</td>
14877 </tr>
14878 <tr class="row-odd"><td>45</td>
14879 <td>DEV_SERDES_10G0_IP1_LN2_TXFCLK</td>
14880 <td>Output clock</td>
14881 </tr>
14882 <tr class="row-even"><td>46</td>
14883 <td>DEV_SERDES_10G0_IP1_LN0_TXMCLK</td>
14884 <td>Output clock</td>
14885 </tr>
14886 <tr class="row-odd"><td>47</td>
14887 <td>DEV_SERDES_10G0_IP3_LN2_RXFCLK</td>
14888 <td>Output clock</td>
14889 </tr>
14890 <tr class="row-even"><td>48</td>
14891 <td>DEV_SERDES_10G0_IP1_LN2_TXMCLK</td>
14892 <td>Output clock</td>
14893 </tr>
14894 <tr class="row-odd"><td>49</td>
14895 <td>DEV_SERDES_10G0_IP3_LN2_TXMCLK</td>
14896 <td>Output clock</td>
14897 </tr>
14898 <tr class="row-even"><td>50</td>
14899 <td>DEV_SERDES_10G0_IP1_LN2_REFCLK</td>
14900 <td>Output clock</td>
14901 </tr>
14902 <tr class="row-odd"><td>51</td>
14903 <td>DEV_SERDES_10G0_IP3_LN2_TXFCLK</td>
14904 <td>Output clock</td>
14905 </tr>
14906 <tr class="row-even"><td>52</td>
14907 <td>DEV_SERDES_10G0_IP3_LN0_TXMCLK</td>
14908 <td>Output clock</td>
14909 </tr>
14910 <tr class="row-odd"><td>53</td>
14911 <td>DEV_SERDES_10G0_IP1_LN3_RXFCLK</td>
14912 <td>Output clock</td>
14913 </tr>
14914 <tr class="row-even"><td>54</td>
14915 <td>DEV_SERDES_10G0_IP1_LN1_RXCLK</td>
14916 <td>Output clock</td>
14917 </tr>
14918 </tbody>
14919 </table>
14920 </div>
14921 <div class="section" id="clocks-for-serdes-16g0-device">
14922 <span id="soc-doc-j721e-public-clks-serdes-16g0"></span><h3>Clocks for SERDES_16G0 Device<a class="headerlink" href="#clocks-for-serdes-16g0-device" title="Permalink to this headline">¶</a></h3>
14923 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_SERDES_16G0</span></a> (ID = 292)</p>
14924 <p>Following is a mapping of Clocks IDs to function:</p>
14925 <table border="1" class="docutils">
14926 <colgroup>
14927 <col width="8%" />
14928 <col width="50%" />
14929 <col width="42%" />
14930 </colgroup>
14931 <thead valign="bottom">
14932 <tr class="row-odd"><th class="head">Clock ID</th>
14933 <th class="head">Name</th>
14934 <th class="head">Function</th>
14935 </tr>
14936 </thead>
14937 <tbody valign="top">
14938 <tr class="row-even"><td>0</td>
14939 <td>DEV_SERDES_16G0_CORE_REF1_CLK</td>
14940 <td>Input muxed clock</td>
14941 </tr>
14942 <tr class="row-odd"><td>1</td>
14943 <td>DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14944 <td>Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK</td>
14945 </tr>
14946 <tr class="row-even"><td>2</td>
14947 <td>DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14948 <td>Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK</td>
14949 </tr>
14950 <tr class="row-odd"><td>3</td>
14951 <td>DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
14952 <td>Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK</td>
14953 </tr>
14954 <tr class="row-even"><td>4</td>
14955 <td>DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
14956 <td>Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK</td>
14957 </tr>
14958 <tr class="row-odd"><td>5</td>
14959 <td>DEV_SERDES_16G0_CLK</td>
14960 <td>Input clock</td>
14961 </tr>
14962 <tr class="row-even"><td>6</td>
14963 <td>DEV_SERDES_16G0_IP1_LN0_TXCLK</td>
14964 <td>Input clock</td>
14965 </tr>
14966 <tr class="row-odd"><td>7</td>
14967 <td>DEV_SERDES_16G0_IP2_LN1_TXCLK</td>
14968 <td>Input clock</td>
14969 </tr>
14970 <tr class="row-even"><td>8</td>
14971 <td>DEV_SERDES_16G0_IP3_LN1_TXCLK</td>
14972 <td>Input clock</td>
14973 </tr>
14974 <tr class="row-odd"><td>9</td>
14975 <td>DEV_SERDES_16G0_IP2_LN0_TXCLK</td>
14976 <td>Input clock</td>
14977 </tr>
14978 <tr class="row-even"><td>10</td>
14979 <td>DEV_SERDES_16G0_IP1_LN1_TXCLK</td>
14980 <td>Input clock</td>
14981 </tr>
14982 <tr class="row-odd"><td>11</td>
14983 <td>DEV_SERDES_16G0_CORE_REF_CLK</td>
14984 <td>Input muxed clock</td>
14985 </tr>
14986 <tr class="row-even"><td>12</td>
14987 <td>DEV_SERDES_16G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14988 <td>Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK</td>
14989 </tr>
14990 <tr class="row-odd"><td>13</td>
14991 <td>DEV_SERDES_16G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14992 <td>Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK</td>
14993 </tr>
14994 <tr class="row-even"><td>14</td>
14995 <td>DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
14996 <td>Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK</td>
14997 </tr>
14998 <tr class="row-odd"><td>15</td>
14999 <td>DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
15000 <td>Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK</td>
15001 </tr>
15002 <tr class="row-even"><td>16</td>
15003 <td>DEV_SERDES_16G0_IP2_LN0_TXFCLK</td>
15004 <td>Output clock</td>
15005 </tr>
15006 <tr class="row-odd"><td>17</td>
15007 <td>DEV_SERDES_16G0_IP1_LN1_REFCLK</td>
15008 <td>Output clock</td>
15009 </tr>
15010 <tr class="row-even"><td>18</td>
15011 <td>DEV_SERDES_16G0_IP3_LN1_TXMCLK</td>
15012 <td>Output clock</td>
15013 </tr>
15014 <tr class="row-odd"><td>19</td>
15015 <td>DEV_SERDES_16G0_IP3_LN1_TXFCLK</td>
15016 <td>Output clock</td>
15017 </tr>
15018 <tr class="row-even"><td>20</td>
15019 <td>DEV_SERDES_16G0_IP1_LN0_RXFCLK</td>
15020 <td>Output clock</td>
15021 </tr>
15022 <tr class="row-odd"><td>21</td>
15023 <td>DEV_SERDES_16G0_IP2_LN1_REFCLK</td>
15024 <td>Output clock</td>
15025 </tr>
15026 <tr class="row-even"><td>22</td>
15027 <td>DEV_SERDES_16G0_IP2_LN1_TXFCLK</td>
15028 <td>Output clock</td>
15029 </tr>
15030 <tr class="row-odd"><td>24</td>
15031 <td>DEV_SERDES_16G0_IP1_LN0_TXFCLK</td>
15032 <td>Output clock</td>
15033 </tr>
15034 <tr class="row-even"><td>25</td>
15035 <td>DEV_SERDES_16G0_IP3_LN1_RXFCLK</td>
15036 <td>Output clock</td>
15037 </tr>
15038 <tr class="row-odd"><td>26</td>
15039 <td>DEV_SERDES_16G0_IP1_LN1_TXMCLK</td>
15040 <td>Output clock</td>
15041 </tr>
15042 <tr class="row-even"><td>27</td>
15043 <td>DEV_SERDES_16G0_IP1_LN1_RXFCLK</td>
15044 <td>Output clock</td>
15045 </tr>
15046 <tr class="row-odd"><td>28</td>
15047 <td>DEV_SERDES_16G0_IP3_LN1_RXCLK</td>
15048 <td>Output clock</td>
15049 </tr>
15050 <tr class="row-even"><td>29</td>
15051 <td>DEV_SERDES_16G0_IP3_LN1_REFCLK</td>
15052 <td>Output clock</td>
15053 </tr>
15054 <tr class="row-odd"><td>30</td>
15055 <td>DEV_SERDES_16G0_IP2_LN1_RXCLK</td>
15056 <td>Output clock</td>
15057 </tr>
15058 <tr class="row-even"><td>31</td>
15059 <td>DEV_SERDES_16G0_IP2_LN0_RXFCLK</td>
15060 <td>Output clock</td>
15061 </tr>
15062 <tr class="row-odd"><td>32</td>
15063 <td>DEV_SERDES_16G0_IP1_LN0_RXCLK</td>
15064 <td>Output clock</td>
15065 </tr>
15066 <tr class="row-even"><td>33</td>
15067 <td>DEV_SERDES_16G0_REF_OUT_CLK</td>
15068 <td>Output clock</td>
15069 </tr>
15070 <tr class="row-odd"><td>34</td>
15071 <td>DEV_SERDES_16G0_REF1_OUT_CLK</td>
15072 <td>Output clock</td>
15073 </tr>
15074 <tr class="row-even"><td>35</td>
15075 <td>DEV_SERDES_16G0_IP1_LN0_REFCLK</td>
15076 <td>Output clock</td>
15077 </tr>
15078 <tr class="row-odd"><td>36</td>
15079 <td>DEV_SERDES_16G0_IP1_LN0_TXMCLK</td>
15080 <td>Output clock</td>
15081 </tr>
15082 <tr class="row-even"><td>37</td>
15083 <td>DEV_SERDES_16G0_IP2_LN1_RXFCLK</td>
15084 <td>Output clock</td>
15085 </tr>
15086 <tr class="row-odd"><td>38</td>
15087 <td>DEV_SERDES_16G0_IP2_LN1_TXMCLK</td>
15088 <td>Output clock</td>
15089 </tr>
15090 <tr class="row-even"><td>39</td>
15091 <td>DEV_SERDES_16G0_IP2_LN0_REFCLK</td>
15092 <td>Output clock</td>
15093 </tr>
15094 <tr class="row-odd"><td>40</td>
15095 <td>DEV_SERDES_16G0_IP2_LN0_TXMCLK</td>
15096 <td>Output clock</td>
15097 </tr>
15098 <tr class="row-even"><td>41</td>
15099 <td>DEV_SERDES_16G0_IP1_LN1_TXFCLK</td>
15100 <td>Output clock</td>
15101 </tr>
15102 <tr class="row-odd"><td>42</td>
15103 <td>DEV_SERDES_16G0_IP2_LN0_RXCLK</td>
15104 <td>Output clock</td>
15105 </tr>
15106 <tr class="row-even"><td>43</td>
15107 <td>DEV_SERDES_16G0_IP1_LN1_RXCLK</td>
15108 <td>Output clock</td>
15109 </tr>
15110 <tr class="row-odd"><td>49</td>
15111 <td>DEV_SERDES_16G0_CMN_REFCLK1_M</td>
15112 <td>Input clock</td>
15113 </tr>
15114 <tr class="row-even"><td>57</td>
15115 <td>DEV_SERDES_16G0_CMN_REFCLK1_P</td>
15116 <td>Input clock</td>
15117 </tr>
15118 </tbody>
15119 </table>
15120 </div>
15121 <div class="section" id="clocks-for-serdes-16g1-device">
15122 <span id="soc-doc-j721e-public-clks-serdes-16g1"></span><h3>Clocks for SERDES_16G1 Device<a class="headerlink" href="#clocks-for-serdes-16g1-device" title="Permalink to this headline">¶</a></h3>
15123 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_SERDES_16G1</span></a> (ID = 293)</p>
15124 <p>Following is a mapping of Clocks IDs to function:</p>
15125 <table border="1" class="docutils">
15126 <colgroup>
15127 <col width="8%" />
15128 <col width="50%" />
15129 <col width="42%" />
15130 </colgroup>
15131 <thead valign="bottom">
15132 <tr class="row-odd"><th class="head">Clock ID</th>
15133 <th class="head">Name</th>
15134 <th class="head">Function</th>
15135 </tr>
15136 </thead>
15137 <tbody valign="top">
15138 <tr class="row-even"><td>0</td>
15139 <td>DEV_SERDES_16G1_CORE_REF1_CLK</td>
15140 <td>Input muxed clock</td>
15141 </tr>
15142 <tr class="row-odd"><td>1</td>
15143 <td>DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15144 <td>Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK</td>
15145 </tr>
15146 <tr class="row-even"><td>2</td>
15147 <td>DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15148 <td>Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK</td>
15149 </tr>
15150 <tr class="row-odd"><td>3</td>
15151 <td>DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
15152 <td>Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK</td>
15153 </tr>
15154 <tr class="row-even"><td>4</td>
15155 <td>DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
15156 <td>Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK</td>
15157 </tr>
15158 <tr class="row-odd"><td>5</td>
15159 <td>DEV_SERDES_16G1_CLK</td>
15160 <td>Input clock</td>
15161 </tr>
15162 <tr class="row-even"><td>6</td>
15163 <td>DEV_SERDES_16G1_IP1_LN0_TXCLK</td>
15164 <td>Input clock</td>
15165 </tr>
15166 <tr class="row-odd"><td>7</td>
15167 <td>DEV_SERDES_16G1_IP2_LN1_TXCLK</td>
15168 <td>Input clock</td>
15169 </tr>
15170 <tr class="row-even"><td>8</td>
15171 <td>DEV_SERDES_16G1_IP4_LN1_TXCLK</td>
15172 <td>Input clock</td>
15173 </tr>
15174 <tr class="row-odd"><td>9</td>
15175 <td>DEV_SERDES_16G1_IP4_LN0_TXCLK</td>
15176 <td>Input clock</td>
15177 </tr>
15178 <tr class="row-even"><td>10</td>
15179 <td>DEV_SERDES_16G1_IP3_LN1_TXCLK</td>
15180 <td>Input clock</td>
15181 </tr>
15182 <tr class="row-odd"><td>11</td>
15183 <td>DEV_SERDES_16G1_IP2_LN0_TXCLK</td>
15184 <td>Input clock</td>
15185 </tr>
15186 <tr class="row-even"><td>12</td>
15187 <td>DEV_SERDES_16G1_IP1_LN1_TXCLK</td>
15188 <td>Input clock</td>
15189 </tr>
15190 <tr class="row-odd"><td>13</td>
15191 <td>DEV_SERDES_16G1_CORE_REF_CLK</td>
15192 <td>Input muxed clock</td>
15193 </tr>
15194 <tr class="row-even"><td>14</td>
15195 <td>DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15196 <td>Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK</td>
15197 </tr>
15198 <tr class="row-odd"><td>15</td>
15199 <td>DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15200 <td>Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK</td>
15201 </tr>
15202 <tr class="row-even"><td>16</td>
15203 <td>DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
15204 <td>Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK</td>
15205 </tr>
15206 <tr class="row-odd"><td>17</td>
15207 <td>DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
15208 <td>Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK</td>
15209 </tr>
15210 <tr class="row-even"><td>18</td>
15211 <td>DEV_SERDES_16G1_IP2_LN0_TXFCLK</td>
15212 <td>Output clock</td>
15213 </tr>
15214 <tr class="row-odd"><td>19</td>
15215 <td>DEV_SERDES_16G1_IP1_LN1_REFCLK</td>
15216 <td>Output clock</td>
15217 </tr>
15218 <tr class="row-even"><td>20</td>
15219 <td>DEV_SERDES_16G1_IP4_LN1_RXFCLK</td>
15220 <td>Output clock</td>
15221 </tr>
15222 <tr class="row-odd"><td>21</td>
15223 <td>DEV_SERDES_16G1_IP3_LN1_TXMCLK</td>
15224 <td>Output clock</td>
15225 </tr>
15226 <tr class="row-even"><td>22</td>
15227 <td>DEV_SERDES_16G1_IP3_LN1_TXFCLK</td>
15228 <td>Output clock</td>
15229 </tr>
15230 <tr class="row-odd"><td>23</td>
15231 <td>DEV_SERDES_16G1_IP1_LN0_RXFCLK</td>
15232 <td>Output clock</td>
15233 </tr>
15234 <tr class="row-even"><td>24</td>
15235 <td>DEV_SERDES_16G1_IP2_LN1_REFCLK</td>
15236 <td>Output clock</td>
15237 </tr>
15238 <tr class="row-odd"><td>25</td>
15239 <td>DEV_SERDES_16G1_IP2_LN1_TXFCLK</td>
15240 <td>Output clock</td>
15241 </tr>
15242 <tr class="row-even"><td>27</td>
15243 <td>DEV_SERDES_16G1_IP1_LN0_TXFCLK</td>
15244 <td>Output clock</td>
15245 </tr>
15246 <tr class="row-odd"><td>28</td>
15247 <td>DEV_SERDES_16G1_IP3_LN1_RXFCLK</td>
15248 <td>Output clock</td>
15249 </tr>
15250 <tr class="row-even"><td>29</td>
15251 <td>DEV_SERDES_16G1_IP1_LN1_TXMCLK</td>
15252 <td>Output clock</td>
15253 </tr>
15254 <tr class="row-odd"><td>30</td>
15255 <td>DEV_SERDES_16G1_IP1_LN1_RXFCLK</td>
15256 <td>Output clock</td>
15257 </tr>
15258 <tr class="row-even"><td>31</td>
15259 <td>DEV_SERDES_16G1_IP4_LN1_REFCLK</td>
15260 <td>Output clock</td>
15261 </tr>
15262 <tr class="row-odd"><td>32</td>
15263 <td>DEV_SERDES_16G1_IP3_LN1_RXCLK</td>
15264 <td>Output clock</td>
15265 </tr>
15266 <tr class="row-even"><td>33</td>
15267 <td>DEV_SERDES_16G1_IP4_LN1_TXMCLK</td>
15268 <td>Output clock</td>
15269 </tr>
15270 <tr class="row-odd"><td>34</td>
15271 <td>DEV_SERDES_16G1_IP3_LN1_REFCLK</td>
15272 <td>Output clock</td>
15273 </tr>
15274 <tr class="row-even"><td>35</td>
15275 <td>DEV_SERDES_16G1_IP4_LN0_REFCLK</td>
15276 <td>Output clock</td>
15277 </tr>
15278 <tr class="row-odd"><td>36</td>
15279 <td>DEV_SERDES_16G1_IP2_LN1_RXCLK</td>
15280 <td>Output clock</td>
15281 </tr>
15282 <tr class="row-even"><td>37</td>
15283 <td>DEV_SERDES_16G1_IP2_LN0_RXFCLK</td>
15284 <td>Output clock</td>
15285 </tr>
15286 <tr class="row-odd"><td>38</td>
15287 <td>DEV_SERDES_16G1_IP1_LN0_RXCLK</td>
15288 <td>Output clock</td>
15289 </tr>
15290 <tr class="row-even"><td>39</td>
15291 <td>DEV_SERDES_16G1_REF_OUT_CLK</td>
15292 <td>Output clock</td>
15293 </tr>
15294 <tr class="row-odd"><td>40</td>
15295 <td>DEV_SERDES_16G1_REF1_OUT_CLK</td>
15296 <td>Output clock</td>
15297 </tr>
15298 <tr class="row-even"><td>41</td>
15299 <td>DEV_SERDES_16G1_IP4_LN1_RXCLK</td>
15300 <td>Output clock</td>
15301 </tr>
15302 <tr class="row-odd"><td>42</td>
15303 <td>DEV_SERDES_16G1_IP1_LN0_REFCLK</td>
15304 <td>Output clock</td>
15305 </tr>
15306 <tr class="row-even"><td>43</td>
15307 <td>DEV_SERDES_16G1_IP1_LN0_TXMCLK</td>
15308 <td>Output clock</td>
15309 </tr>
15310 <tr class="row-odd"><td>44</td>
15311 <td>DEV_SERDES_16G1_IP4_LN0_TXFCLK</td>
15312 <td>Output clock</td>
15313 </tr>
15314 <tr class="row-even"><td>45</td>
15315 <td>DEV_SERDES_16G1_IP4_LN0_RXCLK</td>
15316 <td>Output clock</td>
15317 </tr>
15318 <tr class="row-odd"><td>46</td>
15319 <td>DEV_SERDES_16G1_IP2_LN1_RXFCLK</td>
15320 <td>Output clock</td>
15321 </tr>
15322 <tr class="row-even"><td>47</td>
15323 <td>DEV_SERDES_16G1_IP2_LN1_TXMCLK</td>
15324 <td>Output clock</td>
15325 </tr>
15326 <tr class="row-odd"><td>48</td>
15327 <td>DEV_SERDES_16G1_IP4_LN0_RXFCLK</td>
15328 <td>Output clock</td>
15329 </tr>
15330 <tr class="row-even"><td>49</td>
15331 <td>DEV_SERDES_16G1_IP2_LN0_REFCLK</td>
15332 <td>Output clock</td>
15333 </tr>
15334 <tr class="row-odd"><td>50</td>
15335 <td>DEV_SERDES_16G1_IP2_LN0_TXMCLK</td>
15336 <td>Output clock</td>
15337 </tr>
15338 <tr class="row-even"><td>51</td>
15339 <td>DEV_SERDES_16G1_IP1_LN1_TXFCLK</td>
15340 <td>Output clock</td>
15341 </tr>
15342 <tr class="row-odd"><td>52</td>
15343 <td>DEV_SERDES_16G1_IP2_LN0_RXCLK</td>
15344 <td>Output clock</td>
15345 </tr>
15346 <tr class="row-even"><td>53</td>
15347 <td>DEV_SERDES_16G1_IP4_LN0_TXMCLK</td>
15348 <td>Output clock</td>
15349 </tr>
15350 <tr class="row-odd"><td>54</td>
15351 <td>DEV_SERDES_16G1_IP1_LN1_RXCLK</td>
15352 <td>Output clock</td>
15353 </tr>
15354 <tr class="row-even"><td>55</td>
15355 <td>DEV_SERDES_16G1_IP4_LN1_TXFCLK</td>
15356 <td>Output clock</td>
15357 </tr>
15358 <tr class="row-odd"><td>60</td>
15359 <td>DEV_SERDES_16G1_CMN_REFCLK1_M</td>
15360 <td>Input clock</td>
15361 </tr>
15362 <tr class="row-even"><td>67</td>
15363 <td>DEV_SERDES_16G1_CMN_REFCLK1_P</td>
15364 <td>Input clock</td>
15365 </tr>
15366 </tbody>
15367 </table>
15368 </div>
15369 <div class="section" id="clocks-for-serdes-16g2-device">
15370 <span id="soc-doc-j721e-public-clks-serdes-16g2"></span><h3>Clocks for SERDES_16G2 Device<a class="headerlink" href="#clocks-for-serdes-16g2-device" title="Permalink to this headline">¶</a></h3>
15371 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_SERDES_16G2</span></a> (ID = 294)</p>
15372 <p>Following is a mapping of Clocks IDs to function:</p>
15373 <table border="1" class="docutils">
15374 <colgroup>
15375 <col width="8%" />
15376 <col width="50%" />
15377 <col width="42%" />
15378 </colgroup>
15379 <thead valign="bottom">
15380 <tr class="row-odd"><th class="head">Clock ID</th>
15381 <th class="head">Name</th>
15382 <th class="head">Function</th>
15383 </tr>
15384 </thead>
15385 <tbody valign="top">
15386 <tr class="row-even"><td>0</td>
15387 <td>DEV_SERDES_16G2_CORE_REF1_CLK</td>
15388 <td>Input muxed clock</td>
15389 </tr>
15390 <tr class="row-odd"><td>1</td>
15391 <td>DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15392 <td>Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK</td>
15393 </tr>
15394 <tr class="row-even"><td>2</td>
15395 <td>DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15396 <td>Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK</td>
15397 </tr>
15398 <tr class="row-odd"><td>3</td>
15399 <td>DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
15400 <td>Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK</td>
15401 </tr>
15402 <tr class="row-even"><td>4</td>
15403 <td>DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
15404 <td>Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK</td>
15405 </tr>
15406 <tr class="row-odd"><td>5</td>
15407 <td>DEV_SERDES_16G2_CLK</td>
15408 <td>Input clock</td>
15409 </tr>
15410 <tr class="row-even"><td>6</td>
15411 <td>DEV_SERDES_16G2_IP2_LN1_TXCLK</td>
15412 <td>Input clock</td>
15413 </tr>
15414 <tr class="row-odd"><td>7</td>
15415 <td>DEV_SERDES_16G2_IP4_LN1_TXCLK</td>
15416 <td>Input clock</td>
15417 </tr>
15418 <tr class="row-even"><td>8</td>
15419 <td>DEV_SERDES_16G2_IP4_LN0_TXCLK</td>
15420 <td>Input clock</td>
15421 </tr>
15422 <tr class="row-odd"><td>9</td>
15423 <td>DEV_SERDES_16G2_IP3_LN1_TXCLK</td>
15424 <td>Input clock</td>
15425 </tr>
15426 <tr class="row-even"><td>10</td>
15427 <td>DEV_SERDES_16G2_IP2_LN0_TXCLK</td>
15428 <td>Input clock</td>
15429 </tr>
15430 <tr class="row-odd"><td>11</td>
15431 <td>DEV_SERDES_16G2_CORE_REF_CLK</td>
15432 <td>Input muxed clock</td>
15433 </tr>
15434 <tr class="row-even"><td>12</td>
15435 <td>DEV_SERDES_16G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15436 <td>Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK</td>
15437 </tr>
15438 <tr class="row-odd"><td>13</td>
15439 <td>DEV_SERDES_16G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15440 <td>Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK</td>
15441 </tr>
15442 <tr class="row-even"><td>14</td>
15443 <td>DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
15444 <td>Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK</td>
15445 </tr>
15446 <tr class="row-odd"><td>15</td>
15447 <td>DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
15448 <td>Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK</td>
15449 </tr>
15450 <tr class="row-even"><td>16</td>
15451 <td>DEV_SERDES_16G2_IP2_LN0_TXFCLK</td>
15452 <td>Output clock</td>
15453 </tr>
15454 <tr class="row-odd"><td>17</td>
15455 <td>DEV_SERDES_16G2_IP4_LN1_RXFCLK</td>
15456 <td>Output clock</td>
15457 </tr>
15458 <tr class="row-even"><td>18</td>
15459 <td>DEV_SERDES_16G2_IP3_LN1_TXMCLK</td>
15460 <td>Output clock</td>
15461 </tr>
15462 <tr class="row-odd"><td>19</td>
15463 <td>DEV_SERDES_16G2_IP3_LN1_TXFCLK</td>
15464 <td>Output clock</td>
15465 </tr>
15466 <tr class="row-even"><td>20</td>
15467 <td>DEV_SERDES_16G2_IP2_LN1_REFCLK</td>
15468 <td>Output clock</td>
15469 </tr>
15470 <tr class="row-odd"><td>21</td>
15471 <td>DEV_SERDES_16G2_IP2_LN1_TXFCLK</td>
15472 <td>Output clock</td>
15473 </tr>
15474 <tr class="row-even"><td>23</td>
15475 <td>DEV_SERDES_16G2_IP3_LN1_RXFCLK</td>
15476 <td>Output clock</td>
15477 </tr>
15478 <tr class="row-odd"><td>24</td>
15479 <td>DEV_SERDES_16G2_IP4_LN1_REFCLK</td>
15480 <td>Output clock</td>
15481 </tr>
15482 <tr class="row-even"><td>25</td>
15483 <td>DEV_SERDES_16G2_IP3_LN1_RXCLK</td>
15484 <td>Output clock</td>
15485 </tr>
15486 <tr class="row-odd"><td>26</td>
15487 <td>DEV_SERDES_16G2_IP4_LN1_TXMCLK</td>
15488 <td>Output clock</td>
15489 </tr>
15490 <tr class="row-even"><td>27</td>
15491 <td>DEV_SERDES_16G2_IP3_LN1_REFCLK</td>
15492 <td>Output clock</td>
15493 </tr>
15494 <tr class="row-odd"><td>28</td>
15495 <td>DEV_SERDES_16G2_IP4_LN0_REFCLK</td>
15496 <td>Output clock</td>
15497 </tr>
15498 <tr class="row-even"><td>29</td>
15499 <td>DEV_SERDES_16G2_IP2_LN1_RXCLK</td>
15500 <td>Output clock</td>
15501 </tr>
15502 <tr class="row-odd"><td>30</td>
15503 <td>DEV_SERDES_16G2_IP2_LN0_RXFCLK</td>
15504 <td>Output clock</td>
15505 </tr>
15506 <tr class="row-even"><td>31</td>
15507 <td>DEV_SERDES_16G2_REF_OUT_CLK</td>
15508 <td>Output clock</td>
15509 </tr>
15510 <tr class="row-odd"><td>32</td>
15511 <td>DEV_SERDES_16G2_REF1_OUT_CLK</td>
15512 <td>Output clock</td>
15513 </tr>
15514 <tr class="row-even"><td>33</td>
15515 <td>DEV_SERDES_16G2_IP4_LN1_RXCLK</td>
15516 <td>Output clock</td>
15517 </tr>
15518 <tr class="row-odd"><td>34</td>
15519 <td>DEV_SERDES_16G2_IP4_LN0_TXFCLK</td>
15520 <td>Output clock</td>
15521 </tr>
15522 <tr class="row-even"><td>35</td>
15523 <td>DEV_SERDES_16G2_IP4_LN0_RXCLK</td>
15524 <td>Output clock</td>
15525 </tr>
15526 <tr class="row-odd"><td>36</td>
15527 <td>DEV_SERDES_16G2_IP2_LN1_RXFCLK</td>
15528 <td>Output clock</td>
15529 </tr>
15530 <tr class="row-even"><td>37</td>
15531 <td>DEV_SERDES_16G2_IP2_LN1_TXMCLK</td>
15532 <td>Output clock</td>
15533 </tr>
15534 <tr class="row-odd"><td>38</td>
15535 <td>DEV_SERDES_16G2_IP4_LN0_RXFCLK</td>
15536 <td>Output clock</td>
15537 </tr>
15538 <tr class="row-even"><td>39</td>
15539 <td>DEV_SERDES_16G2_IP2_LN0_REFCLK</td>
15540 <td>Output clock</td>
15541 </tr>
15542 <tr class="row-odd"><td>40</td>
15543 <td>DEV_SERDES_16G2_IP2_LN0_TXMCLK</td>
15544 <td>Output clock</td>
15545 </tr>
15546 <tr class="row-even"><td>41</td>
15547 <td>DEV_SERDES_16G2_IP2_LN0_RXCLK</td>
15548 <td>Output clock</td>
15549 </tr>
15550 <tr class="row-odd"><td>42</td>
15551 <td>DEV_SERDES_16G2_IP4_LN0_TXMCLK</td>
15552 <td>Output clock</td>
15553 </tr>
15554 <tr class="row-even"><td>43</td>
15555 <td>DEV_SERDES_16G2_IP4_LN1_TXFCLK</td>
15556 <td>Output clock</td>
15557 </tr>
15558 <tr class="row-odd"><td>51</td>
15559 <td>DEV_SERDES_16G2_CMN_REFCLK1_M</td>
15560 <td>Input clock</td>
15561 </tr>
15562 <tr class="row-even"><td>61</td>
15563 <td>DEV_SERDES_16G2_CMN_REFCLK1_P</td>
15564 <td>Input clock</td>
15565 </tr>
15566 </tbody>
15567 </table>
15568 </div>
15569 <div class="section" id="clocks-for-serdes-16g3-device">
15570 <span id="soc-doc-j721e-public-clks-serdes-16g3"></span><h3>Clocks for SERDES_16G3 Device<a class="headerlink" href="#clocks-for-serdes-16g3-device" title="Permalink to this headline">¶</a></h3>
15571 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_SERDES_16G3</span></a> (ID = 295)</p>
15572 <p>Following is a mapping of Clocks IDs to function:</p>
15573 <table border="1" class="docutils">
15574 <colgroup>
15575 <col width="8%" />
15576 <col width="50%" />
15577 <col width="42%" />
15578 </colgroup>
15579 <thead valign="bottom">
15580 <tr class="row-odd"><th class="head">Clock ID</th>
15581 <th class="head">Name</th>
15582 <th class="head">Function</th>
15583 </tr>
15584 </thead>
15585 <tbody valign="top">
15586 <tr class="row-even"><td>0</td>
15587 <td>DEV_SERDES_16G3_CORE_REF1_CLK</td>
15588 <td>Input muxed clock</td>
15589 </tr>
15590 <tr class="row-odd"><td>1</td>
15591 <td>DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15592 <td>Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK</td>
15593 </tr>
15594 <tr class="row-even"><td>2</td>
15595 <td>DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15596 <td>Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK</td>
15597 </tr>
15598 <tr class="row-odd"><td>3</td>
15599 <td>DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
15600 <td>Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK</td>
15601 </tr>
15602 <tr class="row-even"><td>4</td>
15603 <td>DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
15604 <td>Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK</td>
15605 </tr>
15606 <tr class="row-odd"><td>5</td>
15607 <td>DEV_SERDES_16G3_CLK</td>
15608 <td>Input clock</td>
15609 </tr>
15610 <tr class="row-even"><td>6</td>
15611 <td>DEV_SERDES_16G3_IP2_LN1_TXCLK</td>
15612 <td>Input clock</td>
15613 </tr>
15614 <tr class="row-odd"><td>7</td>
15615 <td>DEV_SERDES_16G3_IP3_LN1_TXCLK</td>
15616 <td>Input clock</td>
15617 </tr>
15618 <tr class="row-even"><td>8</td>
15619 <td>DEV_SERDES_16G3_IP2_LN0_TXCLK</td>
15620 <td>Input clock</td>
15621 </tr>
15622 <tr class="row-odd"><td>9</td>
15623 <td>DEV_SERDES_16G3_CORE_REF_CLK</td>
15624 <td>Input muxed clock</td>
15625 </tr>
15626 <tr class="row-even"><td>10</td>
15627 <td>DEV_SERDES_16G3_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15628 <td>Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK</td>
15629 </tr>
15630 <tr class="row-odd"><td>11</td>
15631 <td>DEV_SERDES_16G3_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15632 <td>Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK</td>
15633 </tr>
15634 <tr class="row-even"><td>12</td>
15635 <td>DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
15636 <td>Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK</td>
15637 </tr>
15638 <tr class="row-odd"><td>13</td>
15639 <td>DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
15640 <td>Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK</td>
15641 </tr>
15642 <tr class="row-even"><td>14</td>
15643 <td>DEV_SERDES_16G3_IP2_LN0_TXFCLK</td>
15644 <td>Output clock</td>
15645 </tr>
15646 <tr class="row-odd"><td>15</td>
15647 <td>DEV_SERDES_16G3_IP3_LN1_TXMCLK</td>
15648 <td>Output clock</td>
15649 </tr>
15650 <tr class="row-even"><td>16</td>
15651 <td>DEV_SERDES_16G3_IP3_LN1_TXFCLK</td>
15652 <td>Output clock</td>
15653 </tr>
15654 <tr class="row-odd"><td>17</td>
15655 <td>DEV_SERDES_16G3_IP2_LN1_REFCLK</td>
15656 <td>Output clock</td>
15657 </tr>
15658 <tr class="row-even"><td>18</td>
15659 <td>DEV_SERDES_16G3_IP2_LN1_TXFCLK</td>
15660 <td>Output clock</td>
15661 </tr>
15662 <tr class="row-odd"><td>20</td>
15663 <td>DEV_SERDES_16G3_IP3_LN1_RXFCLK</td>
15664 <td>Output clock</td>
15665 </tr>
15666 <tr class="row-even"><td>21</td>
15667 <td>DEV_SERDES_16G3_IP3_LN1_RXCLK</td>
15668 <td>Output clock</td>
15669 </tr>
15670 <tr class="row-odd"><td>22</td>
15671 <td>DEV_SERDES_16G3_IP3_LN1_REFCLK</td>
15672 <td>Output clock</td>
15673 </tr>
15674 <tr class="row-even"><td>23</td>
15675 <td>DEV_SERDES_16G3_IP2_LN1_RXCLK</td>
15676 <td>Output clock</td>
15677 </tr>
15678 <tr class="row-odd"><td>24</td>
15679 <td>DEV_SERDES_16G3_IP2_LN0_RXFCLK</td>
15680 <td>Output clock</td>
15681 </tr>
15682 <tr class="row-even"><td>25</td>
15683 <td>DEV_SERDES_16G3_REF_OUT_CLK</td>
15684 <td>Output clock</td>
15685 </tr>
15686 <tr class="row-odd"><td>26</td>
15687 <td>DEV_SERDES_16G3_REF1_OUT_CLK</td>
15688 <td>Output clock</td>
15689 </tr>
15690 <tr class="row-even"><td>27</td>
15691 <td>DEV_SERDES_16G3_IP2_LN1_RXFCLK</td>
15692 <td>Output clock</td>
15693 </tr>
15694 <tr class="row-odd"><td>28</td>
15695 <td>DEV_SERDES_16G3_IP2_LN1_TXMCLK</td>
15696 <td>Output clock</td>
15697 </tr>
15698 <tr class="row-even"><td>29</td>
15699 <td>DEV_SERDES_16G3_IP2_LN0_REFCLK</td>
15700 <td>Output clock</td>
15701 </tr>
15702 <tr class="row-odd"><td>30</td>
15703 <td>DEV_SERDES_16G3_IP2_LN0_TXMCLK</td>
15704 <td>Output clock</td>
15705 </tr>
15706 <tr class="row-even"><td>31</td>
15707 <td>DEV_SERDES_16G3_IP2_LN0_RXCLK</td>
15708 <td>Output clock</td>
15709 </tr>
15710 <tr class="row-odd"><td>40</td>
15711 <td>DEV_SERDES_16G3_CMN_REFCLK1_M</td>
15712 <td>Input clock</td>
15713 </tr>
15714 <tr class="row-even"><td>51</td>
15715 <td>DEV_SERDES_16G3_CMN_REFCLK1_P</td>
15716 <td>Input clock</td>
15717 </tr>
15718 </tbody>
15719 </table>
15720 </div>
15721 <div class="section" id="clocks-for-stm0-device">
15722 <span id="soc-doc-j721e-public-clks-stm0"></span><h3>Clocks for STM0 Device<a class="headerlink" href="#clocks-for-stm0-device" title="Permalink to this headline">¶</a></h3>
15723 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_STM0</span></a> (ID = 29)</p>
15724 <p>Following is a mapping of Clocks IDs to function:</p>
15725 <table border="1" class="docutils">
15726 <colgroup>
15727 <col width="27%" />
15728 <col width="44%" />
15729 <col width="29%" />
15730 </colgroup>
15731 <thead valign="bottom">
15732 <tr class="row-odd"><th class="head">Clock ID</th>
15733 <th class="head">Name</th>
15734 <th class="head">Function</th>
15735 </tr>
15736 </thead>
15737 <tbody valign="top">
15738 <tr class="row-even"><td>0</td>
15739 <td>DEV_STM0_VBUSP_CLK</td>
15740 <td>Input clock</td>
15741 </tr>
15742 <tr class="row-odd"><td>1</td>
15743 <td>DEV_STM0_CORE_CLK</td>
15744 <td>Input clock</td>
15745 </tr>
15746 <tr class="row-even"><td>2</td>
15747 <td>DEV_STM0_ATB_CLK</td>
15748 <td>Input clock</td>
15749 </tr>
15750 </tbody>
15751 </table>
15752 </div>
15753 <div class="section" id="clocks-for-timer0-device">
15754 <span id="soc-doc-j721e-public-clks-timer0"></span><h3>Clocks for TIMER0 Device<a class="headerlink" href="#clocks-for-timer0-device" title="Permalink to this headline">¶</a></h3>
15755 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER0</span></a> (ID = 49)</p>
15756 <p>Following is a mapping of Clocks IDs to function:</p>
15757 <table border="1" class="docutils">
15758 <colgroup>
15759 <col width="8%" />
15760 <col width="53%" />
15761 <col width="39%" />
15762 </colgroup>
15763 <thead valign="bottom">
15764 <tr class="row-odd"><th class="head">Clock ID</th>
15765 <th class="head">Name</th>
15766 <th class="head">Function</th>
15767 </tr>
15768 </thead>
15769 <tbody valign="top">
15770 <tr class="row-even"><td>0</td>
15771 <td>DEV_TIMER0_TIMER_HCLK_CLK</td>
15772 <td>Input clock</td>
15773 </tr>
15774 <tr class="row-odd"><td>1</td>
15775 <td>DEV_TIMER0_TIMER_TCLK_CLK</td>
15776 <td>Input muxed clock</td>
15777 </tr>
15778 <tr class="row-even"><td>2</td>
15779 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15780 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15781 </tr>
15782 <tr class="row-odd"><td>3</td>
15783 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15784 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15785 </tr>
15786 <tr class="row-even"><td>4</td>
15787 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK</td>
15788 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15789 </tr>
15790 <tr class="row-odd"><td>5</td>
15791 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
15792 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15793 </tr>
15794 <tr class="row-even"><td>6</td>
15795 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
15796 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15797 </tr>
15798 <tr class="row-odd"><td>7</td>
15799 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
15800 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15801 </tr>
15802 <tr class="row-even"><td>8</td>
15803 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
15804 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15805 </tr>
15806 <tr class="row-odd"><td>9</td>
15807 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
15808 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15809 </tr>
15810 <tr class="row-even"><td>10</td>
15811 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
15812 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15813 </tr>
15814 <tr class="row-odd"><td>11</td>
15815 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
15816 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15817 </tr>
15818 <tr class="row-even"><td>12</td>
15819 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
15820 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15821 </tr>
15822 <tr class="row-odd"><td>13</td>
15823 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
15824 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15825 </tr>
15826 <tr class="row-even"><td>14</td>
15827 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2</td>
15828 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15829 </tr>
15830 <tr class="row-odd"><td>15</td>
15831 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3</td>
15832 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15833 </tr>
15834 <tr class="row-even"><td>16</td>
15835 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0</td>
15836 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15837 </tr>
15838 <tr class="row-odd"><td>17</td>
15839 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
15840 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15841 </tr>
15842 <tr class="row-even"><td>18</td>
15843 <td>DEV_TIMER0_TIMER_PWM</td>
15844 <td>Output clock</td>
15845 </tr>
15846 </tbody>
15847 </table>
15848 </div>
15849 <div class="section" id="clocks-for-timer1-device">
15850 <span id="soc-doc-j721e-public-clks-timer1"></span><h3>Clocks for TIMER1 Device<a class="headerlink" href="#clocks-for-timer1-device" title="Permalink to this headline">¶</a></h3>
15851 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER1</span></a> (ID = 50)</p>
15852 <p>Following is a mapping of Clocks IDs to function:</p>
15853 <table border="1" class="docutils">
15854 <colgroup>
15855 <col width="9%" />
15856 <col width="49%" />
15857 <col width="42%" />
15858 </colgroup>
15859 <thead valign="bottom">
15860 <tr class="row-odd"><th class="head">Clock ID</th>
15861 <th class="head">Name</th>
15862 <th class="head">Function</th>
15863 </tr>
15864 </thead>
15865 <tbody valign="top">
15866 <tr class="row-even"><td>0</td>
15867 <td>DEV_TIMER1_TIMER_HCLK_CLK</td>
15868 <td>Input clock</td>
15869 </tr>
15870 <tr class="row-odd"><td>1</td>
15871 <td>DEV_TIMER1_TIMER_TCLK_CLK</td>
15872 <td>Input muxed clock</td>
15873 </tr>
15874 <tr class="row-even"><td>2</td>
15875 <td>DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1</td>
15876 <td>Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK</td>
15877 </tr>
15878 <tr class="row-odd"><td>3</td>
15879 <td>DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM</td>
15880 <td>Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK</td>
15881 </tr>
15882 </tbody>
15883 </table>
15884 </div>
15885 <div class="section" id="clocks-for-timer10-device">
15886 <span id="soc-doc-j721e-public-clks-timer10"></span><h3>Clocks for TIMER10 Device<a class="headerlink" href="#clocks-for-timer10-device" title="Permalink to this headline">¶</a></h3>
15887 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER10</span></a> (ID = 60)</p>
15888 <p>Following is a mapping of Clocks IDs to function:</p>
15889 <table border="1" class="docutils">
15890 <colgroup>
15891 <col width="8%" />
15892 <col width="53%" />
15893 <col width="39%" />
15894 </colgroup>
15895 <thead valign="bottom">
15896 <tr class="row-odd"><th class="head">Clock ID</th>
15897 <th class="head">Name</th>
15898 <th class="head">Function</th>
15899 </tr>
15900 </thead>
15901 <tbody valign="top">
15902 <tr class="row-even"><td>0</td>
15903 <td>DEV_TIMER10_TIMER_HCLK_CLK</td>
15904 <td>Input clock</td>
15905 </tr>
15906 <tr class="row-odd"><td>1</td>
15907 <td>DEV_TIMER10_TIMER_TCLK_CLK</td>
15908 <td>Input muxed clock</td>
15909 </tr>
15910 <tr class="row-even"><td>2</td>
15911 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15912 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15913 </tr>
15914 <tr class="row-odd"><td>3</td>
15915 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15916 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15917 </tr>
15918 <tr class="row-even"><td>4</td>
15919 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK</td>
15920 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15921 </tr>
15922 <tr class="row-odd"><td>5</td>
15923 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
15924 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15925 </tr>
15926 <tr class="row-even"><td>6</td>
15927 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
15928 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15929 </tr>
15930 <tr class="row-odd"><td>7</td>
15931 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
15932 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15933 </tr>
15934 <tr class="row-even"><td>8</td>
15935 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
15936 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15937 </tr>
15938 <tr class="row-odd"><td>9</td>
15939 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
15940 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15941 </tr>
15942 <tr class="row-even"><td>10</td>
15943 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
15944 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15945 </tr>
15946 <tr class="row-odd"><td>11</td>
15947 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
15948 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15949 </tr>
15950 <tr class="row-even"><td>12</td>
15951 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
15952 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15953 </tr>
15954 <tr class="row-odd"><td>13</td>
15955 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
15956 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15957 </tr>
15958 <tr class="row-even"><td>14</td>
15959 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2</td>
15960 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15961 </tr>
15962 <tr class="row-odd"><td>15</td>
15963 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3</td>
15964 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15965 </tr>
15966 <tr class="row-even"><td>16</td>
15967 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0</td>
15968 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15969 </tr>
15970 <tr class="row-odd"><td>17</td>
15971 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
15972 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15973 </tr>
15974 <tr class="row-even"><td>18</td>
15975 <td>DEV_TIMER10_TIMER_PWM</td>
15976 <td>Output clock</td>
15977 </tr>
15978 </tbody>
15979 </table>
15980 </div>
15981 <div class="section" id="clocks-for-timer11-device">
15982 <span id="soc-doc-j721e-public-clks-timer11"></span><h3>Clocks for TIMER11 Device<a class="headerlink" href="#clocks-for-timer11-device" title="Permalink to this headline">¶</a></h3>
15983 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER11</span></a> (ID = 62)</p>
15984 <p>Following is a mapping of Clocks IDs to function:</p>
15985 <table border="1" class="docutils">
15986 <colgroup>
15987 <col width="9%" />
15988 <col width="50%" />
15989 <col width="42%" />
15990 </colgroup>
15991 <thead valign="bottom">
15992 <tr class="row-odd"><th class="head">Clock ID</th>
15993 <th class="head">Name</th>
15994 <th class="head">Function</th>
15995 </tr>
15996 </thead>
15997 <tbody valign="top">
15998 <tr class="row-even"><td>0</td>
15999 <td>DEV_TIMER11_TIMER_HCLK_CLK</td>
16000 <td>Input clock</td>
16001 </tr>
16002 <tr class="row-odd"><td>1</td>
16003 <td>DEV_TIMER11_TIMER_TCLK_CLK</td>
16004 <td>Input muxed clock</td>
16005 </tr>
16006 <tr class="row-even"><td>2</td>
16007 <td>DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11</td>
16008 <td>Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK</td>
16009 </tr>
16010 <tr class="row-odd"><td>3</td>
16011 <td>DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM</td>
16012 <td>Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK</td>
16013 </tr>
16014 </tbody>
16015 </table>
16016 </div>
16017 <div class="section" id="clocks-for-timer12-device">
16018 <span id="soc-doc-j721e-public-clks-timer12"></span><h3>Clocks for TIMER12 Device<a class="headerlink" href="#clocks-for-timer12-device" title="Permalink to this headline">¶</a></h3>
16019 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER12</span></a> (ID = 63)</p>
16020 <p>Following is a mapping of Clocks IDs to function:</p>
16021 <table border="1" class="docutils">
16022 <colgroup>
16023 <col width="8%" />
16024 <col width="53%" />
16025 <col width="39%" />
16026 </colgroup>
16027 <thead valign="bottom">
16028 <tr class="row-odd"><th class="head">Clock ID</th>
16029 <th class="head">Name</th>
16030 <th class="head">Function</th>
16031 </tr>
16032 </thead>
16033 <tbody valign="top">
16034 <tr class="row-even"><td>0</td>
16035 <td>DEV_TIMER12_TIMER_HCLK_CLK</td>
16036 <td>Input clock</td>
16037 </tr>
16038 <tr class="row-odd"><td>1</td>
16039 <td>DEV_TIMER12_TIMER_TCLK_CLK</td>
16040 <td>Input muxed clock</td>
16041 </tr>
16042 <tr class="row-even"><td>2</td>
16043 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16044 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16045 </tr>
16046 <tr class="row-odd"><td>3</td>
16047 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16048 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16049 </tr>
16050 <tr class="row-even"><td>4</td>
16051 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK</td>
16052 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16053 </tr>
16054 <tr class="row-odd"><td>5</td>
16055 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
16056 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16057 </tr>
16058 <tr class="row-even"><td>6</td>
16059 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
16060 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16061 </tr>
16062 <tr class="row-odd"><td>7</td>
16063 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
16064 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16065 </tr>
16066 <tr class="row-even"><td>8</td>
16067 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
16068 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16069 </tr>
16070 <tr class="row-odd"><td>9</td>
16071 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
16072 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16073 </tr>
16074 <tr class="row-even"><td>10</td>
16075 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
16076 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16077 </tr>
16078 <tr class="row-odd"><td>11</td>
16079 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
16080 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16081 </tr>
16082 <tr class="row-even"><td>12</td>
16083 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
16084 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16085 </tr>
16086 <tr class="row-odd"><td>13</td>
16087 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
16088 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16089 </tr>
16090 <tr class="row-even"><td>14</td>
16091 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2</td>
16092 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16093 </tr>
16094 <tr class="row-odd"><td>15</td>
16095 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3</td>
16096 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16097 </tr>
16098 <tr class="row-even"><td>16</td>
16099 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0</td>
16100 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16101 </tr>
16102 <tr class="row-odd"><td>17</td>
16103 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
16104 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
16105 </tr>
16106 <tr class="row-even"><td>18</td>
16107 <td>DEV_TIMER12_TIMER_PWM</td>
16108 <td>Output clock</td>
16109 </tr>
16110 </tbody>
16111 </table>
16112 </div>
16113 <div class="section" id="clocks-for-timer13-device">
16114 <span id="soc-doc-j721e-public-clks-timer13"></span><h3>Clocks for TIMER13 Device<a class="headerlink" href="#clocks-for-timer13-device" title="Permalink to this headline">¶</a></h3>
16115 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER13</span></a> (ID = 64)</p>
16116 <p>Following is a mapping of Clocks IDs to function:</p>
16117 <table border="1" class="docutils">
16118 <colgroup>
16119 <col width="9%" />
16120 <col width="50%" />
16121 <col width="42%" />
16122 </colgroup>
16123 <thead valign="bottom">
16124 <tr class="row-odd"><th class="head">Clock ID</th>
16125 <th class="head">Name</th>
16126 <th class="head">Function</th>
16127 </tr>
16128 </thead>
16129 <tbody valign="top">
16130 <tr class="row-even"><td>0</td>
16131 <td>DEV_TIMER13_TIMER_HCLK_CLK</td>
16132 <td>Input clock</td>
16133 </tr>
16134 <tr class="row-odd"><td>1</td>
16135 <td>DEV_TIMER13_TIMER_TCLK_CLK</td>
16136 <td>Input muxed clock</td>
16137 </tr>
16138 <tr class="row-even"><td>2</td>
16139 <td>DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13</td>
16140 <td>Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK</td>
16141 </tr>
16142 <tr class="row-odd"><td>3</td>
16143 <td>DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM</td>
16144 <td>Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK</td>
16145 </tr>
16146 </tbody>
16147 </table>
16148 </div>
16149 <div class="section" id="clocks-for-timer14-device">
16150 <span id="soc-doc-j721e-public-clks-timer14"></span><h3>Clocks for TIMER14 Device<a class="headerlink" href="#clocks-for-timer14-device" title="Permalink to this headline">¶</a></h3>
16151 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER14</span></a> (ID = 65)</p>
16152 <p>Following is a mapping of Clocks IDs to function:</p>
16153 <table border="1" class="docutils">
16154 <colgroup>
16155 <col width="8%" />
16156 <col width="53%" />
16157 <col width="39%" />
16158 </colgroup>
16159 <thead valign="bottom">
16160 <tr class="row-odd"><th class="head">Clock ID</th>
16161 <th class="head">Name</th>
16162 <th class="head">Function</th>
16163 </tr>
16164 </thead>
16165 <tbody valign="top">
16166 <tr class="row-even"><td>0</td>
16167 <td>DEV_TIMER14_TIMER_HCLK_CLK</td>
16168 <td>Input clock</td>
16169 </tr>
16170 <tr class="row-odd"><td>1</td>
16171 <td>DEV_TIMER14_TIMER_TCLK_CLK</td>
16172 <td>Input muxed clock</td>
16173 </tr>
16174 <tr class="row-even"><td>2</td>
16175 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16176 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16177 </tr>
16178 <tr class="row-odd"><td>3</td>
16179 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16180 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16181 </tr>
16182 <tr class="row-even"><td>4</td>
16183 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK</td>
16184 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16185 </tr>
16186 <tr class="row-odd"><td>5</td>
16187 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
16188 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16189 </tr>
16190 <tr class="row-even"><td>6</td>
16191 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
16192 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16193 </tr>
16194 <tr class="row-odd"><td>7</td>
16195 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
16196 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16197 </tr>
16198 <tr class="row-even"><td>8</td>
16199 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
16200 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16201 </tr>
16202 <tr class="row-odd"><td>9</td>
16203 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
16204 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16205 </tr>
16206 <tr class="row-even"><td>10</td>
16207 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
16208 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16209 </tr>
16210 <tr class="row-odd"><td>11</td>
16211 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
16212 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16213 </tr>
16214 <tr class="row-even"><td>12</td>
16215 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
16216 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16217 </tr>
16218 <tr class="row-odd"><td>13</td>
16219 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
16220 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16221 </tr>
16222 <tr class="row-even"><td>14</td>
16223 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2</td>
16224 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16225 </tr>
16226 <tr class="row-odd"><td>15</td>
16227 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3</td>
16228 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16229 </tr>
16230 <tr class="row-even"><td>16</td>
16231 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0</td>
16232 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16233 </tr>
16234 <tr class="row-odd"><td>17</td>
16235 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
16236 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
16237 </tr>
16238 <tr class="row-even"><td>18</td>
16239 <td>DEV_TIMER14_TIMER_PWM</td>
16240 <td>Output clock</td>
16241 </tr>
16242 </tbody>
16243 </table>
16244 </div>
16245 <div class="section" id="clocks-for-timer15-device">
16246 <span id="soc-doc-j721e-public-clks-timer15"></span><h3>Clocks for TIMER15 Device<a class="headerlink" href="#clocks-for-timer15-device" title="Permalink to this headline">¶</a></h3>
16247 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER15</span></a> (ID = 66)</p>
16248 <p>Following is a mapping of Clocks IDs to function:</p>
16249 <table border="1" class="docutils">
16250 <colgroup>
16251 <col width="9%" />
16252 <col width="50%" />
16253 <col width="42%" />
16254 </colgroup>
16255 <thead valign="bottom">
16256 <tr class="row-odd"><th class="head">Clock ID</th>
16257 <th class="head">Name</th>
16258 <th class="head">Function</th>
16259 </tr>
16260 </thead>
16261 <tbody valign="top">
16262 <tr class="row-even"><td>0</td>
16263 <td>DEV_TIMER15_TIMER_HCLK_CLK</td>
16264 <td>Input clock</td>
16265 </tr>
16266 <tr class="row-odd"><td>1</td>
16267 <td>DEV_TIMER15_TIMER_TCLK_CLK</td>
16268 <td>Input muxed clock</td>
16269 </tr>
16270 <tr class="row-even"><td>2</td>
16271 <td>DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15</td>
16272 <td>Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK</td>
16273 </tr>
16274 <tr class="row-odd"><td>3</td>
16275 <td>DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM</td>
16276 <td>Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK</td>
16277 </tr>
16278 </tbody>
16279 </table>
16280 </div>
16281 <div class="section" id="clocks-for-timer16-device">
16282 <span id="soc-doc-j721e-public-clks-timer16"></span><h3>Clocks for TIMER16 Device<a class="headerlink" href="#clocks-for-timer16-device" title="Permalink to this headline">¶</a></h3>
16283 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER16</span></a> (ID = 67)</p>
16284 <p>Following is a mapping of Clocks IDs to function:</p>
16285 <table border="1" class="docutils">
16286 <colgroup>
16287 <col width="8%" />
16288 <col width="53%" />
16289 <col width="39%" />
16290 </colgroup>
16291 <thead valign="bottom">
16292 <tr class="row-odd"><th class="head">Clock ID</th>
16293 <th class="head">Name</th>
16294 <th class="head">Function</th>
16295 </tr>
16296 </thead>
16297 <tbody valign="top">
16298 <tr class="row-even"><td>0</td>
16299 <td>DEV_TIMER16_TIMER_HCLK_CLK</td>
16300 <td>Input clock</td>
16301 </tr>
16302 <tr class="row-odd"><td>1</td>
16303 <td>DEV_TIMER16_TIMER_TCLK_CLK</td>
16304 <td>Input muxed clock</td>
16305 </tr>
16306 <tr class="row-even"><td>2</td>
16307 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16308 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16309 </tr>
16310 <tr class="row-odd"><td>3</td>
16311 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16312 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16313 </tr>
16314 <tr class="row-even"><td>4</td>
16315 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK</td>
16316 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16317 </tr>
16318 <tr class="row-odd"><td>5</td>
16319 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
16320 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16321 </tr>
16322 <tr class="row-even"><td>6</td>
16323 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
16324 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16325 </tr>
16326 <tr class="row-odd"><td>7</td>
16327 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
16328 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16329 </tr>
16330 <tr class="row-even"><td>8</td>
16331 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
16332 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16333 </tr>
16334 <tr class="row-odd"><td>9</td>
16335 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
16336 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16337 </tr>
16338 <tr class="row-even"><td>10</td>
16339 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
16340 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16341 </tr>
16342 <tr class="row-odd"><td>11</td>
16343 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
16344 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16345 </tr>
16346 <tr class="row-even"><td>12</td>
16347 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
16348 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16349 </tr>
16350 <tr class="row-odd"><td>13</td>
16351 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
16352 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16353 </tr>
16354 <tr class="row-even"><td>14</td>
16355 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2</td>
16356 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16357 </tr>
16358 <tr class="row-odd"><td>15</td>
16359 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3</td>
16360 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16361 </tr>
16362 <tr class="row-even"><td>16</td>
16363 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0</td>
16364 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16365 </tr>
16366 <tr class="row-odd"><td>17</td>
16367 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
16368 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
16369 </tr>
16370 <tr class="row-even"><td>18</td>
16371 <td>DEV_TIMER16_TIMER_PWM</td>
16372 <td>Output clock</td>
16373 </tr>
16374 </tbody>
16375 </table>
16376 </div>
16377 <div class="section" id="clocks-for-timer17-device">
16378 <span id="soc-doc-j721e-public-clks-timer17"></span><h3>Clocks for TIMER17 Device<a class="headerlink" href="#clocks-for-timer17-device" title="Permalink to this headline">¶</a></h3>
16379 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER17</span></a> (ID = 68)</p>
16380 <p>Following is a mapping of Clocks IDs to function:</p>
16381 <table border="1" class="docutils">
16382 <colgroup>
16383 <col width="9%" />
16384 <col width="50%" />
16385 <col width="42%" />
16386 </colgroup>
16387 <thead valign="bottom">
16388 <tr class="row-odd"><th class="head">Clock ID</th>
16389 <th class="head">Name</th>
16390 <th class="head">Function</th>
16391 </tr>
16392 </thead>
16393 <tbody valign="top">
16394 <tr class="row-even"><td>0</td>
16395 <td>DEV_TIMER17_TIMER_HCLK_CLK</td>
16396 <td>Input clock</td>
16397 </tr>
16398 <tr class="row-odd"><td>1</td>
16399 <td>DEV_TIMER17_TIMER_TCLK_CLK</td>
16400 <td>Input muxed clock</td>
16401 </tr>
16402 <tr class="row-even"><td>2</td>
16403 <td>DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17</td>
16404 <td>Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK</td>
16405 </tr>
16406 <tr class="row-odd"><td>3</td>
16407 <td>DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM</td>
16408 <td>Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK</td>
16409 </tr>
16410 </tbody>
16411 </table>
16412 </div>
16413 <div class="section" id="clocks-for-timer18-device">
16414 <span id="soc-doc-j721e-public-clks-timer18"></span><h3>Clocks for TIMER18 Device<a class="headerlink" href="#clocks-for-timer18-device" title="Permalink to this headline">¶</a></h3>
16415 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER18</span></a> (ID = 69)</p>
16416 <p>Following is a mapping of Clocks IDs to function:</p>
16417 <table border="1" class="docutils">
16418 <colgroup>
16419 <col width="8%" />
16420 <col width="53%" />
16421 <col width="39%" />
16422 </colgroup>
16423 <thead valign="bottom">
16424 <tr class="row-odd"><th class="head">Clock ID</th>
16425 <th class="head">Name</th>
16426 <th class="head">Function</th>
16427 </tr>
16428 </thead>
16429 <tbody valign="top">
16430 <tr class="row-even"><td>0</td>
16431 <td>DEV_TIMER18_TIMER_HCLK_CLK</td>
16432 <td>Input clock</td>
16433 </tr>
16434 <tr class="row-odd"><td>1</td>
16435 <td>DEV_TIMER18_TIMER_TCLK_CLK</td>
16436 <td>Input muxed clock</td>
16437 </tr>
16438 <tr class="row-even"><td>2</td>
16439 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16440 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16441 </tr>
16442 <tr class="row-odd"><td>3</td>
16443 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16444 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16445 </tr>
16446 <tr class="row-even"><td>4</td>
16447 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK</td>
16448 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16449 </tr>
16450 <tr class="row-odd"><td>5</td>
16451 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
16452 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16453 </tr>
16454 <tr class="row-even"><td>6</td>
16455 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
16456 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16457 </tr>
16458 <tr class="row-odd"><td>7</td>
16459 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
16460 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16461 </tr>
16462 <tr class="row-even"><td>8</td>
16463 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
16464 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16465 </tr>
16466 <tr class="row-odd"><td>9</td>
16467 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
16468 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16469 </tr>
16470 <tr class="row-even"><td>10</td>
16471 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
16472 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16473 </tr>
16474 <tr class="row-odd"><td>11</td>
16475 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
16476 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16477 </tr>
16478 <tr class="row-even"><td>12</td>
16479 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
16480 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16481 </tr>
16482 <tr class="row-odd"><td>13</td>
16483 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
16484 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16485 </tr>
16486 <tr class="row-even"><td>14</td>
16487 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2</td>
16488 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16489 </tr>
16490 <tr class="row-odd"><td>15</td>
16491 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3</td>
16492 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16493 </tr>
16494 <tr class="row-even"><td>16</td>
16495 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0</td>
16496 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16497 </tr>
16498 <tr class="row-odd"><td>17</td>
16499 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
16500 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
16501 </tr>
16502 <tr class="row-even"><td>18</td>
16503 <td>DEV_TIMER18_TIMER_PWM</td>
16504 <td>Output clock</td>
16505 </tr>
16506 </tbody>
16507 </table>
16508 </div>
16509 <div class="section" id="clocks-for-timer19-device">
16510 <span id="soc-doc-j721e-public-clks-timer19"></span><h3>Clocks for TIMER19 Device<a class="headerlink" href="#clocks-for-timer19-device" title="Permalink to this headline">¶</a></h3>
16511 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER19</span></a> (ID = 70)</p>
16512 <p>Following is a mapping of Clocks IDs to function:</p>
16513 <table border="1" class="docutils">
16514 <colgroup>
16515 <col width="9%" />
16516 <col width="50%" />
16517 <col width="42%" />
16518 </colgroup>
16519 <thead valign="bottom">
16520 <tr class="row-odd"><th class="head">Clock ID</th>
16521 <th class="head">Name</th>
16522 <th class="head">Function</th>
16523 </tr>
16524 </thead>
16525 <tbody valign="top">
16526 <tr class="row-even"><td>0</td>
16527 <td>DEV_TIMER19_TIMER_HCLK_CLK</td>
16528 <td>Input clock</td>
16529 </tr>
16530 <tr class="row-odd"><td>1</td>
16531 <td>DEV_TIMER19_TIMER_TCLK_CLK</td>
16532 <td>Input muxed clock</td>
16533 </tr>
16534 <tr class="row-even"><td>2</td>
16535 <td>DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19</td>
16536 <td>Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK</td>
16537 </tr>
16538 <tr class="row-odd"><td>3</td>
16539 <td>DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM</td>
16540 <td>Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK</td>
16541 </tr>
16542 </tbody>
16543 </table>
16544 </div>
16545 <div class="section" id="clocks-for-timer2-device">
16546 <span id="soc-doc-j721e-public-clks-timer2"></span><h3>Clocks for TIMER2 Device<a class="headerlink" href="#clocks-for-timer2-device" title="Permalink to this headline">¶</a></h3>
16547 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER2</span></a> (ID = 51)</p>
16548 <p>Following is a mapping of Clocks IDs to function:</p>
16549 <table border="1" class="docutils">
16550 <colgroup>
16551 <col width="8%" />
16552 <col width="53%" />
16553 <col width="39%" />
16554 </colgroup>
16555 <thead valign="bottom">
16556 <tr class="row-odd"><th class="head">Clock ID</th>
16557 <th class="head">Name</th>
16558 <th class="head">Function</th>
16559 </tr>
16560 </thead>
16561 <tbody valign="top">
16562 <tr class="row-even"><td>0</td>
16563 <td>DEV_TIMER2_TIMER_HCLK_CLK</td>
16564 <td>Input clock</td>
16565 </tr>
16566 <tr class="row-odd"><td>1</td>
16567 <td>DEV_TIMER2_TIMER_TCLK_CLK</td>
16568 <td>Input muxed clock</td>
16569 </tr>
16570 <tr class="row-even"><td>2</td>
16571 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16572 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16573 </tr>
16574 <tr class="row-odd"><td>3</td>
16575 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16576 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16577 </tr>
16578 <tr class="row-even"><td>4</td>
16579 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK</td>
16580 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16581 </tr>
16582 <tr class="row-odd"><td>5</td>
16583 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
16584 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16585 </tr>
16586 <tr class="row-even"><td>6</td>
16587 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
16588 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16589 </tr>
16590 <tr class="row-odd"><td>7</td>
16591 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
16592 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16593 </tr>
16594 <tr class="row-even"><td>8</td>
16595 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
16596 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16597 </tr>
16598 <tr class="row-odd"><td>9</td>
16599 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
16600 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16601 </tr>
16602 <tr class="row-even"><td>10</td>
16603 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
16604 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16605 </tr>
16606 <tr class="row-odd"><td>11</td>
16607 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
16608 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16609 </tr>
16610 <tr class="row-even"><td>12</td>
16611 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
16612 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16613 </tr>
16614 <tr class="row-odd"><td>13</td>
16615 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
16616 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16617 </tr>
16618 <tr class="row-even"><td>14</td>
16619 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2</td>
16620 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16621 </tr>
16622 <tr class="row-odd"><td>15</td>
16623 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3</td>
16624 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16625 </tr>
16626 <tr class="row-even"><td>16</td>
16627 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0</td>
16628 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16629 </tr>
16630 <tr class="row-odd"><td>17</td>
16631 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
16632 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
16633 </tr>
16634 <tr class="row-even"><td>18</td>
16635 <td>DEV_TIMER2_TIMER_PWM</td>
16636 <td>Output clock</td>
16637 </tr>
16638 </tbody>
16639 </table>
16640 </div>
16641 <div class="section" id="clocks-for-timer3-device">
16642 <span id="soc-doc-j721e-public-clks-timer3"></span><h3>Clocks for TIMER3 Device<a class="headerlink" href="#clocks-for-timer3-device" title="Permalink to this headline">¶</a></h3>
16643 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER3</span></a> (ID = 52)</p>
16644 <p>Following is a mapping of Clocks IDs to function:</p>
16645 <table border="1" class="docutils">
16646 <colgroup>
16647 <col width="9%" />
16648 <col width="49%" />
16649 <col width="42%" />
16650 </colgroup>
16651 <thead valign="bottom">
16652 <tr class="row-odd"><th class="head">Clock ID</th>
16653 <th class="head">Name</th>
16654 <th class="head">Function</th>
16655 </tr>
16656 </thead>
16657 <tbody valign="top">
16658 <tr class="row-even"><td>0</td>
16659 <td>DEV_TIMER3_TIMER_HCLK_CLK</td>
16660 <td>Input clock</td>
16661 </tr>
16662 <tr class="row-odd"><td>1</td>
16663 <td>DEV_TIMER3_TIMER_TCLK_CLK</td>
16664 <td>Input muxed clock</td>
16665 </tr>
16666 <tr class="row-even"><td>2</td>
16667 <td>DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3</td>
16668 <td>Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK</td>
16669 </tr>
16670 <tr class="row-odd"><td>3</td>
16671 <td>DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM</td>
16672 <td>Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK</td>
16673 </tr>
16674 </tbody>
16675 </table>
16676 </div>
16677 <div class="section" id="clocks-for-timer4-device">
16678 <span id="soc-doc-j721e-public-clks-timer4"></span><h3>Clocks for TIMER4 Device<a class="headerlink" href="#clocks-for-timer4-device" title="Permalink to this headline">¶</a></h3>
16679 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER4</span></a> (ID = 53)</p>
16680 <p>Following is a mapping of Clocks IDs to function:</p>
16681 <table border="1" class="docutils">
16682 <colgroup>
16683 <col width="8%" />
16684 <col width="53%" />
16685 <col width="39%" />
16686 </colgroup>
16687 <thead valign="bottom">
16688 <tr class="row-odd"><th class="head">Clock ID</th>
16689 <th class="head">Name</th>
16690 <th class="head">Function</th>
16691 </tr>
16692 </thead>
16693 <tbody valign="top">
16694 <tr class="row-even"><td>0</td>
16695 <td>DEV_TIMER4_TIMER_HCLK_CLK</td>
16696 <td>Input clock</td>
16697 </tr>
16698 <tr class="row-odd"><td>1</td>
16699 <td>DEV_TIMER4_TIMER_TCLK_CLK</td>
16700 <td>Input muxed clock</td>
16701 </tr>
16702 <tr class="row-even"><td>2</td>
16703 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16704 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16705 </tr>
16706 <tr class="row-odd"><td>3</td>
16707 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16708 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16709 </tr>
16710 <tr class="row-even"><td>4</td>
16711 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK</td>
16712 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16713 </tr>
16714 <tr class="row-odd"><td>5</td>
16715 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
16716 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16717 </tr>
16718 <tr class="row-even"><td>6</td>
16719 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
16720 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16721 </tr>
16722 <tr class="row-odd"><td>7</td>
16723 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
16724 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16725 </tr>
16726 <tr class="row-even"><td>8</td>
16727 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
16728 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16729 </tr>
16730 <tr class="row-odd"><td>9</td>
16731 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
16732 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16733 </tr>
16734 <tr class="row-even"><td>10</td>
16735 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
16736 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16737 </tr>
16738 <tr class="row-odd"><td>11</td>
16739 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
16740 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16741 </tr>
16742 <tr class="row-even"><td>12</td>
16743 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
16744 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16745 </tr>
16746 <tr class="row-odd"><td>13</td>
16747 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
16748 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16749 </tr>
16750 <tr class="row-even"><td>14</td>
16751 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2</td>
16752 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16753 </tr>
16754 <tr class="row-odd"><td>15</td>
16755 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3</td>
16756 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16757 </tr>
16758 <tr class="row-even"><td>16</td>
16759 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0</td>
16760 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16761 </tr>
16762 <tr class="row-odd"><td>17</td>
16763 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
16764 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16765 </tr>
16766 <tr class="row-even"><td>18</td>
16767 <td>DEV_TIMER4_TIMER_PWM</td>
16768 <td>Output clock</td>
16769 </tr>
16770 </tbody>
16771 </table>
16772 </div>
16773 <div class="section" id="clocks-for-timer5-device">
16774 <span id="soc-doc-j721e-public-clks-timer5"></span><h3>Clocks for TIMER5 Device<a class="headerlink" href="#clocks-for-timer5-device" title="Permalink to this headline">¶</a></h3>
16775 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER5</span></a> (ID = 54)</p>
16776 <p>Following is a mapping of Clocks IDs to function:</p>
16777 <table border="1" class="docutils">
16778 <colgroup>
16779 <col width="9%" />
16780 <col width="49%" />
16781 <col width="42%" />
16782 </colgroup>
16783 <thead valign="bottom">
16784 <tr class="row-odd"><th class="head">Clock ID</th>
16785 <th class="head">Name</th>
16786 <th class="head">Function</th>
16787 </tr>
16788 </thead>
16789 <tbody valign="top">
16790 <tr class="row-even"><td>0</td>
16791 <td>DEV_TIMER5_TIMER_HCLK_CLK</td>
16792 <td>Input clock</td>
16793 </tr>
16794 <tr class="row-odd"><td>1</td>
16795 <td>DEV_TIMER5_TIMER_TCLK_CLK</td>
16796 <td>Input muxed clock</td>
16797 </tr>
16798 <tr class="row-even"><td>2</td>
16799 <td>DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5</td>
16800 <td>Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK</td>
16801 </tr>
16802 <tr class="row-odd"><td>3</td>
16803 <td>DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM</td>
16804 <td>Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK</td>
16805 </tr>
16806 </tbody>
16807 </table>
16808 </div>
16809 <div class="section" id="clocks-for-timer6-device">
16810 <span id="soc-doc-j721e-public-clks-timer6"></span><h3>Clocks for TIMER6 Device<a class="headerlink" href="#clocks-for-timer6-device" title="Permalink to this headline">¶</a></h3>
16811 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER6</span></a> (ID = 55)</p>
16812 <p>Following is a mapping of Clocks IDs to function:</p>
16813 <table border="1" class="docutils">
16814 <colgroup>
16815 <col width="8%" />
16816 <col width="53%" />
16817 <col width="39%" />
16818 </colgroup>
16819 <thead valign="bottom">
16820 <tr class="row-odd"><th class="head">Clock ID</th>
16821 <th class="head">Name</th>
16822 <th class="head">Function</th>
16823 </tr>
16824 </thead>
16825 <tbody valign="top">
16826 <tr class="row-even"><td>0</td>
16827 <td>DEV_TIMER6_TIMER_HCLK_CLK</td>
16828 <td>Input clock</td>
16829 </tr>
16830 <tr class="row-odd"><td>1</td>
16831 <td>DEV_TIMER6_TIMER_TCLK_CLK</td>
16832 <td>Input muxed clock</td>
16833 </tr>
16834 <tr class="row-even"><td>2</td>
16835 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16836 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16837 </tr>
16838 <tr class="row-odd"><td>3</td>
16839 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16840 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16841 </tr>
16842 <tr class="row-even"><td>4</td>
16843 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK</td>
16844 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16845 </tr>
16846 <tr class="row-odd"><td>5</td>
16847 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
16848 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16849 </tr>
16850 <tr class="row-even"><td>6</td>
16851 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
16852 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16853 </tr>
16854 <tr class="row-odd"><td>7</td>
16855 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
16856 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16857 </tr>
16858 <tr class="row-even"><td>8</td>
16859 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
16860 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16861 </tr>
16862 <tr class="row-odd"><td>9</td>
16863 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
16864 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16865 </tr>
16866 <tr class="row-even"><td>10</td>
16867 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
16868 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16869 </tr>
16870 <tr class="row-odd"><td>11</td>
16871 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
16872 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16873 </tr>
16874 <tr class="row-even"><td>12</td>
16875 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
16876 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16877 </tr>
16878 <tr class="row-odd"><td>13</td>
16879 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
16880 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16881 </tr>
16882 <tr class="row-even"><td>14</td>
16883 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2</td>
16884 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16885 </tr>
16886 <tr class="row-odd"><td>15</td>
16887 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3</td>
16888 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16889 </tr>
16890 <tr class="row-even"><td>16</td>
16891 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0</td>
16892 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16893 </tr>
16894 <tr class="row-odd"><td>17</td>
16895 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
16896 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16897 </tr>
16898 <tr class="row-even"><td>18</td>
16899 <td>DEV_TIMER6_TIMER_PWM</td>
16900 <td>Output clock</td>
16901 </tr>
16902 </tbody>
16903 </table>
16904 </div>
16905 <div class="section" id="clocks-for-timer7-device">
16906 <span id="soc-doc-j721e-public-clks-timer7"></span><h3>Clocks for TIMER7 Device<a class="headerlink" href="#clocks-for-timer7-device" title="Permalink to this headline">¶</a></h3>
16907 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER7</span></a> (ID = 57)</p>
16908 <p>Following is a mapping of Clocks IDs to function:</p>
16909 <table border="1" class="docutils">
16910 <colgroup>
16911 <col width="9%" />
16912 <col width="49%" />
16913 <col width="42%" />
16914 </colgroup>
16915 <thead valign="bottom">
16916 <tr class="row-odd"><th class="head">Clock ID</th>
16917 <th class="head">Name</th>
16918 <th class="head">Function</th>
16919 </tr>
16920 </thead>
16921 <tbody valign="top">
16922 <tr class="row-even"><td>0</td>
16923 <td>DEV_TIMER7_TIMER_HCLK_CLK</td>
16924 <td>Input clock</td>
16925 </tr>
16926 <tr class="row-odd"><td>1</td>
16927 <td>DEV_TIMER7_TIMER_TCLK_CLK</td>
16928 <td>Input muxed clock</td>
16929 </tr>
16930 <tr class="row-even"><td>2</td>
16931 <td>DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7</td>
16932 <td>Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK</td>
16933 </tr>
16934 <tr class="row-odd"><td>3</td>
16935 <td>DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM</td>
16936 <td>Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK</td>
16937 </tr>
16938 </tbody>
16939 </table>
16940 </div>
16941 <div class="section" id="clocks-for-timer8-device">
16942 <span id="soc-doc-j721e-public-clks-timer8"></span><h3>Clocks for TIMER8 Device<a class="headerlink" href="#clocks-for-timer8-device" title="Permalink to this headline">¶</a></h3>
16943 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER8</span></a> (ID = 58)</p>
16944 <p>Following is a mapping of Clocks IDs to function:</p>
16945 <table border="1" class="docutils">
16946 <colgroup>
16947 <col width="8%" />
16948 <col width="53%" />
16949 <col width="39%" />
16950 </colgroup>
16951 <thead valign="bottom">
16952 <tr class="row-odd"><th class="head">Clock ID</th>
16953 <th class="head">Name</th>
16954 <th class="head">Function</th>
16955 </tr>
16956 </thead>
16957 <tbody valign="top">
16958 <tr class="row-even"><td>0</td>
16959 <td>DEV_TIMER8_TIMER_HCLK_CLK</td>
16960 <td>Input clock</td>
16961 </tr>
16962 <tr class="row-odd"><td>1</td>
16963 <td>DEV_TIMER8_TIMER_TCLK_CLK</td>
16964 <td>Input muxed clock</td>
16965 </tr>
16966 <tr class="row-even"><td>2</td>
16967 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16968 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16969 </tr>
16970 <tr class="row-odd"><td>3</td>
16971 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16972 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16973 </tr>
16974 <tr class="row-even"><td>4</td>
16975 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK</td>
16976 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16977 </tr>
16978 <tr class="row-odd"><td>5</td>
16979 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
16980 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16981 </tr>
16982 <tr class="row-even"><td>6</td>
16983 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
16984 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16985 </tr>
16986 <tr class="row-odd"><td>7</td>
16987 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
16988 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16989 </tr>
16990 <tr class="row-even"><td>8</td>
16991 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
16992 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16993 </tr>
16994 <tr class="row-odd"><td>9</td>
16995 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
16996 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16997 </tr>
16998 <tr class="row-even"><td>10</td>
16999 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
17000 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
17001 </tr>
17002 <tr class="row-odd"><td>11</td>
17003 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
17004 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
17005 </tr>
17006 <tr class="row-even"><td>12</td>
17007 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
17008 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
17009 </tr>
17010 <tr class="row-odd"><td>13</td>
17011 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
17012 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
17013 </tr>
17014 <tr class="row-even"><td>14</td>
17015 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2</td>
17016 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
17017 </tr>
17018 <tr class="row-odd"><td>15</td>
17019 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3</td>
17020 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
17021 </tr>
17022 <tr class="row-even"><td>16</td>
17023 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0</td>
17024 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
17025 </tr>
17026 <tr class="row-odd"><td>17</td>
17027 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK</td>
17028 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
17029 </tr>
17030 <tr class="row-even"><td>18</td>
17031 <td>DEV_TIMER8_TIMER_PWM</td>
17032 <td>Output clock</td>
17033 </tr>
17034 </tbody>
17035 </table>
17036 </div>
17037 <div class="section" id="clocks-for-timer9-device">
17038 <span id="soc-doc-j721e-public-clks-timer9"></span><h3>Clocks for TIMER9 Device<a class="headerlink" href="#clocks-for-timer9-device" title="Permalink to this headline">¶</a></h3>
17039 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMER9</span></a> (ID = 59)</p>
17040 <p>Following is a mapping of Clocks IDs to function:</p>
17041 <table border="1" class="docutils">
17042 <colgroup>
17043 <col width="9%" />
17044 <col width="49%" />
17045 <col width="42%" />
17046 </colgroup>
17047 <thead valign="bottom">
17048 <tr class="row-odd"><th class="head">Clock ID</th>
17049 <th class="head">Name</th>
17050 <th class="head">Function</th>
17051 </tr>
17052 </thead>
17053 <tbody valign="top">
17054 <tr class="row-even"><td>0</td>
17055 <td>DEV_TIMER9_TIMER_HCLK_CLK</td>
17056 <td>Input clock</td>
17057 </tr>
17058 <tr class="row-odd"><td>1</td>
17059 <td>DEV_TIMER9_TIMER_TCLK_CLK</td>
17060 <td>Input muxed clock</td>
17061 </tr>
17062 <tr class="row-even"><td>2</td>
17063 <td>DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9</td>
17064 <td>Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK</td>
17065 </tr>
17066 <tr class="row-odd"><td>3</td>
17067 <td>DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM</td>
17068 <td>Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK</td>
17069 </tr>
17070 </tbody>
17071 </table>
17072 </div>
17073 <div class="section" id="clocks-for-timesync-intrtr0-device">
17074 <span id="soc-doc-j721e-public-clks-timesync-intrtr0"></span><h3>Clocks for TIMESYNC_INTRTR0 Device<a class="headerlink" href="#clocks-for-timesync-intrtr0-device" title="Permalink to this headline">¶</a></h3>
17075 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_TIMESYNC_INTRTR0</span></a> (ID = 136)</p>
17076 <p>Following is a mapping of Clocks IDs to function:</p>
17077 <table border="1" class="docutils">
17078 <colgroup>
17079 <col width="21%" />
17080 <col width="55%" />
17081 <col width="23%" />
17082 </colgroup>
17083 <thead valign="bottom">
17084 <tr class="row-odd"><th class="head">Clock ID</th>
17085 <th class="head">Name</th>
17086 <th class="head">Function</th>
17087 </tr>
17088 </thead>
17089 <tbody valign="top">
17090 <tr class="row-even"><td>0</td>
17091 <td>DEV_TIMESYNC_INTRTR0_INTR_CLK</td>
17092 <td>Input clock</td>
17093 </tr>
17094 </tbody>
17095 </table>
17096 </div>
17097 <div class="section" id="clocks-for-uart0-device">
17098 <span id="soc-doc-j721e-public-clks-uart0"></span><h3>Clocks for UART0 Device<a class="headerlink" href="#clocks-for-uart0-device" title="Permalink to this headline">¶</a></h3>
17099 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_UART0</span></a> (ID = 146)</p>
17100 <p>Following is a mapping of Clocks IDs to function:</p>
17101 <table border="1" class="docutils">
17102 <colgroup>
17103 <col width="26%" />
17104 <col width="46%" />
17105 <col width="28%" />
17106 </colgroup>
17107 <thead valign="bottom">
17108 <tr class="row-odd"><th class="head">Clock ID</th>
17109 <th class="head">Name</th>
17110 <th class="head">Function</th>
17111 </tr>
17112 </thead>
17113 <tbody valign="top">
17114 <tr class="row-even"><td>0</td>
17115 <td>DEV_UART0_FCLK_CLK</td>
17116 <td>Input clock</td>
17117 </tr>
17118 <tr class="row-odd"><td>1</td>
17119 <td>DEV_UART0_VBUSP_CLK</td>
17120 <td>Input clock</td>
17121 </tr>
17122 </tbody>
17123 </table>
17124 </div>
17125 <div class="section" id="clocks-for-uart1-device">
17126 <span id="soc-doc-j721e-public-clks-uart1"></span><h3>Clocks for UART1 Device<a class="headerlink" href="#clocks-for-uart1-device" title="Permalink to this headline">¶</a></h3>
17127 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_UART1</span></a> (ID = 278)</p>
17128 <p>Following is a mapping of Clocks IDs to function:</p>
17129 <table border="1" class="docutils">
17130 <colgroup>
17131 <col width="26%" />
17132 <col width="46%" />
17133 <col width="28%" />
17134 </colgroup>
17135 <thead valign="bottom">
17136 <tr class="row-odd"><th class="head">Clock ID</th>
17137 <th class="head">Name</th>
17138 <th class="head">Function</th>
17139 </tr>
17140 </thead>
17141 <tbody valign="top">
17142 <tr class="row-even"><td>0</td>
17143 <td>DEV_UART1_FCLK_CLK</td>
17144 <td>Input clock</td>
17145 </tr>
17146 <tr class="row-odd"><td>1</td>
17147 <td>DEV_UART1_VBUSP_CLK</td>
17148 <td>Input clock</td>
17149 </tr>
17150 </tbody>
17151 </table>
17152 </div>
17153 <div class="section" id="clocks-for-uart2-device">
17154 <span id="soc-doc-j721e-public-clks-uart2"></span><h3>Clocks for UART2 Device<a class="headerlink" href="#clocks-for-uart2-device" title="Permalink to this headline">¶</a></h3>
17155 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_UART2</span></a> (ID = 279)</p>
17156 <p>Following is a mapping of Clocks IDs to function:</p>
17157 <table border="1" class="docutils">
17158 <colgroup>
17159 <col width="26%" />
17160 <col width="46%" />
17161 <col width="28%" />
17162 </colgroup>
17163 <thead valign="bottom">
17164 <tr class="row-odd"><th class="head">Clock ID</th>
17165 <th class="head">Name</th>
17166 <th class="head">Function</th>
17167 </tr>
17168 </thead>
17169 <tbody valign="top">
17170 <tr class="row-even"><td>0</td>
17171 <td>DEV_UART2_FCLK_CLK</td>
17172 <td>Input clock</td>
17173 </tr>
17174 <tr class="row-odd"><td>1</td>
17175 <td>DEV_UART2_VBUSP_CLK</td>
17176 <td>Input clock</td>
17177 </tr>
17178 </tbody>
17179 </table>
17180 </div>
17181 <div class="section" id="clocks-for-uart3-device">
17182 <span id="soc-doc-j721e-public-clks-uart3"></span><h3>Clocks for UART3 Device<a class="headerlink" href="#clocks-for-uart3-device" title="Permalink to this headline">¶</a></h3>
17183 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_UART3</span></a> (ID = 280)</p>
17184 <p>Following is a mapping of Clocks IDs to function:</p>
17185 <table border="1" class="docutils">
17186 <colgroup>
17187 <col width="26%" />
17188 <col width="46%" />
17189 <col width="28%" />
17190 </colgroup>
17191 <thead valign="bottom">
17192 <tr class="row-odd"><th class="head">Clock ID</th>
17193 <th class="head">Name</th>
17194 <th class="head">Function</th>
17195 </tr>
17196 </thead>
17197 <tbody valign="top">
17198 <tr class="row-even"><td>0</td>
17199 <td>DEV_UART3_FCLK_CLK</td>
17200 <td>Input clock</td>
17201 </tr>
17202 <tr class="row-odd"><td>1</td>
17203 <td>DEV_UART3_VBUSP_CLK</td>
17204 <td>Input clock</td>
17205 </tr>
17206 </tbody>
17207 </table>
17208 </div>
17209 <div class="section" id="clocks-for-uart4-device">
17210 <span id="soc-doc-j721e-public-clks-uart4"></span><h3>Clocks for UART4 Device<a class="headerlink" href="#clocks-for-uart4-device" title="Permalink to this headline">¶</a></h3>
17211 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_UART4</span></a> (ID = 281)</p>
17212 <p>Following is a mapping of Clocks IDs to function:</p>
17213 <table border="1" class="docutils">
17214 <colgroup>
17215 <col width="26%" />
17216 <col width="46%" />
17217 <col width="28%" />
17218 </colgroup>
17219 <thead valign="bottom">
17220 <tr class="row-odd"><th class="head">Clock ID</th>
17221 <th class="head">Name</th>
17222 <th class="head">Function</th>
17223 </tr>
17224 </thead>
17225 <tbody valign="top">
17226 <tr class="row-even"><td>0</td>
17227 <td>DEV_UART4_FCLK_CLK</td>
17228 <td>Input clock</td>
17229 </tr>
17230 <tr class="row-odd"><td>1</td>
17231 <td>DEV_UART4_VBUSP_CLK</td>
17232 <td>Input clock</td>
17233 </tr>
17234 </tbody>
17235 </table>
17236 </div>
17237 <div class="section" id="clocks-for-uart5-device">
17238 <span id="soc-doc-j721e-public-clks-uart5"></span><h3>Clocks for UART5 Device<a class="headerlink" href="#clocks-for-uart5-device" title="Permalink to this headline">¶</a></h3>
17239 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_UART5</span></a> (ID = 282)</p>
17240 <p>Following is a mapping of Clocks IDs to function:</p>
17241 <table border="1" class="docutils">
17242 <colgroup>
17243 <col width="26%" />
17244 <col width="46%" />
17245 <col width="28%" />
17246 </colgroup>
17247 <thead valign="bottom">
17248 <tr class="row-odd"><th class="head">Clock ID</th>
17249 <th class="head">Name</th>
17250 <th class="head">Function</th>
17251 </tr>
17252 </thead>
17253 <tbody valign="top">
17254 <tr class="row-even"><td>0</td>
17255 <td>DEV_UART5_FCLK_CLK</td>
17256 <td>Input clock</td>
17257 </tr>
17258 <tr class="row-odd"><td>1</td>
17259 <td>DEV_UART5_VBUSP_CLK</td>
17260 <td>Input clock</td>
17261 </tr>
17262 </tbody>
17263 </table>
17264 </div>
17265 <div class="section" id="clocks-for-uart6-device">
17266 <span id="soc-doc-j721e-public-clks-uart6"></span><h3>Clocks for UART6 Device<a class="headerlink" href="#clocks-for-uart6-device" title="Permalink to this headline">¶</a></h3>
17267 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_UART6</span></a> (ID = 283)</p>
17268 <p>Following is a mapping of Clocks IDs to function:</p>
17269 <table border="1" class="docutils">
17270 <colgroup>
17271 <col width="26%" />
17272 <col width="46%" />
17273 <col width="28%" />
17274 </colgroup>
17275 <thead valign="bottom">
17276 <tr class="row-odd"><th class="head">Clock ID</th>
17277 <th class="head">Name</th>
17278 <th class="head">Function</th>
17279 </tr>
17280 </thead>
17281 <tbody valign="top">
17282 <tr class="row-even"><td>0</td>
17283 <td>DEV_UART6_FCLK_CLK</td>
17284 <td>Input clock</td>
17285 </tr>
17286 <tr class="row-odd"><td>1</td>
17287 <td>DEV_UART6_VBUSP_CLK</td>
17288 <td>Input clock</td>
17289 </tr>
17290 </tbody>
17291 </table>
17292 </div>
17293 <div class="section" id="clocks-for-uart7-device">
17294 <span id="soc-doc-j721e-public-clks-uart7"></span><h3>Clocks for UART7 Device<a class="headerlink" href="#clocks-for-uart7-device" title="Permalink to this headline">¶</a></h3>
17295 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_UART7</span></a> (ID = 284)</p>
17296 <p>Following is a mapping of Clocks IDs to function:</p>
17297 <table border="1" class="docutils">
17298 <colgroup>
17299 <col width="26%" />
17300 <col width="46%" />
17301 <col width="28%" />
17302 </colgroup>
17303 <thead valign="bottom">
17304 <tr class="row-odd"><th class="head">Clock ID</th>
17305 <th class="head">Name</th>
17306 <th class="head">Function</th>
17307 </tr>
17308 </thead>
17309 <tbody valign="top">
17310 <tr class="row-even"><td>0</td>
17311 <td>DEV_UART7_FCLK_CLK</td>
17312 <td>Input clock</td>
17313 </tr>
17314 <tr class="row-odd"><td>1</td>
17315 <td>DEV_UART7_VBUSP_CLK</td>
17316 <td>Input clock</td>
17317 </tr>
17318 </tbody>
17319 </table>
17320 </div>
17321 <div class="section" id="clocks-for-uart8-device">
17322 <span id="soc-doc-j721e-public-clks-uart8"></span><h3>Clocks for UART8 Device<a class="headerlink" href="#clocks-for-uart8-device" title="Permalink to this headline">¶</a></h3>
17323 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_UART8</span></a> (ID = 285)</p>
17324 <p>Following is a mapping of Clocks IDs to function:</p>
17325 <table border="1" class="docutils">
17326 <colgroup>
17327 <col width="26%" />
17328 <col width="46%" />
17329 <col width="28%" />
17330 </colgroup>
17331 <thead valign="bottom">
17332 <tr class="row-odd"><th class="head">Clock ID</th>
17333 <th class="head">Name</th>
17334 <th class="head">Function</th>
17335 </tr>
17336 </thead>
17337 <tbody valign="top">
17338 <tr class="row-even"><td>0</td>
17339 <td>DEV_UART8_FCLK_CLK</td>
17340 <td>Input clock</td>
17341 </tr>
17342 <tr class="row-odd"><td>1</td>
17343 <td>DEV_UART8_VBUSP_CLK</td>
17344 <td>Input clock</td>
17345 </tr>
17346 </tbody>
17347 </table>
17348 </div>
17349 <div class="section" id="clocks-for-uart9-device">
17350 <span id="soc-doc-j721e-public-clks-uart9"></span><h3>Clocks for UART9 Device<a class="headerlink" href="#clocks-for-uart9-device" title="Permalink to this headline">¶</a></h3>
17351 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_UART9</span></a> (ID = 286)</p>
17352 <p>Following is a mapping of Clocks IDs to function:</p>
17353 <table border="1" class="docutils">
17354 <colgroup>
17355 <col width="26%" />
17356 <col width="46%" />
17357 <col width="28%" />
17358 </colgroup>
17359 <thead valign="bottom">
17360 <tr class="row-odd"><th class="head">Clock ID</th>
17361 <th class="head">Name</th>
17362 <th class="head">Function</th>
17363 </tr>
17364 </thead>
17365 <tbody valign="top">
17366 <tr class="row-even"><td>0</td>
17367 <td>DEV_UART9_FCLK_CLK</td>
17368 <td>Input clock</td>
17369 </tr>
17370 <tr class="row-odd"><td>1</td>
17371 <td>DEV_UART9_VBUSP_CLK</td>
17372 <td>Input clock</td>
17373 </tr>
17374 </tbody>
17375 </table>
17376 </div>
17377 <div class="section" id="clocks-for-ufs0-device">
17378 <span id="soc-doc-j721e-public-clks-ufs0"></span><h3>Clocks for UFS0 Device<a class="headerlink" href="#clocks-for-ufs0-device" title="Permalink to this headline">¶</a></h3>
17379 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_UFS0</span></a> (ID = 277)</p>
17380 <p>Following is a mapping of Clocks IDs to function:</p>
17381 <table border="1" class="docutils">
17382 <colgroup>
17383 <col width="9%" />
17384 <col width="51%" />
17385 <col width="40%" />
17386 </colgroup>
17387 <thead valign="bottom">
17388 <tr class="row-odd"><th class="head">Clock ID</th>
17389 <th class="head">Name</th>
17390 <th class="head">Function</th>
17391 </tr>
17392 </thead>
17393 <tbody valign="top">
17394 <tr class="row-even"><td>0</td>
17395 <td>DEV_UFS0_UFSHCI_HCLK_CLK</td>
17396 <td>Input clock</td>
17397 </tr>
17398 <tr class="row-odd"><td>1</td>
17399 <td>DEV_UFS0_UFSHCI_MCLK_CLK</td>
17400 <td>Input muxed clock</td>
17401 </tr>
17402 <tr class="row-even"><td>2</td>
17403 <td>DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
17404 <td>Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK</td>
17405 </tr>
17406 <tr class="row-odd"><td>3</td>
17407 <td>DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
17408 <td>Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK</td>
17409 </tr>
17410 <tr class="row-even"><td>4</td>
17411 <td>DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK</td>
17412 <td>Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK</td>
17413 </tr>
17414 <tr class="row-odd"><td>5</td>
17415 <td>DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
17416 <td>Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK</td>
17417 </tr>
17418 <tr class="row-even"><td>6</td>
17419 <td>DEV_UFS0_UFSHCI_MPHY_REFCLK</td>
17420 <td>Output clock</td>
17421 </tr>
17422 </tbody>
17423 </table>
17424 </div>
17425 <div class="section" id="clocks-for-usb0-device">
17426 <span id="soc-doc-j721e-public-clks-usb0"></span><h3>Clocks for USB0 Device<a class="headerlink" href="#clocks-for-usb0-device" title="Permalink to this headline">¶</a></h3>
17427 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_USB0</span></a> (ID = 288)</p>
17428 <p>Following is a mapping of Clocks IDs to function:</p>
17429 <table border="1" class="docutils">
17430 <colgroup>
17431 <col width="9%" />
17432 <col width="48%" />
17433 <col width="43%" />
17434 </colgroup>
17435 <thead valign="bottom">
17436 <tr class="row-odd"><th class="head">Clock ID</th>
17437 <th class="head">Name</th>
17438 <th class="head">Function</th>
17439 </tr>
17440 </thead>
17441 <tbody valign="top">
17442 <tr class="row-even"><td>0</td>
17443 <td>DEV_USB0_PIPE_REFCLK</td>
17444 <td>Input muxed clock</td>
17445 </tr>
17446 <tr class="row-odd"><td>1</td>
17447 <td>DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_REFCLK</td>
17448 <td>Parent input clock option to DEV_USB0_PIPE_REFCLK</td>
17449 </tr>
17450 <tr class="row-even"><td>2</td>
17451 <td>DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_REFCLK</td>
17452 <td>Parent input clock option to DEV_USB0_PIPE_REFCLK</td>
17453 </tr>
17454 <tr class="row-odd"><td>3</td>
17455 <td>DEV_USB0_CLK_LPM_CLK</td>
17456 <td>Input clock</td>
17457 </tr>
17458 <tr class="row-even"><td>4</td>
17459 <td>DEV_USB0_BUF_CLK</td>
17460 <td>Input clock</td>
17461 </tr>
17462 <tr class="row-odd"><td>5</td>
17463 <td>DEV_USB0_USB2_APB_PCLK_CLK</td>
17464 <td>Input clock</td>
17465 </tr>
17466 <tr class="row-even"><td>6</td>
17467 <td>DEV_USB0_PIPE_RXCLK</td>
17468 <td>Input muxed clock</td>
17469 </tr>
17470 <tr class="row-odd"><td>7</td>
17471 <td>DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXCLK</td>
17472 <td>Parent input clock option to DEV_USB0_PIPE_RXCLK</td>
17473 </tr>
17474 <tr class="row-even"><td>8</td>
17475 <td>DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXCLK</td>
17476 <td>Parent input clock option to DEV_USB0_PIPE_RXCLK</td>
17477 </tr>
17478 <tr class="row-odd"><td>9</td>
17479 <td>DEV_USB0_PIPE_TXMCLK</td>
17480 <td>Input muxed clock</td>
17481 </tr>
17482 <tr class="row-even"><td>10</td>
17483 <td>DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXMCLK</td>
17484 <td>Parent input clock option to DEV_USB0_PIPE_TXMCLK</td>
17485 </tr>
17486 <tr class="row-odd"><td>11</td>
17487 <td>DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXMCLK</td>
17488 <td>Parent input clock option to DEV_USB0_PIPE_TXMCLK</td>
17489 </tr>
17490 <tr class="row-even"><td>12</td>
17491 <td>DEV_USB0_PIPE_RXFCLK</td>
17492 <td>Input muxed clock</td>
17493 </tr>
17494 <tr class="row-odd"><td>13</td>
17495 <td>DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXFCLK</td>
17496 <td>Parent input clock option to DEV_USB0_PIPE_RXFCLK</td>
17497 </tr>
17498 <tr class="row-even"><td>14</td>
17499 <td>DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXFCLK</td>
17500 <td>Parent input clock option to DEV_USB0_PIPE_RXFCLK</td>
17501 </tr>
17502 <tr class="row-odd"><td>15</td>
17503 <td>DEV_USB0_USB2_REFCLOCK_CLK</td>
17504 <td>Input muxed clock</td>
17505 </tr>
17506 <tr class="row-even"><td>16</td>
17507 <td>DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
17508 <td>Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK</td>
17509 </tr>
17510 <tr class="row-odd"><td>17</td>
17511 <td>DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
17512 <td>Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK</td>
17513 </tr>
17514 <tr class="row-even"><td>18</td>
17515 <td>DEV_USB0_PCLK_CLK</td>
17516 <td>Input clock</td>
17517 </tr>
17518 <tr class="row-odd"><td>19</td>
17519 <td>DEV_USB0_ACLK_CLK</td>
17520 <td>Input clock</td>
17521 </tr>
17522 <tr class="row-even"><td>20</td>
17523 <td>DEV_USB0_PIPE_TXFCLK</td>
17524 <td>Input muxed clock</td>
17525 </tr>
17526 <tr class="row-odd"><td>21</td>
17527 <td>DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXFCLK</td>
17528 <td>Parent input clock option to DEV_USB0_PIPE_TXFCLK</td>
17529 </tr>
17530 <tr class="row-even"><td>22</td>
17531 <td>DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXFCLK</td>
17532 <td>Parent input clock option to DEV_USB0_PIPE_TXFCLK</td>
17533 </tr>
17534 <tr class="row-odd"><td>23</td>
17535 <td>DEV_USB0_PIPE_TXCLK</td>
17536 <td>Output clock</td>
17537 </tr>
17538 </tbody>
17539 </table>
17540 </div>
17541 <div class="section" id="clocks-for-usb1-device">
17542 <span id="soc-doc-j721e-public-clks-usb1"></span><h3>Clocks for USB1 Device<a class="headerlink" href="#clocks-for-usb1-device" title="Permalink to this headline">¶</a></h3>
17543 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_USB1</span></a> (ID = 289)</p>
17544 <p>Following is a mapping of Clocks IDs to function:</p>
17545 <table border="1" class="docutils">
17546 <colgroup>
17547 <col width="9%" />
17548 <col width="48%" />
17549 <col width="43%" />
17550 </colgroup>
17551 <thead valign="bottom">
17552 <tr class="row-odd"><th class="head">Clock ID</th>
17553 <th class="head">Name</th>
17554 <th class="head">Function</th>
17555 </tr>
17556 </thead>
17557 <tbody valign="top">
17558 <tr class="row-even"><td>0</td>
17559 <td>DEV_USB1_PIPE_REFCLK</td>
17560 <td>Input muxed clock</td>
17561 </tr>
17562 <tr class="row-odd"><td>1</td>
17563 <td>DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_REFCLK</td>
17564 <td>Parent input clock option to DEV_USB1_PIPE_REFCLK</td>
17565 </tr>
17566 <tr class="row-even"><td>2</td>
17567 <td>DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_REFCLK</td>
17568 <td>Parent input clock option to DEV_USB1_PIPE_REFCLK</td>
17569 </tr>
17570 <tr class="row-odd"><td>3</td>
17571 <td>DEV_USB1_CLK_LPM_CLK</td>
17572 <td>Input clock</td>
17573 </tr>
17574 <tr class="row-even"><td>4</td>
17575 <td>DEV_USB1_BUF_CLK</td>
17576 <td>Input clock</td>
17577 </tr>
17578 <tr class="row-odd"><td>5</td>
17579 <td>DEV_USB1_USB2_APB_PCLK_CLK</td>
17580 <td>Input clock</td>
17581 </tr>
17582 <tr class="row-even"><td>6</td>
17583 <td>DEV_USB1_PIPE_RXCLK</td>
17584 <td>Input muxed clock</td>
17585 </tr>
17586 <tr class="row-odd"><td>7</td>
17587 <td>DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXCLK</td>
17588 <td>Parent input clock option to DEV_USB1_PIPE_RXCLK</td>
17589 </tr>
17590 <tr class="row-even"><td>8</td>
17591 <td>DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXCLK</td>
17592 <td>Parent input clock option to DEV_USB1_PIPE_RXCLK</td>
17593 </tr>
17594 <tr class="row-odd"><td>9</td>
17595 <td>DEV_USB1_PIPE_TXMCLK</td>
17596 <td>Input muxed clock</td>
17597 </tr>
17598 <tr class="row-even"><td>10</td>
17599 <td>DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXMCLK</td>
17600 <td>Parent input clock option to DEV_USB1_PIPE_TXMCLK</td>
17601 </tr>
17602 <tr class="row-odd"><td>11</td>
17603 <td>DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXMCLK</td>
17604 <td>Parent input clock option to DEV_USB1_PIPE_TXMCLK</td>
17605 </tr>
17606 <tr class="row-even"><td>12</td>
17607 <td>DEV_USB1_PIPE_RXFCLK</td>
17608 <td>Input muxed clock</td>
17609 </tr>
17610 <tr class="row-odd"><td>13</td>
17611 <td>DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXFCLK</td>
17612 <td>Parent input clock option to DEV_USB1_PIPE_RXFCLK</td>
17613 </tr>
17614 <tr class="row-even"><td>14</td>
17615 <td>DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXFCLK</td>
17616 <td>Parent input clock option to DEV_USB1_PIPE_RXFCLK</td>
17617 </tr>
17618 <tr class="row-odd"><td>15</td>
17619 <td>DEV_USB1_USB2_REFCLOCK_CLK</td>
17620 <td>Input muxed clock</td>
17621 </tr>
17622 <tr class="row-even"><td>16</td>
17623 <td>DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
17624 <td>Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK</td>
17625 </tr>
17626 <tr class="row-odd"><td>17</td>
17627 <td>DEV_USB1_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
17628 <td>Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK</td>
17629 </tr>
17630 <tr class="row-even"><td>18</td>
17631 <td>DEV_USB1_PCLK_CLK</td>
17632 <td>Input clock</td>
17633 </tr>
17634 <tr class="row-odd"><td>19</td>
17635 <td>DEV_USB1_ACLK_CLK</td>
17636 <td>Input clock</td>
17637 </tr>
17638 <tr class="row-even"><td>20</td>
17639 <td>DEV_USB1_PIPE_TXFCLK</td>
17640 <td>Input muxed clock</td>
17641 </tr>
17642 <tr class="row-odd"><td>21</td>
17643 <td>DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXFCLK</td>
17644 <td>Parent input clock option to DEV_USB1_PIPE_TXFCLK</td>
17645 </tr>
17646 <tr class="row-even"><td>22</td>
17647 <td>DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXFCLK</td>
17648 <td>Parent input clock option to DEV_USB1_PIPE_TXFCLK</td>
17649 </tr>
17650 <tr class="row-odd"><td>23</td>
17651 <td>DEV_USB1_PIPE_TXCLK</td>
17652 <td>Output clock</td>
17653 </tr>
17654 </tbody>
17655 </table>
17656 </div>
17657 <div class="section" id="clocks-for-vpac0-device">
17658 <span id="soc-doc-j721e-public-clks-vpac0"></span><h3>Clocks for VPAC0 Device<a class="headerlink" href="#clocks-for-vpac0-device" title="Permalink to this headline">¶</a></h3>
17659 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_VPAC0</span></a> (ID = 290)</p>
17660 <p>Following is a mapping of Clocks IDs to function:</p>
17661 <table border="1" class="docutils">
17662 <colgroup>
17663 <col width="25%" />
17664 <col width="48%" />
17665 <col width="27%" />
17666 </colgroup>
17667 <thead valign="bottom">
17668 <tr class="row-odd"><th class="head">Clock ID</th>
17669 <th class="head">Name</th>
17670 <th class="head">Function</th>
17671 </tr>
17672 </thead>
17673 <tbody valign="top">
17674 <tr class="row-even"><td>0</td>
17675 <td>DEV_VPAC0_CLK</td>
17676 <td>Input clock</td>
17677 </tr>
17678 <tr class="row-odd"><td>1</td>
17679 <td>DEV_VPAC0_PLL_DCO_CLK</td>
17680 <td>Input clock</td>
17681 </tr>
17682 </tbody>
17683 </table>
17684 </div>
17685 <div class="section" id="clocks-for-vpfe0-device">
17686 <span id="soc-doc-j721e-public-clks-vpfe0"></span><h3>Clocks for VPFE0 Device<a class="headerlink" href="#clocks-for-vpfe0-device" title="Permalink to this headline">¶</a></h3>
17687 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_VPFE0</span></a> (ID = 291)</p>
17688 <p>Following is a mapping of Clocks IDs to function:</p>
17689 <table border="1" class="docutils">
17690 <colgroup>
17691 <col width="24%" />
17692 <col width="49%" />
17693 <col width="27%" />
17694 </colgroup>
17695 <thead valign="bottom">
17696 <tr class="row-odd"><th class="head">Clock ID</th>
17697 <th class="head">Name</th>
17698 <th class="head">Function</th>
17699 </tr>
17700 </thead>
17701 <tbody valign="top">
17702 <tr class="row-even"><td>0</td>
17703 <td>DEV_VPFE0_CCD_PCLK_CLK</td>
17704 <td>Input clock</td>
17705 </tr>
17706 <tr class="row-odd"><td>1</td>
17707 <td>DEV_VPFE0_VPFE_CLK</td>
17708 <td>Input clock</td>
17709 </tr>
17710 </tbody>
17711 </table>
17712 </div>
17713 <div class="section" id="clocks-for-wkupmcu2main-vd-device">
17714 <span id="soc-doc-j721e-public-clks-wkupmcu2main-vd"></span><h3>Clocks for WKUPMCU2MAIN_VD Device<a class="headerlink" href="#clocks-for-wkupmcu2main-vd-device" title="Permalink to this headline">¶</a></h3>
17715 <p><strong>This device has no defined clocks.</strong></p>
17716 </div>
17717 <div class="section" id="clocks-for-wkup-ddpa0-device">
17718 <span id="soc-doc-j721e-public-clks-wkup-ddpa0"></span><h3>Clocks for WKUP_DDPA0 Device<a class="headerlink" href="#clocks-for-wkup-ddpa0-device" title="Permalink to this headline">¶</a></h3>
17719 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_WKUP_DDPA0</span></a> (ID = 145)</p>
17720 <p>Following is a mapping of Clocks IDs to function:</p>
17721 <table border="1" class="docutils">
17722 <colgroup>
17723 <col width="24%" />
17724 <col width="50%" />
17725 <col width="26%" />
17726 </colgroup>
17727 <thead valign="bottom">
17728 <tr class="row-odd"><th class="head">Clock ID</th>
17729 <th class="head">Name</th>
17730 <th class="head">Function</th>
17731 </tr>
17732 </thead>
17733 <tbody valign="top">
17734 <tr class="row-even"><td>0</td>
17735 <td>DEV_WKUP_DDPA0_DDPA_CLK</td>
17736 <td>Input clock</td>
17737 </tr>
17738 </tbody>
17739 </table>
17740 </div>
17741 <div class="section" id="clocks-for-wkup-dmsc0-device">
17742 <span id="soc-doc-j721e-public-clks-wkup-dmsc0"></span><h3>Clocks for WKUP_DMSC0 Device<a class="headerlink" href="#clocks-for-wkup-dmsc0-device" title="Permalink to this headline">¶</a></h3>
17743 <p><strong>This device has no defined clocks.</strong></p>
17744 </div>
17745 <div class="section" id="clocks-for-wkup-esm0-device">
17746 <span id="soc-doc-j721e-public-clks-wkup-esm0"></span><h3>Clocks for WKUP_ESM0 Device<a class="headerlink" href="#clocks-for-wkup-esm0-device" title="Permalink to this headline">¶</a></h3>
17747 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_WKUP_ESM0</span></a> (ID = 99)</p>
17748 <p>Following is a mapping of Clocks IDs to function:</p>
17749 <table border="1" class="docutils">
17750 <colgroup>
17751 <col width="27%" />
17752 <col width="43%" />
17753 <col width="30%" />
17754 </colgroup>
17755 <thead valign="bottom">
17756 <tr class="row-odd"><th class="head">Clock ID</th>
17757 <th class="head">Name</th>
17758 <th class="head">Function</th>
17759 </tr>
17760 </thead>
17761 <tbody valign="top">
17762 <tr class="row-even"><td>0</td>
17763 <td>DEV_WKUP_ESM0_CLK</td>
17764 <td>Input clock</td>
17765 </tr>
17766 </tbody>
17767 </table>
17768 </div>
17769 <div class="section" id="clocks-for-wkup-gpio0-device">
17770 <span id="soc-doc-j721e-public-clks-wkup-gpio0"></span><h3>Clocks for WKUP_GPIO0 Device<a class="headerlink" href="#clocks-for-wkup-gpio0-device" title="Permalink to this headline">¶</a></h3>
17771 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_WKUP_GPIO0</span></a> (ID = 113)</p>
17772 <p>Following is a mapping of Clocks IDs to function:</p>
17773 <table border="1" class="docutils">
17774 <colgroup>
17775 <col width="24%" />
17776 <col width="49%" />
17777 <col width="27%" />
17778 </colgroup>
17779 <thead valign="bottom">
17780 <tr class="row-odd"><th class="head">Clock ID</th>
17781 <th class="head">Name</th>
17782 <th class="head">Function</th>
17783 </tr>
17784 </thead>
17785 <tbody valign="top">
17786 <tr class="row-even"><td>0</td>
17787 <td>DEV_WKUP_GPIO0_MMR_CLK</td>
17788 <td>Input clock</td>
17789 </tr>
17790 </tbody>
17791 </table>
17792 </div>
17793 <div class="section" id="clocks-for-wkup-gpio1-device">
17794 <span id="soc-doc-j721e-public-clks-wkup-gpio1"></span><h3>Clocks for WKUP_GPIO1 Device<a class="headerlink" href="#clocks-for-wkup-gpio1-device" title="Permalink to this headline">¶</a></h3>
17795 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_WKUP_GPIO1</span></a> (ID = 114)</p>
17796 <p>Following is a mapping of Clocks IDs to function:</p>
17797 <table border="1" class="docutils">
17798 <colgroup>
17799 <col width="24%" />
17800 <col width="49%" />
17801 <col width="27%" />
17802 </colgroup>
17803 <thead valign="bottom">
17804 <tr class="row-odd"><th class="head">Clock ID</th>
17805 <th class="head">Name</th>
17806 <th class="head">Function</th>
17807 </tr>
17808 </thead>
17809 <tbody valign="top">
17810 <tr class="row-even"><td>0</td>
17811 <td>DEV_WKUP_GPIO1_MMR_CLK</td>
17812 <td>Input clock</td>
17813 </tr>
17814 </tbody>
17815 </table>
17816 </div>
17817 <div class="section" id="clocks-for-wkup-gpiomux-intrtr0-device">
17818 <span id="soc-doc-j721e-public-clks-wkup-gpiomux-intrtr0"></span><h3>Clocks for WKUP_GPIOMUX_INTRTR0 Device<a class="headerlink" href="#clocks-for-wkup-gpiomux-intrtr0-device" title="Permalink to this headline">¶</a></h3>
17819 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_WKUP_GPIOMUX_INTRTR0</span></a> (ID = 137)</p>
17820 <p>Following is a mapping of Clocks IDs to function:</p>
17821 <table border="1" class="docutils">
17822 <colgroup>
17823 <col width="20%" />
17824 <col width="58%" />
17825 <col width="22%" />
17826 </colgroup>
17827 <thead valign="bottom">
17828 <tr class="row-odd"><th class="head">Clock ID</th>
17829 <th class="head">Name</th>
17830 <th class="head">Function</th>
17831 </tr>
17832 </thead>
17833 <tbody valign="top">
17834 <tr class="row-even"><td>0</td>
17835 <td>DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK</td>
17836 <td>Input clock</td>
17837 </tr>
17838 </tbody>
17839 </table>
17840 </div>
17841 <div class="section" id="clocks-for-wkup-i2c0-device">
17842 <span id="soc-doc-j721e-public-clks-wkup-i2c0"></span><h3>Clocks for WKUP_I2C0 Device<a class="headerlink" href="#clocks-for-wkup-i2c0-device" title="Permalink to this headline">¶</a></h3>
17843 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_WKUP_I2C0</span></a> (ID = 197)</p>
17844 <p>Following is a mapping of Clocks IDs to function:</p>
17845 <table border="1" class="docutils">
17846 <colgroup>
17847 <col width="9%" />
17848 <col width="50%" />
17849 <col width="41%" />
17850 </colgroup>
17851 <thead valign="bottom">
17852 <tr class="row-odd"><th class="head">Clock ID</th>
17853 <th class="head">Name</th>
17854 <th class="head">Function</th>
17855 </tr>
17856 </thead>
17857 <tbody valign="top">
17858 <tr class="row-even"><td>0</td>
17859 <td>DEV_WKUP_I2C0_PISYS_CLK</td>
17860 <td>Input muxed clock</td>
17861 </tr>
17862 <tr class="row-odd"><td>1</td>
17863 <td>DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK</td>
17864 <td>Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK</td>
17865 </tr>
17866 <tr class="row-even"><td>2</td>
17867 <td>DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
17868 <td>Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK</td>
17869 </tr>
17870 <tr class="row-odd"><td>3</td>
17871 <td>DEV_WKUP_I2C0_PISCL</td>
17872 <td>Input clock</td>
17873 </tr>
17874 <tr class="row-even"><td>4</td>
17875 <td>DEV_WKUP_I2C0_CLK</td>
17876 <td>Input clock</td>
17877 </tr>
17878 <tr class="row-odd"><td>5</td>
17879 <td>DEV_WKUP_I2C0_PORSCL</td>
17880 <td>Output clock</td>
17881 </tr>
17882 </tbody>
17883 </table>
17884 </div>
17885 <div class="section" id="clocks-for-wkup-porz-sync0-device">
17886 <span id="soc-doc-j721e-public-clks-wkup-porz-sync0"></span><h3>Clocks for WKUP_PORZ_SYNC0 Device<a class="headerlink" href="#clocks-for-wkup-porz-sync0-device" title="Permalink to this headline">¶</a></h3>
17887 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_WKUP_PORZ_SYNC0</span></a> (ID = 132)</p>
17888 <p>Following is a mapping of Clocks IDs to function:</p>
17889 <table border="1" class="docutils">
17890 <colgroup>
17891 <col width="20%" />
17892 <col width="59%" />
17893 <col width="21%" />
17894 </colgroup>
17895 <thead valign="bottom">
17896 <tr class="row-odd"><th class="head">Clock ID</th>
17897 <th class="head">Name</th>
17898 <th class="head">Function</th>
17899 </tr>
17900 </thead>
17901 <tbody valign="top">
17902 <tr class="row-even"><td>0</td>
17903 <td>DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK</td>
17904 <td>Input clock</td>
17905 </tr>
17906 </tbody>
17907 </table>
17908 </div>
17909 <div class="section" id="clocks-for-wkup-psc0-device">
17910 <span id="soc-doc-j721e-public-clks-wkup-psc0"></span><h3>Clocks for WKUP_PSC0 Device<a class="headerlink" href="#clocks-for-wkup-psc0-device" title="Permalink to this headline">¶</a></h3>
17911 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_WKUP_PSC0</span></a> (ID = 138)</p>
17912 <p>Following is a mapping of Clocks IDs to function:</p>
17913 <table border="1" class="docutils">
17914 <colgroup>
17915 <col width="24%" />
17916 <col width="49%" />
17917 <col width="27%" />
17918 </colgroup>
17919 <thead valign="bottom">
17920 <tr class="row-odd"><th class="head">Clock ID</th>
17921 <th class="head">Name</th>
17922 <th class="head">Function</th>
17923 </tr>
17924 </thead>
17925 <tbody valign="top">
17926 <tr class="row-even"><td>0</td>
17927 <td>DEV_WKUP_PSC0_SLOW_CLK</td>
17928 <td>Input clock</td>
17929 </tr>
17930 <tr class="row-odd"><td>1</td>
17931 <td>DEV_WKUP_PSC0_CLK</td>
17932 <td>Input clock</td>
17933 </tr>
17934 </tbody>
17935 </table>
17936 </div>
17937 <div class="section" id="clocks-for-wkup-uart0-device">
17938 <span id="soc-doc-j721e-public-clks-wkup-uart0"></span><h3>Clocks for WKUP_UART0 Device<a class="headerlink" href="#clocks-for-wkup-uart0-device" title="Permalink to this headline">¶</a></h3>
17939 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_WKUP_UART0</span></a> (ID = 287)</p>
17940 <p>Following is a mapping of Clocks IDs to function:</p>
17941 <table border="1" class="docutils">
17942 <colgroup>
17943 <col width="10%" />
17944 <col width="46%" />
17945 <col width="44%" />
17946 </colgroup>
17947 <thead valign="bottom">
17948 <tr class="row-odd"><th class="head">Clock ID</th>
17949 <th class="head">Name</th>
17950 <th class="head">Function</th>
17951 </tr>
17952 </thead>
17953 <tbody valign="top">
17954 <tr class="row-even"><td>0</td>
17955 <td>DEV_WKUP_UART0_FCLK_CLK</td>
17956 <td>Input muxed clock</td>
17957 </tr>
17958 <tr class="row-odd"><td>1</td>
17959 <td>DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0</td>
17960 <td>Parent input clock option to DEV_WKUP_UART0_FCLK_CLK</td>
17961 </tr>
17962 <tr class="row-even"><td>2</td>
17963 <td>DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
17964 <td>Parent input clock option to DEV_WKUP_UART0_FCLK_CLK</td>
17965 </tr>
17966 <tr class="row-odd"><td>3</td>
17967 <td>DEV_WKUP_UART0_VBUSP_CLK</td>
17968 <td>Input clock</td>
17969 </tr>
17970 </tbody>
17971 </table>
17972 </div>
17973 <div class="section" id="clocks-for-wkup-vtm0-device">
17974 <span id="soc-doc-j721e-public-clks-wkup-vtm0"></span><h3>Clocks for WKUP_VTM0 Device<a class="headerlink" href="#clocks-for-wkup-vtm0-device" title="Permalink to this headline">¶</a></h3>
17975 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j721e-public-devices-desc-device-list"><span class="std std-ref">J721E_DEV_WKUP_VTM0</span></a> (ID = 154)</p>
17976 <p>Following is a mapping of Clocks IDs to function:</p>
17977 <table border="1" class="docutils">
17978 <colgroup>
17979 <col width="23%" />
17980 <col width="53%" />
17981 <col width="25%" />
17982 </colgroup>
17983 <thead valign="bottom">
17984 <tr class="row-odd"><th class="head">Clock ID</th>
17985 <th class="head">Name</th>
17986 <th class="head">Function</th>
17987 </tr>
17988 </thead>
17989 <tbody valign="top">
17990 <tr class="row-even"><td>0</td>
17991 <td>DEV_WKUP_VTM0_FIX_REF2_CLK</td>
17992 <td>Input clock</td>
17993 </tr>
17994 <tr class="row-odd"><td>1</td>
17995 <td>DEV_WKUP_VTM0_VBUSP_CLK</td>
17996 <td>Input clock</td>
17997 </tr>
17998 <tr class="row-even"><td>2</td>
17999 <td>DEV_WKUP_VTM0_FIX_REF_CLK</td>
18000 <td>Input clock</td>
18001 </tr>
18002 </tbody>
18003 </table>
18004 </div>
18005 </div>
18006 </div>
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