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 184 <h1>J721E Host Descriptions<a class="headerlink" href="#j721e-host-descriptions" title="Permalink to this headline">¶</a></h1>
 185 <div class="section" id="introduction">
 186 <span id="soc-doc-j721e-public-host-desc-intro"></span><h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
 187 <p>This chapter provides information of Host IDs that are permitted in
 188 the J721E SoC. These host IDs represent processing entities (or PEs)
 189 which is mandatory identification of a Host in a processor.</p>
 190 <p>Typically a host is a ‘compute entity’ which may be an actual
 191 processor or even a virtual machine. We just use host or processing
 192 entity to indicate the same thing.</p>
 193 </div>
 194 <div class="section" id="enumeration-of-host-ids">
 195 <span id="soc-doc-j721e-public-host-desc-host-list"></span><h2>Enumeration of Host IDs<a class="headerlink" href="#enumeration-of-host-ids" title="Permalink to this headline">¶</a></h2>
 196 <table border="1" class="docutils">
 197 <colgroup>
 198 <col width="13%" />
 199 <col width="15%" />
 200 <col width="23%" />
 201 <col width="49%" />
 202 </colgroup>
 203 <thead valign="bottom">
 204 <tr class="row-odd"><th class="head">Host ID</th>
 205 <th class="head">Host Name</th>
 206 <th class="head">Security Status</th>
 207 <th class="head">Description</th>
 208 </tr>
 209 </thead>
 210 <tbody valign="top">
 211 <tr class="row-even"><td>0</td>
 212 <td>DMSC</td>
 213 <td>Secure</td>
 214 <td>Security Controller</td>
 215 </tr>
 216 <tr class="row-odd"><td>254</td>
 217 <td>DM</td>
 218 <td>Non Secure</td>
 219 <td>Device Management</td>
 220 </tr>
 221 <tr class="row-even"><td>3</td>
 222 <td>MCU_0_R5_0</td>
 223 <td>Non Secure</td>
 224 <td>Cortex R5 context 0 on MCU island</td>
 225 </tr>
 226 <tr class="row-odd"><td>4</td>
 227 <td>MCU_0_R5_1</td>
 228 <td>Secure</td>
 229 <td>Cortex R5 context 1 on MCU island(Boot)</td>
 230 </tr>
 231 <tr class="row-even"><td>5</td>
 232 <td>MCU_0_R5_2</td>
 233 <td>Non Secure</td>
 234 <td>Cortex R5 context 2 on MCU island</td>
 235 </tr>
 236 <tr class="row-odd"><td>6</td>
 237 <td>MCU_0_R5_3</td>
 238 <td>Secure</td>
 239 <td>Cortex R5 context 3 on MCU island</td>
 240 </tr>
 241 <tr class="row-even"><td>10</td>
 242 <td>A72_0</td>
 243 <td>Secure</td>
 244 <td>Cortex A72 context 0 on Main island</td>
 245 </tr>
 246 <tr class="row-odd"><td>11</td>
 247 <td>A72_1</td>
 248 <td>Secure</td>
 249 <td>Cortex A72 context 1 on Main island</td>
 250 </tr>
 251 <tr class="row-even"><td>12</td>
 252 <td>A72_2</td>
 253 <td>Non Secure</td>
 254 <td>Cortex A72 context 2 on Main island</td>
 255 </tr>
 256 <tr class="row-odd"><td>13</td>
 257 <td>A72_3</td>
 258 <td>Non Secure</td>
 259 <td>Cortex A72 context 3 on Main island</td>
 260 </tr>
 261 <tr class="row-even"><td>14</td>
 262 <td>A72_4</td>
 263 <td>Non Secure</td>
 264 <td>Cortex A72 context 4 on Main island</td>
 265 </tr>
 266 <tr class="row-odd"><td>20</td>
 267 <td>C7X_0</td>
 268 <td>Secure</td>
 269 <td>C7x Context 0 on Main island</td>
 270 </tr>
 271 <tr class="row-even"><td>21</td>
 272 <td>C7X_1</td>
 273 <td>Non Secure</td>
 274 <td>C7x context 1 on Main island</td>
 275 </tr>
 276 <tr class="row-odd"><td>25</td>
 277 <td>C6X_0_0</td>
 278 <td>Secure</td>
 279 <td>C6x_0 Context 0 on Main island</td>
 280 </tr>
 281 <tr class="row-even"><td>26</td>
 282 <td>C6X_0_1</td>
 283 <td>Non Secure</td>
 284 <td>C6x_0 context 1 on Main island</td>
 285 </tr>
 286 <tr class="row-odd"><td>27</td>
 287 <td>C6X_1_0</td>
 288 <td>Secure</td>
 289 <td>C6x_1 Context 0 on Main island</td>
 290 </tr>
 291 <tr class="row-even"><td>28</td>
 292 <td>C6X_1_1</td>
 293 <td>Non Secure</td>
 294 <td>C6x_1 context 1 on Main island</td>
 295 </tr>
 296 <tr class="row-odd"><td>30</td>
 297 <td>GPU_0</td>
 298 <td>Non Secure</td>
 299 <td>RGX context 0 on Main island</td>
 300 </tr>
 301 <tr class="row-even"><td>35</td>
 302 <td>MAIN_0_R5_0</td>
 303 <td>Non Secure</td>
 304 <td>Cortex R5_0 context 0 on Main island</td>
 305 </tr>
 306 <tr class="row-odd"><td>36</td>
 307 <td>MAIN_0_R5_1</td>
 308 <td>Secure</td>
 309 <td>Cortex R5_0 context 1 on Main island</td>
 310 </tr>
 311 <tr class="row-even"><td>37</td>
 312 <td>MAIN_0_R5_2</td>
 313 <td>Non Secure</td>
 314 <td>Cortex R5_0 context 2 on Main island</td>
 315 </tr>
 316 <tr class="row-odd"><td>38</td>
 317 <td>MAIN_0_R5_3</td>
 318 <td>Secure</td>
 319 <td>Cortex R5_0 context 3 on MCU island</td>
 320 </tr>
 321 <tr class="row-even"><td>40</td>
 322 <td>MAIN_1_R5_0</td>
 323 <td>Non Secure</td>
 324 <td>Cortex R5_1 context 0 on Main island</td>
 325 </tr>
 326 <tr class="row-odd"><td>41</td>
 327 <td>MAIN_1_R5_1</td>
 328 <td>Secure</td>
 329 <td>Cortex R5_1 context 1 on Main island</td>
 330 </tr>
 331 <tr class="row-even"><td>42</td>
 332 <td>MAIN_1_R5_2</td>
 333 <td>Non Secure</td>
 334 <td>Cortex R5_1 context 2 on Main island</td>
 335 </tr>
 336 <tr class="row-odd"><td>43</td>
 337 <td>MAIN_1_R5_3</td>
 338 <td>Secure</td>
 339 <td>Cortex R5_1 context 3 on MCU island</td>
 340 </tr>
 341 <tr class="row-even"><td>50</td>
 342 <td>ICSSG_0</td>
 343 <td>Non Secure</td>
 344 <td>ICSSG context 0 on Main island</td>
 345 </tr>
 346 <tr class="row-odd"><td>250</td>
 347 <td>DM2DMSC</td>
 348 <td>Secure</td>
 349 <td>DM to DMSC communication</td>
 350 </tr>
 351 <tr class="row-even"><td>251</td>
 352 <td>DMSC2DM</td>
 353 <td>Non Secure</td>
 354 <td>DMSC to DM communication</td>
 355 </tr>
 356 </tbody>
 357 </table>
 358 <div class="admonition note">
 359 <p class="first admonition-title">Note</p>
 360 <ul class="last simple">
 361 <li>Description provides an intended purpose
 362 of the host ID, though on some systems,
 363 this might be used differently, backing memory and
 364 link allocations are made with the specified purpose
 365 in mind</li>
 366 <li>Security Status provides an intended purpose for the
 367 Host context</li>
 368 </ul>
 369 </div>
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