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 186 <h1>J721E Processor Descriptions<a class="headerlink" href="#j721e-processor-descriptions" title="Permalink to this headline">¶</a></h1>
 187 <div class="section" id="introduction">
 188 <span id="soc-doc-j721e-public-proc-desc-intro"></span><h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
 189 <p>This chapter provides information of Processor and Host IDs that are permitted
 190 in the J721E SoC. These Processor IDs represent an actual physical processor
 191 on the SoC.</p>
 192 <p>NOTE: This should not be confused with HOST_ID.</p>
 193 </div>
 194 <div class="section" id="enumeration-of-processor-ids">
 195 <span id="soc-doc-j721e-public-proc-desc-processors-list"></span><h2>Enumeration of Processor IDs<a class="headerlink" href="#enumeration-of-processor-ids" title="Permalink to this headline">¶</a></h2>
 196 <table border="1" class="docutils">
 197 <colgroup>
 198 <col width="15%" />
 199 <col width="17%" />
 200 <col width="68%" />
 201 </colgroup>
 202 <thead valign="bottom">
 203 <tr class="row-odd"><th class="head">Processor ID</th>
 204 <th class="head">Processor Name</th>
 205 <th class="head">Location in SoC</th>
 206 </tr>
 207 </thead>
 208 <tbody valign="top">
 209 <tr class="row-even"><td>0x20</td>
 210 <td>A72SS0_CORE0</td>
 211 <td>COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_DMSC_WRAP: (Cluster 0 Processor 0)</td>
 212 </tr>
 213 <tr class="row-odd"><td>0x21</td>
 214 <td>A72SS0_CORE1</td>
 215 <td>COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_DMSC_WRAP: (Cluster 0 Processor 1)</td>
 216 </tr>
 217 <tr class="row-even"><td>0x03</td>
 218 <td>C66SS0_CORE0</td>
 219 <td>J7_MAIN_SEC_MMR_MAIN_0: (Cluster 2 Processor 0)</td>
 220 </tr>
 221 <tr class="row-odd"><td>0x04</td>
 222 <td>C66SS1_CORE0</td>
 223 <td>J7_MAIN_SEC_MMR_MAIN_0: (Cluster 3 Processor 0)</td>
 224 </tr>
 225 <tr class="row-even"><td>0x30</td>
 226 <td>C71SS0</td>
 227 <td>COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_DMSC_WRAP: (Cluster 4 Processor 0)</td>
 228 </tr>
 229 <tr class="row-odd"><td>0x01</td>
 230 <td>MCU_R5FSS0_CORE0</td>
 231 <td>J7_MCU_SEC_MMR_MCU_0: (Cluster 0 Processor 0)</td>
 232 </tr>
 233 <tr class="row-even"><td>0x02</td>
 234 <td>MCU_R5FSS0_CORE1</td>
 235 <td>J7_MCU_SEC_MMR_MCU_0: (Cluster 0 Processor 1)</td>
 236 </tr>
 237 <tr class="row-odd"><td>0x06</td>
 238 <td>R5FSS0_CORE0</td>
 239 <td>J7_MAIN_SEC_MMR_MAIN_0: (Cluster 0 Processor 0)</td>
 240 </tr>
 241 <tr class="row-even"><td>0x07</td>
 242 <td>R5FSS0_CORE1</td>
 243 <td>J7_MAIN_SEC_MMR_MAIN_0: (Cluster 0 Processor 1)</td>
 244 </tr>
 245 <tr class="row-odd"><td>0x08</td>
 246 <td>R5FSS1_CORE0</td>
 247 <td>J7_MAIN_SEC_MMR_MAIN_0: (Cluster 1 Processor 0)</td>
 248 </tr>
 249 <tr class="row-even"><td>0x09</td>
 250 <td>R5FSS1_CORE1</td>
 251 <td>J7_MAIN_SEC_MMR_MAIN_0: (Cluster 1 Processor 1)</td>
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