packages/ti/drv/sciclient/soc/sysfw/binaries/system-firmware-public-documentation/5_soc_doc/j721e_legacy/psil_cfg.html

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 118 <li class="toctree-l3 current"><a class="current reference internal" href="#">J721E_LEGACY PSI-L Device Descriptions</a><ul>
 119 <li class="toctree-l4"><a class="reference internal" href="#introduction">Introduction</a></li>
 120 <li class="toctree-l4"><a class="reference internal" href="#psi-l-proxy-device-ids">PSI-L Proxy Device IDs</a></li>
 121 <li class="toctree-l4"><a class="reference internal" href="#psi-l-source-and-destination-thread-ids">PSI-L Source and Destination Thread IDs</a></li>
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 180   <div class="section" id="j721e-legacy-psi-l-device-descriptions">
 181 <h1>J721E_LEGACY PSI-L Device Descriptions<a class="headerlink" href="#j721e-legacy-psi-l-device-descriptions" title="Permalink to this headline">¶</a></h1>
 182 <div class="section" id="introduction">
 183 <h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
 184 <p>This chapter provides information on the PSI-L devices in the J721E_LEGACY SoC.
 185 Some System Firmware TISCI messages take device specific inputs. This chapter
 186 provides information on the valid values for PSI-L TISCI message parameters.</p>
 187 </div>
 188 <div class="section" id="psi-l-proxy-device-ids">
 189 <span id="pub-soc-j721e-legacy-psil-proxy-device-ids"></span><h2>PSI-L Proxy Device IDs<a class="headerlink" href="#psi-l-proxy-device-ids" title="Permalink to this headline">¶</a></h2>
 190 <p>Some System Firmware TISCI message APIs require the PSI-L Proxy device ID be
 191 provided as part of the request. Based on <a class="reference internal" href="devices.html"><span class="doc">J721E_LEGACY Device IDs</span></a> these are the valid PSI-L Proxy device IDs.</p>
 192 <table border="1" class="docutils">
 193 <colgroup>
 194 <col width="52%" />
 195 <col width="48%" />
 196 </colgroup>
 197 <thead valign="bottom">
 198 <tr class="row-odd"><th class="head">PSI-L Proxy Device Name</th>
 199 <th class="head">PSI-L Proxy Device ID</th>
 200 </tr>
 201 </thead>
 202 <tbody valign="top">
 203 <tr class="row-even"><td>J721E_DEV_NAVSS0</td>
 204 <td>199</td>
 205 </tr>
 206 <tr class="row-odd"><td>J721E_DEV_MCU_NAVSS0</td>
 207 <td>232</td>
 208 </tr>
 209 </tbody>
 210 </table>
 211 </div>
 212 <div class="section" id="psi-l-source-and-destination-thread-ids">
 213 <span id="pub-soc-j721e-legacy-psil-thread-ids"></span><h2>PSI-L Source and Destination Thread IDs<a class="headerlink" href="#psi-l-source-and-destination-thread-ids" title="Permalink to this headline">¶</a></h2>
 214 <p>This section describes valid PSI-L source and destination thread IDs for each
 215 thread type. The thread IDs are used in the PSI-L based TISCI messages.</p>
 216 <div class="admonition warning">
 217 <p class="first admonition-title">Warning</p>
 218 <p class="last">PSI-L threads marked as reserved for use by DMSC <strong>cannot</strong> be linked to
 219 another thread.</p>
 220 </div>
 221 <table border="1" class="docutils">
 222 <colgroup>
 223 <col width="68%" />
 224 <col width="32%" />
 225 </colgroup>
 226 <thead valign="bottom">
 227 <tr class="row-odd"><th class="head">Thread Type</th>
 228 <th class="head">Thread Range</th>
 229 </tr>
 230 </thead>
 231 <tbody valign="top">
 232 <tr class="row-even"><td>udmap0_trstrm_tx</td>
 233 <td>0x8 to 0x8</td>
 234 </tr>
 235 <tr class="row-odd"><td>udmap0_cfgstrm_tx</td>
 236 <td>0x20 to 0x20</td>
 237 </tr>
 238 <tr class="row-even"><td>navss_main_udmap0_tx</td>
 239 <td>0x1000 to 0x108b</td>
 240 </tr>
 241 <tr class="row-odd"><td>navss_main_saul0_rx</td>
 242 <td>0x4000 to 0x4003</td>
 243 </tr>
 244 <tr class="row-even"><td>navss_main_icssg0_rx</td>
 245 <td>0x4100 to 0x4104</td>
 246 </tr>
 247 <tr class="row-odd"><td>navss_main_icssg1_rx</td>
 248 <td>0x4200 to 0x4204</td>
 249 </tr>
 250 <tr class="row-even"><td>navss_main_pdma_main_debug_ccmcu_rx</td>
 251 <td>0x4300 to 0x4302</td>
 252 </tr>
 253 <tr class="row-odd"><td>navss_main_pdma_main_debug_mainc66_rx</td>
 254 <td>0x4304 to 0x4305</td>
 255 </tr>
 256 <tr class="row-even"><td>navss_main_pdma_main_mcasp_g0_rx</td>
 257 <td>0x4400 to 0x4402</td>
 258 </tr>
 259 <tr class="row-odd"><td>navss_main_pdma_main_aasrc_rx</td>
 260 <td>0x4404 to 0x440b</td>
 261 </tr>
 262 <tr class="row-even"><td>navss_main_pdma_main_mcasp_g1_rx</td>
 263 <td>0x4500 to 0x4508</td>
 264 </tr>
 265 <tr class="row-odd"><td>navss_main_pdma_main_misc_g0_rx</td>
 266 <td>0x4600 to 0x460a</td>
 267 </tr>
 268 <tr class="row-even"><td>navss_main_pdma_main_misc_g1_rx</td>
 269 <td>0x460c to 0x4616</td>
 270 </tr>
 271 <tr class="row-odd"><td>navss_main_pdma_main_misc_g2_rx</td>
 272 <td>0x4618 to 0x4622</td>
 273 </tr>
 274 <tr class="row-even"><td>navss_main_pdma_main_misc_g3_rx</td>
 275 <td>0x4624 to 0x462e</td>
 276 </tr>
 277 <tr class="row-odd"><td>navss_main_pdma_main_usart_g0_rx</td>
 278 <td>0x4700 to 0x4701</td>
 279 </tr>
 280 <tr class="row-even"><td>navss_main_pdma_main_usart_g1_rx</td>
 281 <td>0x4702 to 0x4703</td>
 282 </tr>
 283 <tr class="row-odd"><td>navss_main_pdma_main_usart_g2_rx</td>
 284 <td>0x4704 to 0x4709</td>
 285 </tr>
 286 <tr class="row-even"><td>navss_main_pdma_main_mcan_rx</td>
 287 <td>0x470c to 0x4729</td>
 288 </tr>
 289 <tr class="row-odd"><td>navss_main_msmc0_rx</td>
 290 <td>0x4800 to 0x481f</td>
 291 </tr>
 292 <tr class="row-even"><td>navss_main_vpac_tc0_cc_rx</td>
 293 <td>0x4820 to 0x483f</td>
 294 </tr>
 295 <tr class="row-odd"><td>navss_main_vpac_tc1_cc_rx</td>
 296 <td>0x4840 to 0x487f</td>
 297 </tr>
 298 <tr class="row-even"><td>navss_main_dmpac_tc0_cc_rx</td>
 299 <td>0x4880 to 0x489f</td>
 300 </tr>
 301 <tr class="row-odd"><td>navss_main_csi_rx</td>
 302 <td>0x4900 to 0x49ff</td>
 303 </tr>
 304 <tr class="row-even"><td>navss_main_cpsw9_rx</td>
 305 <td>0x4a00 to 0x4a00</td>
 306 </tr>
 307 <tr class="row-odd"><td>navss_mcu_udmap0_tx</td>
 308 <td>0x6000 to 0x602d</td>
 309 </tr>
 310 <tr class="row-even"><td>navss_mcu_udmap0_tx
 311 (<strong>Reserved by System Firmware</strong>)</td>
 312 <td>0x602e to 0x602f</td>
 313 </tr>
 314 <tr class="row-odd"><td>navss_mcu_pdma_cpsw0_rx</td>
 315 <td>0x7000 to 0x7000</td>
 316 </tr>
 317 <tr class="row-even"><td>navss_mcu_pdma_mcu0_rx</td>
 318 <td>0x7100 to 0x7106</td>
 319 </tr>
 320 <tr class="row-odd"><td>navss_mcu_pdma_mcu1_rx</td>
 321 <td>0x7200 to 0x7207</td>
 322 </tr>
 323 <tr class="row-even"><td>navss_mcu_pdma_mcu2_rx</td>
 324 <td>0x7300 to 0x7303</td>
 325 </tr>
 326 <tr class="row-odd"><td>navss_mcu_pdma_adc_rx</td>
 327 <td>0x7400 to 0x7403</td>
 328 </tr>
 329 <tr class="row-even"><td>navss_mcu_saul0_rx
 330 (<strong>Reserved by System Firmware</strong>)</td>
 331 <td>0x7500 to 0x7501</td>
 332 </tr>
 333 <tr class="row-odd"><td>navss_mcu_saul0_rx</td>
 334 <td>0x7502 to 0x7503</td>
 335 </tr>
 336 <tr class="row-even"><td>navss_main_udmap0_rx</td>
 337 <td>0x9000 to 0x908b</td>
 338 </tr>
 339 <tr class="row-odd"><td>navss_main_saul0_tx</td>
 340 <td>0xc000 to 0xc001</td>
 341 </tr>
 342 <tr class="row-even"><td>navss_main_icssg0_tx</td>
 343 <td>0xc100 to 0xc108</td>
 344 </tr>
 345 <tr class="row-odd"><td>navss_main_icssg1_tx</td>
 346 <td>0xc200 to 0xc208</td>
 347 </tr>
 348 <tr class="row-even"><td>navss_main_pdma_main_mcasp_g0_tx</td>
 349 <td>0xc400 to 0xc402</td>
 350 </tr>
 351 <tr class="row-odd"><td>navss_main_pdma_main_aasrc_tx</td>
 352 <td>0xc404 to 0xc40b</td>
 353 </tr>
 354 <tr class="row-even"><td>navss_main_pdma_main_mcasp_g1_tx</td>
 355 <td>0xc500 to 0xc508</td>
 356 </tr>
 357 <tr class="row-odd"><td>navss_main_pdma_main_misc_g0_tx</td>
 358 <td>0xc600 to 0xc60a</td>
 359 </tr>
 360 <tr class="row-even"><td>navss_main_pdma_main_misc_g1_tx</td>
 361 <td>0xc60c to 0xc616</td>
 362 </tr>
 363 <tr class="row-odd"><td>navss_main_pdma_main_misc_g2_tx</td>
 364 <td>0xc618 to 0xc622</td>
 365 </tr>
 366 <tr class="row-even"><td>navss_main_pdma_main_misc_g3_tx</td>
 367 <td>0xc624 to 0xc62e</td>
 368 </tr>
 369 <tr class="row-odd"><td>navss_main_pdma_main_usart_g0_tx</td>
 370 <td>0xc700 to 0xc701</td>
 371 </tr>
 372 <tr class="row-even"><td>navss_main_pdma_main_usart_g1_tx</td>
 373 <td>0xc702 to 0xc703</td>
 374 </tr>
 375 <tr class="row-odd"><td>navss_main_pdma_main_usart_g2_tx</td>
 376 <td>0xc704 to 0xc709</td>
 377 </tr>
 378 <tr class="row-even"><td>navss_main_pdma_main_mcan_tx</td>
 379 <td>0xc70c to 0xc729</td>
 380 </tr>
 381 <tr class="row-odd"><td>navss_main_msmc0_tx</td>
 382 <td>0xc800 to 0xc81f</td>
 383 </tr>
 384 <tr class="row-even"><td>navss_main_vpac_tc0_cc_tx</td>
 385 <td>0xc820 to 0xc83f</td>
 386 </tr>
 387 <tr class="row-odd"><td>navss_main_vpac_tc1_cc_tx</td>
 388 <td>0xc840 to 0xc87f</td>
 389 </tr>
 390 <tr class="row-even"><td>navss_main_dmpac_tc0_cc_tx</td>
 391 <td>0xc880 to 0xc89f</td>
 392 </tr>
 393 <tr class="row-odd"><td>navss_main_csi_tx</td>
 394 <td>0xc900 to 0xc9ff</td>
 395 </tr>
 396 <tr class="row-even"><td>navss_main_cpsw9_tx</td>
 397 <td>0xca00 to 0xca07</td>
 398 </tr>
 399 <tr class="row-odd"><td>navss_mcu_udmap0_rx</td>
 400 <td>0xe000 to 0xe02c</td>
 401 </tr>
 402 <tr class="row-even"><td>navss_mcu_udmap0_rx
 403 (<strong>Reserved by System Firmware</strong>)</td>
 404 <td>0xe02d to 0xe02f</td>
 405 </tr>
 406 <tr class="row-odd"><td>navss_mcu_pdma_cpsw0_tx</td>
 407 <td>0xf000 to 0xf007</td>
 408 </tr>
 409 <tr class="row-even"><td>navss_mcu_pdma_mcu0_tx</td>
 410 <td>0xf100 to 0xf106</td>
 411 </tr>
 412 <tr class="row-odd"><td>navss_mcu_pdma_mcu1_tx</td>
 413 <td>0xf200 to 0xf207</td>
 414 </tr>
 415 <tr class="row-even"><td>navss_mcu_pdma_mcu2_tx</td>
 416 <td>0xf300 to 0xf303</td>
 417 </tr>
 418 <tr class="row-odd"><td>navss_mcu_pdma_adc_tx</td>
 419 <td>0xf400 to 0xf3ff</td>
 420 </tr>
 421 <tr class="row-even"><td>navss_mcu_saul0_tx
 422 (<strong>Reserved by System Firmware</strong>)</td>
 423 <td>0xf500 to 0xf500</td>
 424 </tr>
 425 <tr class="row-odd"><td>navss_mcu_saul0_tx</td>
 426 <td>0xf501 to 0xf501</td>
 427 </tr>
 428 </tbody>
 429 </table>
 430 </div>
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