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 120 <li class="toctree-l4"><a class="reference internal" href="#clock-for-j784s4-device">Clock for J784S4 Device</a></li>
 121 <li class="toctree-l4"><a class="reference internal" href="#device-wise-clock-id-list-for-j784s4-soc">Device wise clock ID list for J784S4 SoC</a></li>
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 184   <div class="section" id="j784s4-clock-identifiers">
 185 <h1>J784S4 Clock Identifiers<a class="headerlink" href="#j784s4-clock-identifiers" title="Permalink to this headline">¶</a></h1>
 186 <div class="section" id="clock-for-j784s4-device">
 187 <span id="soc-doc-j784s4-public-clks-desc-intro"></span><h2>Clock for J784S4 Device<a class="headerlink" href="#clock-for-j784s4-device" title="Permalink to this headline">¶</a></h2>
 188 <p>This chapter provides information on clock IDs that identify clocks
 189 incoming and outgoing from devices identified via
 190 <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">device IDs</span></a>
 191 in J784S4 SoC.</p>
 192 <p>TISCI message Power Management APIs define a device ID and clock ID as
 193 parameters allowing a user to specify granular control of clocks
 194 for a particular SoC subsystem.</p>
 195 </div>
 196 <div class="section" id="device-wise-clock-id-list-for-j784s4-soc">
 197 <span id="soc-doc-j784s4-public-clks-dev-list"></span><h2>Device wise clock ID list for J784S4 SoC<a class="headerlink" href="#device-wise-clock-id-list-for-j784s4-soc" title="Permalink to this headline">¶</a></h2>
 198 <p>This is an enumerated list of clocks per device ID that can be
 199 controlled via the power management clock APIs</p>
 200 <p>The following table describes functions implemented by clocks</p>
 201 <table border="1" class="docutils">
 202 <colgroup>
 203 <col width="27%" />
 204 <col width="73%" />
 205 </colgroup>
 206 <thead valign="bottom">
 207 <tr class="row-odd"><th class="head">Function</th>
 208 <th class="head">Description</th>
 209 </tr>
 210 </thead>
 211 <tbody valign="top">
 212 <tr class="row-even"><td>Input clock</td>
 213 <td>Clock input to the SoC subsystem</td>
 214 </tr>
 215 <tr class="row-odd"><td>Output clock</td>
 216 <td>Clock output from the SoC subsystem</td>
 217 </tr>
 218 <tr class="row-even"><td>Input muxed clock</td>
 219 <td>Clock input to the SoC subsystem, but can choose one of the parent clocks as a clock source</td>
 220 </tr>
 221 <tr class="row-odd"><td>Parent input clock option to XYZ</td>
 222 <td>One of the parent clocks that can be used as a source clock to a input muxed clock</td>
 223 </tr>
 224 </tbody>
 225 </table>
 226 <p>Also note: There are devices which do not have clock information.
 227 These do have chapters in this document associated with them, however, these would be marked as:</p>
 228 <p><strong>This device has no defined clocks.</strong></p>
 229 <p>The chapters corresponding to the devices are organized alphabetically per device name for ease of readability.</p>
 230 <div class="section" id="clocks-for-a72ss0-device">
 231 <span id="soc-doc-j784s4-public-clks-a72ss0"></span><h3>Clocks for A72SS0 Device<a class="headerlink" href="#clocks-for-a72ss0-device" title="Permalink to this headline">¶</a></h3>
 232 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_A72SS0</span></a> (ID = 7)</p>
 233 <p>Following is a mapping of Clocks IDs to function:</p>
 234 <table border="1" class="docutils">
 235 <colgroup>
 236 <col width="18%" />
 237 <col width="62%" />
 238 <col width="21%" />
 239 </colgroup>
 240 <thead valign="bottom">
 241 <tr class="row-odd"><th class="head">Clock ID</th>
 242 <th class="head">Name</th>
 243 <th class="head">Function</th>
 244 </tr>
 245 </thead>
 246 <tbody valign="top">
 247 <tr class="row-even"><td>0</td>
 248 <td>DEV_A72SS0_ARM0_CLK_CLK</td>
 249 <td>Input clock</td>
 250 </tr>
 251 <tr class="row-odd"><td>2</td>
 252 <td>DEV_A72SS0_ARM0_DIVH_CLK8_OBSCLK_OUT_CLK</td>
 253 <td>Output clock</td>
 254 </tr>
 255 <tr class="row-even"><td>3</td>
 256 <td>DEV_A72SS0_ARM0_MSMC_CLK_CLK</td>
 257 <td>Input clock</td>
 258 </tr>
 259 <tr class="row-odd"><td>4</td>
 260 <td>DEV_A72SS0_ARM0_PLL_CTRL_CLK_CLK</td>
 261 <td>Input clock</td>
 262 </tr>
 263 </tbody>
 264 </table>
 265 </div>
 266 <div class="section" id="clocks-for-a72ss0-core0-device">
 267 <span id="soc-doc-j784s4-public-clks-a72ss0-core0"></span><h3>Clocks for A72SS0_CORE0 Device<a class="headerlink" href="#clocks-for-a72ss0-core0-device" title="Permalink to this headline">¶</a></h3>
 268 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_A72SS0_CORE0</span></a> (ID = 9)</p>
 269 <p>Following is a mapping of Clocks IDs to function:</p>
 270 <table border="1" class="docutils">
 271 <colgroup>
 272 <col width="21%" />
 273 <col width="55%" />
 274 <col width="23%" />
 275 </colgroup>
 276 <thead valign="bottom">
 277 <tr class="row-odd"><th class="head">Clock ID</th>
 278 <th class="head">Name</th>
 279 <th class="head">Function</th>
 280 </tr>
 281 </thead>
 282 <tbody valign="top">
 283 <tr class="row-even"><td>0</td>
 284 <td>DEV_A72SS0_CORE0_ARM0_CLK_CLK</td>
 285 <td>Input clock</td>
 286 </tr>
 287 </tbody>
 288 </table>
 289 </div>
 290 <div class="section" id="clocks-for-a72ss0-core1-device">
 291 <span id="soc-doc-j784s4-public-clks-a72ss0-core1"></span><h3>Clocks for A72SS0_CORE1 Device<a class="headerlink" href="#clocks-for-a72ss0-core1-device" title="Permalink to this headline">¶</a></h3>
 292 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_A72SS0_CORE1</span></a> (ID = 10)</p>
 293 <p>Following is a mapping of Clocks IDs to function:</p>
 294 <table border="1" class="docutils">
 295 <colgroup>
 296 <col width="21%" />
 297 <col width="55%" />
 298 <col width="23%" />
 299 </colgroup>
 300 <thead valign="bottom">
 301 <tr class="row-odd"><th class="head">Clock ID</th>
 302 <th class="head">Name</th>
 303 <th class="head">Function</th>
 304 </tr>
 305 </thead>
 306 <tbody valign="top">
 307 <tr class="row-even"><td>0</td>
 308 <td>DEV_A72SS0_CORE1_ARM0_CLK_CLK</td>
 309 <td>Input clock</td>
 310 </tr>
 311 </tbody>
 312 </table>
 313 </div>
 314 <div class="section" id="clocks-for-a72ss0-core2-device">
 315 <span id="soc-doc-j784s4-public-clks-a72ss0-core2"></span><h3>Clocks for A72SS0_CORE2 Device<a class="headerlink" href="#clocks-for-a72ss0-core2-device" title="Permalink to this headline">¶</a></h3>
 316 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_A72SS0_CORE2</span></a> (ID = 11)</p>
 317 <p>Following is a mapping of Clocks IDs to function:</p>
 318 <table border="1" class="docutils">
 319 <colgroup>
 320 <col width="21%" />
 321 <col width="55%" />
 322 <col width="23%" />
 323 </colgroup>
 324 <thead valign="bottom">
 325 <tr class="row-odd"><th class="head">Clock ID</th>
 326 <th class="head">Name</th>
 327 <th class="head">Function</th>
 328 </tr>
 329 </thead>
 330 <tbody valign="top">
 331 <tr class="row-even"><td>0</td>
 332 <td>DEV_A72SS0_CORE2_ARM0_CLK_CLK</td>
 333 <td>Input clock</td>
 334 </tr>
 335 </tbody>
 336 </table>
 337 </div>
 338 <div class="section" id="clocks-for-a72ss0-core3-device">
 339 <span id="soc-doc-j784s4-public-clks-a72ss0-core3"></span><h3>Clocks for A72SS0_CORE3 Device<a class="headerlink" href="#clocks-for-a72ss0-core3-device" title="Permalink to this headline">¶</a></h3>
 340 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_A72SS0_CORE3</span></a> (ID = 12)</p>
 341 <p>Following is a mapping of Clocks IDs to function:</p>
 342 <table border="1" class="docutils">
 343 <colgroup>
 344 <col width="21%" />
 345 <col width="55%" />
 346 <col width="23%" />
 347 </colgroup>
 348 <thead valign="bottom">
 349 <tr class="row-odd"><th class="head">Clock ID</th>
 350 <th class="head">Name</th>
 351 <th class="head">Function</th>
 352 </tr>
 353 </thead>
 354 <tbody valign="top">
 355 <tr class="row-even"><td>0</td>
 356 <td>DEV_A72SS0_CORE3_ARM0_CLK_CLK</td>
 357 <td>Input clock</td>
 358 </tr>
 359 </tbody>
 360 </table>
 361 </div>
 362 <div class="section" id="clocks-for-a72ss1-device">
 363 <span id="soc-doc-j784s4-public-clks-a72ss1"></span><h3>Clocks for A72SS1 Device<a class="headerlink" href="#clocks-for-a72ss1-device" title="Permalink to this headline">¶</a></h3>
 364 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_A72SS1</span></a> (ID = 8)</p>
 365 <p>Following is a mapping of Clocks IDs to function:</p>
 366 <table border="1" class="docutils">
 367 <colgroup>
 368 <col width="18%" />
 369 <col width="62%" />
 370 <col width="21%" />
 371 </colgroup>
 372 <thead valign="bottom">
 373 <tr class="row-odd"><th class="head">Clock ID</th>
 374 <th class="head">Name</th>
 375 <th class="head">Function</th>
 376 </tr>
 377 </thead>
 378 <tbody valign="top">
 379 <tr class="row-even"><td>0</td>
 380 <td>DEV_A72SS1_ARM1_CLK_CLK</td>
 381 <td>Input clock</td>
 382 </tr>
 383 <tr class="row-odd"><td>2</td>
 384 <td>DEV_A72SS1_ARM1_DIVH_CLK8_OBSCLK_OUT_CLK</td>
 385 <td>Output clock</td>
 386 </tr>
 387 <tr class="row-even"><td>6</td>
 388 <td>DEV_A72SS1_ARM1_PLL_CTRL_CLK_CLK</td>
 389 <td>Input clock</td>
 390 </tr>
 391 </tbody>
 392 </table>
 393 </div>
 394 <div class="section" id="clocks-for-a72ss1-core0-device">
 395 <span id="soc-doc-j784s4-public-clks-a72ss1-core0"></span><h3>Clocks for A72SS1_CORE0 Device<a class="headerlink" href="#clocks-for-a72ss1-core0-device" title="Permalink to this headline">¶</a></h3>
 396 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_A72SS1_CORE0</span></a> (ID = 13)</p>
 397 <p>Following is a mapping of Clocks IDs to function:</p>
 398 <table border="1" class="docutils">
 399 <colgroup>
 400 <col width="21%" />
 401 <col width="55%" />
 402 <col width="23%" />
 403 </colgroup>
 404 <thead valign="bottom">
 405 <tr class="row-odd"><th class="head">Clock ID</th>
 406 <th class="head">Name</th>
 407 <th class="head">Function</th>
 408 </tr>
 409 </thead>
 410 <tbody valign="top">
 411 <tr class="row-even"><td>0</td>
 412 <td>DEV_A72SS1_CORE0_ARM1_CLK_CLK</td>
 413 <td>Input clock</td>
 414 </tr>
 415 </tbody>
 416 </table>
 417 </div>
 418 <div class="section" id="clocks-for-a72ss1-core1-device">
 419 <span id="soc-doc-j784s4-public-clks-a72ss1-core1"></span><h3>Clocks for A72SS1_CORE1 Device<a class="headerlink" href="#clocks-for-a72ss1-core1-device" title="Permalink to this headline">¶</a></h3>
 420 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_A72SS1_CORE1</span></a> (ID = 14)</p>
 421 <p>Following is a mapping of Clocks IDs to function:</p>
 422 <table border="1" class="docutils">
 423 <colgroup>
 424 <col width="21%" />
 425 <col width="55%" />
 426 <col width="23%" />
 427 </colgroup>
 428 <thead valign="bottom">
 429 <tr class="row-odd"><th class="head">Clock ID</th>
 430 <th class="head">Name</th>
 431 <th class="head">Function</th>
 432 </tr>
 433 </thead>
 434 <tbody valign="top">
 435 <tr class="row-even"><td>0</td>
 436 <td>DEV_A72SS1_CORE1_ARM1_CLK_CLK</td>
 437 <td>Input clock</td>
 438 </tr>
 439 </tbody>
 440 </table>
 441 </div>
 442 <div class="section" id="clocks-for-a72ss1-core2-device">
 443 <span id="soc-doc-j784s4-public-clks-a72ss1-core2"></span><h3>Clocks for A72SS1_CORE2 Device<a class="headerlink" href="#clocks-for-a72ss1-core2-device" title="Permalink to this headline">¶</a></h3>
 444 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_A72SS1_CORE2</span></a> (ID = 15)</p>
 445 <p>Following is a mapping of Clocks IDs to function:</p>
 446 <table border="1" class="docutils">
 447 <colgroup>
 448 <col width="21%" />
 449 <col width="55%" />
 450 <col width="23%" />
 451 </colgroup>
 452 <thead valign="bottom">
 453 <tr class="row-odd"><th class="head">Clock ID</th>
 454 <th class="head">Name</th>
 455 <th class="head">Function</th>
 456 </tr>
 457 </thead>
 458 <tbody valign="top">
 459 <tr class="row-even"><td>0</td>
 460 <td>DEV_A72SS1_CORE2_ARM1_CLK_CLK</td>
 461 <td>Input clock</td>
 462 </tr>
 463 </tbody>
 464 </table>
 465 </div>
 466 <div class="section" id="clocks-for-a72ss1-core3-device">
 467 <span id="soc-doc-j784s4-public-clks-a72ss1-core3"></span><h3>Clocks for A72SS1_CORE3 Device<a class="headerlink" href="#clocks-for-a72ss1-core3-device" title="Permalink to this headline">¶</a></h3>
 468 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_A72SS1_CORE3</span></a> (ID = 16)</p>
 469 <p>Following is a mapping of Clocks IDs to function:</p>
 470 <table border="1" class="docutils">
 471 <colgroup>
 472 <col width="21%" />
 473 <col width="55%" />
 474 <col width="23%" />
 475 </colgroup>
 476 <thead valign="bottom">
 477 <tr class="row-odd"><th class="head">Clock ID</th>
 478 <th class="head">Name</th>
 479 <th class="head">Function</th>
 480 </tr>
 481 </thead>
 482 <tbody valign="top">
 483 <tr class="row-even"><td>0</td>
 484 <td>DEV_A72SS1_CORE3_ARM1_CLK_CLK</td>
 485 <td>Input clock</td>
 486 </tr>
 487 </tbody>
 488 </table>
 489 </div>
 490 <div class="section" id="clocks-for-aggr-atb0-device">
 491 <span id="soc-doc-j784s4-public-clks-aggr-atb0"></span><h3>Clocks for AGGR_ATB0 Device<a class="headerlink" href="#clocks-for-aggr-atb0-device" title="Permalink to this headline">¶</a></h3>
 492 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_AGGR_ATB0</span></a> (ID = 186)</p>
 493 <p>Following is a mapping of Clocks IDs to function:</p>
 494 <table border="1" class="docutils">
 495 <colgroup>
 496 <col width="25%" />
 497 <col width="48%" />
 498 <col width="27%" />
 499 </colgroup>
 500 <thead valign="bottom">
 501 <tr class="row-odd"><th class="head">Clock ID</th>
 502 <th class="head">Name</th>
 503 <th class="head">Function</th>
 504 </tr>
 505 </thead>
 506 <tbody valign="top">
 507 <tr class="row-even"><td>0</td>
 508 <td>DEV_AGGR_ATB0_DBG_CLK</td>
 509 <td>Input clock</td>
 510 </tr>
 511 </tbody>
 512 </table>
 513 </div>
 514 <div class="section" id="clocks-for-atl0-device">
 515 <span id="soc-doc-j784s4-public-clks-atl0"></span><h3>Clocks for ATL0 Device<a class="headerlink" href="#clocks-for-atl0-device" title="Permalink to this headline">¶</a></h3>
 516 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_ATL0</span></a> (ID = 2)</p>
 517 <p>Following is a mapping of Clocks IDs to function:</p>
 518 <table border="1" class="docutils">
 519 <colgroup>
 520 <col width="9%" />
 521 <col width="50%" />
 522 <col width="41%" />
 523 </colgroup>
 524 <thead valign="bottom">
 525 <tr class="row-odd"><th class="head">Clock ID</th>
 526 <th class="head">Name</th>
 527 <th class="head">Function</th>
 528 </tr>
 529 </thead>
 530 <tbody valign="top">
 531 <tr class="row-even"><td>0</td>
 532 <td>DEV_ATL0_ATL_CLK</td>
 533 <td>Input muxed clock</td>
 534 </tr>
 535 <tr class="row-odd"><td>1</td>
 536 <td>DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK</td>
 537 <td>Parent input clock option to DEV_ATL0_ATL_CLK</td>
 538 </tr>
 539 <tr class="row-even"><td>2</td>
 540 <td>DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
 541 <td>Parent input clock option to DEV_ATL0_ATL_CLK</td>
 542 </tr>
 543 <tr class="row-odd"><td>5</td>
 544 <td>DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK</td>
 545 <td>Parent input clock option to DEV_ATL0_ATL_CLK</td>
 546 </tr>
 547 <tr class="row-even"><td>6</td>
 548 <td>DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
 549 <td>Parent input clock option to DEV_ATL0_ATL_CLK</td>
 550 </tr>
 551 <tr class="row-odd"><td>7</td>
 552 <td>DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
 553 <td>Parent input clock option to DEV_ATL0_ATL_CLK</td>
 554 </tr>
 555 <tr class="row-even"><td>9</td>
 556 <td>DEV_ATL0_ATL_IO_PORT_ATCLK_OUT</td>
 557 <td>Output clock</td>
 558 </tr>
 559 <tr class="row-odd"><td>10</td>
 560 <td>DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1</td>
 561 <td>Output clock</td>
 562 </tr>
 563 <tr class="row-even"><td>11</td>
 564 <td>DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2</td>
 565 <td>Output clock</td>
 566 </tr>
 567 <tr class="row-odd"><td>12</td>
 568 <td>DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3</td>
 569 <td>Output clock</td>
 570 </tr>
 571 <tr class="row-even"><td>13</td>
 572 <td>DEV_ATL0_ATL_IO_PORT_AWS</td>
 573 <td>Input muxed clock</td>
 574 </tr>
 575 <tr class="row-odd"><td>14</td>
 576 <td>DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT</td>
 577 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS</td>
 578 </tr>
 579 <tr class="row-even"><td>15</td>
 580 <td>DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT</td>
 581 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS</td>
 582 </tr>
 583 <tr class="row-odd"><td>16</td>
 584 <td>DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0</td>
 585 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS</td>
 586 </tr>
 587 <tr class="row-even"><td>17</td>
 588 <td>DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0</td>
 589 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS</td>
 590 </tr>
 591 <tr class="row-odd"><td>18</td>
 592 <td>DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0</td>
 593 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS</td>
 594 </tr>
 595 <tr class="row-even"><td>26</td>
 596 <td>DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0</td>
 597 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS</td>
 598 </tr>
 599 <tr class="row-odd"><td>27</td>
 600 <td>DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0</td>
 601 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS</td>
 602 </tr>
 603 <tr class="row-even"><td>28</td>
 604 <td>DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT</td>
 605 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS</td>
 606 </tr>
 607 <tr class="row-odd"><td>29</td>
 608 <td>DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT</td>
 609 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS</td>
 610 </tr>
 611 <tr class="row-even"><td>30</td>
 612 <td>DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT</td>
 613 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS</td>
 614 </tr>
 615 <tr class="row-odd"><td>38</td>
 616 <td>DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
 617 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS</td>
 618 </tr>
 619 <tr class="row-even"><td>39</td>
 620 <td>DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
 621 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS</td>
 622 </tr>
 623 <tr class="row-odd"><td>46</td>
 624 <td>DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 625 <td>Input muxed clock</td>
 626 </tr>
 627 <tr class="row-even"><td>47</td>
 628 <td>DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT</td>
 629 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 630 </tr>
 631 <tr class="row-odd"><td>48</td>
 632 <td>DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT</td>
 633 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 634 </tr>
 635 <tr class="row-even"><td>49</td>
 636 <td>DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0</td>
 637 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 638 </tr>
 639 <tr class="row-odd"><td>50</td>
 640 <td>DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0</td>
 641 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 642 </tr>
 643 <tr class="row-even"><td>51</td>
 644 <td>DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0</td>
 645 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 646 </tr>
 647 <tr class="row-odd"><td>59</td>
 648 <td>DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0</td>
 649 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 650 </tr>
 651 <tr class="row-even"><td>60</td>
 652 <td>DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0</td>
 653 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 654 </tr>
 655 <tr class="row-odd"><td>61</td>
 656 <td>DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT</td>
 657 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 658 </tr>
 659 <tr class="row-even"><td>62</td>
 660 <td>DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT</td>
 661 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 662 </tr>
 663 <tr class="row-odd"><td>63</td>
 664 <td>DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT</td>
 665 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 666 </tr>
 667 <tr class="row-even"><td>71</td>
 668 <td>DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
 669 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 670 </tr>
 671 <tr class="row-odd"><td>72</td>
 672 <td>DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
 673 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_1</td>
 674 </tr>
 675 <tr class="row-even"><td>85</td>
 676 <td>DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 677 <td>Input muxed clock</td>
 678 </tr>
 679 <tr class="row-odd"><td>86</td>
 680 <td>DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT</td>
 681 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 682 </tr>
 683 <tr class="row-even"><td>87</td>
 684 <td>DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT</td>
 685 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 686 </tr>
 687 <tr class="row-odd"><td>88</td>
 688 <td>DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0</td>
 689 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 690 </tr>
 691 <tr class="row-even"><td>89</td>
 692 <td>DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0</td>
 693 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 694 </tr>
 695 <tr class="row-odd"><td>90</td>
 696 <td>DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0</td>
 697 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 698 </tr>
 699 <tr class="row-even"><td>98</td>
 700 <td>DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0</td>
 701 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 702 </tr>
 703 <tr class="row-odd"><td>99</td>
 704 <td>DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0</td>
 705 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 706 </tr>
 707 <tr class="row-even"><td>100</td>
 708 <td>DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT</td>
 709 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 710 </tr>
 711 <tr class="row-odd"><td>101</td>
 712 <td>DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT</td>
 713 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 714 </tr>
 715 <tr class="row-even"><td>102</td>
 716 <td>DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT</td>
 717 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 718 </tr>
 719 <tr class="row-odd"><td>110</td>
 720 <td>DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
 721 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 722 </tr>
 723 <tr class="row-even"><td>111</td>
 724 <td>DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
 725 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_2</td>
 726 </tr>
 727 <tr class="row-odd"><td>118</td>
 728 <td>DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 729 <td>Input muxed clock</td>
 730 </tr>
 731 <tr class="row-even"><td>119</td>
 732 <td>DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT</td>
 733 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 734 </tr>
 735 <tr class="row-odd"><td>120</td>
 736 <td>DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT</td>
 737 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 738 </tr>
 739 <tr class="row-even"><td>121</td>
 740 <td>DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0</td>
 741 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 742 </tr>
 743 <tr class="row-odd"><td>122</td>
 744 <td>DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0</td>
 745 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 746 </tr>
 747 <tr class="row-even"><td>123</td>
 748 <td>DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0</td>
 749 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 750 </tr>
 751 <tr class="row-odd"><td>131</td>
 752 <td>DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0</td>
 753 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 754 </tr>
 755 <tr class="row-even"><td>132</td>
 756 <td>DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0</td>
 757 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 758 </tr>
 759 <tr class="row-odd"><td>133</td>
 760 <td>DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT</td>
 761 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 762 </tr>
 763 <tr class="row-even"><td>134</td>
 764 <td>DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT</td>
 765 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 766 </tr>
 767 <tr class="row-odd"><td>135</td>
 768 <td>DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT</td>
 769 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 770 </tr>
 771 <tr class="row-even"><td>143</td>
 772 <td>DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
 773 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 774 </tr>
 775 <tr class="row-odd"><td>144</td>
 776 <td>DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
 777 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_AWS_3</td>
 778 </tr>
 779 <tr class="row-even"><td>157</td>
 780 <td>DEV_ATL0_ATL_IO_PORT_BWS</td>
 781 <td>Input muxed clock</td>
 782 </tr>
 783 <tr class="row-odd"><td>158</td>
 784 <td>DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT</td>
 785 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS</td>
 786 </tr>
 787 <tr class="row-even"><td>159</td>
 788 <td>DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT</td>
 789 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS</td>
 790 </tr>
 791 <tr class="row-odd"><td>160</td>
 792 <td>DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT</td>
 793 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS</td>
 794 </tr>
 795 <tr class="row-even"><td>161</td>
 796 <td>DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT</td>
 797 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS</td>
 798 </tr>
 799 <tr class="row-odd"><td>162</td>
 800 <td>DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT</td>
 801 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS</td>
 802 </tr>
 803 <tr class="row-even"><td>170</td>
 804 <td>DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT</td>
 805 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS</td>
 806 </tr>
 807 <tr class="row-odd"><td>171</td>
 808 <td>DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT</td>
 809 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS</td>
 810 </tr>
 811 <tr class="row-even"><td>172</td>
 812 <td>DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT</td>
 813 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS</td>
 814 </tr>
 815 <tr class="row-odd"><td>173</td>
 816 <td>DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT</td>
 817 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS</td>
 818 </tr>
 819 <tr class="row-even"><td>174</td>
 820 <td>DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT</td>
 821 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS</td>
 822 </tr>
 823 <tr class="row-odd"><td>182</td>
 824 <td>DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
 825 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS</td>
 826 </tr>
 827 <tr class="row-even"><td>183</td>
 828 <td>DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
 829 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS</td>
 830 </tr>
 831 <tr class="row-odd"><td>190</td>
 832 <td>DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 833 <td>Input muxed clock</td>
 834 </tr>
 835 <tr class="row-even"><td>191</td>
 836 <td>DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT</td>
 837 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 838 </tr>
 839 <tr class="row-odd"><td>192</td>
 840 <td>DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT</td>
 841 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 842 </tr>
 843 <tr class="row-even"><td>193</td>
 844 <td>DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT</td>
 845 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 846 </tr>
 847 <tr class="row-odd"><td>194</td>
 848 <td>DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT</td>
 849 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 850 </tr>
 851 <tr class="row-even"><td>195</td>
 852 <td>DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT</td>
 853 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 854 </tr>
 855 <tr class="row-odd"><td>203</td>
 856 <td>DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT</td>
 857 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 858 </tr>
 859 <tr class="row-even"><td>204</td>
 860 <td>DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT</td>
 861 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 862 </tr>
 863 <tr class="row-odd"><td>205</td>
 864 <td>DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT</td>
 865 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 866 </tr>
 867 <tr class="row-even"><td>206</td>
 868 <td>DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT</td>
 869 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 870 </tr>
 871 <tr class="row-odd"><td>207</td>
 872 <td>DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT</td>
 873 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 874 </tr>
 875 <tr class="row-even"><td>215</td>
 876 <td>DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
 877 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 878 </tr>
 879 <tr class="row-odd"><td>216</td>
 880 <td>DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
 881 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_1</td>
 882 </tr>
 883 <tr class="row-even"><td>229</td>
 884 <td>DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 885 <td>Input muxed clock</td>
 886 </tr>
 887 <tr class="row-odd"><td>230</td>
 888 <td>DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT</td>
 889 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 890 </tr>
 891 <tr class="row-even"><td>231</td>
 892 <td>DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT</td>
 893 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 894 </tr>
 895 <tr class="row-odd"><td>232</td>
 896 <td>DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT</td>
 897 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 898 </tr>
 899 <tr class="row-even"><td>233</td>
 900 <td>DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT</td>
 901 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 902 </tr>
 903 <tr class="row-odd"><td>234</td>
 904 <td>DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT</td>
 905 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 906 </tr>
 907 <tr class="row-even"><td>242</td>
 908 <td>DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT</td>
 909 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 910 </tr>
 911 <tr class="row-odd"><td>243</td>
 912 <td>DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT</td>
 913 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 914 </tr>
 915 <tr class="row-even"><td>244</td>
 916 <td>DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT</td>
 917 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 918 </tr>
 919 <tr class="row-odd"><td>245</td>
 920 <td>DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT</td>
 921 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 922 </tr>
 923 <tr class="row-even"><td>246</td>
 924 <td>DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT</td>
 925 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 926 </tr>
 927 <tr class="row-odd"><td>254</td>
 928 <td>DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
 929 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 930 </tr>
 931 <tr class="row-even"><td>255</td>
 932 <td>DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
 933 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_2</td>
 934 </tr>
 935 <tr class="row-odd"><td>262</td>
 936 <td>DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 937 <td>Input muxed clock</td>
 938 </tr>
 939 <tr class="row-even"><td>263</td>
 940 <td>DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT</td>
 941 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 942 </tr>
 943 <tr class="row-odd"><td>264</td>
 944 <td>DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT</td>
 945 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 946 </tr>
 947 <tr class="row-even"><td>265</td>
 948 <td>DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT</td>
 949 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 950 </tr>
 951 <tr class="row-odd"><td>266</td>
 952 <td>DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT</td>
 953 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 954 </tr>
 955 <tr class="row-even"><td>267</td>
 956 <td>DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT</td>
 957 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 958 </tr>
 959 <tr class="row-odd"><td>275</td>
 960 <td>DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT</td>
 961 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 962 </tr>
 963 <tr class="row-even"><td>276</td>
 964 <td>DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT</td>
 965 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 966 </tr>
 967 <tr class="row-odd"><td>277</td>
 968 <td>DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT</td>
 969 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 970 </tr>
 971 <tr class="row-even"><td>278</td>
 972 <td>DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT</td>
 973 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 974 </tr>
 975 <tr class="row-odd"><td>279</td>
 976 <td>DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT</td>
 977 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 978 </tr>
 979 <tr class="row-even"><td>287</td>
 980 <td>DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
 981 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 982 </tr>
 983 <tr class="row-odd"><td>288</td>
 984 <td>DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
 985 <td>Parent input clock option to DEV_ATL0_ATL_IO_PORT_BWS_3</td>
 986 </tr>
 987 <tr class="row-even"><td>301</td>
 988 <td>DEV_ATL0_VBUS_CLK</td>
 989 <td>Input clock</td>
 990 </tr>
 991 </tbody>
 992 </table>
 993 </div>
 994 <div class="section" id="clocks-for-board0-device">
 995 <span id="soc-doc-j784s4-public-clks-board0"></span><h3>Clocks for BOARD0 Device<a class="headerlink" href="#clocks-for-board0-device" title="Permalink to this headline">¶</a></h3>
 996 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_BOARD0</span></a> (ID = 157)</p>
 997 <div class="admonition note">
 998 <p class="first admonition-title">Note</p>
 999 <p>BOARD0 is a special device that represents the board on which
1000 the SoC is mounted.</p>
1001 <p>Clocks that are incoming to or outgoing from the SoC are
1002 represented in this section from the <em>perspective of the board</em>.</p>
1003 <p>Function documented here implies:</p>
1004 <table border="1" class="docutils">
1005 <colgroup>
1006 <col width="15%" />
1007 <col width="85%" />
1008 </colgroup>
1009 <thead valign="bottom">
1010 <tr class="row-odd"><th class="head">Function</th>
1011 <th class="head">Description</th>
1012 </tr>
1013 </thead>
1014 <tbody valign="top">
1015 <tr class="row-even"><td>Input clock</td>
1016 <td>Clock is supplied from SoC to the board (It is an output of the SoC)</td>
1017 </tr>
1018 <tr class="row-odd"><td>Output clock</td>
1019 <td>Clock is supplied from board to the SoC (It is an output of the Board and input to the SoC)</td>
1020 </tr>
1021 </tbody>
1022 </table>
1023 <p class="last"><strong>NOTE: Clocks which can be bi-directional are listed as Output clock</strong></p>
1024 </div>
1025 <p>Following is a mapping of Clocks IDs to function:</p>
1026 <table border="1" class="docutils">
1027 <colgroup>
1028 <col width="8%" />
1029 <col width="53%" />
1030 <col width="39%" />
1031 </colgroup>
1032 <thead valign="bottom">
1033 <tr class="row-odd"><th class="head">Clock ID</th>
1034 <th class="head">Name</th>
1035 <th class="head">Function</th>
1036 </tr>
1037 </thead>
1038 <tbody valign="top">
1039 <tr class="row-even"><td>0</td>
1040 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1041 <td>Input muxed clock</td>
1042 </tr>
1043 <tr class="row-odd"><td>1</td>
1044 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT</td>
1045 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1046 </tr>
1047 <tr class="row-even"><td>2</td>
1048 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT</td>
1049 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1050 </tr>
1051 <tr class="row-odd"><td>3</td>
1052 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT</td>
1053 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1054 </tr>
1055 <tr class="row-even"><td>4</td>
1056 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT</td>
1057 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1058 </tr>
1059 <tr class="row-odd"><td>5</td>
1060 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT</td>
1061 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1062 </tr>
1063 <tr class="row-even"><td>13</td>
1064 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT</td>
1065 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1066 </tr>
1067 <tr class="row-odd"><td>14</td>
1068 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT</td>
1069 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1070 </tr>
1071 <tr class="row-even"><td>15</td>
1072 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT</td>
1073 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1074 </tr>
1075 <tr class="row-odd"><td>16</td>
1076 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT</td>
1077 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1078 </tr>
1079 <tr class="row-even"><td>17</td>
1080 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT</td>
1081 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1082 </tr>
1083 <tr class="row-odd"><td>25</td>
1084 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
1085 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1086 </tr>
1087 <tr class="row-even"><td>26</td>
1088 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
1089 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1090 </tr>
1091 <tr class="row-odd"><td>27</td>
1092 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
1093 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1094 </tr>
1095 <tr class="row-even"><td>28</td>
1096 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
1097 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1098 </tr>
1099 <tr class="row-odd"><td>29</td>
1100 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
1101 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN</td>
1102 </tr>
1103 <tr class="row-even"><td>33</td>
1104 <td>DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT</td>
1105 <td>Output clock</td>
1106 </tr>
1107 <tr class="row-odd"><td>34</td>
1108 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1109 <td>Input muxed clock</td>
1110 </tr>
1111 <tr class="row-even"><td>35</td>
1112 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT</td>
1113 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1114 </tr>
1115 <tr class="row-odd"><td>36</td>
1116 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT</td>
1117 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1118 </tr>
1119 <tr class="row-even"><td>37</td>
1120 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT</td>
1121 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1122 </tr>
1123 <tr class="row-odd"><td>38</td>
1124 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT</td>
1125 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1126 </tr>
1127 <tr class="row-even"><td>39</td>
1128 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT</td>
1129 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1130 </tr>
1131 <tr class="row-odd"><td>47</td>
1132 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT</td>
1133 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1134 </tr>
1135 <tr class="row-even"><td>48</td>
1136 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT</td>
1137 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1138 </tr>
1139 <tr class="row-odd"><td>49</td>
1140 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT</td>
1141 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1142 </tr>
1143 <tr class="row-even"><td>50</td>
1144 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT</td>
1145 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1146 </tr>
1147 <tr class="row-odd"><td>51</td>
1148 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT</td>
1149 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1150 </tr>
1151 <tr class="row-even"><td>59</td>
1152 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
1153 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1154 </tr>
1155 <tr class="row-odd"><td>60</td>
1156 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
1157 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1158 </tr>
1159 <tr class="row-even"><td>61</td>
1160 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
1161 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1162 </tr>
1163 <tr class="row-odd"><td>62</td>
1164 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
1165 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1166 </tr>
1167 <tr class="row-even"><td>63</td>
1168 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
1169 <td>Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN</td>
1170 </tr>
1171 <tr class="row-odd"><td>67</td>
1172 <td>DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT</td>
1173 <td>Output clock</td>
1174 </tr>
1175 <tr class="row-even"><td>68</td>
1176 <td>DEV_BOARD0_CPTS0_RFT_CLK_OUT</td>
1177 <td>Output clock</td>
1178 </tr>
1179 <tr class="row-odd"><td>69</td>
1180 <td>DEV_BOARD0_CSI0_RXCLKN_OUT</td>
1181 <td>Output clock</td>
1182 </tr>
1183 <tr class="row-even"><td>70</td>
1184 <td>DEV_BOARD0_CSI0_RXCLKP_OUT</td>
1185 <td>Output clock</td>
1186 </tr>
1187 <tr class="row-odd"><td>71</td>
1188 <td>DEV_BOARD0_CSI0_TXCLKN_IN</td>
1189 <td>Input clock</td>
1190 </tr>
1191 <tr class="row-even"><td>72</td>
1192 <td>DEV_BOARD0_CSI0_TXCLKP_IN</td>
1193 <td>Input clock</td>
1194 </tr>
1195 <tr class="row-odd"><td>73</td>
1196 <td>DEV_BOARD0_CSI1_RXCLKN_OUT</td>
1197 <td>Output clock</td>
1198 </tr>
1199 <tr class="row-even"><td>74</td>
1200 <td>DEV_BOARD0_CSI1_RXCLKP_OUT</td>
1201 <td>Output clock</td>
1202 </tr>
1203 <tr class="row-odd"><td>75</td>
1204 <td>DEV_BOARD0_CSI1_TXCLKN_IN</td>
1205 <td>Input clock</td>
1206 </tr>
1207 <tr class="row-even"><td>76</td>
1208 <td>DEV_BOARD0_CSI1_TXCLKP_IN</td>
1209 <td>Input clock</td>
1210 </tr>
1211 <tr class="row-odd"><td>77</td>
1212 <td>DEV_BOARD0_CSI2_RXCLKN_OUT</td>
1213 <td>Output clock</td>
1214 </tr>
1215 <tr class="row-even"><td>78</td>
1216 <td>DEV_BOARD0_CSI2_RXCLKP_OUT</td>
1217 <td>Output clock</td>
1218 </tr>
1219 <tr class="row-odd"><td>95</td>
1220 <td>DEV_BOARD0_DSI0_TXCLKN_IN</td>
1221 <td>Input clock</td>
1222 </tr>
1223 <tr class="row-even"><td>96</td>
1224 <td>DEV_BOARD0_DSI0_TXCLKP_IN</td>
1225 <td>Input clock</td>
1226 </tr>
1227 <tr class="row-odd"><td>97</td>
1228 <td>DEV_BOARD0_DSI1_TXCLKN_IN</td>
1229 <td>Input clock</td>
1230 </tr>
1231 <tr class="row-even"><td>98</td>
1232 <td>DEV_BOARD0_DSI1_TXCLKP_IN</td>
1233 <td>Input clock</td>
1234 </tr>
1235 <tr class="row-odd"><td>99</td>
1236 <td>DEV_BOARD0_EXT_REFCLK1_OUT</td>
1237 <td>Output clock</td>
1238 </tr>
1239 <tr class="row-even"><td>100</td>
1240 <td>DEV_BOARD0_GPMC0_CLKOUT_IN</td>
1241 <td>Input clock</td>
1242 </tr>
1243 <tr class="row-odd"><td>101</td>
1244 <td>DEV_BOARD0_GPMC0_CLK_OUT</td>
1245 <td>Output clock</td>
1246 </tr>
1247 <tr class="row-even"><td>102</td>
1248 <td>DEV_BOARD0_GPMC0_FCLK_MUX_IN</td>
1249 <td>Input clock</td>
1250 </tr>
1251 <tr class="row-odd"><td>103</td>
1252 <td>DEV_BOARD0_HYP0_RXFLCLK_IN</td>
1253 <td>Input clock</td>
1254 </tr>
1255 <tr class="row-even"><td>104</td>
1256 <td>DEV_BOARD0_HYP0_RXPMCLK_OUT</td>
1257 <td>Output clock</td>
1258 </tr>
1259 <tr class="row-odd"><td>105</td>
1260 <td>DEV_BOARD0_HYP0_TXFLCLK_OUT</td>
1261 <td>Output clock</td>
1262 </tr>
1263 <tr class="row-even"><td>106</td>
1264 <td>DEV_BOARD0_HYP0_TXPMCLK_IN</td>
1265 <td>Input clock</td>
1266 </tr>
1267 <tr class="row-odd"><td>107</td>
1268 <td>DEV_BOARD0_HYP1_RXFLCLK_IN</td>
1269 <td>Input clock</td>
1270 </tr>
1271 <tr class="row-even"><td>108</td>
1272 <td>DEV_BOARD0_HYP1_RXPMCLK_OUT</td>
1273 <td>Output clock</td>
1274 </tr>
1275 <tr class="row-odd"><td>109</td>
1276 <td>DEV_BOARD0_HYP1_TXFLCLK_OUT</td>
1277 <td>Output clock</td>
1278 </tr>
1279 <tr class="row-even"><td>110</td>
1280 <td>DEV_BOARD0_HYP1_TXPMCLK_IN</td>
1281 <td>Input clock</td>
1282 </tr>
1283 <tr class="row-odd"><td>111</td>
1284 <td>DEV_BOARD0_I2C0_SCL_IN</td>
1285 <td>Input clock</td>
1286 </tr>
1287 <tr class="row-even"><td>112</td>
1288 <td>DEV_BOARD0_I2C0_SCL_OUT</td>
1289 <td>Output clock</td>
1290 </tr>
1291 <tr class="row-odd"><td>113</td>
1292 <td>DEV_BOARD0_I2C1_SCL_IN</td>
1293 <td>Input clock</td>
1294 </tr>
1295 <tr class="row-even"><td>114</td>
1296 <td>DEV_BOARD0_I2C1_SCL_OUT</td>
1297 <td>Output clock</td>
1298 </tr>
1299 <tr class="row-odd"><td>115</td>
1300 <td>DEV_BOARD0_I2C2_SCL_IN</td>
1301 <td>Input clock</td>
1302 </tr>
1303 <tr class="row-even"><td>116</td>
1304 <td>DEV_BOARD0_I2C2_SCL_OUT</td>
1305 <td>Output clock</td>
1306 </tr>
1307 <tr class="row-odd"><td>117</td>
1308 <td>DEV_BOARD0_I2C3_SCL_IN</td>
1309 <td>Input clock</td>
1310 </tr>
1311 <tr class="row-even"><td>118</td>
1312 <td>DEV_BOARD0_I2C3_SCL_OUT</td>
1313 <td>Output clock</td>
1314 </tr>
1315 <tr class="row-odd"><td>119</td>
1316 <td>DEV_BOARD0_I2C4_SCL_IN</td>
1317 <td>Input clock</td>
1318 </tr>
1319 <tr class="row-even"><td>120</td>
1320 <td>DEV_BOARD0_I2C4_SCL_OUT</td>
1321 <td>Output clock</td>
1322 </tr>
1323 <tr class="row-odd"><td>121</td>
1324 <td>DEV_BOARD0_I2C5_SCL_IN</td>
1325 <td>Input clock</td>
1326 </tr>
1327 <tr class="row-even"><td>122</td>
1328 <td>DEV_BOARD0_I2C5_SCL_OUT</td>
1329 <td>Output clock</td>
1330 </tr>
1331 <tr class="row-odd"><td>123</td>
1332 <td>DEV_BOARD0_I2C6_SCL_IN</td>
1333 <td>Input clock</td>
1334 </tr>
1335 <tr class="row-even"><td>124</td>
1336 <td>DEV_BOARD0_I2C6_SCL_OUT</td>
1337 <td>Output clock</td>
1338 </tr>
1339 <tr class="row-odd"><td>125</td>
1340 <td>DEV_BOARD0_LED_CLK_OUT</td>
1341 <td>Output clock</td>
1342 </tr>
1343 <tr class="row-even"><td>126</td>
1344 <td>DEV_BOARD0_MCAN0_RX_OUT</td>
1345 <td>Output clock</td>
1346 </tr>
1347 <tr class="row-odd"><td>127</td>
1348 <td>DEV_BOARD0_MCAN10_RX_OUT</td>
1349 <td>Output clock</td>
1350 </tr>
1351 <tr class="row-even"><td>128</td>
1352 <td>DEV_BOARD0_MCAN11_RX_OUT</td>
1353 <td>Output clock</td>
1354 </tr>
1355 <tr class="row-odd"><td>129</td>
1356 <td>DEV_BOARD0_MCAN12_RX_OUT</td>
1357 <td>Output clock</td>
1358 </tr>
1359 <tr class="row-even"><td>130</td>
1360 <td>DEV_BOARD0_MCAN13_RX_OUT</td>
1361 <td>Output clock</td>
1362 </tr>
1363 <tr class="row-odd"><td>131</td>
1364 <td>DEV_BOARD0_MCAN14_RX_OUT</td>
1365 <td>Output clock</td>
1366 </tr>
1367 <tr class="row-even"><td>132</td>
1368 <td>DEV_BOARD0_MCAN15_RX_OUT</td>
1369 <td>Output clock</td>
1370 </tr>
1371 <tr class="row-odd"><td>133</td>
1372 <td>DEV_BOARD0_MCAN16_RX_OUT</td>
1373 <td>Output clock</td>
1374 </tr>
1375 <tr class="row-even"><td>134</td>
1376 <td>DEV_BOARD0_MCAN17_RX_OUT</td>
1377 <td>Output clock</td>
1378 </tr>
1379 <tr class="row-odd"><td>135</td>
1380 <td>DEV_BOARD0_MCAN1_RX_OUT</td>
1381 <td>Output clock</td>
1382 </tr>
1383 <tr class="row-even"><td>136</td>
1384 <td>DEV_BOARD0_MCAN2_RX_OUT</td>
1385 <td>Output clock</td>
1386 </tr>
1387 <tr class="row-odd"><td>137</td>
1388 <td>DEV_BOARD0_MCAN3_RX_OUT</td>
1389 <td>Output clock</td>
1390 </tr>
1391 <tr class="row-even"><td>138</td>
1392 <td>DEV_BOARD0_MCAN4_RX_OUT</td>
1393 <td>Output clock</td>
1394 </tr>
1395 <tr class="row-odd"><td>139</td>
1396 <td>DEV_BOARD0_MCAN5_RX_OUT</td>
1397 <td>Output clock</td>
1398 </tr>
1399 <tr class="row-even"><td>140</td>
1400 <td>DEV_BOARD0_MCAN6_RX_OUT</td>
1401 <td>Output clock</td>
1402 </tr>
1403 <tr class="row-odd"><td>141</td>
1404 <td>DEV_BOARD0_MCAN7_RX_OUT</td>
1405 <td>Output clock</td>
1406 </tr>
1407 <tr class="row-even"><td>142</td>
1408 <td>DEV_BOARD0_MCAN8_RX_OUT</td>
1409 <td>Output clock</td>
1410 </tr>
1411 <tr class="row-odd"><td>143</td>
1412 <td>DEV_BOARD0_MCAN9_RX_OUT</td>
1413 <td>Output clock</td>
1414 </tr>
1415 <tr class="row-even"><td>144</td>
1416 <td>DEV_BOARD0_MCASP0_ACLKR_IN</td>
1417 <td>Input clock</td>
1418 </tr>
1419 <tr class="row-odd"><td>145</td>
1420 <td>DEV_BOARD0_MCASP0_ACLKR_OUT</td>
1421 <td>Output clock</td>
1422 </tr>
1423 <tr class="row-even"><td>146</td>
1424 <td>DEV_BOARD0_MCASP0_ACLKX_IN</td>
1425 <td>Input clock</td>
1426 </tr>
1427 <tr class="row-odd"><td>147</td>
1428 <td>DEV_BOARD0_MCASP0_ACLKX_OUT</td>
1429 <td>Output clock</td>
1430 </tr>
1431 <tr class="row-even"><td>148</td>
1432 <td>DEV_BOARD0_MCASP0_AFSR_OUT</td>
1433 <td>Output clock</td>
1434 </tr>
1435 <tr class="row-odd"><td>149</td>
1436 <td>DEV_BOARD0_MCASP0_AFSX_OUT</td>
1437 <td>Output clock</td>
1438 </tr>
1439 <tr class="row-even"><td>150</td>
1440 <td>DEV_BOARD0_MCASP1_ACLKR_IN</td>
1441 <td>Input clock</td>
1442 </tr>
1443 <tr class="row-odd"><td>151</td>
1444 <td>DEV_BOARD0_MCASP1_ACLKR_OUT</td>
1445 <td>Output clock</td>
1446 </tr>
1447 <tr class="row-even"><td>152</td>
1448 <td>DEV_BOARD0_MCASP1_ACLKX_IN</td>
1449 <td>Input clock</td>
1450 </tr>
1451 <tr class="row-odd"><td>153</td>
1452 <td>DEV_BOARD0_MCASP1_ACLKX_OUT</td>
1453 <td>Output clock</td>
1454 </tr>
1455 <tr class="row-even"><td>154</td>
1456 <td>DEV_BOARD0_MCASP1_AFSR_OUT</td>
1457 <td>Output clock</td>
1458 </tr>
1459 <tr class="row-odd"><td>155</td>
1460 <td>DEV_BOARD0_MCASP1_AFSX_OUT</td>
1461 <td>Output clock</td>
1462 </tr>
1463 <tr class="row-even"><td>156</td>
1464 <td>DEV_BOARD0_MCASP2_ACLKR_IN</td>
1465 <td>Input clock</td>
1466 </tr>
1467 <tr class="row-odd"><td>157</td>
1468 <td>DEV_BOARD0_MCASP2_ACLKR_OUT</td>
1469 <td>Output clock</td>
1470 </tr>
1471 <tr class="row-even"><td>158</td>
1472 <td>DEV_BOARD0_MCASP2_ACLKX_IN</td>
1473 <td>Input clock</td>
1474 </tr>
1475 <tr class="row-odd"><td>159</td>
1476 <td>DEV_BOARD0_MCASP2_ACLKX_OUT</td>
1477 <td>Output clock</td>
1478 </tr>
1479 <tr class="row-even"><td>160</td>
1480 <td>DEV_BOARD0_MCASP2_AFSR_OUT</td>
1481 <td>Output clock</td>
1482 </tr>
1483 <tr class="row-odd"><td>161</td>
1484 <td>DEV_BOARD0_MCASP2_AFSX_OUT</td>
1485 <td>Output clock</td>
1486 </tr>
1487 <tr class="row-even"><td>162</td>
1488 <td>DEV_BOARD0_MCASP3_ACLKR_IN</td>
1489 <td>Input clock</td>
1490 </tr>
1491 <tr class="row-odd"><td>163</td>
1492 <td>DEV_BOARD0_MCASP3_ACLKR_OUT</td>
1493 <td>Output clock</td>
1494 </tr>
1495 <tr class="row-even"><td>164</td>
1496 <td>DEV_BOARD0_MCASP3_ACLKX_IN</td>
1497 <td>Input clock</td>
1498 </tr>
1499 <tr class="row-odd"><td>165</td>
1500 <td>DEV_BOARD0_MCASP3_ACLKX_OUT</td>
1501 <td>Output clock</td>
1502 </tr>
1503 <tr class="row-even"><td>166</td>
1504 <td>DEV_BOARD0_MCASP3_AFSR_OUT</td>
1505 <td>Output clock</td>
1506 </tr>
1507 <tr class="row-odd"><td>167</td>
1508 <td>DEV_BOARD0_MCASP3_AFSX_OUT</td>
1509 <td>Output clock</td>
1510 </tr>
1511 <tr class="row-even"><td>168</td>
1512 <td>DEV_BOARD0_MCASP4_ACLKR_IN</td>
1513 <td>Input clock</td>
1514 </tr>
1515 <tr class="row-odd"><td>169</td>
1516 <td>DEV_BOARD0_MCASP4_ACLKR_OUT</td>
1517 <td>Output clock</td>
1518 </tr>
1519 <tr class="row-even"><td>170</td>
1520 <td>DEV_BOARD0_MCASP4_ACLKX_IN</td>
1521 <td>Input clock</td>
1522 </tr>
1523 <tr class="row-odd"><td>171</td>
1524 <td>DEV_BOARD0_MCASP4_ACLKX_OUT</td>
1525 <td>Output clock</td>
1526 </tr>
1527 <tr class="row-even"><td>172</td>
1528 <td>DEV_BOARD0_MCASP4_AFSR_OUT</td>
1529 <td>Output clock</td>
1530 </tr>
1531 <tr class="row-odd"><td>173</td>
1532 <td>DEV_BOARD0_MCASP4_AFSX_OUT</td>
1533 <td>Output clock</td>
1534 </tr>
1535 <tr class="row-even"><td>174</td>
1536 <td>DEV_BOARD0_MCU_CLKOUT0_IN</td>
1537 <td>Input muxed clock</td>
1538 </tr>
1539 <tr class="row-odd"><td>175</td>
1540 <td>DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5</td>
1541 <td>Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN</td>
1542 </tr>
1543 <tr class="row-even"><td>176</td>
1544 <td>DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10</td>
1545 <td>Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN</td>
1546 </tr>
1547 <tr class="row-odd"><td>177</td>
1548 <td>DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT</td>
1549 <td>Output clock</td>
1550 </tr>
1551 <tr class="row-even"><td>178</td>
1552 <td>DEV_BOARD0_MCU_EXT_REFCLK0_OUT</td>
1553 <td>Output clock</td>
1554 </tr>
1555 <tr class="row-odd"><td>179</td>
1556 <td>DEV_BOARD0_MCU_HYPERBUS0_CK_IN</td>
1557 <td>Input clock</td>
1558 </tr>
1559 <tr class="row-even"><td>180</td>
1560 <td>DEV_BOARD0_MCU_HYPERBUS0_CKN_IN</td>
1561 <td>Input clock</td>
1562 </tr>
1563 <tr class="row-odd"><td>181</td>
1564 <td>DEV_BOARD0_MCU_I2C0_SCL_IN</td>
1565 <td>Input clock</td>
1566 </tr>
1567 <tr class="row-even"><td>182</td>
1568 <td>DEV_BOARD0_MCU_I2C0_SCL_OUT</td>
1569 <td>Output clock</td>
1570 </tr>
1571 <tr class="row-odd"><td>183</td>
1572 <td>DEV_BOARD0_MCU_I2C1_SCL_IN</td>
1573 <td>Input clock</td>
1574 </tr>
1575 <tr class="row-even"><td>184</td>
1576 <td>DEV_BOARD0_MCU_I2C1_SCL_OUT</td>
1577 <td>Output clock</td>
1578 </tr>
1579 <tr class="row-odd"><td>185</td>
1580 <td>DEV_BOARD0_MCU_I3C0_SCL_IN</td>
1581 <td>Input clock</td>
1582 </tr>
1583 <tr class="row-even"><td>186</td>
1584 <td>DEV_BOARD0_MCU_I3C0_SCL_OUT</td>
1585 <td>Output clock</td>
1586 </tr>
1587 <tr class="row-odd"><td>187</td>
1588 <td>DEV_BOARD0_MCU_I3C0_SDA_OUT</td>
1589 <td>Output clock</td>
1590 </tr>
1591 <tr class="row-even"><td>188</td>
1592 <td>DEV_BOARD0_MCU_MCAN0_RX_OUT</td>
1593 <td>Output clock</td>
1594 </tr>
1595 <tr class="row-odd"><td>189</td>
1596 <td>DEV_BOARD0_MCU_MCAN1_RX_OUT</td>
1597 <td>Output clock</td>
1598 </tr>
1599 <tr class="row-even"><td>190</td>
1600 <td>DEV_BOARD0_MCU_MDIO0_MDC_IN</td>
1601 <td>Input clock</td>
1602 </tr>
1603 <tr class="row-odd"><td>191</td>
1604 <td>DEV_BOARD0_MCU_OBSCLK0_IN</td>
1605 <td>Input muxed clock</td>
1606 </tr>
1607 <tr class="row-even"><td>192</td>
1608 <td>DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0</td>
1609 <td>Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN</td>
1610 </tr>
1611 <tr class="row-odd"><td>193</td>
1612 <td>DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
1613 <td>Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN</td>
1614 </tr>
1615 <tr class="row-even"><td>224</td>
1616 <td>DEV_BOARD0_MCU_OSPI0_CLK_IN</td>
1617 <td>Input clock</td>
1618 </tr>
1619 <tr class="row-odd"><td>225</td>
1620 <td>DEV_BOARD0_MCU_OSPI0_DQS_OUT</td>
1621 <td>Output clock</td>
1622 </tr>
1623 <tr class="row-even"><td>226</td>
1624 <td>DEV_BOARD0_MCU_OSPI0_LBCLKO_IN</td>
1625 <td>Input clock</td>
1626 </tr>
1627 <tr class="row-odd"><td>227</td>
1628 <td>DEV_BOARD0_MCU_OSPI0_LBCLKO_OUT</td>
1629 <td>Output clock</td>
1630 </tr>
1631 <tr class="row-even"><td>228</td>
1632 <td>DEV_BOARD0_MCU_OSPI1_CLK_IN</td>
1633 <td>Input clock</td>
1634 </tr>
1635 <tr class="row-odd"><td>229</td>
1636 <td>DEV_BOARD0_MCU_OSPI1_DQS_OUT</td>
1637 <td>Output clock</td>
1638 </tr>
1639 <tr class="row-even"><td>230</td>
1640 <td>DEV_BOARD0_MCU_OSPI1_LBCLKO_IN</td>
1641 <td>Input clock</td>
1642 </tr>
1643 <tr class="row-odd"><td>231</td>
1644 <td>DEV_BOARD0_MCU_OSPI1_LBCLKO_OUT</td>
1645 <td>Output clock</td>
1646 </tr>
1647 <tr class="row-even"><td>232</td>
1648 <td>DEV_BOARD0_MCU_RGMII1_RXC_OUT</td>
1649 <td>Output clock</td>
1650 </tr>
1651 <tr class="row-odd"><td>233</td>
1652 <td>DEV_BOARD0_MCU_RGMII1_TXC_IN</td>
1653 <td>Input clock</td>
1654 </tr>
1655 <tr class="row-even"><td>234</td>
1656 <td>DEV_BOARD0_MCU_RMII1_REF_CLK_OUT</td>
1657 <td>Output clock</td>
1658 </tr>
1659 <tr class="row-odd"><td>235</td>
1660 <td>DEV_BOARD0_MCU_SPI0_CLK_IN</td>
1661 <td>Input clock</td>
1662 </tr>
1663 <tr class="row-even"><td>236</td>
1664 <td>DEV_BOARD0_MCU_SPI0_CLK_OUT</td>
1665 <td>Output clock</td>
1666 </tr>
1667 <tr class="row-odd"><td>237</td>
1668 <td>DEV_BOARD0_MCU_SPI1_CLK_IN</td>
1669 <td>Input clock</td>
1670 </tr>
1671 <tr class="row-even"><td>238</td>
1672 <td>DEV_BOARD0_MCU_SPI1_CLK_OUT</td>
1673 <td>Output clock</td>
1674 </tr>
1675 <tr class="row-odd"><td>239</td>
1676 <td>DEV_BOARD0_MCU_SYSCLKOUT0_IN</td>
1677 <td>Input clock</td>
1678 </tr>
1679 <tr class="row-even"><td>240</td>
1680 <td>DEV_BOARD0_MDIO0_MDC_IN</td>
1681 <td>Input clock</td>
1682 </tr>
1683 <tr class="row-odd"><td>241</td>
1684 <td>DEV_BOARD0_MDIO1_MDC_IN</td>
1685 <td>Input clock</td>
1686 </tr>
1687 <tr class="row-even"><td>243</td>
1688 <td>DEV_BOARD0_MMC1_CLKLB_IN</td>
1689 <td>Input clock</td>
1690 </tr>
1691 <tr class="row-odd"><td>244</td>
1692 <td>DEV_BOARD0_MMC1_CLKLB_OUT</td>
1693 <td>Output clock</td>
1694 </tr>
1695 <tr class="row-even"><td>245</td>
1696 <td>DEV_BOARD0_MMC1_CLK_IN</td>
1697 <td>Input clock</td>
1698 </tr>
1699 <tr class="row-odd"><td>246</td>
1700 <td>DEV_BOARD0_MMC1_CLK_OUT</td>
1701 <td>Output clock</td>
1702 </tr>
1703 <tr class="row-even"><td>247</td>
1704 <td>DEV_BOARD0_OBSCLK0_IN</td>
1705 <td>Input clock</td>
1706 </tr>
1707 <tr class="row-odd"><td>248</td>
1708 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK</td>
1709 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1710 </tr>
1711 <tr class="row-even"><td>249</td>
1712 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK</td>
1713 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1714 </tr>
1715 <tr class="row-odd"><td>250</td>
1716 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK</td>
1717 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1718 </tr>
1719 <tr class="row-even"><td>251</td>
1720 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK</td>
1721 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1722 </tr>
1723 <tr class="row-odd"><td>252</td>
1724 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
1725 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1726 </tr>
1727 <tr class="row-even"><td>253</td>
1728 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK</td>
1729 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1730 </tr>
1731 <tr class="row-odd"><td>254</td>
1732 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK</td>
1733 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1734 </tr>
1735 <tr class="row-even"><td>255</td>
1736 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK</td>
1737 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1738 </tr>
1739 <tr class="row-odd"><td>256</td>
1740 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_27_HSDIVOUT0_CLK</td>
1741 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1742 </tr>
1743 <tr class="row-even"><td>257</td>
1744 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_28_HSDIVOUT0_CLK</td>
1745 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1746 </tr>
1747 <tr class="row-odd"><td>260</td>
1748 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK</td>
1749 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1750 </tr>
1751 <tr class="row-even"><td>261</td>
1752 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0</td>
1753 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1754 </tr>
1755 <tr class="row-odd"><td>262</td>
1756 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK</td>
1757 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1758 </tr>
1759 <tr class="row-even"><td>264</td>
1760 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK</td>
1761 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1762 </tr>
1763 <tr class="row-odd"><td>265</td>
1764 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK</td>
1765 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1766 </tr>
1767 <tr class="row-even"><td>267</td>
1768 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK</td>
1769 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1770 </tr>
1771 <tr class="row-odd"><td>268</td>
1772 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_TX_REF_SYMBOLCLK</td>
1773 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1774 </tr>
1775 <tr class="row-even"><td>269</td>
1776 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_19P2M_CLK</td>
1777 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1778 </tr>
1779 <tr class="row-odd"><td>270</td>
1780 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_26M_CLK</td>
1781 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1782 </tr>
1783 <tr class="row-even"><td>273</td>
1784 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK</td>
1785 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1786 </tr>
1787 <tr class="row-odd"><td>274</td>
1788 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3</td>
1789 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1790 </tr>
1791 <tr class="row-even"><td>275</td>
1792 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
1793 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1794 </tr>
1795 <tr class="row-odd"><td>276</td>
1796 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
1797 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1798 </tr>
1799 <tr class="row-even"><td>277</td>
1800 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0</td>
1801 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1802 </tr>
1803 <tr class="row-odd"><td>278</td>
1804 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
1805 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1806 </tr>
1807 <tr class="row-even"><td>279</td>
1808 <td>DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
1809 <td>Parent input clock option to DEV_BOARD0_OBSCLK0_IN</td>
1810 </tr>
1811 <tr class="row-odd"><td>280</td>
1812 <td>DEV_BOARD0_OBSCLK1_IN</td>
1813 <td>Input clock</td>
1814 </tr>
1815 <tr class="row-even"><td>281</td>
1816 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK</td>
1817 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1818 </tr>
1819 <tr class="row-odd"><td>282</td>
1820 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK</td>
1821 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1822 </tr>
1823 <tr class="row-even"><td>283</td>
1824 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK</td>
1825 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1826 </tr>
1827 <tr class="row-odd"><td>284</td>
1828 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK</td>
1829 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1830 </tr>
1831 <tr class="row-even"><td>285</td>
1832 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
1833 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1834 </tr>
1835 <tr class="row-odd"><td>286</td>
1836 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK</td>
1837 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1838 </tr>
1839 <tr class="row-even"><td>287</td>
1840 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK</td>
1841 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1842 </tr>
1843 <tr class="row-odd"><td>288</td>
1844 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK</td>
1845 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1846 </tr>
1847 <tr class="row-even"><td>289</td>
1848 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_27_HSDIVOUT0_CLK</td>
1849 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1850 </tr>
1851 <tr class="row-odd"><td>290</td>
1852 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_28_HSDIVOUT0_CLK</td>
1853 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1854 </tr>
1855 <tr class="row-even"><td>293</td>
1856 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK</td>
1857 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1858 </tr>
1859 <tr class="row-odd"><td>294</td>
1860 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_OBSCLK1_MUX_OUT0</td>
1861 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1862 </tr>
1863 <tr class="row-even"><td>295</td>
1864 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK</td>
1865 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1866 </tr>
1867 <tr class="row-odd"><td>297</td>
1868 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK</td>
1869 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1870 </tr>
1871 <tr class="row-even"><td>298</td>
1872 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK</td>
1873 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1874 </tr>
1875 <tr class="row-odd"><td>300</td>
1876 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK</td>
1877 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1878 </tr>
1879 <tr class="row-even"><td>301</td>
1880 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_TX_REF_SYMBOLCLK</td>
1881 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1882 </tr>
1883 <tr class="row-odd"><td>302</td>
1884 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_19P2M_CLK</td>
1885 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1886 </tr>
1887 <tr class="row-even"><td>303</td>
1888 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_MPHY_M31_VCO_26M_CLK</td>
1889 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1890 </tr>
1891 <tr class="row-odd"><td>306</td>
1892 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK</td>
1893 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1894 </tr>
1895 <tr class="row-even"><td>307</td>
1896 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3</td>
1897 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1898 </tr>
1899 <tr class="row-odd"><td>308</td>
1900 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
1901 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1902 </tr>
1903 <tr class="row-even"><td>309</td>
1904 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
1905 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1906 </tr>
1907 <tr class="row-odd"><td>310</td>
1908 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0</td>
1909 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1910 </tr>
1911 <tr class="row-even"><td>311</td>
1912 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
1913 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1914 </tr>
1915 <tr class="row-odd"><td>312</td>
1916 <td>DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
1917 <td>Parent input clock option to DEV_BOARD0_OBSCLK1_IN</td>
1918 </tr>
1919 <tr class="row-even"><td>321</td>
1920 <td>DEV_BOARD0_RGMII1_RXC_OUT</td>
1921 <td>Output clock</td>
1922 </tr>
1923 <tr class="row-odd"><td>322</td>
1924 <td>DEV_BOARD0_RGMII1_TXC_IN</td>
1925 <td>Input clock</td>
1926 </tr>
1927 <tr class="row-even"><td>323</td>
1928 <td>DEV_BOARD0_RMII_REF_CLK_OUT</td>
1929 <td>Output clock</td>
1930 </tr>
1931 <tr class="row-odd"><td>324</td>
1932 <td>DEV_BOARD0_SERDES0_REFCLK_N_IN</td>
1933 <td>Input clock</td>
1934 </tr>
1935 <tr class="row-even"><td>325</td>
1936 <td>DEV_BOARD0_SERDES0_REFCLK_N_OUT</td>
1937 <td>Output clock</td>
1938 </tr>
1939 <tr class="row-odd"><td>326</td>
1940 <td>DEV_BOARD0_SERDES0_REFCLK_P_IN</td>
1941 <td>Input clock</td>
1942 </tr>
1943 <tr class="row-even"><td>327</td>
1944 <td>DEV_BOARD0_SERDES0_REFCLK_P_OUT</td>
1945 <td>Output clock</td>
1946 </tr>
1947 <tr class="row-odd"><td>328</td>
1948 <td>DEV_BOARD0_SERDES1_REFCLK_N_IN</td>
1949 <td>Input clock</td>
1950 </tr>
1951 <tr class="row-even"><td>329</td>
1952 <td>DEV_BOARD0_SERDES1_REFCLK_N_OUT</td>
1953 <td>Output clock</td>
1954 </tr>
1955 <tr class="row-odd"><td>330</td>
1956 <td>DEV_BOARD0_SERDES1_REFCLK_P_IN</td>
1957 <td>Input clock</td>
1958 </tr>
1959 <tr class="row-even"><td>331</td>
1960 <td>DEV_BOARD0_SERDES1_REFCLK_P_OUT</td>
1961 <td>Output clock</td>
1962 </tr>
1963 <tr class="row-odd"><td>332</td>
1964 <td>DEV_BOARD0_SERDES2_REFCLK_N_IN</td>
1965 <td>Input clock</td>
1966 </tr>
1967 <tr class="row-even"><td>333</td>
1968 <td>DEV_BOARD0_SERDES2_REFCLK_N_OUT</td>
1969 <td>Output clock</td>
1970 </tr>
1971 <tr class="row-odd"><td>334</td>
1972 <td>DEV_BOARD0_SERDES2_REFCLK_P_IN</td>
1973 <td>Input clock</td>
1974 </tr>
1975 <tr class="row-even"><td>335</td>
1976 <td>DEV_BOARD0_SERDES2_REFCLK_P_OUT</td>
1977 <td>Output clock</td>
1978 </tr>
1979 <tr class="row-odd"><td>336</td>
1980 <td>DEV_BOARD0_SERDES4_REFCLK_N_IN</td>
1981 <td>Input clock</td>
1982 </tr>
1983 <tr class="row-even"><td>337</td>
1984 <td>DEV_BOARD0_SERDES4_REFCLK_N_OUT</td>
1985 <td>Output clock</td>
1986 </tr>
1987 <tr class="row-odd"><td>338</td>
1988 <td>DEV_BOARD0_SERDES4_REFCLK_P_IN</td>
1989 <td>Input clock</td>
1990 </tr>
1991 <tr class="row-even"><td>339</td>
1992 <td>DEV_BOARD0_SERDES4_REFCLK_P_OUT</td>
1993 <td>Output clock</td>
1994 </tr>
1995 <tr class="row-odd"><td>340</td>
1996 <td>DEV_BOARD0_SPI0_CLK_IN</td>
1997 <td>Input clock</td>
1998 </tr>
1999 <tr class="row-even"><td>341</td>
2000 <td>DEV_BOARD0_SPI0_CLK_OUT</td>
2001 <td>Output clock</td>
2002 </tr>
2003 <tr class="row-odd"><td>342</td>
2004 <td>DEV_BOARD0_SPI1_CLK_IN</td>
2005 <td>Input clock</td>
2006 </tr>
2007 <tr class="row-even"><td>343</td>
2008 <td>DEV_BOARD0_SPI1_CLK_OUT</td>
2009 <td>Output clock</td>
2010 </tr>
2011 <tr class="row-odd"><td>344</td>
2012 <td>DEV_BOARD0_SPI2_CLK_IN</td>
2013 <td>Input clock</td>
2014 </tr>
2015 <tr class="row-even"><td>345</td>
2016 <td>DEV_BOARD0_SPI2_CLK_OUT</td>
2017 <td>Output clock</td>
2018 </tr>
2019 <tr class="row-odd"><td>346</td>
2020 <td>DEV_BOARD0_SPI3_CLK_IN</td>
2021 <td>Input clock</td>
2022 </tr>
2023 <tr class="row-even"><td>347</td>
2024 <td>DEV_BOARD0_SPI3_CLK_OUT</td>
2025 <td>Output clock</td>
2026 </tr>
2027 <tr class="row-odd"><td>348</td>
2028 <td>DEV_BOARD0_SPI5_CLK_IN</td>
2029 <td>Input clock</td>
2030 </tr>
2031 <tr class="row-even"><td>349</td>
2032 <td>DEV_BOARD0_SPI5_CLK_OUT</td>
2033 <td>Output clock</td>
2034 </tr>
2035 <tr class="row-odd"><td>350</td>
2036 <td>DEV_BOARD0_SPI6_CLK_IN</td>
2037 <td>Input clock</td>
2038 </tr>
2039 <tr class="row-even"><td>351</td>
2040 <td>DEV_BOARD0_SPI6_CLK_OUT</td>
2041 <td>Output clock</td>
2042 </tr>
2043 <tr class="row-odd"><td>352</td>
2044 <td>DEV_BOARD0_SPI7_CLK_IN</td>
2045 <td>Input clock</td>
2046 </tr>
2047 <tr class="row-even"><td>353</td>
2048 <td>DEV_BOARD0_SPI7_CLK_OUT</td>
2049 <td>Output clock</td>
2050 </tr>
2051 <tr class="row-odd"><td>354</td>
2052 <td>DEV_BOARD0_SYSCLKOUT0_IN</td>
2053 <td>Input clock</td>
2054 </tr>
2055 <tr class="row-even"><td>355</td>
2056 <td>DEV_BOARD0_TCK_OUT</td>
2057 <td>Output clock</td>
2058 </tr>
2059 <tr class="row-odd"><td>356</td>
2060 <td>DEV_BOARD0_TRC_CLK_IN</td>
2061 <td>Input clock</td>
2062 </tr>
2063 <tr class="row-even"><td>357</td>
2064 <td>DEV_BOARD0_UFS0_REF_CLK_IN</td>
2065 <td>Input clock</td>
2066 </tr>
2067 <tr class="row-odd"><td>358</td>
2068 <td>DEV_BOARD0_VOUT0_EXTPCLKIN_OUT</td>
2069 <td>Output clock</td>
2070 </tr>
2071 <tr class="row-even"><td>359</td>
2072 <td>DEV_BOARD0_VOUT0_PCLK_IN</td>
2073 <td>Input clock</td>
2074 </tr>
2075 <tr class="row-odd"><td>360</td>
2076 <td>DEV_BOARD0_WKUP_I2C0_SCL_IN</td>
2077 <td>Input clock</td>
2078 </tr>
2079 <tr class="row-even"><td>361</td>
2080 <td>DEV_BOARD0_WKUP_I2C0_SCL_OUT</td>
2081 <td>Output clock</td>
2082 </tr>
2083 <tr class="row-odd"><td>363</td>
2084 <td>DEV_BOARD0_HFOSC1_CLK_OUT</td>
2085 <td>Output clock</td>
2086 </tr>
2087 </tbody>
2088 </table>
2089 </div>
2090 <div class="section" id="clocks-for-c71x-0-pbist-vd-device">
2091 <span id="soc-doc-j784s4-public-clks-c71x-0-pbist-vd"></span><h3>Clocks for C71X_0_PBIST_VD Device<a class="headerlink" href="#clocks-for-c71x-0-pbist-vd-device" title="Permalink to this headline">¶</a></h3>
2092 <p><strong>This device has no defined clocks.</strong></p>
2093 </div>
2094 <div class="section" id="clocks-for-c71x-1-pbist-vd-device">
2095 <span id="soc-doc-j784s4-public-clks-c71x-1-pbist-vd"></span><h3>Clocks for C71X_1_PBIST_VD Device<a class="headerlink" href="#clocks-for-c71x-1-pbist-vd-device" title="Permalink to this headline">¶</a></h3>
2096 <p><strong>This device has no defined clocks.</strong></p>
2097 </div>
2098 <div class="section" id="clocks-for-cmpevent-intrtr0-device">
2099 <span id="soc-doc-j784s4-public-clks-cmpevent-intrtr0"></span><h3>Clocks for CMPEVENT_INTRTR0 Device<a class="headerlink" href="#clocks-for-cmpevent-intrtr0-device" title="Permalink to this headline">¶</a></h3>
2100 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CMPEVENT_INTRTR0</span></a> (ID = 210)</p>
2101 <p>Following is a mapping of Clocks IDs to function:</p>
2102 <table border="1" class="docutils">
2103 <colgroup>
2104 <col width="21%" />
2105 <col width="55%" />
2106 <col width="23%" />
2107 </colgroup>
2108 <thead valign="bottom">
2109 <tr class="row-odd"><th class="head">Clock ID</th>
2110 <th class="head">Name</th>
2111 <th class="head">Function</th>
2112 </tr>
2113 </thead>
2114 <tbody valign="top">
2115 <tr class="row-even"><td>0</td>
2116 <td>DEV_CMPEVENT_INTRTR0_INTR_CLK</td>
2117 <td>Input clock</td>
2118 </tr>
2119 </tbody>
2120 </table>
2121 </div>
2122 <div class="section" id="clocks-for-codec0-device">
2123 <span id="soc-doc-j784s4-public-clks-codec0"></span><h3>Clocks for CODEC0 Device<a class="headerlink" href="#clocks-for-codec0-device" title="Permalink to this headline">¶</a></h3>
2124 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CODEC0</span></a> (ID = 241)</p>
2125 <p>Following is a mapping of Clocks IDs to function:</p>
2126 <table border="1" class="docutils">
2127 <colgroup>
2128 <col width="24%" />
2129 <col width="50%" />
2130 <col width="26%" />
2131 </colgroup>
2132 <thead valign="bottom">
2133 <tr class="row-odd"><th class="head">Clock ID</th>
2134 <th class="head">Name</th>
2135 <th class="head">Function</th>
2136 </tr>
2137 </thead>
2138 <tbody valign="top">
2139 <tr class="row-even"><td>0</td>
2140 <td>DEV_CODEC0_VPU_ACLK_CLK</td>
2141 <td>Input clock</td>
2142 </tr>
2143 <tr class="row-odd"><td>1</td>
2144 <td>DEV_CODEC0_VPU_BCLK_CLK</td>
2145 <td>Input clock</td>
2146 </tr>
2147 <tr class="row-even"><td>2</td>
2148 <td>DEV_CODEC0_VPU_CCLK_CLK</td>
2149 <td>Input clock</td>
2150 </tr>
2151 <tr class="row-odd"><td>3</td>
2152 <td>DEV_CODEC0_VPU_PCLK_CLK</td>
2153 <td>Input clock</td>
2154 </tr>
2155 </tbody>
2156 </table>
2157 </div>
2158 <div class="section" id="clocks-for-codec1-device">
2159 <span id="soc-doc-j784s4-public-clks-codec1"></span><h3>Clocks for CODEC1 Device<a class="headerlink" href="#clocks-for-codec1-device" title="Permalink to this headline">¶</a></h3>
2160 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CODEC1</span></a> (ID = 242)</p>
2161 <p>Following is a mapping of Clocks IDs to function:</p>
2162 <table border="1" class="docutils">
2163 <colgroup>
2164 <col width="24%" />
2165 <col width="50%" />
2166 <col width="26%" />
2167 </colgroup>
2168 <thead valign="bottom">
2169 <tr class="row-odd"><th class="head">Clock ID</th>
2170 <th class="head">Name</th>
2171 <th class="head">Function</th>
2172 </tr>
2173 </thead>
2174 <tbody valign="top">
2175 <tr class="row-even"><td>0</td>
2176 <td>DEV_CODEC1_VPU_ACLK_CLK</td>
2177 <td>Input clock</td>
2178 </tr>
2179 <tr class="row-odd"><td>1</td>
2180 <td>DEV_CODEC1_VPU_BCLK_CLK</td>
2181 <td>Input clock</td>
2182 </tr>
2183 <tr class="row-even"><td>2</td>
2184 <td>DEV_CODEC1_VPU_CCLK_CLK</td>
2185 <td>Input clock</td>
2186 </tr>
2187 <tr class="row-odd"><td>3</td>
2188 <td>DEV_CODEC1_VPU_PCLK_CLK</td>
2189 <td>Input clock</td>
2190 </tr>
2191 </tbody>
2192 </table>
2193 </div>
2194 <div class="section" id="clocks-for-compute-cluster0-device">
2195 <span id="soc-doc-j784s4-public-clks-compute-cluster0"></span><h3>Clocks for COMPUTE_CLUSTER0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-device" title="Permalink to this headline">¶</a></h3>
2196 <p><strong>This device has no defined clocks.</strong></p>
2197 </div>
2198 <div class="section" id="clocks-for-compute-cluster0-ac71-4-dft-embed-pbist-0-device">
2199 <span id="soc-doc-j784s4-public-clks-compute-cluster0-ac71-4-dft-embed-pbist-0"></span><h3>Clocks for COMPUTE_CLUSTER0_AC71_4_DFT_EMBED_PBIST_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-ac71-4-dft-embed-pbist-0-device" title="Permalink to this headline">¶</a></h3>
2200 <p><strong>This device has no defined clocks.</strong></p>
2201 </div>
2202 <div class="section" id="clocks-for-compute-cluster0-ac71-5-dft-embed-pbist-0-device">
2203 <span id="soc-doc-j784s4-public-clks-compute-cluster0-ac71-5-dft-embed-pbist-0"></span><h3>Clocks for COMPUTE_CLUSTER0_AC71_5_DFT_EMBED_PBIST_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-ac71-5-dft-embed-pbist-0-device" title="Permalink to this headline">¶</a></h3>
2204 <p><strong>This device has no defined clocks.</strong></p>
2205 </div>
2206 <div class="section" id="clocks-for-compute-cluster0-ac71-6-dft-embed-pbist-0-device">
2207 <span id="soc-doc-j784s4-public-clks-compute-cluster0-ac71-6-dft-embed-pbist-0"></span><h3>Clocks for COMPUTE_CLUSTER0_AC71_6_DFT_EMBED_PBIST_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-ac71-6-dft-embed-pbist-0-device" title="Permalink to this headline">¶</a></h3>
2208 <p><strong>This device has no defined clocks.</strong></p>
2209 </div>
2210 <div class="section" id="clocks-for-compute-cluster0-ac71-7-dft-embed-pbist-0-device">
2211 <span id="soc-doc-j784s4-public-clks-compute-cluster0-ac71-7-dft-embed-pbist-0"></span><h3>Clocks for COMPUTE_CLUSTER0_AC71_7_DFT_EMBED_PBIST_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-ac71-7-dft-embed-pbist-0-device" title="Permalink to this headline">¶</a></h3>
2212 <p><strong>This device has no defined clocks.</strong></p>
2213 </div>
2214 <div class="section" id="clocks-for-compute-cluster0-arm0-dft-embed-pbist-0-device">
2215 <span id="soc-doc-j784s4-public-clks-compute-cluster0-arm0-dft-embed-pbist-0"></span><h3>Clocks for COMPUTE_CLUSTER0_ARM0_DFT_EMBED_PBIST_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-arm0-dft-embed-pbist-0-device" title="Permalink to this headline">¶</a></h3>
2216 <p><strong>This device has no defined clocks.</strong></p>
2217 </div>
2218 <div class="section" id="clocks-for-compute-cluster0-arm0-dft-embed-pbist-1-device">
2219 <span id="soc-doc-j784s4-public-clks-compute-cluster0-arm0-dft-embed-pbist-1"></span><h3>Clocks for COMPUTE_CLUSTER0_ARM0_DFT_EMBED_PBIST_1 Device<a class="headerlink" href="#clocks-for-compute-cluster0-arm0-dft-embed-pbist-1-device" title="Permalink to this headline">¶</a></h3>
2220 <p><strong>This device has no defined clocks.</strong></p>
2221 </div>
2222 <div class="section" id="clocks-for-compute-cluster0-arm1-dft-embed-pbist-0-device">
2223 <span id="soc-doc-j784s4-public-clks-compute-cluster0-arm1-dft-embed-pbist-0"></span><h3>Clocks for COMPUTE_CLUSTER0_ARM1_DFT_EMBED_PBIST_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-arm1-dft-embed-pbist-0-device" title="Permalink to this headline">¶</a></h3>
2224 <p><strong>This device has no defined clocks.</strong></p>
2225 </div>
2226 <div class="section" id="clocks-for-compute-cluster0-arm1-dft-embed-pbist-1-device">
2227 <span id="soc-doc-j784s4-public-clks-compute-cluster0-arm1-dft-embed-pbist-1"></span><h3>Clocks for COMPUTE_CLUSTER0_ARM1_DFT_EMBED_PBIST_1 Device<a class="headerlink" href="#clocks-for-compute-cluster0-arm1-dft-embed-pbist-1-device" title="Permalink to this headline">¶</a></h3>
2228 <p><strong>This device has no defined clocks.</strong></p>
2229 </div>
2230 <div class="section" id="clocks-for-compute-cluster0-aw4-msmc-dft-embed-pbist-0-device">
2231 <span id="soc-doc-j784s4-public-clks-compute-cluster0-aw4-msmc-dft-embed-pbist-0"></span><h3>Clocks for COMPUTE_CLUSTER0_AW4_MSMC_DFT_EMBED_PBIST_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-aw4-msmc-dft-embed-pbist-0-device" title="Permalink to this headline">¶</a></h3>
2232 <p><strong>This device has no defined clocks.</strong></p>
2233 </div>
2234 <div class="section" id="clocks-for-compute-cluster0-aw5-msmc-dft-embed-pbist-0-device">
2235 <span id="soc-doc-j784s4-public-clks-compute-cluster0-aw5-msmc-dft-embed-pbist-0"></span><h3>Clocks for COMPUTE_CLUSTER0_AW5_MSMC_DFT_EMBED_PBIST_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-aw5-msmc-dft-embed-pbist-0-device" title="Permalink to this headline">¶</a></h3>
2236 <p><strong>This device has no defined clocks.</strong></p>
2237 </div>
2238 <div class="section" id="clocks-for-compute-cluster0-aw6-msmc-dft-embed-pbist-0-device">
2239 <span id="soc-doc-j784s4-public-clks-compute-cluster0-aw6-msmc-dft-embed-pbist-0"></span><h3>Clocks for COMPUTE_CLUSTER0_AW6_MSMC_DFT_EMBED_PBIST_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-aw6-msmc-dft-embed-pbist-0-device" title="Permalink to this headline">¶</a></h3>
2240 <p><strong>This device has no defined clocks.</strong></p>
2241 </div>
2242 <div class="section" id="clocks-for-compute-cluster0-aw7-msmc-dft-embed-pbist-0-device">
2243 <span id="soc-doc-j784s4-public-clks-compute-cluster0-aw7-msmc-dft-embed-pbist-0"></span><h3>Clocks for COMPUTE_CLUSTER0_AW7_MSMC_DFT_EMBED_PBIST_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-aw7-msmc-dft-embed-pbist-0-device" title="Permalink to this headline">¶</a></h3>
2244 <p><strong>This device has no defined clocks.</strong></p>
2245 </div>
2246 <div class="section" id="clocks-for-compute-cluster0-c71ss0-device">
2247 <span id="soc-doc-j784s4-public-clks-compute-cluster0-c71ss0"></span><h3>Clocks for COMPUTE_CLUSTER0_C71SS0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-c71ss0-device" title="Permalink to this headline">¶</a></h3>
2248 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_COMPUTE_CLUSTER0_C71SS0</span></a> (ID = 30)</p>
2249 <p>Following is a mapping of Clocks IDs to function:</p>
2250 <table border="1" class="docutils">
2251 <colgroup>
2252 <col width="14%" />
2253 <col width="69%" />
2254 <col width="17%" />
2255 </colgroup>
2256 <thead valign="bottom">
2257 <tr class="row-odd"><th class="head">Clock ID</th>
2258 <th class="head">Name</th>
2259 <th class="head">Function</th>
2260 </tr>
2261 </thead>
2262 <tbody valign="top">
2263 <tr class="row-even"><td>3</td>
2264 <td>DEV_COMPUTE_CLUSTER0_C71SS0_C7X_CLK</td>
2265 <td>Input clock</td>
2266 </tr>
2267 <tr class="row-odd"><td>4</td>
2268 <td>DEV_COMPUTE_CLUSTER0_C71SS0_C7X_DIVH_CLK4_OBSCLK_OUT_CLK</td>
2269 <td>Output clock</td>
2270 </tr>
2271 </tbody>
2272 </table>
2273 </div>
2274 <div class="section" id="clocks-for-compute-cluster0-c71ss0-core0-device">
2275 <span id="soc-doc-j784s4-public-clks-compute-cluster0-c71ss0-core0"></span><h3>Clocks for COMPUTE_CLUSTER0_C71SS0_CORE0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-c71ss0-core0-device" title="Permalink to this headline">¶</a></h3>
2276 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_COMPUTE_CLUSTER0_C71SS0_CORE0</span></a> (ID = 31)</p>
2277 <p>Following is a mapping of Clocks IDs to function:</p>
2278 <table border="1" class="docutils">
2279 <colgroup>
2280 <col width="16%" />
2281 <col width="68%" />
2282 <col width="17%" />
2283 </colgroup>
2284 <thead valign="bottom">
2285 <tr class="row-odd"><th class="head">Clock ID</th>
2286 <th class="head">Name</th>
2287 <th class="head">Function</th>
2288 </tr>
2289 </thead>
2290 <tbody valign="top">
2291 <tr class="row-even"><td>0</td>
2292 <td>DEV_COMPUTE_CLUSTER0_C71SS0_CORE0_C7X_CLK</td>
2293 <td>Input clock</td>
2294 </tr>
2295 <tr class="row-odd"><td>2</td>
2296 <td>DEV_COMPUTE_CLUSTER0_C71SS0_CORE0_PLL_CTRL_CLK_CLK</td>
2297 <td>Input clock</td>
2298 </tr>
2299 </tbody>
2300 </table>
2301 </div>
2302 <div class="section" id="clocks-for-compute-cluster0-c71ss0-mma-0-device">
2303 <span id="soc-doc-j784s4-public-clks-compute-cluster0-c71ss0-mma-0"></span><h3>Clocks for COMPUTE_CLUSTER0_C71SS0_MMA_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-c71ss0-mma-0-device" title="Permalink to this headline">¶</a></h3>
2304 <p><strong>This device has no defined clocks.</strong></p>
2305 </div>
2306 <div class="section" id="clocks-for-compute-cluster0-c71ss1-device">
2307 <span id="soc-doc-j784s4-public-clks-compute-cluster0-c71ss1"></span><h3>Clocks for COMPUTE_CLUSTER0_C71SS1 Device<a class="headerlink" href="#clocks-for-compute-cluster0-c71ss1-device" title="Permalink to this headline">¶</a></h3>
2308 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_COMPUTE_CLUSTER0_C71SS1</span></a> (ID = 33)</p>
2309 <p>Following is a mapping of Clocks IDs to function:</p>
2310 <table border="1" class="docutils">
2311 <colgroup>
2312 <col width="19%" />
2313 <col width="60%" />
2314 <col width="21%" />
2315 </colgroup>
2316 <thead valign="bottom">
2317 <tr class="row-odd"><th class="head">Clock ID</th>
2318 <th class="head">Name</th>
2319 <th class="head">Function</th>
2320 </tr>
2321 </thead>
2322 <tbody valign="top">
2323 <tr class="row-even"><td>3</td>
2324 <td>DEV_COMPUTE_CLUSTER0_C71SS1_C7X_CLK</td>
2325 <td>Input clock</td>
2326 </tr>
2327 </tbody>
2328 </table>
2329 </div>
2330 <div class="section" id="clocks-for-compute-cluster0-c71ss1-core0-device">
2331 <span id="soc-doc-j784s4-public-clks-compute-cluster0-c71ss1-core0"></span><h3>Clocks for COMPUTE_CLUSTER0_C71SS1_CORE0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-c71ss1-core0-device" title="Permalink to this headline">¶</a></h3>
2332 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_COMPUTE_CLUSTER0_C71SS1_CORE0</span></a> (ID = 34)</p>
2333 <p>Following is a mapping of Clocks IDs to function:</p>
2334 <table border="1" class="docutils">
2335 <colgroup>
2336 <col width="16%" />
2337 <col width="68%" />
2338 <col width="17%" />
2339 </colgroup>
2340 <thead valign="bottom">
2341 <tr class="row-odd"><th class="head">Clock ID</th>
2342 <th class="head">Name</th>
2343 <th class="head">Function</th>
2344 </tr>
2345 </thead>
2346 <tbody valign="top">
2347 <tr class="row-even"><td>0</td>
2348 <td>DEV_COMPUTE_CLUSTER0_C71SS1_CORE0_C7X_CLK</td>
2349 <td>Input clock</td>
2350 </tr>
2351 <tr class="row-odd"><td>2</td>
2352 <td>DEV_COMPUTE_CLUSTER0_C71SS1_CORE0_PLL_CTRL_CLK_CLK</td>
2353 <td>Input clock</td>
2354 </tr>
2355 </tbody>
2356 </table>
2357 </div>
2358 <div class="section" id="clocks-for-compute-cluster0-c71ss1-mma-0-device">
2359 <span id="soc-doc-j784s4-public-clks-compute-cluster0-c71ss1-mma-0"></span><h3>Clocks for COMPUTE_CLUSTER0_C71SS1_MMA_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-c71ss1-mma-0-device" title="Permalink to this headline">¶</a></h3>
2360 <p><strong>This device has no defined clocks.</strong></p>
2361 </div>
2362 <div class="section" id="clocks-for-compute-cluster0-c71ss2-device">
2363 <span id="soc-doc-j784s4-public-clks-compute-cluster0-c71ss2"></span><h3>Clocks for COMPUTE_CLUSTER0_C71SS2 Device<a class="headerlink" href="#clocks-for-compute-cluster0-c71ss2-device" title="Permalink to this headline">¶</a></h3>
2364 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_COMPUTE_CLUSTER0_C71SS2</span></a> (ID = 37)</p>
2365 <p>Following is a mapping of Clocks IDs to function:</p>
2366 <table border="1" class="docutils">
2367 <colgroup>
2368 <col width="19%" />
2369 <col width="60%" />
2370 <col width="21%" />
2371 </colgroup>
2372 <thead valign="bottom">
2373 <tr class="row-odd"><th class="head">Clock ID</th>
2374 <th class="head">Name</th>
2375 <th class="head">Function</th>
2376 </tr>
2377 </thead>
2378 <tbody valign="top">
2379 <tr class="row-even"><td>3</td>
2380 <td>DEV_COMPUTE_CLUSTER0_C71SS2_C7X_CLK</td>
2381 <td>Input clock</td>
2382 </tr>
2383 </tbody>
2384 </table>
2385 </div>
2386 <div class="section" id="clocks-for-compute-cluster0-c71ss2-core0-device">
2387 <span id="soc-doc-j784s4-public-clks-compute-cluster0-c71ss2-core0"></span><h3>Clocks for COMPUTE_CLUSTER0_C71SS2_CORE0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-c71ss2-core0-device" title="Permalink to this headline">¶</a></h3>
2388 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_COMPUTE_CLUSTER0_C71SS2_CORE0</span></a> (ID = 38)</p>
2389 <p>Following is a mapping of Clocks IDs to function:</p>
2390 <table border="1" class="docutils">
2391 <colgroup>
2392 <col width="18%" />
2393 <col width="63%" />
2394 <col width="19%" />
2395 </colgroup>
2396 <thead valign="bottom">
2397 <tr class="row-odd"><th class="head">Clock ID</th>
2398 <th class="head">Name</th>
2399 <th class="head">Function</th>
2400 </tr>
2401 </thead>
2402 <tbody valign="top">
2403 <tr class="row-even"><td>0</td>
2404 <td>DEV_COMPUTE_CLUSTER0_C71SS2_CORE0_C7X_CLK</td>
2405 <td>Input clock</td>
2406 </tr>
2407 </tbody>
2408 </table>
2409 </div>
2410 <div class="section" id="clocks-for-compute-cluster0-c71ss2-mma-0-device">
2411 <span id="soc-doc-j784s4-public-clks-compute-cluster0-c71ss2-mma-0"></span><h3>Clocks for COMPUTE_CLUSTER0_C71SS2_MMA_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-c71ss2-mma-0-device" title="Permalink to this headline">¶</a></h3>
2412 <p><strong>This device has no defined clocks.</strong></p>
2413 </div>
2414 <div class="section" id="clocks-for-compute-cluster0-c71ss3-device">
2415 <span id="soc-doc-j784s4-public-clks-compute-cluster0-c71ss3"></span><h3>Clocks for COMPUTE_CLUSTER0_C71SS3 Device<a class="headerlink" href="#clocks-for-compute-cluster0-c71ss3-device" title="Permalink to this headline">¶</a></h3>
2416 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_COMPUTE_CLUSTER0_C71SS3</span></a> (ID = 40)</p>
2417 <p>Following is a mapping of Clocks IDs to function:</p>
2418 <table border="1" class="docutils">
2419 <colgroup>
2420 <col width="19%" />
2421 <col width="60%" />
2422 <col width="21%" />
2423 </colgroup>
2424 <thead valign="bottom">
2425 <tr class="row-odd"><th class="head">Clock ID</th>
2426 <th class="head">Name</th>
2427 <th class="head">Function</th>
2428 </tr>
2429 </thead>
2430 <tbody valign="top">
2431 <tr class="row-even"><td>3</td>
2432 <td>DEV_COMPUTE_CLUSTER0_C71SS3_C7X_CLK</td>
2433 <td>Input clock</td>
2434 </tr>
2435 </tbody>
2436 </table>
2437 </div>
2438 <div class="section" id="clocks-for-compute-cluster0-c71ss3-core0-device">
2439 <span id="soc-doc-j784s4-public-clks-compute-cluster0-c71ss3-core0"></span><h3>Clocks for COMPUTE_CLUSTER0_C71SS3_CORE0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-c71ss3-core0-device" title="Permalink to this headline">¶</a></h3>
2440 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_COMPUTE_CLUSTER0_C71SS3_CORE0</span></a> (ID = 41)</p>
2441 <p>Following is a mapping of Clocks IDs to function:</p>
2442 <table border="1" class="docutils">
2443 <colgroup>
2444 <col width="18%" />
2445 <col width="63%" />
2446 <col width="19%" />
2447 </colgroup>
2448 <thead valign="bottom">
2449 <tr class="row-odd"><th class="head">Clock ID</th>
2450 <th class="head">Name</th>
2451 <th class="head">Function</th>
2452 </tr>
2453 </thead>
2454 <tbody valign="top">
2455 <tr class="row-even"><td>0</td>
2456 <td>DEV_COMPUTE_CLUSTER0_C71SS3_CORE0_C7X_CLK</td>
2457 <td>Input clock</td>
2458 </tr>
2459 </tbody>
2460 </table>
2461 </div>
2462 <div class="section" id="clocks-for-compute-cluster0-c71ss3-mma-0-device">
2463 <span id="soc-doc-j784s4-public-clks-compute-cluster0-c71ss3-mma-0"></span><h3>Clocks for COMPUTE_CLUSTER0_C71SS3_MMA_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-c71ss3-mma-0-device" title="Permalink to this headline">¶</a></h3>
2464 <p><strong>This device has no defined clocks.</strong></p>
2465 </div>
2466 <div class="section" id="clocks-for-compute-cluster0-cfg-wrap-0-device">
2467 <span id="soc-doc-j784s4-public-clks-compute-cluster0-cfg-wrap-0"></span><h3>Clocks for COMPUTE_CLUSTER0_CFG_WRAP_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-cfg-wrap-0-device" title="Permalink to this headline">¶</a></h3>
2468 <p><strong>This device has no defined clocks.</strong></p>
2469 </div>
2470 <div class="section" id="clocks-for-compute-cluster0-clec-device">
2471 <span id="soc-doc-j784s4-public-clks-compute-cluster0-clec"></span><h3>Clocks for COMPUTE_CLUSTER0_CLEC Device<a class="headerlink" href="#clocks-for-compute-cluster0-clec-device" title="Permalink to this headline">¶</a></h3>
2472 <p><strong>This device has no defined clocks.</strong></p>
2473 </div>
2474 <div class="section" id="clocks-for-compute-cluster0-core-core-device">
2475 <span id="soc-doc-j784s4-public-clks-compute-cluster0-core-core"></span><h3>Clocks for COMPUTE_CLUSTER0_CORE_CORE Device<a class="headerlink" href="#clocks-for-compute-cluster0-core-core-device" title="Permalink to this headline">¶</a></h3>
2476 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_COMPUTE_CLUSTER0_CORE_CORE</span></a> (ID = 45)</p>
2477 <p>Following is a mapping of Clocks IDs to function:</p>
2478 <table border="1" class="docutils">
2479 <colgroup>
2480 <col width="17%" />
2481 <col width="65%" />
2482 <col width="18%" />
2483 </colgroup>
2484 <thead valign="bottom">
2485 <tr class="row-odd"><th class="head">Clock ID</th>
2486 <th class="head">Name</th>
2487 <th class="head">Function</th>
2488 </tr>
2489 </thead>
2490 <tbody valign="top">
2491 <tr class="row-even"><td>1</td>
2492 <td>DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK</td>
2493 <td>Input clock</td>
2494 </tr>
2495 </tbody>
2496 </table>
2497 </div>
2498 <div class="section" id="clocks-for-compute-cluster0-ddr32ss-emif-0-device">
2499 <span id="soc-doc-j784s4-public-clks-compute-cluster0-ddr32ss-emif-0"></span><h3>Clocks for COMPUTE_CLUSTER0_DDR32SS_EMIF_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-ddr32ss-emif-0-device" title="Permalink to this headline">¶</a></h3>
2500 <p><strong>This device has no defined clocks.</strong></p>
2501 </div>
2502 <div class="section" id="clocks-for-compute-cluster0-ddr32ss-emif-1-device">
2503 <span id="soc-doc-j784s4-public-clks-compute-cluster0-ddr32ss-emif-1"></span><h3>Clocks for COMPUTE_CLUSTER0_DDR32SS_EMIF_1 Device<a class="headerlink" href="#clocks-for-compute-cluster0-ddr32ss-emif-1-device" title="Permalink to this headline">¶</a></h3>
2504 <p><strong>This device has no defined clocks.</strong></p>
2505 </div>
2506 <div class="section" id="clocks-for-compute-cluster0-ddr32ss-emif-2-device">
2507 <span id="soc-doc-j784s4-public-clks-compute-cluster0-ddr32ss-emif-2"></span><h3>Clocks for COMPUTE_CLUSTER0_DDR32SS_EMIF_2 Device<a class="headerlink" href="#clocks-for-compute-cluster0-ddr32ss-emif-2-device" title="Permalink to this headline">¶</a></h3>
2508 <p><strong>This device has no defined clocks.</strong></p>
2509 </div>
2510 <div class="section" id="clocks-for-compute-cluster0-ddr32ss-emif-3-device">
2511 <span id="soc-doc-j784s4-public-clks-compute-cluster0-ddr32ss-emif-3"></span><h3>Clocks for COMPUTE_CLUSTER0_DDR32SS_EMIF_3 Device<a class="headerlink" href="#clocks-for-compute-cluster0-ddr32ss-emif-3-device" title="Permalink to this headline">¶</a></h3>
2512 <p><strong>This device has no defined clocks.</strong></p>
2513 </div>
2514 <div class="section" id="clocks-for-compute-cluster0-debug-wrap-0-device">
2515 <span id="soc-doc-j784s4-public-clks-compute-cluster0-debug-wrap-0"></span><h3>Clocks for COMPUTE_CLUSTER0_DEBUG_WRAP_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-debug-wrap-0-device" title="Permalink to this headline">¶</a></h3>
2516 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0</span></a> (ID = 50)</p>
2517 <p>Following is a mapping of Clocks IDs to function:</p>
2518 <table border="1" class="docutils">
2519 <colgroup>
2520 <col width="16%" />
2521 <col width="66%" />
2522 <col width="18%" />
2523 </colgroup>
2524 <thead valign="bottom">
2525 <tr class="row-odd"><th class="head">Clock ID</th>
2526 <th class="head">Name</th>
2527 <th class="head">Function</th>
2528 </tr>
2529 </thead>
2530 <tbody valign="top">
2531 <tr class="row-even"><td>0</td>
2532 <td>DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK1_CLK_CLK</td>
2533 <td>Input clock</td>
2534 </tr>
2535 <tr class="row-odd"><td>1</td>
2536 <td>DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK2_CLK_CLK</td>
2537 <td>Input clock</td>
2538 </tr>
2539 </tbody>
2540 </table>
2541 </div>
2542 <div class="section" id="clocks-for-compute-cluster0-dmsc-wrap-0-device">
2543 <span id="soc-doc-j784s4-public-clks-compute-cluster0-dmsc-wrap-0"></span><h3>Clocks for COMPUTE_CLUSTER0_DMSC_WRAP_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-dmsc-wrap-0-device" title="Permalink to this headline">¶</a></h3>
2544 <p><strong>This device has no defined clocks.</strong></p>
2545 </div>
2546 <div class="section" id="clocks-for-compute-cluster0-dru0-device">
2547 <span id="soc-doc-j784s4-public-clks-compute-cluster0-dru0"></span><h3>Clocks for COMPUTE_CLUSTER0_DRU0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-dru0-device" title="Permalink to this headline">¶</a></h3>
2548 <p><strong>This device has no defined clocks.</strong></p>
2549 </div>
2550 <div class="section" id="clocks-for-compute-cluster0-dru4-device">
2551 <span id="soc-doc-j784s4-public-clks-compute-cluster0-dru4"></span><h3>Clocks for COMPUTE_CLUSTER0_DRU4 Device<a class="headerlink" href="#clocks-for-compute-cluster0-dru4-device" title="Permalink to this headline">¶</a></h3>
2552 <p><strong>This device has no defined clocks.</strong></p>
2553 </div>
2554 <div class="section" id="clocks-for-compute-cluster0-dru5-device">
2555 <span id="soc-doc-j784s4-public-clks-compute-cluster0-dru5"></span><h3>Clocks for COMPUTE_CLUSTER0_DRU5 Device<a class="headerlink" href="#clocks-for-compute-cluster0-dru5-device" title="Permalink to this headline">¶</a></h3>
2556 <p><strong>This device has no defined clocks.</strong></p>
2557 </div>
2558 <div class="section" id="clocks-for-compute-cluster0-dru6-device">
2559 <span id="soc-doc-j784s4-public-clks-compute-cluster0-dru6"></span><h3>Clocks for COMPUTE_CLUSTER0_DRU6 Device<a class="headerlink" href="#clocks-for-compute-cluster0-dru6-device" title="Permalink to this headline">¶</a></h3>
2560 <p><strong>This device has no defined clocks.</strong></p>
2561 </div>
2562 <div class="section" id="clocks-for-compute-cluster0-dru7-device">
2563 <span id="soc-doc-j784s4-public-clks-compute-cluster0-dru7"></span><h3>Clocks for COMPUTE_CLUSTER0_DRU7 Device<a class="headerlink" href="#clocks-for-compute-cluster0-dru7-device" title="Permalink to this headline">¶</a></h3>
2564 <p><strong>This device has no defined clocks.</strong></p>
2565 </div>
2566 <div class="section" id="clocks-for-compute-cluster0-en-msmc-domain-0-device">
2567 <span id="soc-doc-j784s4-public-clks-compute-cluster0-en-msmc-domain-0"></span><h3>Clocks for COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-en-msmc-domain-0-device" title="Permalink to this headline">¶</a></h3>
2568 <p><strong>This device has no defined clocks.</strong></p>
2569 </div>
2570 <div class="section" id="clocks-for-compute-cluster0-gic500ss-device">
2571 <span id="soc-doc-j784s4-public-clks-compute-cluster0-gic500ss"></span><h3>Clocks for COMPUTE_CLUSTER0_GIC500SS Device<a class="headerlink" href="#clocks-for-compute-cluster0-gic500ss-device" title="Permalink to this headline">¶</a></h3>
2572 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS</span></a> (ID = 58)</p>
2573 <p>Following is a mapping of Clocks IDs to function:</p>
2574 <table border="1" class="docutils">
2575 <colgroup>
2576 <col width="18%" />
2577 <col width="62%" />
2578 <col width="20%" />
2579 </colgroup>
2580 <thead valign="bottom">
2581 <tr class="row-odd"><th class="head">Clock ID</th>
2582 <th class="head">Name</th>
2583 <th class="head">Function</th>
2584 </tr>
2585 </thead>
2586 <tbody valign="top">
2587 <tr class="row-even"><td>0</td>
2588 <td>DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK</td>
2589 <td>Input clock</td>
2590 </tr>
2591 </tbody>
2592 </table>
2593 </div>
2594 <div class="section" id="clocks-for-compute-cluster0-msmc2-wrap-0-device">
2595 <span id="soc-doc-j784s4-public-clks-compute-cluster0-msmc2-wrap-0"></span><h3>Clocks for COMPUTE_CLUSTER0_MSMC2_WRAP_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-msmc2-wrap-0-device" title="Permalink to this headline">¶</a></h3>
2596 <p><strong>This device has no defined clocks.</strong></p>
2597 </div>
2598 <div class="section" id="clocks-for-compute-cluster0-msmc-dft-embed-pbist-0-device">
2599 <span id="soc-doc-j784s4-public-clks-compute-cluster0-msmc-dft-embed-pbist-0"></span><h3>Clocks for COMPUTE_CLUSTER0_MSMC_DFT_EMBED_PBIST_0 Device<a class="headerlink" href="#clocks-for-compute-cluster0-msmc-dft-embed-pbist-0-device" title="Permalink to this headline">¶</a></h3>
2600 <p><strong>This device has no defined clocks.</strong></p>
2601 </div>
2602 <div class="section" id="clocks-for-cpsw1-device">
2603 <span id="soc-doc-j784s4-public-clks-cpsw1"></span><h3>Clocks for CPSW1 Device<a class="headerlink" href="#clocks-for-cpsw1-device" title="Permalink to this headline">¶</a></h3>
2604 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CPSW1</span></a> (ID = 62)</p>
2605 <p>Following is a mapping of Clocks IDs to function:</p>
2606 <table border="1" class="docutils">
2607 <colgroup>
2608 <col width="9%" />
2609 <col width="53%" />
2610 <col width="38%" />
2611 </colgroup>
2612 <thead valign="bottom">
2613 <tr class="row-odd"><th class="head">Clock ID</th>
2614 <th class="head">Name</th>
2615 <th class="head">Function</th>
2616 </tr>
2617 </thead>
2618 <tbody valign="top">
2619 <tr class="row-even"><td>0</td>
2620 <td>DEV_CPSW1_CPPI_CLK_CLK</td>
2621 <td>Input clock</td>
2622 </tr>
2623 <tr class="row-odd"><td>1</td>
2624 <td>DEV_CPSW1_CPTS_GENF0</td>
2625 <td>Output clock</td>
2626 </tr>
2627 <tr class="row-even"><td>3</td>
2628 <td>DEV_CPSW1_CPTS_RFT_CLK</td>
2629 <td>Input muxed clock</td>
2630 </tr>
2631 <tr class="row-odd"><td>4</td>
2632 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
2633 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2634 </tr>
2635 <tr class="row-even"><td>5</td>
2636 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
2637 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2638 </tr>
2639 <tr class="row-odd"><td>6</td>
2640 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
2641 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2642 </tr>
2643 <tr class="row-even"><td>7</td>
2644 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
2645 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2646 </tr>
2647 <tr class="row-odd"><td>8</td>
2648 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
2649 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2650 </tr>
2651 <tr class="row-even"><td>9</td>
2652 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
2653 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2654 </tr>
2655 <tr class="row-odd"><td>10</td>
2656 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK</td>
2657 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2658 </tr>
2659 <tr class="row-even"><td>11</td>
2660 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK</td>
2661 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2662 </tr>
2663 <tr class="row-odd"><td>12</td>
2664 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK</td>
2665 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2666 </tr>
2667 <tr class="row-even"><td>13</td>
2668 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK</td>
2669 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2670 </tr>
2671 <tr class="row-odd"><td>14</td>
2672 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK</td>
2673 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2674 </tr>
2675 <tr class="row-even"><td>15</td>
2676 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK</td>
2677 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2678 </tr>
2679 <tr class="row-odd"><td>16</td>
2680 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK</td>
2681 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2682 </tr>
2683 <tr class="row-even"><td>17</td>
2684 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK</td>
2685 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2686 </tr>
2687 <tr class="row-odd"><td>18</td>
2688 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
2689 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2690 </tr>
2691 <tr class="row-even"><td>19</td>
2692 <td>DEV_CPSW1_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
2693 <td>Parent input clock option to DEV_CPSW1_CPTS_RFT_CLK</td>
2694 </tr>
2695 <tr class="row-odd"><td>20</td>
2696 <td>DEV_CPSW1_GMII1_MR_CLK</td>
2697 <td>Input clock</td>
2698 </tr>
2699 <tr class="row-even"><td>21</td>
2700 <td>DEV_CPSW1_GMII1_MT_CLK</td>
2701 <td>Input clock</td>
2702 </tr>
2703 <tr class="row-odd"><td>22</td>
2704 <td>DEV_CPSW1_GMII_RFT_CLK</td>
2705 <td>Input clock</td>
2706 </tr>
2707 <tr class="row-even"><td>23</td>
2708 <td>DEV_CPSW1_MDIO_MDCLK_O</td>
2709 <td>Output clock</td>
2710 </tr>
2711 <tr class="row-odd"><td>24</td>
2712 <td>DEV_CPSW1_RGMII1_RXC_I</td>
2713 <td>Input clock</td>
2714 </tr>
2715 <tr class="row-even"><td>26</td>
2716 <td>DEV_CPSW1_RGMII1_TXC_O</td>
2717 <td>Output clock</td>
2718 </tr>
2719 <tr class="row-odd"><td>27</td>
2720 <td>DEV_CPSW1_RGMII_MHZ_250_CLK</td>
2721 <td>Input clock</td>
2722 </tr>
2723 <tr class="row-even"><td>28</td>
2724 <td>DEV_CPSW1_RGMII_MHZ_50_CLK</td>
2725 <td>Input clock</td>
2726 </tr>
2727 <tr class="row-odd"><td>29</td>
2728 <td>DEV_CPSW1_RGMII_MHZ_5_CLK</td>
2729 <td>Input clock</td>
2730 </tr>
2731 <tr class="row-even"><td>30</td>
2732 <td>DEV_CPSW1_RMII_MHZ_50_CLK</td>
2733 <td>Input clock</td>
2734 </tr>
2735 </tbody>
2736 </table>
2737 </div>
2738 <div class="section" id="clocks-for-cpsw-9xuss-j7am0-device">
2739 <span id="soc-doc-j784s4-public-clks-cpsw-9xuss-j7am0"></span><h3>Clocks for CPSW_9XUSS_J7AM0 Device<a class="headerlink" href="#clocks-for-cpsw-9xuss-j7am0-device" title="Permalink to this headline">¶</a></h3>
2740 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CPSW_9XUSS_J7AM0</span></a> (ID = 64)</p>
2741 <p>Following is a mapping of Clocks IDs to function:</p>
2742 <table border="1" class="docutils">
2743 <colgroup>
2744 <col width="8%" />
2745 <col width="53%" />
2746 <col width="40%" />
2747 </colgroup>
2748 <thead valign="bottom">
2749 <tr class="row-odd"><th class="head">Clock ID</th>
2750 <th class="head">Name</th>
2751 <th class="head">Function</th>
2752 </tr>
2753 </thead>
2754 <tbody valign="top">
2755 <tr class="row-even"><td>0</td>
2756 <td>DEV_CPSW_9XUSS_J7AM0_CPPI_CLK_CLK</td>
2757 <td>Input clock</td>
2758 </tr>
2759 <tr class="row-odd"><td>1</td>
2760 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_GENF0</td>
2761 <td>Output clock</td>
2762 </tr>
2763 <tr class="row-even"><td>3</td>
2764 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2765 <td>Input muxed clock</td>
2766 </tr>
2767 <tr class="row-odd"><td>4</td>
2768 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
2769 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2770 </tr>
2771 <tr class="row-even"><td>5</td>
2772 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
2773 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2774 </tr>
2775 <tr class="row-odd"><td>6</td>
2776 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
2777 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2778 </tr>
2779 <tr class="row-even"><td>7</td>
2780 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
2781 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2782 </tr>
2783 <tr class="row-odd"><td>8</td>
2784 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
2785 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2786 </tr>
2787 <tr class="row-even"><td>9</td>
2788 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
2789 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2790 </tr>
2791 <tr class="row-odd"><td>10</td>
2792 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK</td>
2793 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2794 </tr>
2795 <tr class="row-even"><td>11</td>
2796 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK</td>
2797 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2798 </tr>
2799 <tr class="row-odd"><td>12</td>
2800 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK</td>
2801 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2802 </tr>
2803 <tr class="row-even"><td>13</td>
2804 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK</td>
2805 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2806 </tr>
2807 <tr class="row-odd"><td>14</td>
2808 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK</td>
2809 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2810 </tr>
2811 <tr class="row-even"><td>15</td>
2812 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK</td>
2813 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2814 </tr>
2815 <tr class="row-odd"><td>16</td>
2816 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK</td>
2817 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2818 </tr>
2819 <tr class="row-even"><td>17</td>
2820 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK</td>
2821 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2822 </tr>
2823 <tr class="row-odd"><td>18</td>
2824 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
2825 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2826 </tr>
2827 <tr class="row-even"><td>19</td>
2828 <td>DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
2829 <td>Parent input clock option to DEV_CPSW_9XUSS_J7AM0_CPTS_RFT_CLK</td>
2830 </tr>
2831 <tr class="row-odd"><td>22</td>
2832 <td>DEV_CPSW_9XUSS_J7AM0_GMII1_MR_CLK</td>
2833 <td>Input clock</td>
2834 </tr>
2835 <tr class="row-even"><td>23</td>
2836 <td>DEV_CPSW_9XUSS_J7AM0_GMII1_MT_CLK</td>
2837 <td>Input clock</td>
2838 </tr>
2839 <tr class="row-odd"><td>24</td>
2840 <td>DEV_CPSW_9XUSS_J7AM0_GMII2_MR_CLK</td>
2841 <td>Input clock</td>
2842 </tr>
2843 <tr class="row-even"><td>25</td>
2844 <td>DEV_CPSW_9XUSS_J7AM0_GMII2_MT_CLK</td>
2845 <td>Input clock</td>
2846 </tr>
2847 <tr class="row-odd"><td>26</td>
2848 <td>DEV_CPSW_9XUSS_J7AM0_GMII3_MR_CLK</td>
2849 <td>Input clock</td>
2850 </tr>
2851 <tr class="row-even"><td>27</td>
2852 <td>DEV_CPSW_9XUSS_J7AM0_GMII3_MT_CLK</td>
2853 <td>Input clock</td>
2854 </tr>
2855 <tr class="row-odd"><td>28</td>
2856 <td>DEV_CPSW_9XUSS_J7AM0_GMII4_MR_CLK</td>
2857 <td>Input clock</td>
2858 </tr>
2859 <tr class="row-even"><td>29</td>
2860 <td>DEV_CPSW_9XUSS_J7AM0_GMII4_MT_CLK</td>
2861 <td>Input clock</td>
2862 </tr>
2863 <tr class="row-odd"><td>30</td>
2864 <td>DEV_CPSW_9XUSS_J7AM0_GMII5_MR_CLK</td>
2865 <td>Input clock</td>
2866 </tr>
2867 <tr class="row-even"><td>31</td>
2868 <td>DEV_CPSW_9XUSS_J7AM0_GMII5_MT_CLK</td>
2869 <td>Input clock</td>
2870 </tr>
2871 <tr class="row-odd"><td>32</td>
2872 <td>DEV_CPSW_9XUSS_J7AM0_GMII6_MR_CLK</td>
2873 <td>Input clock</td>
2874 </tr>
2875 <tr class="row-even"><td>33</td>
2876 <td>DEV_CPSW_9XUSS_J7AM0_GMII6_MT_CLK</td>
2877 <td>Input clock</td>
2878 </tr>
2879 <tr class="row-odd"><td>34</td>
2880 <td>DEV_CPSW_9XUSS_J7AM0_GMII7_MR_CLK</td>
2881 <td>Input clock</td>
2882 </tr>
2883 <tr class="row-even"><td>35</td>
2884 <td>DEV_CPSW_9XUSS_J7AM0_GMII7_MT_CLK</td>
2885 <td>Input clock</td>
2886 </tr>
2887 <tr class="row-odd"><td>36</td>
2888 <td>DEV_CPSW_9XUSS_J7AM0_GMII8_MR_CLK</td>
2889 <td>Input clock</td>
2890 </tr>
2891 <tr class="row-even"><td>37</td>
2892 <td>DEV_CPSW_9XUSS_J7AM0_GMII8_MT_CLK</td>
2893 <td>Input clock</td>
2894 </tr>
2895 <tr class="row-odd"><td>38</td>
2896 <td>DEV_CPSW_9XUSS_J7AM0_GMII_RFT_CLK</td>
2897 <td>Input clock</td>
2898 </tr>
2899 <tr class="row-even"><td>39</td>
2900 <td>DEV_CPSW_9XUSS_J7AM0_MDIO_MDCLK_O</td>
2901 <td>Output clock</td>
2902 </tr>
2903 <tr class="row-odd"><td>56</td>
2904 <td>DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_250_CLK</td>
2905 <td>Input clock</td>
2906 </tr>
2907 <tr class="row-even"><td>57</td>
2908 <td>DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_50_CLK</td>
2909 <td>Input clock</td>
2910 </tr>
2911 <tr class="row-odd"><td>58</td>
2912 <td>DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_5_CLK</td>
2913 <td>Input clock</td>
2914 </tr>
2915 <tr class="row-even"><td>59</td>
2916 <td>DEV_CPSW_9XUSS_J7AM0_RMII_MHZ_50_CLK</td>
2917 <td>Input clock</td>
2918 </tr>
2919 <tr class="row-odd"><td>60</td>
2920 <td>DEV_CPSW_9XUSS_J7AM0_SERDES1_REFCLK</td>
2921 <td>Input clock</td>
2922 </tr>
2923 <tr class="row-even"><td>61</td>
2924 <td>DEV_CPSW_9XUSS_J7AM0_SERDES1_RXCLK</td>
2925 <td>Input clock</td>
2926 </tr>
2927 <tr class="row-odd"><td>62</td>
2928 <td>DEV_CPSW_9XUSS_J7AM0_SERDES1_RXFCLK</td>
2929 <td>Input clock</td>
2930 </tr>
2931 <tr class="row-even"><td>63</td>
2932 <td>DEV_CPSW_9XUSS_J7AM0_SERDES1_TXCLK</td>
2933 <td>Output clock</td>
2934 </tr>
2935 <tr class="row-odd"><td>64</td>
2936 <td>DEV_CPSW_9XUSS_J7AM0_SERDES1_TXFCLK</td>
2937 <td>Input clock</td>
2938 </tr>
2939 <tr class="row-even"><td>65</td>
2940 <td>DEV_CPSW_9XUSS_J7AM0_SERDES1_TXMCLK</td>
2941 <td>Input clock</td>
2942 </tr>
2943 <tr class="row-odd"><td>66</td>
2944 <td>DEV_CPSW_9XUSS_J7AM0_SERDES2_REFCLK</td>
2945 <td>Input clock</td>
2946 </tr>
2947 <tr class="row-even"><td>67</td>
2948 <td>DEV_CPSW_9XUSS_J7AM0_SERDES2_RXCLK</td>
2949 <td>Input clock</td>
2950 </tr>
2951 <tr class="row-odd"><td>68</td>
2952 <td>DEV_CPSW_9XUSS_J7AM0_SERDES2_RXFCLK</td>
2953 <td>Input clock</td>
2954 </tr>
2955 <tr class="row-even"><td>69</td>
2956 <td>DEV_CPSW_9XUSS_J7AM0_SERDES2_TXCLK</td>
2957 <td>Output clock</td>
2958 </tr>
2959 <tr class="row-odd"><td>70</td>
2960 <td>DEV_CPSW_9XUSS_J7AM0_SERDES2_TXFCLK</td>
2961 <td>Input clock</td>
2962 </tr>
2963 <tr class="row-even"><td>71</td>
2964 <td>DEV_CPSW_9XUSS_J7AM0_SERDES2_TXMCLK</td>
2965 <td>Input clock</td>
2966 </tr>
2967 <tr class="row-odd"><td>72</td>
2968 <td>DEV_CPSW_9XUSS_J7AM0_SERDES3_REFCLK</td>
2969 <td>Input clock</td>
2970 </tr>
2971 <tr class="row-even"><td>73</td>
2972 <td>DEV_CPSW_9XUSS_J7AM0_SERDES3_RXCLK</td>
2973 <td>Input clock</td>
2974 </tr>
2975 <tr class="row-odd"><td>74</td>
2976 <td>DEV_CPSW_9XUSS_J7AM0_SERDES3_RXFCLK</td>
2977 <td>Input clock</td>
2978 </tr>
2979 <tr class="row-even"><td>75</td>
2980 <td>DEV_CPSW_9XUSS_J7AM0_SERDES3_TXCLK</td>
2981 <td>Output clock</td>
2982 </tr>
2983 <tr class="row-odd"><td>76</td>
2984 <td>DEV_CPSW_9XUSS_J7AM0_SERDES3_TXFCLK</td>
2985 <td>Input clock</td>
2986 </tr>
2987 <tr class="row-even"><td>77</td>
2988 <td>DEV_CPSW_9XUSS_J7AM0_SERDES3_TXMCLK</td>
2989 <td>Input clock</td>
2990 </tr>
2991 <tr class="row-odd"><td>78</td>
2992 <td>DEV_CPSW_9XUSS_J7AM0_SERDES4_REFCLK</td>
2993 <td>Input clock</td>
2994 </tr>
2995 <tr class="row-even"><td>79</td>
2996 <td>DEV_CPSW_9XUSS_J7AM0_SERDES4_RXCLK</td>
2997 <td>Input clock</td>
2998 </tr>
2999 <tr class="row-odd"><td>80</td>
3000 <td>DEV_CPSW_9XUSS_J7AM0_SERDES4_RXFCLK</td>
3001 <td>Input clock</td>
3002 </tr>
3003 <tr class="row-even"><td>81</td>
3004 <td>DEV_CPSW_9XUSS_J7AM0_SERDES4_TXCLK</td>
3005 <td>Output clock</td>
3006 </tr>
3007 <tr class="row-odd"><td>82</td>
3008 <td>DEV_CPSW_9XUSS_J7AM0_SERDES4_TXFCLK</td>
3009 <td>Input clock</td>
3010 </tr>
3011 <tr class="row-even"><td>83</td>
3012 <td>DEV_CPSW_9XUSS_J7AM0_SERDES4_TXMCLK</td>
3013 <td>Input clock</td>
3014 </tr>
3015 <tr class="row-odd"><td>84</td>
3016 <td>DEV_CPSW_9XUSS_J7AM0_SERDES5_REFCLK</td>
3017 <td>Input clock</td>
3018 </tr>
3019 <tr class="row-even"><td>85</td>
3020 <td>DEV_CPSW_9XUSS_J7AM0_SERDES5_RXCLK</td>
3021 <td>Input clock</td>
3022 </tr>
3023 <tr class="row-odd"><td>86</td>
3024 <td>DEV_CPSW_9XUSS_J7AM0_SERDES5_RXFCLK</td>
3025 <td>Input clock</td>
3026 </tr>
3027 <tr class="row-even"><td>87</td>
3028 <td>DEV_CPSW_9XUSS_J7AM0_SERDES5_TXCLK</td>
3029 <td>Output clock</td>
3030 </tr>
3031 <tr class="row-odd"><td>88</td>
3032 <td>DEV_CPSW_9XUSS_J7AM0_SERDES5_TXFCLK</td>
3033 <td>Input clock</td>
3034 </tr>
3035 <tr class="row-even"><td>89</td>
3036 <td>DEV_CPSW_9XUSS_J7AM0_SERDES5_TXMCLK</td>
3037 <td>Input clock</td>
3038 </tr>
3039 <tr class="row-odd"><td>90</td>
3040 <td>DEV_CPSW_9XUSS_J7AM0_SERDES6_REFCLK</td>
3041 <td>Input clock</td>
3042 </tr>
3043 <tr class="row-even"><td>91</td>
3044 <td>DEV_CPSW_9XUSS_J7AM0_SERDES6_RXCLK</td>
3045 <td>Input clock</td>
3046 </tr>
3047 <tr class="row-odd"><td>92</td>
3048 <td>DEV_CPSW_9XUSS_J7AM0_SERDES6_RXFCLK</td>
3049 <td>Input clock</td>
3050 </tr>
3051 <tr class="row-even"><td>93</td>
3052 <td>DEV_CPSW_9XUSS_J7AM0_SERDES6_TXCLK</td>
3053 <td>Output clock</td>
3054 </tr>
3055 <tr class="row-odd"><td>94</td>
3056 <td>DEV_CPSW_9XUSS_J7AM0_SERDES6_TXFCLK</td>
3057 <td>Input clock</td>
3058 </tr>
3059 <tr class="row-even"><td>95</td>
3060 <td>DEV_CPSW_9XUSS_J7AM0_SERDES6_TXMCLK</td>
3061 <td>Input clock</td>
3062 </tr>
3063 <tr class="row-odd"><td>96</td>
3064 <td>DEV_CPSW_9XUSS_J7AM0_SERDES7_REFCLK</td>
3065 <td>Input clock</td>
3066 </tr>
3067 <tr class="row-even"><td>97</td>
3068 <td>DEV_CPSW_9XUSS_J7AM0_SERDES7_RXCLK</td>
3069 <td>Input clock</td>
3070 </tr>
3071 <tr class="row-odd"><td>98</td>
3072 <td>DEV_CPSW_9XUSS_J7AM0_SERDES7_RXFCLK</td>
3073 <td>Input clock</td>
3074 </tr>
3075 <tr class="row-even"><td>99</td>
3076 <td>DEV_CPSW_9XUSS_J7AM0_SERDES7_TXCLK</td>
3077 <td>Output clock</td>
3078 </tr>
3079 <tr class="row-odd"><td>100</td>
3080 <td>DEV_CPSW_9XUSS_J7AM0_SERDES7_TXFCLK</td>
3081 <td>Input clock</td>
3082 </tr>
3083 <tr class="row-even"><td>101</td>
3084 <td>DEV_CPSW_9XUSS_J7AM0_SERDES7_TXMCLK</td>
3085 <td>Input clock</td>
3086 </tr>
3087 <tr class="row-odd"><td>102</td>
3088 <td>DEV_CPSW_9XUSS_J7AM0_SERDES8_REFCLK</td>
3089 <td>Input clock</td>
3090 </tr>
3091 <tr class="row-even"><td>103</td>
3092 <td>DEV_CPSW_9XUSS_J7AM0_SERDES8_RXCLK</td>
3093 <td>Input clock</td>
3094 </tr>
3095 <tr class="row-odd"><td>104</td>
3096 <td>DEV_CPSW_9XUSS_J7AM0_SERDES8_RXFCLK</td>
3097 <td>Input clock</td>
3098 </tr>
3099 <tr class="row-even"><td>105</td>
3100 <td>DEV_CPSW_9XUSS_J7AM0_SERDES8_TXCLK</td>
3101 <td>Output clock</td>
3102 </tr>
3103 <tr class="row-odd"><td>106</td>
3104 <td>DEV_CPSW_9XUSS_J7AM0_SERDES8_TXFCLK</td>
3105 <td>Input clock</td>
3106 </tr>
3107 <tr class="row-even"><td>107</td>
3108 <td>DEV_CPSW_9XUSS_J7AM0_SERDES8_TXMCLK</td>
3109 <td>Input clock</td>
3110 </tr>
3111 </tbody>
3112 </table>
3113 </div>
3114 <div class="section" id="clocks-for-cpt2-aggr0-device">
3115 <span id="soc-doc-j784s4-public-clks-cpt2-aggr0"></span><h3>Clocks for CPT2_AGGR0 Device<a class="headerlink" href="#clocks-for-cpt2-aggr0-device" title="Permalink to this headline">¶</a></h3>
3116 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CPT2_AGGR0</span></a> (ID = 70)</p>
3117 <p>Following is a mapping of Clocks IDs to function:</p>
3118 <table border="1" class="docutils">
3119 <colgroup>
3120 <col width="24%" />
3121 <col width="50%" />
3122 <col width="26%" />
3123 </colgroup>
3124 <thead valign="bottom">
3125 <tr class="row-odd"><th class="head">Clock ID</th>
3126 <th class="head">Name</th>
3127 <th class="head">Function</th>
3128 </tr>
3129 </thead>
3130 <tbody valign="top">
3131 <tr class="row-even"><td>0</td>
3132 <td>DEV_CPT2_AGGR0_VCLK_CLK</td>
3133 <td>Input clock</td>
3134 </tr>
3135 </tbody>
3136 </table>
3137 </div>
3138 <div class="section" id="clocks-for-cpt2-aggr1-device">
3139 <span id="soc-doc-j784s4-public-clks-cpt2-aggr1"></span><h3>Clocks for CPT2_AGGR1 Device<a class="headerlink" href="#clocks-for-cpt2-aggr1-device" title="Permalink to this headline">¶</a></h3>
3140 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CPT2_AGGR1</span></a> (ID = 65)</p>
3141 <p>Following is a mapping of Clocks IDs to function:</p>
3142 <table border="1" class="docutils">
3143 <colgroup>
3144 <col width="24%" />
3145 <col width="50%" />
3146 <col width="26%" />
3147 </colgroup>
3148 <thead valign="bottom">
3149 <tr class="row-odd"><th class="head">Clock ID</th>
3150 <th class="head">Name</th>
3151 <th class="head">Function</th>
3152 </tr>
3153 </thead>
3154 <tbody valign="top">
3155 <tr class="row-even"><td>0</td>
3156 <td>DEV_CPT2_AGGR1_VCLK_CLK</td>
3157 <td>Input clock</td>
3158 </tr>
3159 </tbody>
3160 </table>
3161 </div>
3162 <div class="section" id="clocks-for-cpt2-aggr2-device">
3163 <span id="soc-doc-j784s4-public-clks-cpt2-aggr2"></span><h3>Clocks for CPT2_AGGR2 Device<a class="headerlink" href="#clocks-for-cpt2-aggr2-device" title="Permalink to this headline">¶</a></h3>
3164 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CPT2_AGGR2</span></a> (ID = 67)</p>
3165 <p>Following is a mapping of Clocks IDs to function:</p>
3166 <table border="1" class="docutils">
3167 <colgroup>
3168 <col width="24%" />
3169 <col width="50%" />
3170 <col width="26%" />
3171 </colgroup>
3172 <thead valign="bottom">
3173 <tr class="row-odd"><th class="head">Clock ID</th>
3174 <th class="head">Name</th>
3175 <th class="head">Function</th>
3176 </tr>
3177 </thead>
3178 <tbody valign="top">
3179 <tr class="row-even"><td>0</td>
3180 <td>DEV_CPT2_AGGR2_VCLK_CLK</td>
3181 <td>Input clock</td>
3182 </tr>
3183 </tbody>
3184 </table>
3185 </div>
3186 <div class="section" id="clocks-for-cpt2-aggr3-device">
3187 <span id="soc-doc-j784s4-public-clks-cpt2-aggr3"></span><h3>Clocks for CPT2_AGGR3 Device<a class="headerlink" href="#clocks-for-cpt2-aggr3-device" title="Permalink to this headline">¶</a></h3>
3188 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CPT2_AGGR3</span></a> (ID = 69)</p>
3189 <p>Following is a mapping of Clocks IDs to function:</p>
3190 <table border="1" class="docutils">
3191 <colgroup>
3192 <col width="24%" />
3193 <col width="50%" />
3194 <col width="26%" />
3195 </colgroup>
3196 <thead valign="bottom">
3197 <tr class="row-odd"><th class="head">Clock ID</th>
3198 <th class="head">Name</th>
3199 <th class="head">Function</th>
3200 </tr>
3201 </thead>
3202 <tbody valign="top">
3203 <tr class="row-even"><td>0</td>
3204 <td>DEV_CPT2_AGGR3_VCLK_CLK</td>
3205 <td>Input clock</td>
3206 </tr>
3207 </tbody>
3208 </table>
3209 </div>
3210 <div class="section" id="clocks-for-cpt2-aggr4-device">
3211 <span id="soc-doc-j784s4-public-clks-cpt2-aggr4"></span><h3>Clocks for CPT2_AGGR4 Device<a class="headerlink" href="#clocks-for-cpt2-aggr4-device" title="Permalink to this headline">¶</a></h3>
3212 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CPT2_AGGR4</span></a> (ID = 68)</p>
3213 <p>Following is a mapping of Clocks IDs to function:</p>
3214 <table border="1" class="docutils">
3215 <colgroup>
3216 <col width="24%" />
3217 <col width="50%" />
3218 <col width="26%" />
3219 </colgroup>
3220 <thead valign="bottom">
3221 <tr class="row-odd"><th class="head">Clock ID</th>
3222 <th class="head">Name</th>
3223 <th class="head">Function</th>
3224 </tr>
3225 </thead>
3226 <tbody valign="top">
3227 <tr class="row-even"><td>0</td>
3228 <td>DEV_CPT2_AGGR4_VCLK_CLK</td>
3229 <td>Input clock</td>
3230 </tr>
3231 </tbody>
3232 </table>
3233 </div>
3234 <div class="section" id="clocks-for-cpt2-aggr5-device">
3235 <span id="soc-doc-j784s4-public-clks-cpt2-aggr5"></span><h3>Clocks for CPT2_AGGR5 Device<a class="headerlink" href="#clocks-for-cpt2-aggr5-device" title="Permalink to this headline">¶</a></h3>
3236 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CPT2_AGGR5</span></a> (ID = 66)</p>
3237 <p>Following is a mapping of Clocks IDs to function:</p>
3238 <table border="1" class="docutils">
3239 <colgroup>
3240 <col width="24%" />
3241 <col width="50%" />
3242 <col width="26%" />
3243 </colgroup>
3244 <thead valign="bottom">
3245 <tr class="row-odd"><th class="head">Clock ID</th>
3246 <th class="head">Name</th>
3247 <th class="head">Function</th>
3248 </tr>
3249 </thead>
3250 <tbody valign="top">
3251 <tr class="row-even"><td>0</td>
3252 <td>DEV_CPT2_AGGR5_VCLK_CLK</td>
3253 <td>Input clock</td>
3254 </tr>
3255 </tbody>
3256 </table>
3257 </div>
3258 <div class="section" id="clocks-for-csi-psilss0-device">
3259 <span id="soc-doc-j784s4-public-clks-csi-psilss0"></span><h3>Clocks for CSI_PSILSS0 Device<a class="headerlink" href="#clocks-for-csi-psilss0-device" title="Permalink to this headline">¶</a></h3>
3260 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CSI_PSILSS0</span></a> (ID = 189)</p>
3261 <p>Following is a mapping of Clocks IDs to function:</p>
3262 <table border="1" class="docutils">
3263 <colgroup>
3264 <col width="24%" />
3265 <col width="51%" />
3266 <col width="25%" />
3267 </colgroup>
3268 <thead valign="bottom">
3269 <tr class="row-odd"><th class="head">Clock ID</th>
3270 <th class="head">Name</th>
3271 <th class="head">Function</th>
3272 </tr>
3273 </thead>
3274 <tbody valign="top">
3275 <tr class="row-even"><td>0</td>
3276 <td>DEV_CSI_PSILSS0_MAIN_CLK</td>
3277 <td>Input clock</td>
3278 </tr>
3279 </tbody>
3280 </table>
3281 </div>
3282 <div class="section" id="clocks-for-csi-rx-if0-device">
3283 <span id="soc-doc-j784s4-public-clks-csi-rx-if0"></span><h3>Clocks for CSI_RX_IF0 Device<a class="headerlink" href="#clocks-for-csi-rx-if0-device" title="Permalink to this headline">¶</a></h3>
3284 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CSI_RX_IF0</span></a> (ID = 72)</p>
3285 <p>Following is a mapping of Clocks IDs to function:</p>
3286 <table border="1" class="docutils">
3287 <colgroup>
3288 <col width="20%" />
3289 <col width="58%" />
3290 <col width="22%" />
3291 </colgroup>
3292 <thead valign="bottom">
3293 <tr class="row-odd"><th class="head">Clock ID</th>
3294 <th class="head">Name</th>
3295 <th class="head">Function</th>
3296 </tr>
3297 </thead>
3298 <tbody valign="top">
3299 <tr class="row-even"><td>0</td>
3300 <td>DEV_CSI_RX_IF0_MAIN_CLK_CLK</td>
3301 <td>Input clock</td>
3302 </tr>
3303 <tr class="row-odd"><td>1</td>
3304 <td>DEV_CSI_RX_IF0_PPI_D_RX_ULPS_ESC</td>
3305 <td>Input clock</td>
3306 </tr>
3307 <tr class="row-even"><td>2</td>
3308 <td>DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK</td>
3309 <td>Input clock</td>
3310 </tr>
3311 <tr class="row-odd"><td>3</td>
3312 <td>DEV_CSI_RX_IF0_VBUS_CLK_CLK</td>
3313 <td>Input clock</td>
3314 </tr>
3315 <tr class="row-even"><td>4</td>
3316 <td>DEV_CSI_RX_IF0_VP_CLK_CLK</td>
3317 <td>Input clock</td>
3318 </tr>
3319 </tbody>
3320 </table>
3321 </div>
3322 <div class="section" id="clocks-for-csi-rx-if1-device">
3323 <span id="soc-doc-j784s4-public-clks-csi-rx-if1"></span><h3>Clocks for CSI_RX_IF1 Device<a class="headerlink" href="#clocks-for-csi-rx-if1-device" title="Permalink to this headline">¶</a></h3>
3324 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CSI_RX_IF1</span></a> (ID = 73)</p>
3325 <p>Following is a mapping of Clocks IDs to function:</p>
3326 <table border="1" class="docutils">
3327 <colgroup>
3328 <col width="20%" />
3329 <col width="58%" />
3330 <col width="22%" />
3331 </colgroup>
3332 <thead valign="bottom">
3333 <tr class="row-odd"><th class="head">Clock ID</th>
3334 <th class="head">Name</th>
3335 <th class="head">Function</th>
3336 </tr>
3337 </thead>
3338 <tbody valign="top">
3339 <tr class="row-even"><td>0</td>
3340 <td>DEV_CSI_RX_IF1_MAIN_CLK_CLK</td>
3341 <td>Input clock</td>
3342 </tr>
3343 <tr class="row-odd"><td>1</td>
3344 <td>DEV_CSI_RX_IF1_PPI_D_RX_ULPS_ESC</td>
3345 <td>Input clock</td>
3346 </tr>
3347 <tr class="row-even"><td>2</td>
3348 <td>DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK</td>
3349 <td>Input clock</td>
3350 </tr>
3351 <tr class="row-odd"><td>3</td>
3352 <td>DEV_CSI_RX_IF1_VBUS_CLK_CLK</td>
3353 <td>Input clock</td>
3354 </tr>
3355 <tr class="row-even"><td>4</td>
3356 <td>DEV_CSI_RX_IF1_VP_CLK_CLK</td>
3357 <td>Input clock</td>
3358 </tr>
3359 </tbody>
3360 </table>
3361 </div>
3362 <div class="section" id="clocks-for-csi-rx-if2-device">
3363 <span id="soc-doc-j784s4-public-clks-csi-rx-if2"></span><h3>Clocks for CSI_RX_IF2 Device<a class="headerlink" href="#clocks-for-csi-rx-if2-device" title="Permalink to this headline">¶</a></h3>
3364 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CSI_RX_IF2</span></a> (ID = 74)</p>
3365 <p>Following is a mapping of Clocks IDs to function:</p>
3366 <table border="1" class="docutils">
3367 <colgroup>
3368 <col width="20%" />
3369 <col width="58%" />
3370 <col width="22%" />
3371 </colgroup>
3372 <thead valign="bottom">
3373 <tr class="row-odd"><th class="head">Clock ID</th>
3374 <th class="head">Name</th>
3375 <th class="head">Function</th>
3376 </tr>
3377 </thead>
3378 <tbody valign="top">
3379 <tr class="row-even"><td>0</td>
3380 <td>DEV_CSI_RX_IF2_MAIN_CLK_CLK</td>
3381 <td>Input clock</td>
3382 </tr>
3383 <tr class="row-odd"><td>1</td>
3384 <td>DEV_CSI_RX_IF2_PPI_D_RX_ULPS_ESC</td>
3385 <td>Input clock</td>
3386 </tr>
3387 <tr class="row-even"><td>2</td>
3388 <td>DEV_CSI_RX_IF2_PPI_RX_BYTE_CLK</td>
3389 <td>Input clock</td>
3390 </tr>
3391 <tr class="row-odd"><td>3</td>
3392 <td>DEV_CSI_RX_IF2_VBUS_CLK_CLK</td>
3393 <td>Input clock</td>
3394 </tr>
3395 <tr class="row-even"><td>4</td>
3396 <td>DEV_CSI_RX_IF2_VP_CLK_CLK</td>
3397 <td>Input clock</td>
3398 </tr>
3399 </tbody>
3400 </table>
3401 </div>
3402 <div class="section" id="clocks-for-csi-tx-if-v2-0-device">
3403 <span id="soc-doc-j784s4-public-clks-csi-tx-if-v2-0"></span><h3>Clocks for CSI_TX_IF_V2_0 Device<a class="headerlink" href="#clocks-for-csi-tx-if-v2-0-device" title="Permalink to this headline">¶</a></h3>
3404 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CSI_TX_IF_V2_0</span></a> (ID = 75)</p>
3405 <p>Following is a mapping of Clocks IDs to function:</p>
3406 <table border="1" class="docutils">
3407 <colgroup>
3408 <col width="17%" />
3409 <col width="64%" />
3410 <col width="19%" />
3411 </colgroup>
3412 <thead valign="bottom">
3413 <tr class="row-odd"><th class="head">Clock ID</th>
3414 <th class="head">Name</th>
3415 <th class="head">Function</th>
3416 </tr>
3417 </thead>
3418 <tbody valign="top">
3419 <tr class="row-even"><td>2</td>
3420 <td>DEV_CSI_TX_IF_V2_0_DPHY_TXBYTECLKHS_CL_CLK</td>
3421 <td>Input clock</td>
3422 </tr>
3423 <tr class="row-odd"><td>3</td>
3424 <td>DEV_CSI_TX_IF_V2_0_ESC_CLK_CLK</td>
3425 <td>Input clock</td>
3426 </tr>
3427 <tr class="row-even"><td>4</td>
3428 <td>DEV_CSI_TX_IF_V2_0_MAIN_CLK_CLK</td>
3429 <td>Input clock</td>
3430 </tr>
3431 <tr class="row-odd"><td>5</td>
3432 <td>DEV_CSI_TX_IF_V2_0_VBUS_CLK_CLK</td>
3433 <td>Input clock</td>
3434 </tr>
3435 </tbody>
3436 </table>
3437 </div>
3438 <div class="section" id="clocks-for-csi-tx-if-v2-1-device">
3439 <span id="soc-doc-j784s4-public-clks-csi-tx-if-v2-1"></span><h3>Clocks for CSI_TX_IF_V2_1 Device<a class="headerlink" href="#clocks-for-csi-tx-if-v2-1-device" title="Permalink to this headline">¶</a></h3>
3440 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_CSI_TX_IF_V2_1</span></a> (ID = 76)</p>
3441 <p>Following is a mapping of Clocks IDs to function:</p>
3442 <table border="1" class="docutils">
3443 <colgroup>
3444 <col width="17%" />
3445 <col width="64%" />
3446 <col width="19%" />
3447 </colgroup>
3448 <thead valign="bottom">
3449 <tr class="row-odd"><th class="head">Clock ID</th>
3450 <th class="head">Name</th>
3451 <th class="head">Function</th>
3452 </tr>
3453 </thead>
3454 <tbody valign="top">
3455 <tr class="row-even"><td>2</td>
3456 <td>DEV_CSI_TX_IF_V2_1_DPHY_TXBYTECLKHS_CL_CLK</td>
3457 <td>Input clock</td>
3458 </tr>
3459 <tr class="row-odd"><td>3</td>
3460 <td>DEV_CSI_TX_IF_V2_1_ESC_CLK_CLK</td>
3461 <td>Input clock</td>
3462 </tr>
3463 <tr class="row-even"><td>4</td>
3464 <td>DEV_CSI_TX_IF_V2_1_MAIN_CLK_CLK</td>
3465 <td>Input clock</td>
3466 </tr>
3467 <tr class="row-odd"><td>5</td>
3468 <td>DEV_CSI_TX_IF_V2_1_VBUS_CLK_CLK</td>
3469 <td>Input clock</td>
3470 </tr>
3471 </tbody>
3472 </table>
3473 </div>
3474 <div class="section" id="clocks-for-dcc0-device">
3475 <span id="soc-doc-j784s4-public-clks-dcc0"></span><h3>Clocks for DCC0 Device<a class="headerlink" href="#clocks-for-dcc0-device" title="Permalink to this headline">¶</a></h3>
3476 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DCC0</span></a> (ID = 78)</p>
3477 <p>Following is a mapping of Clocks IDs to function:</p>
3478 <table border="1" class="docutils">
3479 <colgroup>
3480 <col width="24%" />
3481 <col width="51%" />
3482 <col width="25%" />
3483 </colgroup>
3484 <thead valign="bottom">
3485 <tr class="row-odd"><th class="head">Clock ID</th>
3486 <th class="head">Name</th>
3487 <th class="head">Function</th>
3488 </tr>
3489 </thead>
3490 <tbody valign="top">
3491 <tr class="row-even"><td>0</td>
3492 <td>DEV_DCC0_DCC_CLKSRC0_CLK</td>
3493 <td>Input clock</td>
3494 </tr>
3495 <tr class="row-odd"><td>1</td>
3496 <td>DEV_DCC0_DCC_CLKSRC1_CLK</td>
3497 <td>Input clock</td>
3498 </tr>
3499 <tr class="row-even"><td>2</td>
3500 <td>DEV_DCC0_DCC_CLKSRC2_CLK</td>
3501 <td>Input clock</td>
3502 </tr>
3503 <tr class="row-odd"><td>3</td>
3504 <td>DEV_DCC0_DCC_CLKSRC3_CLK</td>
3505 <td>Input clock</td>
3506 </tr>
3507 <tr class="row-even"><td>4</td>
3508 <td>DEV_DCC0_DCC_CLKSRC4_CLK</td>
3509 <td>Input clock</td>
3510 </tr>
3511 <tr class="row-odd"><td>5</td>
3512 <td>DEV_DCC0_DCC_CLKSRC5_CLK</td>
3513 <td>Input clock</td>
3514 </tr>
3515 <tr class="row-even"><td>6</td>
3516 <td>DEV_DCC0_DCC_CLKSRC6_CLK</td>
3517 <td>Input clock</td>
3518 </tr>
3519 <tr class="row-odd"><td>7</td>
3520 <td>DEV_DCC0_DCC_CLKSRC7_CLK</td>
3521 <td>Input clock</td>
3522 </tr>
3523 <tr class="row-even"><td>8</td>
3524 <td>DEV_DCC0_DCC_INPUT00_CLK</td>
3525 <td>Input clock</td>
3526 </tr>
3527 <tr class="row-odd"><td>9</td>
3528 <td>DEV_DCC0_DCC_INPUT01_CLK</td>
3529 <td>Input clock</td>
3530 </tr>
3531 <tr class="row-even"><td>10</td>
3532 <td>DEV_DCC0_DCC_INPUT02_CLK</td>
3533 <td>Input clock</td>
3534 </tr>
3535 <tr class="row-odd"><td>11</td>
3536 <td>DEV_DCC0_DCC_INPUT10_CLK</td>
3537 <td>Input clock</td>
3538 </tr>
3539 <tr class="row-even"><td>12</td>
3540 <td>DEV_DCC0_VBUS_CLK</td>
3541 <td>Input clock</td>
3542 </tr>
3543 </tbody>
3544 </table>
3545 </div>
3546 <div class="section" id="clocks-for-dcc1-device">
3547 <span id="soc-doc-j784s4-public-clks-dcc1"></span><h3>Clocks for DCC1 Device<a class="headerlink" href="#clocks-for-dcc1-device" title="Permalink to this headline">¶</a></h3>
3548 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DCC1</span></a> (ID = 79)</p>
3549 <p>Following is a mapping of Clocks IDs to function:</p>
3550 <table border="1" class="docutils">
3551 <colgroup>
3552 <col width="24%" />
3553 <col width="51%" />
3554 <col width="25%" />
3555 </colgroup>
3556 <thead valign="bottom">
3557 <tr class="row-odd"><th class="head">Clock ID</th>
3558 <th class="head">Name</th>
3559 <th class="head">Function</th>
3560 </tr>
3561 </thead>
3562 <tbody valign="top">
3563 <tr class="row-even"><td>0</td>
3564 <td>DEV_DCC1_DCC_CLKSRC0_CLK</td>
3565 <td>Input clock</td>
3566 </tr>
3567 <tr class="row-odd"><td>1</td>
3568 <td>DEV_DCC1_DCC_CLKSRC1_CLK</td>
3569 <td>Input clock</td>
3570 </tr>
3571 <tr class="row-even"><td>2</td>
3572 <td>DEV_DCC1_DCC_CLKSRC2_CLK</td>
3573 <td>Input clock</td>
3574 </tr>
3575 <tr class="row-odd"><td>3</td>
3576 <td>DEV_DCC1_DCC_CLKSRC3_CLK</td>
3577 <td>Input clock</td>
3578 </tr>
3579 <tr class="row-even"><td>4</td>
3580 <td>DEV_DCC1_DCC_CLKSRC4_CLK</td>
3581 <td>Input clock</td>
3582 </tr>
3583 <tr class="row-odd"><td>5</td>
3584 <td>DEV_DCC1_DCC_CLKSRC5_CLK</td>
3585 <td>Input clock</td>
3586 </tr>
3587 <tr class="row-even"><td>6</td>
3588 <td>DEV_DCC1_DCC_CLKSRC6_CLK</td>
3589 <td>Input clock</td>
3590 </tr>
3591 <tr class="row-odd"><td>7</td>
3592 <td>DEV_DCC1_DCC_CLKSRC7_CLK</td>
3593 <td>Input clock</td>
3594 </tr>
3595 <tr class="row-even"><td>8</td>
3596 <td>DEV_DCC1_DCC_INPUT00_CLK</td>
3597 <td>Input clock</td>
3598 </tr>
3599 <tr class="row-odd"><td>9</td>
3600 <td>DEV_DCC1_DCC_INPUT01_CLK</td>
3601 <td>Input clock</td>
3602 </tr>
3603 <tr class="row-even"><td>10</td>
3604 <td>DEV_DCC1_DCC_INPUT02_CLK</td>
3605 <td>Input clock</td>
3606 </tr>
3607 <tr class="row-odd"><td>11</td>
3608 <td>DEV_DCC1_DCC_INPUT10_CLK</td>
3609 <td>Input clock</td>
3610 </tr>
3611 <tr class="row-even"><td>12</td>
3612 <td>DEV_DCC1_VBUS_CLK</td>
3613 <td>Input clock</td>
3614 </tr>
3615 </tbody>
3616 </table>
3617 </div>
3618 <div class="section" id="clocks-for-dcc2-device">
3619 <span id="soc-doc-j784s4-public-clks-dcc2"></span><h3>Clocks for DCC2 Device<a class="headerlink" href="#clocks-for-dcc2-device" title="Permalink to this headline">¶</a></h3>
3620 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DCC2</span></a> (ID = 80)</p>
3621 <p>Following is a mapping of Clocks IDs to function:</p>
3622 <table border="1" class="docutils">
3623 <colgroup>
3624 <col width="24%" />
3625 <col width="51%" />
3626 <col width="25%" />
3627 </colgroup>
3628 <thead valign="bottom">
3629 <tr class="row-odd"><th class="head">Clock ID</th>
3630 <th class="head">Name</th>
3631 <th class="head">Function</th>
3632 </tr>
3633 </thead>
3634 <tbody valign="top">
3635 <tr class="row-even"><td>0</td>
3636 <td>DEV_DCC2_DCC_CLKSRC0_CLK</td>
3637 <td>Input clock</td>
3638 </tr>
3639 <tr class="row-odd"><td>1</td>
3640 <td>DEV_DCC2_DCC_CLKSRC1_CLK</td>
3641 <td>Input clock</td>
3642 </tr>
3643 <tr class="row-even"><td>3</td>
3644 <td>DEV_DCC2_DCC_CLKSRC3_CLK</td>
3645 <td>Input clock</td>
3646 </tr>
3647 <tr class="row-odd"><td>4</td>
3648 <td>DEV_DCC2_DCC_CLKSRC4_CLK</td>
3649 <td>Input clock</td>
3650 </tr>
3651 <tr class="row-even"><td>5</td>
3652 <td>DEV_DCC2_DCC_CLKSRC5_CLK</td>
3653 <td>Input clock</td>
3654 </tr>
3655 <tr class="row-odd"><td>6</td>
3656 <td>DEV_DCC2_DCC_CLKSRC6_CLK</td>
3657 <td>Input clock</td>
3658 </tr>
3659 <tr class="row-even"><td>7</td>
3660 <td>DEV_DCC2_DCC_CLKSRC7_CLK</td>
3661 <td>Input clock</td>
3662 </tr>
3663 <tr class="row-odd"><td>8</td>
3664 <td>DEV_DCC2_DCC_INPUT00_CLK</td>
3665 <td>Input clock</td>
3666 </tr>
3667 <tr class="row-even"><td>9</td>
3668 <td>DEV_DCC2_DCC_INPUT01_CLK</td>
3669 <td>Input clock</td>
3670 </tr>
3671 <tr class="row-odd"><td>10</td>
3672 <td>DEV_DCC2_DCC_INPUT02_CLK</td>
3673 <td>Input clock</td>
3674 </tr>
3675 <tr class="row-even"><td>11</td>
3676 <td>DEV_DCC2_DCC_INPUT10_CLK</td>
3677 <td>Input clock</td>
3678 </tr>
3679 <tr class="row-odd"><td>12</td>
3680 <td>DEV_DCC2_VBUS_CLK</td>
3681 <td>Input clock</td>
3682 </tr>
3683 </tbody>
3684 </table>
3685 </div>
3686 <div class="section" id="clocks-for-dcc3-device">
3687 <span id="soc-doc-j784s4-public-clks-dcc3"></span><h3>Clocks for DCC3 Device<a class="headerlink" href="#clocks-for-dcc3-device" title="Permalink to this headline">¶</a></h3>
3688 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DCC3</span></a> (ID = 81)</p>
3689 <p>Following is a mapping of Clocks IDs to function:</p>
3690 <table border="1" class="docutils">
3691 <colgroup>
3692 <col width="24%" />
3693 <col width="51%" />
3694 <col width="25%" />
3695 </colgroup>
3696 <thead valign="bottom">
3697 <tr class="row-odd"><th class="head">Clock ID</th>
3698 <th class="head">Name</th>
3699 <th class="head">Function</th>
3700 </tr>
3701 </thead>
3702 <tbody valign="top">
3703 <tr class="row-even"><td>0</td>
3704 <td>DEV_DCC3_DCC_CLKSRC0_CLK</td>
3705 <td>Input clock</td>
3706 </tr>
3707 <tr class="row-odd"><td>1</td>
3708 <td>DEV_DCC3_DCC_CLKSRC1_CLK</td>
3709 <td>Input clock</td>
3710 </tr>
3711 <tr class="row-even"><td>2</td>
3712 <td>DEV_DCC3_DCC_CLKSRC2_CLK</td>
3713 <td>Input clock</td>
3714 </tr>
3715 <tr class="row-odd"><td>3</td>
3716 <td>DEV_DCC3_DCC_CLKSRC3_CLK</td>
3717 <td>Input clock</td>
3718 </tr>
3719 <tr class="row-even"><td>5</td>
3720 <td>DEV_DCC3_DCC_CLKSRC5_CLK</td>
3721 <td>Input clock</td>
3722 </tr>
3723 <tr class="row-odd"><td>6</td>
3724 <td>DEV_DCC3_DCC_CLKSRC6_CLK</td>
3725 <td>Input clock</td>
3726 </tr>
3727 <tr class="row-even"><td>7</td>
3728 <td>DEV_DCC3_DCC_CLKSRC7_CLK</td>
3729 <td>Input clock</td>
3730 </tr>
3731 <tr class="row-odd"><td>8</td>
3732 <td>DEV_DCC3_DCC_INPUT00_CLK</td>
3733 <td>Input clock</td>
3734 </tr>
3735 <tr class="row-even"><td>9</td>
3736 <td>DEV_DCC3_DCC_INPUT01_CLK</td>
3737 <td>Input clock</td>
3738 </tr>
3739 <tr class="row-odd"><td>10</td>
3740 <td>DEV_DCC3_DCC_INPUT02_CLK</td>
3741 <td>Input clock</td>
3742 </tr>
3743 <tr class="row-even"><td>11</td>
3744 <td>DEV_DCC3_DCC_INPUT10_CLK</td>
3745 <td>Input clock</td>
3746 </tr>
3747 <tr class="row-odd"><td>12</td>
3748 <td>DEV_DCC3_VBUS_CLK</td>
3749 <td>Input clock</td>
3750 </tr>
3751 </tbody>
3752 </table>
3753 </div>
3754 <div class="section" id="clocks-for-dcc4-device">
3755 <span id="soc-doc-j784s4-public-clks-dcc4"></span><h3>Clocks for DCC4 Device<a class="headerlink" href="#clocks-for-dcc4-device" title="Permalink to this headline">¶</a></h3>
3756 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DCC4</span></a> (ID = 82)</p>
3757 <p>Following is a mapping of Clocks IDs to function:</p>
3758 <table border="1" class="docutils">
3759 <colgroup>
3760 <col width="24%" />
3761 <col width="51%" />
3762 <col width="25%" />
3763 </colgroup>
3764 <thead valign="bottom">
3765 <tr class="row-odd"><th class="head">Clock ID</th>
3766 <th class="head">Name</th>
3767 <th class="head">Function</th>
3768 </tr>
3769 </thead>
3770 <tbody valign="top">
3771 <tr class="row-even"><td>0</td>
3772 <td>DEV_DCC4_DCC_CLKSRC0_CLK</td>
3773 <td>Input clock</td>
3774 </tr>
3775 <tr class="row-odd"><td>1</td>
3776 <td>DEV_DCC4_DCC_CLKSRC1_CLK</td>
3777 <td>Input clock</td>
3778 </tr>
3779 <tr class="row-even"><td>2</td>
3780 <td>DEV_DCC4_DCC_CLKSRC2_CLK</td>
3781 <td>Input clock</td>
3782 </tr>
3783 <tr class="row-odd"><td>3</td>
3784 <td>DEV_DCC4_DCC_CLKSRC3_CLK</td>
3785 <td>Input clock</td>
3786 </tr>
3787 <tr class="row-even"><td>4</td>
3788 <td>DEV_DCC4_DCC_CLKSRC4_CLK</td>
3789 <td>Input clock</td>
3790 </tr>
3791 <tr class="row-odd"><td>5</td>
3792 <td>DEV_DCC4_DCC_CLKSRC5_CLK</td>
3793 <td>Input clock</td>
3794 </tr>
3795 <tr class="row-even"><td>6</td>
3796 <td>DEV_DCC4_DCC_CLKSRC6_CLK</td>
3797 <td>Input clock</td>
3798 </tr>
3799 <tr class="row-odd"><td>7</td>
3800 <td>DEV_DCC4_DCC_CLKSRC7_CLK</td>
3801 <td>Input clock</td>
3802 </tr>
3803 <tr class="row-even"><td>8</td>
3804 <td>DEV_DCC4_DCC_INPUT00_CLK</td>
3805 <td>Input clock</td>
3806 </tr>
3807 <tr class="row-odd"><td>9</td>
3808 <td>DEV_DCC4_DCC_INPUT01_CLK</td>
3809 <td>Input clock</td>
3810 </tr>
3811 <tr class="row-even"><td>10</td>
3812 <td>DEV_DCC4_DCC_INPUT02_CLK</td>
3813 <td>Input clock</td>
3814 </tr>
3815 <tr class="row-odd"><td>11</td>
3816 <td>DEV_DCC4_DCC_INPUT10_CLK</td>
3817 <td>Input clock</td>
3818 </tr>
3819 <tr class="row-even"><td>12</td>
3820 <td>DEV_DCC4_VBUS_CLK</td>
3821 <td>Input clock</td>
3822 </tr>
3823 </tbody>
3824 </table>
3825 </div>
3826 <div class="section" id="clocks-for-dcc5-device">
3827 <span id="soc-doc-j784s4-public-clks-dcc5"></span><h3>Clocks for DCC5 Device<a class="headerlink" href="#clocks-for-dcc5-device" title="Permalink to this headline">¶</a></h3>
3828 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DCC5</span></a> (ID = 83)</p>
3829 <p>Following is a mapping of Clocks IDs to function:</p>
3830 <table border="1" class="docutils">
3831 <colgroup>
3832 <col width="24%" />
3833 <col width="51%" />
3834 <col width="25%" />
3835 </colgroup>
3836 <thead valign="bottom">
3837 <tr class="row-odd"><th class="head">Clock ID</th>
3838 <th class="head">Name</th>
3839 <th class="head">Function</th>
3840 </tr>
3841 </thead>
3842 <tbody valign="top">
3843 <tr class="row-even"><td>1</td>
3844 <td>DEV_DCC5_DCC_CLKSRC1_CLK</td>
3845 <td>Input clock</td>
3846 </tr>
3847 <tr class="row-odd"><td>2</td>
3848 <td>DEV_DCC5_DCC_CLKSRC2_CLK</td>
3849 <td>Input clock</td>
3850 </tr>
3851 <tr class="row-even"><td>3</td>
3852 <td>DEV_DCC5_DCC_CLKSRC3_CLK</td>
3853 <td>Input clock</td>
3854 </tr>
3855 <tr class="row-odd"><td>4</td>
3856 <td>DEV_DCC5_DCC_CLKSRC4_CLK</td>
3857 <td>Input clock</td>
3858 </tr>
3859 <tr class="row-even"><td>6</td>
3860 <td>DEV_DCC5_DCC_CLKSRC6_CLK</td>
3861 <td>Input clock</td>
3862 </tr>
3863 <tr class="row-odd"><td>7</td>
3864 <td>DEV_DCC5_DCC_CLKSRC7_CLK</td>
3865 <td>Input clock</td>
3866 </tr>
3867 <tr class="row-even"><td>8</td>
3868 <td>DEV_DCC5_DCC_INPUT00_CLK</td>
3869 <td>Input clock</td>
3870 </tr>
3871 <tr class="row-odd"><td>9</td>
3872 <td>DEV_DCC5_DCC_INPUT01_CLK</td>
3873 <td>Input clock</td>
3874 </tr>
3875 <tr class="row-even"><td>10</td>
3876 <td>DEV_DCC5_DCC_INPUT02_CLK</td>
3877 <td>Input clock</td>
3878 </tr>
3879 <tr class="row-odd"><td>11</td>
3880 <td>DEV_DCC5_DCC_INPUT10_CLK</td>
3881 <td>Input clock</td>
3882 </tr>
3883 <tr class="row-even"><td>12</td>
3884 <td>DEV_DCC5_VBUS_CLK</td>
3885 <td>Input clock</td>
3886 </tr>
3887 </tbody>
3888 </table>
3889 </div>
3890 <div class="section" id="clocks-for-dcc6-device">
3891 <span id="soc-doc-j784s4-public-clks-dcc6"></span><h3>Clocks for DCC6 Device<a class="headerlink" href="#clocks-for-dcc6-device" title="Permalink to this headline">¶</a></h3>
3892 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DCC6</span></a> (ID = 84)</p>
3893 <p>Following is a mapping of Clocks IDs to function:</p>
3894 <table border="1" class="docutils">
3895 <colgroup>
3896 <col width="24%" />
3897 <col width="51%" />
3898 <col width="25%" />
3899 </colgroup>
3900 <thead valign="bottom">
3901 <tr class="row-odd"><th class="head">Clock ID</th>
3902 <th class="head">Name</th>
3903 <th class="head">Function</th>
3904 </tr>
3905 </thead>
3906 <tbody valign="top">
3907 <tr class="row-even"><td>0</td>
3908 <td>DEV_DCC6_DCC_CLKSRC0_CLK</td>
3909 <td>Input clock</td>
3910 </tr>
3911 <tr class="row-odd"><td>1</td>
3912 <td>DEV_DCC6_DCC_CLKSRC1_CLK</td>
3913 <td>Input clock</td>
3914 </tr>
3915 <tr class="row-even"><td>2</td>
3916 <td>DEV_DCC6_DCC_CLKSRC2_CLK</td>
3917 <td>Input clock</td>
3918 </tr>
3919 <tr class="row-odd"><td>3</td>
3920 <td>DEV_DCC6_DCC_CLKSRC3_CLK</td>
3921 <td>Input clock</td>
3922 </tr>
3923 <tr class="row-even"><td>4</td>
3924 <td>DEV_DCC6_DCC_CLKSRC4_CLK</td>
3925 <td>Input clock</td>
3926 </tr>
3927 <tr class="row-odd"><td>5</td>
3928 <td>DEV_DCC6_DCC_CLKSRC5_CLK</td>
3929 <td>Input clock</td>
3930 </tr>
3931 <tr class="row-even"><td>6</td>
3932 <td>DEV_DCC6_DCC_CLKSRC6_CLK</td>
3933 <td>Input clock</td>
3934 </tr>
3935 <tr class="row-odd"><td>7</td>
3936 <td>DEV_DCC6_DCC_CLKSRC7_CLK</td>
3937 <td>Input clock</td>
3938 </tr>
3939 <tr class="row-even"><td>8</td>
3940 <td>DEV_DCC6_DCC_INPUT00_CLK</td>
3941 <td>Input clock</td>
3942 </tr>
3943 <tr class="row-odd"><td>9</td>
3944 <td>DEV_DCC6_DCC_INPUT01_CLK</td>
3945 <td>Input clock</td>
3946 </tr>
3947 <tr class="row-even"><td>10</td>
3948 <td>DEV_DCC6_DCC_INPUT02_CLK</td>
3949 <td>Input clock</td>
3950 </tr>
3951 <tr class="row-odd"><td>11</td>
3952 <td>DEV_DCC6_DCC_INPUT10_CLK</td>
3953 <td>Input clock</td>
3954 </tr>
3955 <tr class="row-even"><td>12</td>
3956 <td>DEV_DCC6_VBUS_CLK</td>
3957 <td>Input clock</td>
3958 </tr>
3959 </tbody>
3960 </table>
3961 </div>
3962 <div class="section" id="clocks-for-dcc7-device">
3963 <span id="soc-doc-j784s4-public-clks-dcc7"></span><h3>Clocks for DCC7 Device<a class="headerlink" href="#clocks-for-dcc7-device" title="Permalink to this headline">¶</a></h3>
3964 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DCC7</span></a> (ID = 85)</p>
3965 <p>Following is a mapping of Clocks IDs to function:</p>
3966 <table border="1" class="docutils">
3967 <colgroup>
3968 <col width="24%" />
3969 <col width="51%" />
3970 <col width="25%" />
3971 </colgroup>
3972 <thead valign="bottom">
3973 <tr class="row-odd"><th class="head">Clock ID</th>
3974 <th class="head">Name</th>
3975 <th class="head">Function</th>
3976 </tr>
3977 </thead>
3978 <tbody valign="top">
3979 <tr class="row-even"><td>0</td>
3980 <td>DEV_DCC7_DCC_CLKSRC0_CLK</td>
3981 <td>Input clock</td>
3982 </tr>
3983 <tr class="row-odd"><td>1</td>
3984 <td>DEV_DCC7_DCC_CLKSRC1_CLK</td>
3985 <td>Input clock</td>
3986 </tr>
3987 <tr class="row-even"><td>2</td>
3988 <td>DEV_DCC7_DCC_CLKSRC2_CLK</td>
3989 <td>Input clock</td>
3990 </tr>
3991 <tr class="row-odd"><td>5</td>
3992 <td>DEV_DCC7_DCC_CLKSRC5_CLK</td>
3993 <td>Input clock</td>
3994 </tr>
3995 <tr class="row-even"><td>6</td>
3996 <td>DEV_DCC7_DCC_CLKSRC6_CLK</td>
3997 <td>Input clock</td>
3998 </tr>
3999 <tr class="row-odd"><td>7</td>
4000 <td>DEV_DCC7_DCC_CLKSRC7_CLK</td>
4001 <td>Input clock</td>
4002 </tr>
4003 <tr class="row-even"><td>8</td>
4004 <td>DEV_DCC7_DCC_INPUT00_CLK</td>
4005 <td>Input clock</td>
4006 </tr>
4007 <tr class="row-odd"><td>9</td>
4008 <td>DEV_DCC7_DCC_INPUT01_CLK</td>
4009 <td>Input clock</td>
4010 </tr>
4011 <tr class="row-even"><td>10</td>
4012 <td>DEV_DCC7_DCC_INPUT02_CLK</td>
4013 <td>Input clock</td>
4014 </tr>
4015 <tr class="row-odd"><td>11</td>
4016 <td>DEV_DCC7_DCC_INPUT10_CLK</td>
4017 <td>Input clock</td>
4018 </tr>
4019 <tr class="row-even"><td>12</td>
4020 <td>DEV_DCC7_VBUS_CLK</td>
4021 <td>Input clock</td>
4022 </tr>
4023 </tbody>
4024 </table>
4025 </div>
4026 <div class="section" id="clocks-for-dcc8-device">
4027 <span id="soc-doc-j784s4-public-clks-dcc8"></span><h3>Clocks for DCC8 Device<a class="headerlink" href="#clocks-for-dcc8-device" title="Permalink to this headline">¶</a></h3>
4028 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DCC8</span></a> (ID = 86)</p>
4029 <p>Following is a mapping of Clocks IDs to function:</p>
4030 <table border="1" class="docutils">
4031 <colgroup>
4032 <col width="24%" />
4033 <col width="51%" />
4034 <col width="25%" />
4035 </colgroup>
4036 <thead valign="bottom">
4037 <tr class="row-odd"><th class="head">Clock ID</th>
4038 <th class="head">Name</th>
4039 <th class="head">Function</th>
4040 </tr>
4041 </thead>
4042 <tbody valign="top">
4043 <tr class="row-even"><td>0</td>
4044 <td>DEV_DCC8_DCC_CLKSRC0_CLK</td>
4045 <td>Input clock</td>
4046 </tr>
4047 <tr class="row-odd"><td>1</td>
4048 <td>DEV_DCC8_DCC_CLKSRC1_CLK</td>
4049 <td>Input clock</td>
4050 </tr>
4051 <tr class="row-even"><td>2</td>
4052 <td>DEV_DCC8_DCC_CLKSRC2_CLK</td>
4053 <td>Input clock</td>
4054 </tr>
4055 <tr class="row-odd"><td>3</td>
4056 <td>DEV_DCC8_DCC_CLKSRC3_CLK</td>
4057 <td>Input clock</td>
4058 </tr>
4059 <tr class="row-even"><td>4</td>
4060 <td>DEV_DCC8_DCC_CLKSRC4_CLK</td>
4061 <td>Input clock</td>
4062 </tr>
4063 <tr class="row-odd"><td>5</td>
4064 <td>DEV_DCC8_DCC_CLKSRC5_CLK</td>
4065 <td>Input clock</td>
4066 </tr>
4067 <tr class="row-even"><td>6</td>
4068 <td>DEV_DCC8_DCC_CLKSRC6_CLK</td>
4069 <td>Input clock</td>
4070 </tr>
4071 <tr class="row-odd"><td>7</td>
4072 <td>DEV_DCC8_DCC_CLKSRC7_CLK</td>
4073 <td>Input clock</td>
4074 </tr>
4075 <tr class="row-even"><td>8</td>
4076 <td>DEV_DCC8_DCC_INPUT00_CLK</td>
4077 <td>Input clock</td>
4078 </tr>
4079 <tr class="row-odd"><td>9</td>
4080 <td>DEV_DCC8_DCC_INPUT01_CLK</td>
4081 <td>Input clock</td>
4082 </tr>
4083 <tr class="row-even"><td>10</td>
4084 <td>DEV_DCC8_DCC_INPUT02_CLK</td>
4085 <td>Input clock</td>
4086 </tr>
4087 <tr class="row-odd"><td>11</td>
4088 <td>DEV_DCC8_DCC_INPUT10_CLK</td>
4089 <td>Input clock</td>
4090 </tr>
4091 <tr class="row-even"><td>12</td>
4092 <td>DEV_DCC8_VBUS_CLK</td>
4093 <td>Input clock</td>
4094 </tr>
4095 </tbody>
4096 </table>
4097 </div>
4098 <div class="section" id="clocks-for-dcc9-device">
4099 <span id="soc-doc-j784s4-public-clks-dcc9"></span><h3>Clocks for DCC9 Device<a class="headerlink" href="#clocks-for-dcc9-device" title="Permalink to this headline">¶</a></h3>
4100 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DCC9</span></a> (ID = 87)</p>
4101 <p>Following is a mapping of Clocks IDs to function:</p>
4102 <table border="1" class="docutils">
4103 <colgroup>
4104 <col width="24%" />
4105 <col width="51%" />
4106 <col width="25%" />
4107 </colgroup>
4108 <thead valign="bottom">
4109 <tr class="row-odd"><th class="head">Clock ID</th>
4110 <th class="head">Name</th>
4111 <th class="head">Function</th>
4112 </tr>
4113 </thead>
4114 <tbody valign="top">
4115 <tr class="row-even"><td>0</td>
4116 <td>DEV_DCC9_DCC_CLKSRC0_CLK</td>
4117 <td>Input clock</td>
4118 </tr>
4119 <tr class="row-odd"><td>1</td>
4120 <td>DEV_DCC9_DCC_CLKSRC1_CLK</td>
4121 <td>Input clock</td>
4122 </tr>
4123 <tr class="row-even"><td>2</td>
4124 <td>DEV_DCC9_DCC_CLKSRC2_CLK</td>
4125 <td>Input clock</td>
4126 </tr>
4127 <tr class="row-odd"><td>3</td>
4128 <td>DEV_DCC9_DCC_CLKSRC3_CLK</td>
4129 <td>Input clock</td>
4130 </tr>
4131 <tr class="row-even"><td>4</td>
4132 <td>DEV_DCC9_DCC_CLKSRC4_CLK</td>
4133 <td>Input clock</td>
4134 </tr>
4135 <tr class="row-odd"><td>5</td>
4136 <td>DEV_DCC9_DCC_CLKSRC5_CLK</td>
4137 <td>Input clock</td>
4138 </tr>
4139 <tr class="row-even"><td>6</td>
4140 <td>DEV_DCC9_DCC_CLKSRC6_CLK</td>
4141 <td>Input clock</td>
4142 </tr>
4143 <tr class="row-odd"><td>8</td>
4144 <td>DEV_DCC9_DCC_INPUT00_CLK</td>
4145 <td>Input clock</td>
4146 </tr>
4147 <tr class="row-even"><td>9</td>
4148 <td>DEV_DCC9_DCC_INPUT01_CLK</td>
4149 <td>Input clock</td>
4150 </tr>
4151 <tr class="row-odd"><td>10</td>
4152 <td>DEV_DCC9_DCC_INPUT02_CLK</td>
4153 <td>Input clock</td>
4154 </tr>
4155 <tr class="row-even"><td>11</td>
4156 <td>DEV_DCC9_DCC_INPUT10_CLK</td>
4157 <td>Input clock</td>
4158 </tr>
4159 <tr class="row-odd"><td>12</td>
4160 <td>DEV_DCC9_VBUS_CLK</td>
4161 <td>Input clock</td>
4162 </tr>
4163 </tbody>
4164 </table>
4165 </div>
4166 <div class="section" id="clocks-for-ddr0-device">
4167 <span id="soc-doc-j784s4-public-clks-ddr0"></span><h3>Clocks for DDR0 Device<a class="headerlink" href="#clocks-for-ddr0-device" title="Permalink to this headline">¶</a></h3>
4168 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DDR0</span></a> (ID = 191)</p>
4169 <p>Following is a mapping of Clocks IDs to function:</p>
4170 <table border="1" class="docutils">
4171 <colgroup>
4172 <col width="23%" />
4173 <col width="53%" />
4174 <col width="25%" />
4175 </colgroup>
4176 <thead valign="bottom">
4177 <tr class="row-odd"><th class="head">Clock ID</th>
4178 <th class="head">Name</th>
4179 <th class="head">Function</th>
4180 </tr>
4181 </thead>
4182 <tbody valign="top">
4183 <tr class="row-even"><td>0</td>
4184 <td>DEV_DDR0_DDRSS_CFG_CLK</td>
4185 <td>Input clock</td>
4186 </tr>
4187 <tr class="row-odd"><td>1</td>
4188 <td>DEV_DDR0_DDRSS_DDR_PLL_CLK</td>
4189 <td>Input clock</td>
4190 </tr>
4191 <tr class="row-even"><td>4</td>
4192 <td>DEV_DDR0_DDRSS_VBUS_CLK</td>
4193 <td>Input clock</td>
4194 </tr>
4195 <tr class="row-odd"><td>5</td>
4196 <td>DEV_DDR0_PLL_CTRL_CLK</td>
4197 <td>Input clock</td>
4198 </tr>
4199 </tbody>
4200 </table>
4201 </div>
4202 <div class="section" id="clocks-for-ddr1-device">
4203 <span id="soc-doc-j784s4-public-clks-ddr1"></span><h3>Clocks for DDR1 Device<a class="headerlink" href="#clocks-for-ddr1-device" title="Permalink to this headline">¶</a></h3>
4204 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DDR1</span></a> (ID = 192)</p>
4205 <p>Following is a mapping of Clocks IDs to function:</p>
4206 <table border="1" class="docutils">
4207 <colgroup>
4208 <col width="23%" />
4209 <col width="53%" />
4210 <col width="25%" />
4211 </colgroup>
4212 <thead valign="bottom">
4213 <tr class="row-odd"><th class="head">Clock ID</th>
4214 <th class="head">Name</th>
4215 <th class="head">Function</th>
4216 </tr>
4217 </thead>
4218 <tbody valign="top">
4219 <tr class="row-even"><td>0</td>
4220 <td>DEV_DDR1_DDRSS_CFG_CLK</td>
4221 <td>Input clock</td>
4222 </tr>
4223 <tr class="row-odd"><td>1</td>
4224 <td>DEV_DDR1_DDRSS_DDR_PLL_CLK</td>
4225 <td>Input clock</td>
4226 </tr>
4227 <tr class="row-even"><td>4</td>
4228 <td>DEV_DDR1_DDRSS_VBUS_CLK</td>
4229 <td>Input clock</td>
4230 </tr>
4231 <tr class="row-odd"><td>5</td>
4232 <td>DEV_DDR1_PLL_CTRL_CLK</td>
4233 <td>Input clock</td>
4234 </tr>
4235 </tbody>
4236 </table>
4237 </div>
4238 <div class="section" id="clocks-for-ddr2-device">
4239 <span id="soc-doc-j784s4-public-clks-ddr2"></span><h3>Clocks for DDR2 Device<a class="headerlink" href="#clocks-for-ddr2-device" title="Permalink to this headline">¶</a></h3>
4240 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DDR2</span></a> (ID = 193)</p>
4241 <p>Following is a mapping of Clocks IDs to function:</p>
4242 <table border="1" class="docutils">
4243 <colgroup>
4244 <col width="23%" />
4245 <col width="53%" />
4246 <col width="25%" />
4247 </colgroup>
4248 <thead valign="bottom">
4249 <tr class="row-odd"><th class="head">Clock ID</th>
4250 <th class="head">Name</th>
4251 <th class="head">Function</th>
4252 </tr>
4253 </thead>
4254 <tbody valign="top">
4255 <tr class="row-even"><td>0</td>
4256 <td>DEV_DDR2_DDRSS_CFG_CLK</td>
4257 <td>Input clock</td>
4258 </tr>
4259 <tr class="row-odd"><td>1</td>
4260 <td>DEV_DDR2_DDRSS_DDR_PLL_CLK</td>
4261 <td>Input clock</td>
4262 </tr>
4263 <tr class="row-even"><td>4</td>
4264 <td>DEV_DDR2_DDRSS_VBUS_CLK</td>
4265 <td>Input clock</td>
4266 </tr>
4267 <tr class="row-odd"><td>5</td>
4268 <td>DEV_DDR2_PLL_CTRL_CLK</td>
4269 <td>Input clock</td>
4270 </tr>
4271 </tbody>
4272 </table>
4273 </div>
4274 <div class="section" id="clocks-for-ddr3-device">
4275 <span id="soc-doc-j784s4-public-clks-ddr3"></span><h3>Clocks for DDR3 Device<a class="headerlink" href="#clocks-for-ddr3-device" title="Permalink to this headline">¶</a></h3>
4276 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DDR3</span></a> (ID = 194)</p>
4277 <p>Following is a mapping of Clocks IDs to function:</p>
4278 <table border="1" class="docutils">
4279 <colgroup>
4280 <col width="23%" />
4281 <col width="53%" />
4282 <col width="25%" />
4283 </colgroup>
4284 <thead valign="bottom">
4285 <tr class="row-odd"><th class="head">Clock ID</th>
4286 <th class="head">Name</th>
4287 <th class="head">Function</th>
4288 </tr>
4289 </thead>
4290 <tbody valign="top">
4291 <tr class="row-even"><td>0</td>
4292 <td>DEV_DDR3_DDRSS_CFG_CLK</td>
4293 <td>Input clock</td>
4294 </tr>
4295 <tr class="row-odd"><td>1</td>
4296 <td>DEV_DDR3_DDRSS_DDR_PLL_CLK</td>
4297 <td>Input clock</td>
4298 </tr>
4299 <tr class="row-even"><td>4</td>
4300 <td>DEV_DDR3_DDRSS_VBUS_CLK</td>
4301 <td>Input clock</td>
4302 </tr>
4303 <tr class="row-odd"><td>5</td>
4304 <td>DEV_DDR3_PLL_CTRL_CLK</td>
4305 <td>Input clock</td>
4306 </tr>
4307 </tbody>
4308 </table>
4309 </div>
4310 <div class="section" id="clocks-for-debugss-wrap0-device">
4311 <span id="soc-doc-j784s4-public-clks-debugss-wrap0"></span><h3>Clocks for DEBUGSS_WRAP0 Device<a class="headerlink" href="#clocks-for-debugss-wrap0-device" title="Permalink to this headline">¶</a></h3>
4312 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DEBUGSS_WRAP0</span></a> (ID = 91)</p>
4313 <p>Following is a mapping of Clocks IDs to function:</p>
4314 <table border="1" class="docutils">
4315 <colgroup>
4316 <col width="20%" />
4317 <col width="57%" />
4318 <col width="23%" />
4319 </colgroup>
4320 <thead valign="bottom">
4321 <tr class="row-odd"><th class="head">Clock ID</th>
4322 <th class="head">Name</th>
4323 <th class="head">Function</th>
4324 </tr>
4325 </thead>
4326 <tbody valign="top">
4327 <tr class="row-even"><td>0</td>
4328 <td>DEV_DEBUGSS_WRAP0_ATB_CLK</td>
4329 <td>Input clock</td>
4330 </tr>
4331 <tr class="row-odd"><td>1</td>
4332 <td>DEV_DEBUGSS_WRAP0_CORE_CLK</td>
4333 <td>Input clock</td>
4334 </tr>
4335 <tr class="row-even"><td>2</td>
4336 <td>DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK</td>
4337 <td>Output clock</td>
4338 </tr>
4339 <tr class="row-odd"><td>20</td>
4340 <td>DEV_DEBUGSS_WRAP0_JTAG_TCK</td>
4341 <td>Input clock</td>
4342 </tr>
4343 <tr class="row-even"><td>22</td>
4344 <td>DEV_DEBUGSS_WRAP0_TREXPT_CLK</td>
4345 <td>Input clock</td>
4346 </tr>
4347 </tbody>
4348 </table>
4349 </div>
4350 <div class="section" id="clocks-for-debugsuspendrtr0-device">
4351 <span id="soc-doc-j784s4-public-clks-debugsuspendrtr0"></span><h3>Clocks for DEBUGSUSPENDRTR0 Device<a class="headerlink" href="#clocks-for-debugsuspendrtr0-device" title="Permalink to this headline">¶</a></h3>
4352 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DEBUGSUSPENDRTR0</span></a> (ID = 190)</p>
4353 <p>Following is a mapping of Clocks IDs to function:</p>
4354 <table border="1" class="docutils">
4355 <colgroup>
4356 <col width="21%" />
4357 <col width="55%" />
4358 <col width="23%" />
4359 </colgroup>
4360 <thead valign="bottom">
4361 <tr class="row-odd"><th class="head">Clock ID</th>
4362 <th class="head">Name</th>
4363 <th class="head">Function</th>
4364 </tr>
4365 </thead>
4366 <tbody valign="top">
4367 <tr class="row-even"><td>0</td>
4368 <td>DEV_DEBUGSUSPENDRTR0_INTR_CLK</td>
4369 <td>Input clock</td>
4370 </tr>
4371 </tbody>
4372 </table>
4373 </div>
4374 <div class="section" id="clocks-for-dmpac0-device">
4375 <span id="soc-doc-j784s4-public-clks-dmpac0"></span><h3>Clocks for DMPAC0 Device<a class="headerlink" href="#clocks-for-dmpac0-device" title="Permalink to this headline">¶</a></h3>
4376 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DMPAC0</span></a> (ID = 92)</p>
4377 <p>Following is a mapping of Clocks IDs to function:</p>
4378 <table border="1" class="docutils">
4379 <colgroup>
4380 <col width="29%" />
4381 <col width="39%" />
4382 <col width="32%" />
4383 </colgroup>
4384 <thead valign="bottom">
4385 <tr class="row-odd"><th class="head">Clock ID</th>
4386 <th class="head">Name</th>
4387 <th class="head">Function</th>
4388 </tr>
4389 </thead>
4390 <tbody valign="top">
4391 <tr class="row-even"><td>0</td>
4392 <td>DEV_DMPAC0_CLK</td>
4393 <td>Input clock</td>
4394 </tr>
4395 </tbody>
4396 </table>
4397 </div>
4398 <div class="section" id="clocks-for-dmpac0-ctset-0-device">
4399 <span id="soc-doc-j784s4-public-clks-dmpac0-ctset-0"></span><h3>Clocks for DMPAC0_CTSET_0 Device<a class="headerlink" href="#clocks-for-dmpac0-ctset-0-device" title="Permalink to this headline">¶</a></h3>
4400 <p><strong>This device has no defined clocks.</strong></p>
4401 </div>
4402 <div class="section" id="clocks-for-dmpac0-intd-0-device">
4403 <span id="soc-doc-j784s4-public-clks-dmpac0-intd-0"></span><h3>Clocks for DMPAC0_INTD_0 Device<a class="headerlink" href="#clocks-for-dmpac0-intd-0-device" title="Permalink to this headline">¶</a></h3>
4404 <p><strong>This device has no defined clocks.</strong></p>
4405 </div>
4406 <div class="section" id="clocks-for-dmpac0-sde-0-device">
4407 <span id="soc-doc-j784s4-public-clks-dmpac0-sde-0"></span><h3>Clocks for DMPAC0_SDE_0 Device<a class="headerlink" href="#clocks-for-dmpac0-sde-0-device" title="Permalink to this headline">¶</a></h3>
4408 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DMPAC0_SDE_0</span></a> (ID = 96)</p>
4409 <p>Following is a mapping of Clocks IDs to function:</p>
4410 <table border="1" class="docutils">
4411 <colgroup>
4412 <col width="26%" />
4413 <col width="47%" />
4414 <col width="28%" />
4415 </colgroup>
4416 <thead valign="bottom">
4417 <tr class="row-odd"><th class="head">Clock ID</th>
4418 <th class="head">Name</th>
4419 <th class="head">Function</th>
4420 </tr>
4421 </thead>
4422 <tbody valign="top">
4423 <tr class="row-even"><td>0</td>
4424 <td>DEV_DMPAC0_SDE_0_CLK</td>
4425 <td>Input clock</td>
4426 </tr>
4427 </tbody>
4428 </table>
4429 </div>
4430 <div class="section" id="clocks-for-dmpac0-utc-0-device">
4431 <span id="soc-doc-j784s4-public-clks-dmpac0-utc-0"></span><h3>Clocks for DMPAC0_UTC_0 Device<a class="headerlink" href="#clocks-for-dmpac0-utc-0-device" title="Permalink to this headline">¶</a></h3>
4432 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DMPAC0_UTC_0</span></a> (ID = 95)</p>
4433 <p>Following is a mapping of Clocks IDs to function:</p>
4434 <table border="1" class="docutils">
4435 <colgroup>
4436 <col width="21%" />
4437 <col width="56%" />
4438 <col width="23%" />
4439 </colgroup>
4440 <thead valign="bottom">
4441 <tr class="row-odd"><th class="head">Clock ID</th>
4442 <th class="head">Name</th>
4443 <th class="head">Function</th>
4444 </tr>
4445 </thead>
4446 <tbody valign="top">
4447 <tr class="row-even"><td>0</td>
4448 <td>DEV_DMPAC0_UTC_0_PSIL_LEAF_CLK</td>
4449 <td>Input clock</td>
4450 </tr>
4451 </tbody>
4452 </table>
4453 </div>
4454 <div class="section" id="clocks-for-dmpac-vpac-psilss0-device">
4455 <span id="soc-doc-j784s4-public-clks-dmpac-vpac-psilss0"></span><h3>Clocks for DMPAC_VPAC_PSILSS0 Device<a class="headerlink" href="#clocks-for-dmpac-vpac-psilss0-device" title="Permalink to this headline">¶</a></h3>
4456 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DMPAC_VPAC_PSILSS0</span></a> (ID = 195)</p>
4457 <p>Following is a mapping of Clocks IDs to function:</p>
4458 <table border="1" class="docutils">
4459 <colgroup>
4460 <col width="21%" />
4461 <col width="57%" />
4462 <col width="22%" />
4463 </colgroup>
4464 <thead valign="bottom">
4465 <tr class="row-odd"><th class="head">Clock ID</th>
4466 <th class="head">Name</th>
4467 <th class="head">Function</th>
4468 </tr>
4469 </thead>
4470 <tbody valign="top">
4471 <tr class="row-even"><td>0</td>
4472 <td>DEV_DMPAC_VPAC_PSILSS0_MAIN_CLK</td>
4473 <td>Input clock</td>
4474 </tr>
4475 </tbody>
4476 </table>
4477 </div>
4478 <div class="section" id="clocks-for-dphy-rx0-device">
4479 <span id="soc-doc-j784s4-public-clks-dphy-rx0"></span><h3>Clocks for DPHY_RX0 Device<a class="headerlink" href="#clocks-for-dphy-rx0-device" title="Permalink to this headline">¶</a></h3>
4480 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DPHY_RX0</span></a> (ID = 212)</p>
4481 <p>Following is a mapping of Clocks IDs to function:</p>
4482 <table border="1" class="docutils">
4483 <colgroup>
4484 <col width="21%" />
4485 <col width="55%" />
4486 <col width="24%" />
4487 </colgroup>
4488 <thead valign="bottom">
4489 <tr class="row-odd"><th class="head">Clock ID</th>
4490 <th class="head">Name</th>
4491 <th class="head">Function</th>
4492 </tr>
4493 </thead>
4494 <tbody valign="top">
4495 <tr class="row-even"><td>2</td>
4496 <td>DEV_DPHY_RX0_IO_RX_CL_L_M</td>
4497 <td>Input clock</td>
4498 </tr>
4499 <tr class="row-odd"><td>3</td>
4500 <td>DEV_DPHY_RX0_IO_RX_CL_L_P</td>
4501 <td>Input clock</td>
4502 </tr>
4503 <tr class="row-even"><td>4</td>
4504 <td>DEV_DPHY_RX0_JTAG_TCK</td>
4505 <td>Input clock</td>
4506 </tr>
4507 <tr class="row-odd"><td>5</td>
4508 <td>DEV_DPHY_RX0_MAIN_CLK_CLK</td>
4509 <td>Input clock</td>
4510 </tr>
4511 <tr class="row-even"><td>6</td>
4512 <td>DEV_DPHY_RX0_PPI_D_RX_ULPS_ESC</td>
4513 <td>Output clock</td>
4514 </tr>
4515 <tr class="row-odd"><td>7</td>
4516 <td>DEV_DPHY_RX0_PPI_RX_BYTE_CLK</td>
4517 <td>Output clock</td>
4518 </tr>
4519 </tbody>
4520 </table>
4521 </div>
4522 <div class="section" id="clocks-for-dphy-rx1-device">
4523 <span id="soc-doc-j784s4-public-clks-dphy-rx1"></span><h3>Clocks for DPHY_RX1 Device<a class="headerlink" href="#clocks-for-dphy-rx1-device" title="Permalink to this headline">¶</a></h3>
4524 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DPHY_RX1</span></a> (ID = 213)</p>
4525 <p>Following is a mapping of Clocks IDs to function:</p>
4526 <table border="1" class="docutils">
4527 <colgroup>
4528 <col width="21%" />
4529 <col width="55%" />
4530 <col width="24%" />
4531 </colgroup>
4532 <thead valign="bottom">
4533 <tr class="row-odd"><th class="head">Clock ID</th>
4534 <th class="head">Name</th>
4535 <th class="head">Function</th>
4536 </tr>
4537 </thead>
4538 <tbody valign="top">
4539 <tr class="row-even"><td>2</td>
4540 <td>DEV_DPHY_RX1_IO_RX_CL_L_M</td>
4541 <td>Input clock</td>
4542 </tr>
4543 <tr class="row-odd"><td>3</td>
4544 <td>DEV_DPHY_RX1_IO_RX_CL_L_P</td>
4545 <td>Input clock</td>
4546 </tr>
4547 <tr class="row-even"><td>4</td>
4548 <td>DEV_DPHY_RX1_JTAG_TCK</td>
4549 <td>Input clock</td>
4550 </tr>
4551 <tr class="row-odd"><td>5</td>
4552 <td>DEV_DPHY_RX1_MAIN_CLK_CLK</td>
4553 <td>Input clock</td>
4554 </tr>
4555 <tr class="row-even"><td>6</td>
4556 <td>DEV_DPHY_RX1_PPI_D_RX_ULPS_ESC</td>
4557 <td>Output clock</td>
4558 </tr>
4559 <tr class="row-odd"><td>7</td>
4560 <td>DEV_DPHY_RX1_PPI_RX_BYTE_CLK</td>
4561 <td>Output clock</td>
4562 </tr>
4563 </tbody>
4564 </table>
4565 </div>
4566 <div class="section" id="clocks-for-dphy-rx2-device">
4567 <span id="soc-doc-j784s4-public-clks-dphy-rx2"></span><h3>Clocks for DPHY_RX2 Device<a class="headerlink" href="#clocks-for-dphy-rx2-device" title="Permalink to this headline">¶</a></h3>
4568 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DPHY_RX2</span></a> (ID = 214)</p>
4569 <p>Following is a mapping of Clocks IDs to function:</p>
4570 <table border="1" class="docutils">
4571 <colgroup>
4572 <col width="21%" />
4573 <col width="55%" />
4574 <col width="24%" />
4575 </colgroup>
4576 <thead valign="bottom">
4577 <tr class="row-odd"><th class="head">Clock ID</th>
4578 <th class="head">Name</th>
4579 <th class="head">Function</th>
4580 </tr>
4581 </thead>
4582 <tbody valign="top">
4583 <tr class="row-even"><td>2</td>
4584 <td>DEV_DPHY_RX2_IO_RX_CL_L_M</td>
4585 <td>Input clock</td>
4586 </tr>
4587 <tr class="row-odd"><td>3</td>
4588 <td>DEV_DPHY_RX2_IO_RX_CL_L_P</td>
4589 <td>Input clock</td>
4590 </tr>
4591 <tr class="row-even"><td>4</td>
4592 <td>DEV_DPHY_RX2_JTAG_TCK</td>
4593 <td>Input clock</td>
4594 </tr>
4595 <tr class="row-odd"><td>5</td>
4596 <td>DEV_DPHY_RX2_MAIN_CLK_CLK</td>
4597 <td>Input clock</td>
4598 </tr>
4599 <tr class="row-even"><td>6</td>
4600 <td>DEV_DPHY_RX2_PPI_D_RX_ULPS_ESC</td>
4601 <td>Output clock</td>
4602 </tr>
4603 <tr class="row-odd"><td>7</td>
4604 <td>DEV_DPHY_RX2_PPI_RX_BYTE_CLK</td>
4605 <td>Output clock</td>
4606 </tr>
4607 </tbody>
4608 </table>
4609 </div>
4610 <div class="section" id="clocks-for-dphy-tx0-device">
4611 <span id="soc-doc-j784s4-public-clks-dphy-tx0"></span><h3>Clocks for DPHY_TX0 Device<a class="headerlink" href="#clocks-for-dphy-tx0-device" title="Permalink to this headline">¶</a></h3>
4612 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DPHY_TX0</span></a> (ID = 402)</p>
4613 <p>Following is a mapping of Clocks IDs to function:</p>
4614 <table border="1" class="docutils">
4615 <colgroup>
4616 <col width="9%" />
4617 <col width="50%" />
4618 <col width="41%" />
4619 </colgroup>
4620 <thead valign="bottom">
4621 <tr class="row-odd"><th class="head">Clock ID</th>
4622 <th class="head">Name</th>
4623 <th class="head">Function</th>
4624 </tr>
4625 </thead>
4626 <tbody valign="top">
4627 <tr class="row-even"><td>0</td>
4628 <td>DEV_DPHY_TX0_CK_M</td>
4629 <td>Output clock</td>
4630 </tr>
4631 <tr class="row-odd"><td>1</td>
4632 <td>DEV_DPHY_TX0_CK_P</td>
4633 <td>Output clock</td>
4634 </tr>
4635 <tr class="row-even"><td>2</td>
4636 <td>DEV_DPHY_TX0_CLK</td>
4637 <td>Input clock</td>
4638 </tr>
4639 <tr class="row-odd"><td>3</td>
4640 <td>DEV_DPHY_TX0_DPHY_REF_CLK</td>
4641 <td>Input muxed clock</td>
4642 </tr>
4643 <tr class="row-even"><td>4</td>
4644 <td>DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
4645 <td>Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK</td>
4646 </tr>
4647 <tr class="row-odd"><td>5</td>
4648 <td>DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
4649 <td>Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK</td>
4650 </tr>
4651 <tr class="row-even"><td>6</td>
4652 <td>DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
4653 <td>Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK</td>
4654 </tr>
4655 <tr class="row-odd"><td>7</td>
4656 <td>DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
4657 <td>Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK</td>
4658 </tr>
4659 <tr class="row-even"><td>8</td>
4660 <td>DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK</td>
4661 <td>Output clock</td>
4662 </tr>
4663 <tr class="row-odd"><td>9</td>
4664 <td>DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK</td>
4665 <td>Input clock</td>
4666 </tr>
4667 <tr class="row-even"><td>10</td>
4668 <td>DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK</td>
4669 <td>Output clock</td>
4670 </tr>
4671 <tr class="row-odd"><td>12</td>
4672 <td>DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK</td>
4673 <td>Input clock</td>
4674 </tr>
4675 <tr class="row-even"><td>13</td>
4676 <td>DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK</td>
4677 <td>Output clock</td>
4678 </tr>
4679 <tr class="row-odd"><td>20</td>
4680 <td>DEV_DPHY_TX0_PSM_CLK</td>
4681 <td>Input clock</td>
4682 </tr>
4683 <tr class="row-even"><td>24</td>
4684 <td>DEV_DPHY_TX0_TAP_TCK</td>
4685 <td>Input clock</td>
4686 </tr>
4687 </tbody>
4688 </table>
4689 </div>
4690 <div class="section" id="clocks-for-dphy-tx1-device">
4691 <span id="soc-doc-j784s4-public-clks-dphy-tx1"></span><h3>Clocks for DPHY_TX1 Device<a class="headerlink" href="#clocks-for-dphy-tx1-device" title="Permalink to this headline">¶</a></h3>
4692 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DPHY_TX1</span></a> (ID = 403)</p>
4693 <p>Following is a mapping of Clocks IDs to function:</p>
4694 <table border="1" class="docutils">
4695 <colgroup>
4696 <col width="9%" />
4697 <col width="50%" />
4698 <col width="41%" />
4699 </colgroup>
4700 <thead valign="bottom">
4701 <tr class="row-odd"><th class="head">Clock ID</th>
4702 <th class="head">Name</th>
4703 <th class="head">Function</th>
4704 </tr>
4705 </thead>
4706 <tbody valign="top">
4707 <tr class="row-even"><td>0</td>
4708 <td>DEV_DPHY_TX1_CK_M</td>
4709 <td>Output clock</td>
4710 </tr>
4711 <tr class="row-odd"><td>1</td>
4712 <td>DEV_DPHY_TX1_CK_P</td>
4713 <td>Output clock</td>
4714 </tr>
4715 <tr class="row-even"><td>2</td>
4716 <td>DEV_DPHY_TX1_CLK</td>
4717 <td>Input clock</td>
4718 </tr>
4719 <tr class="row-odd"><td>3</td>
4720 <td>DEV_DPHY_TX1_DPHY_REF_CLK</td>
4721 <td>Input muxed clock</td>
4722 </tr>
4723 <tr class="row-even"><td>4</td>
4724 <td>DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
4725 <td>Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK</td>
4726 </tr>
4727 <tr class="row-odd"><td>5</td>
4728 <td>DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
4729 <td>Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK</td>
4730 </tr>
4731 <tr class="row-even"><td>6</td>
4732 <td>DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
4733 <td>Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK</td>
4734 </tr>
4735 <tr class="row-odd"><td>7</td>
4736 <td>DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
4737 <td>Parent input clock option to DEV_DPHY_TX1_DPHY_REF_CLK</td>
4738 </tr>
4739 <tr class="row-even"><td>8</td>
4740 <td>DEV_DPHY_TX1_IP1_PPI_M_RXCLKESC_CLK</td>
4741 <td>Output clock</td>
4742 </tr>
4743 <tr class="row-odd"><td>9</td>
4744 <td>DEV_DPHY_TX1_IP1_PPI_M_TXCLKESC_CLK</td>
4745 <td>Input clock</td>
4746 </tr>
4747 <tr class="row-even"><td>10</td>
4748 <td>DEV_DPHY_TX1_IP1_PPI_TXBYTECLKHS_CL_CLK</td>
4749 <td>Output clock</td>
4750 </tr>
4751 <tr class="row-odd"><td>13</td>
4752 <td>DEV_DPHY_TX1_IP2_PPI_TXBYTECLKHS_CL_CLK</td>
4753 <td>Output clock</td>
4754 </tr>
4755 <tr class="row-even"><td>20</td>
4756 <td>DEV_DPHY_TX1_PSM_CLK</td>
4757 <td>Input clock</td>
4758 </tr>
4759 <tr class="row-odd"><td>24</td>
4760 <td>DEV_DPHY_TX1_TAP_TCK</td>
4761 <td>Input clock</td>
4762 </tr>
4763 </tbody>
4764 </table>
4765 </div>
4766 <div class="section" id="clocks-for-dss0-device">
4767 <span id="soc-doc-j784s4-public-clks-dss0"></span><h3>Clocks for DSS0 Device<a class="headerlink" href="#clocks-for-dss0-device" title="Permalink to this headline">¶</a></h3>
4768 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DSS0</span></a> (ID = 218)</p>
4769 <p>Following is a mapping of Clocks IDs to function:</p>
4770 <table border="1" class="docutils">
4771 <colgroup>
4772 <col width="8%" />
4773 <col width="52%" />
4774 <col width="41%" />
4775 </colgroup>
4776 <thead valign="bottom">
4777 <tr class="row-odd"><th class="head">Clock ID</th>
4778 <th class="head">Name</th>
4779 <th class="head">Function</th>
4780 </tr>
4781 </thead>
4782 <tbody valign="top">
4783 <tr class="row-even"><td>0</td>
4784 <td>DEV_DSS0_DSS_FUNC_CLK</td>
4785 <td>Input clock</td>
4786 </tr>
4787 <tr class="row-odd"><td>1</td>
4788 <td>DEV_DSS0_DSS_INST0_DPI_0_IN_CLK</td>
4789 <td>Input clock</td>
4790 </tr>
4791 <tr class="row-even"><td>2</td>
4792 <td>DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK</td>
4793 <td>Input muxed clock</td>
4794 </tr>
4795 <tr class="row-odd"><td>3</td>
4796 <td>DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK</td>
4797 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK</td>
4798 </tr>
4799 <tr class="row-even"><td>4</td>
4800 <td>DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0</td>
4801 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK</td>
4802 </tr>
4803 <tr class="row-odd"><td>5</td>
4804 <td>DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK</td>
4805 <td>Input muxed clock</td>
4806 </tr>
4807 <tr class="row-even"><td>6</td>
4808 <td>DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK</td>
4809 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK</td>
4810 </tr>
4811 <tr class="row-odd"><td>7</td>
4812 <td>DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0</td>
4813 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK</td>
4814 </tr>
4815 <tr class="row-even"><td>8</td>
4816 <td>DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0</td>
4817 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK</td>
4818 </tr>
4819 <tr class="row-odd"><td>9</td>
4820 <td>DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK</td>
4821 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK</td>
4822 </tr>
4823 <tr class="row-even"><td>10</td>
4824 <td>DEV_DSS0_DSS_INST0_DPI_2_IN_CLK</td>
4825 <td>Input muxed clock</td>
4826 </tr>
4827 <tr class="row-odd"><td>11</td>
4828 <td>DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK</td>
4829 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK</td>
4830 </tr>
4831 <tr class="row-even"><td>12</td>
4832 <td>DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK</td>
4833 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK</td>
4834 </tr>
4835 <tr class="row-odd"><td>13</td>
4836 <td>DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0</td>
4837 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_CLK</td>
4838 </tr>
4839 <tr class="row-even"><td>14</td>
4840 <td>DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK</td>
4841 <td>Input muxed clock</td>
4842 </tr>
4843 <tr class="row-odd"><td>15</td>
4844 <td>DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK</td>
4845 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK</td>
4846 </tr>
4847 <tr class="row-even"><td>16</td>
4848 <td>DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK</td>
4849 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK</td>
4850 </tr>
4851 <tr class="row-odd"><td>17</td>
4852 <td>DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0</td>
4853 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK</td>
4854 </tr>
4855 <tr class="row-even"><td>18</td>
4856 <td>DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK</td>
4857 <td>Input muxed clock</td>
4858 </tr>
4859 <tr class="row-odd"><td>19</td>
4860 <td>DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK</td>
4861 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK</td>
4862 </tr>
4863 <tr class="row-even"><td>20</td>
4864 <td>DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK</td>
4865 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK</td>
4866 </tr>
4867 <tr class="row-odd"><td>21</td>
4868 <td>DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK_DUP0</td>
4869 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK</td>
4870 </tr>
4871 <tr class="row-even"><td>22</td>
4872 <td>DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0</td>
4873 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK</td>
4874 </tr>
4875 <tr class="row-odd"><td>23</td>
4876 <td>DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0</td>
4877 <td>Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK</td>
4878 </tr>
4879 <tr class="row-even"><td>24</td>
4880 <td>DEV_DSS0_DSS_INST0_PARA_1_OUT_CLK</td>
4881 <td>Output clock</td>
4882 </tr>
4883 <tr class="row-odd"><td>25</td>
4884 <td>DEV_DSS0_DSS_INST0_PARA_3_OUT_CLK</td>
4885 <td>Output clock</td>
4886 </tr>
4887 <tr class="row-even"><td>26</td>
4888 <td>DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK</td>
4889 <td>Output clock</td>
4890 </tr>
4891 <tr class="row-odd"><td>27</td>
4892 <td>DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK</td>
4893 <td>Output clock</td>
4894 </tr>
4895 <tr class="row-even"><td>28</td>
4896 <td>DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK</td>
4897 <td>Output clock</td>
4898 </tr>
4899 <tr class="row-odd"><td>29</td>
4900 <td>DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK</td>
4901 <td>Output clock</td>
4902 </tr>
4903 <tr class="row-even"><td>30</td>
4904 <td>DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK</td>
4905 <td>Output clock</td>
4906 </tr>
4907 </tbody>
4908 </table>
4909 </div>
4910 <div class="section" id="clocks-for-dss-dsi0-device">
4911 <span id="soc-doc-j784s4-public-clks-dss-dsi0"></span><h3>Clocks for DSS_DSI0 Device<a class="headerlink" href="#clocks-for-dss-dsi0-device" title="Permalink to this headline">¶</a></h3>
4912 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DSS_DSI0</span></a> (ID = 215)</p>
4913 <p>Following is a mapping of Clocks IDs to function:</p>
4914 <table border="1" class="docutils">
4915 <colgroup>
4916 <col width="19%" />
4917 <col width="61%" />
4918 <col width="20%" />
4919 </colgroup>
4920 <thead valign="bottom">
4921 <tr class="row-odd"><th class="head">Clock ID</th>
4922 <th class="head">Name</th>
4923 <th class="head">Function</th>
4924 </tr>
4925 </thead>
4926 <tbody valign="top">
4927 <tr class="row-even"><td>0</td>
4928 <td>DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK</td>
4929 <td>Input clock</td>
4930 </tr>
4931 <tr class="row-odd"><td>1</td>
4932 <td>DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK</td>
4933 <td>Input clock</td>
4934 </tr>
4935 <tr class="row-even"><td>2</td>
4936 <td>DEV_DSS_DSI0_DPI_0_CLK</td>
4937 <td>Input clock</td>
4938 </tr>
4939 <tr class="row-odd"><td>3</td>
4940 <td>DEV_DSS_DSI0_PLL_CTRL_CLK</td>
4941 <td>Input clock</td>
4942 </tr>
4943 <tr class="row-even"><td>4</td>
4944 <td>DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK</td>
4945 <td>Input clock</td>
4946 </tr>
4947 <tr class="row-odd"><td>5</td>
4948 <td>DEV_DSS_DSI0_SYS_CLK</td>
4949 <td>Input clock</td>
4950 </tr>
4951 </tbody>
4952 </table>
4953 </div>
4954 <div class="section" id="clocks-for-dss-dsi1-device">
4955 <span id="soc-doc-j784s4-public-clks-dss-dsi1"></span><h3>Clocks for DSS_DSI1 Device<a class="headerlink" href="#clocks-for-dss-dsi1-device" title="Permalink to this headline">¶</a></h3>
4956 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DSS_DSI1</span></a> (ID = 216)</p>
4957 <p>Following is a mapping of Clocks IDs to function:</p>
4958 <table border="1" class="docutils">
4959 <colgroup>
4960 <col width="19%" />
4961 <col width="61%" />
4962 <col width="20%" />
4963 </colgroup>
4964 <thead valign="bottom">
4965 <tr class="row-odd"><th class="head">Clock ID</th>
4966 <th class="head">Name</th>
4967 <th class="head">Function</th>
4968 </tr>
4969 </thead>
4970 <tbody valign="top">
4971 <tr class="row-even"><td>0</td>
4972 <td>DEV_DSS_DSI1_DPHY_0_RX_ESC_CLK</td>
4973 <td>Input clock</td>
4974 </tr>
4975 <tr class="row-odd"><td>1</td>
4976 <td>DEV_DSS_DSI1_DPHY_0_TX_ESC_CLK</td>
4977 <td>Input clock</td>
4978 </tr>
4979 <tr class="row-even"><td>2</td>
4980 <td>DEV_DSS_DSI1_DPI_0_CLK</td>
4981 <td>Input clock</td>
4982 </tr>
4983 <tr class="row-odd"><td>3</td>
4984 <td>DEV_DSS_DSI1_PLL_CTRL_CLK</td>
4985 <td>Input clock</td>
4986 </tr>
4987 <tr class="row-even"><td>4</td>
4988 <td>DEV_DSS_DSI1_PPI_0_TXBYTECLKHS_CL_CLK</td>
4989 <td>Input clock</td>
4990 </tr>
4991 <tr class="row-odd"><td>5</td>
4992 <td>DEV_DSS_DSI1_SYS_CLK</td>
4993 <td>Input clock</td>
4994 </tr>
4995 </tbody>
4996 </table>
4997 </div>
4998 <div class="section" id="clocks-for-dss-edp0-device">
4999 <span id="soc-doc-j784s4-public-clks-dss-edp0"></span><h3>Clocks for DSS_EDP0 Device<a class="headerlink" href="#clocks-for-dss-edp0-device" title="Permalink to this headline">¶</a></h3>
5000 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_DSS_EDP0</span></a> (ID = 217)</p>
5001 <p>Following is a mapping of Clocks IDs to function:</p>
5002 <table border="1" class="docutils">
5003 <colgroup>
5004 <col width="22%" />
5005 <col width="53%" />
5006 <col width="25%" />
5007 </colgroup>
5008 <thead valign="bottom">
5009 <tr class="row-odd"><th class="head">Clock ID</th>
5010 <th class="head">Name</th>
5011 <th class="head">Function</th>
5012 </tr>
5013 </thead>
5014 <tbody valign="top">
5015 <tr class="row-even"><td>0</td>
5016 <td>DEV_DSS_EDP0_AIF_I2S_CLK</td>
5017 <td>Input clock</td>
5018 </tr>
5019 <tr class="row-odd"><td>6</td>
5020 <td>DEV_DSS_EDP0_DPI_2_2X_CLK</td>
5021 <td>Input clock</td>
5022 </tr>
5023 <tr class="row-even"><td>7</td>
5024 <td>DEV_DSS_EDP0_DPI_2_CLK</td>
5025 <td>Input clock</td>
5026 </tr>
5027 <tr class="row-odd"><td>8</td>
5028 <td>DEV_DSS_EDP0_DPI_3_CLK</td>
5029 <td>Input clock</td>
5030 </tr>
5031 <tr class="row-even"><td>9</td>
5032 <td>DEV_DSS_EDP0_DPI_4_CLK</td>
5033 <td>Input clock</td>
5034 </tr>
5035 <tr class="row-odd"><td>10</td>
5036 <td>DEV_DSS_EDP0_DPI_5_CLK</td>
5037 <td>Input clock</td>
5038 </tr>
5039 <tr class="row-even"><td>11</td>
5040 <td>DEV_DSS_EDP0_DPTX_MOD_CLK</td>
5041 <td>Input clock</td>
5042 </tr>
5043 <tr class="row-odd"><td>12</td>
5044 <td>DEV_DSS_EDP0_PHY_LN0_REFCLK</td>
5045 <td>Input clock</td>
5046 </tr>
5047 <tr class="row-even"><td>13</td>
5048 <td>DEV_DSS_EDP0_PHY_LN0_RXCLK</td>
5049 <td>Input clock</td>
5050 </tr>
5051 <tr class="row-odd"><td>14</td>
5052 <td>DEV_DSS_EDP0_PHY_LN0_RXFCLK</td>
5053 <td>Input clock</td>
5054 </tr>
5055 <tr class="row-even"><td>15</td>
5056 <td>DEV_DSS_EDP0_PHY_LN0_TXCLK</td>
5057 <td>Output clock</td>
5058 </tr>
5059 <tr class="row-odd"><td>16</td>
5060 <td>DEV_DSS_EDP0_PHY_LN0_TXFCLK</td>
5061 <td>Input clock</td>
5062 </tr>
5063 <tr class="row-even"><td>17</td>
5064 <td>DEV_DSS_EDP0_PHY_LN0_TXMCLK</td>
5065 <td>Input clock</td>
5066 </tr>
5067 <tr class="row-odd"><td>18</td>
5068 <td>DEV_DSS_EDP0_PHY_LN1_REFCLK</td>
5069 <td>Input clock</td>
5070 </tr>
5071 <tr class="row-even"><td>19</td>
5072 <td>DEV_DSS_EDP0_PHY_LN1_RXCLK</td>
5073 <td>Input clock</td>
5074 </tr>
5075 <tr class="row-odd"><td>20</td>
5076 <td>DEV_DSS_EDP0_PHY_LN1_RXFCLK</td>
5077 <td>Input clock</td>
5078 </tr>
5079 <tr class="row-even"><td>21</td>
5080 <td>DEV_DSS_EDP0_PHY_LN1_TXCLK</td>
5081 <td>Output clock</td>
5082 </tr>
5083 <tr class="row-odd"><td>22</td>
5084 <td>DEV_DSS_EDP0_PHY_LN1_TXFCLK</td>
5085 <td>Input clock</td>
5086 </tr>
5087 <tr class="row-even"><td>23</td>
5088 <td>DEV_DSS_EDP0_PHY_LN1_TXMCLK</td>
5089 <td>Input clock</td>
5090 </tr>
5091 <tr class="row-odd"><td>24</td>
5092 <td>DEV_DSS_EDP0_PHY_LN2_REFCLK</td>
5093 <td>Input clock</td>
5094 </tr>
5095 <tr class="row-even"><td>25</td>
5096 <td>DEV_DSS_EDP0_PHY_LN2_RXCLK</td>
5097 <td>Input clock</td>
5098 </tr>
5099 <tr class="row-odd"><td>26</td>
5100 <td>DEV_DSS_EDP0_PHY_LN2_RXFCLK</td>
5101 <td>Input clock</td>
5102 </tr>
5103 <tr class="row-even"><td>27</td>
5104 <td>DEV_DSS_EDP0_PHY_LN2_TXCLK</td>
5105 <td>Output clock</td>
5106 </tr>
5107 <tr class="row-odd"><td>28</td>
5108 <td>DEV_DSS_EDP0_PHY_LN2_TXFCLK</td>
5109 <td>Input clock</td>
5110 </tr>
5111 <tr class="row-even"><td>29</td>
5112 <td>DEV_DSS_EDP0_PHY_LN2_TXMCLK</td>
5113 <td>Input clock</td>
5114 </tr>
5115 <tr class="row-odd"><td>30</td>
5116 <td>DEV_DSS_EDP0_PHY_LN3_REFCLK</td>
5117 <td>Input clock</td>
5118 </tr>
5119 <tr class="row-even"><td>31</td>
5120 <td>DEV_DSS_EDP0_PHY_LN3_RXCLK</td>
5121 <td>Input clock</td>
5122 </tr>
5123 <tr class="row-odd"><td>32</td>
5124 <td>DEV_DSS_EDP0_PHY_LN3_RXFCLK</td>
5125 <td>Input clock</td>
5126 </tr>
5127 <tr class="row-even"><td>33</td>
5128 <td>DEV_DSS_EDP0_PHY_LN3_TXCLK</td>
5129 <td>Output clock</td>
5130 </tr>
5131 <tr class="row-odd"><td>34</td>
5132 <td>DEV_DSS_EDP0_PHY_LN3_TXFCLK</td>
5133 <td>Input clock</td>
5134 </tr>
5135 <tr class="row-even"><td>35</td>
5136 <td>DEV_DSS_EDP0_PHY_LN3_TXMCLK</td>
5137 <td>Input clock</td>
5138 </tr>
5139 <tr class="row-odd"><td>36</td>
5140 <td>DEV_DSS_EDP0_PLL_CTRL_CLK</td>
5141 <td>Input clock</td>
5142 </tr>
5143 </tbody>
5144 </table>
5145 </div>
5146 <div class="section" id="clocks-for-ecap0-device">
5147 <span id="soc-doc-j784s4-public-clks-ecap0"></span><h3>Clocks for ECAP0 Device<a class="headerlink" href="#clocks-for-ecap0-device" title="Permalink to this headline">¶</a></h3>
5148 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_ECAP0</span></a> (ID = 126)</p>
5149 <p>Following is a mapping of Clocks IDs to function:</p>
5150 <table border="1" class="docutils">
5151 <colgroup>
5152 <col width="27%" />
5153 <col width="44%" />
5154 <col width="29%" />
5155 </colgroup>
5156 <thead valign="bottom">
5157 <tr class="row-odd"><th class="head">Clock ID</th>
5158 <th class="head">Name</th>
5159 <th class="head">Function</th>
5160 </tr>
5161 </thead>
5162 <tbody valign="top">
5163 <tr class="row-even"><td>0</td>
5164 <td>DEV_ECAP0_VBUS_CLK</td>
5165 <td>Input clock</td>
5166 </tr>
5167 </tbody>
5168 </table>
5169 </div>
5170 <div class="section" id="clocks-for-ecap1-device">
5171 <span id="soc-doc-j784s4-public-clks-ecap1"></span><h3>Clocks for ECAP1 Device<a class="headerlink" href="#clocks-for-ecap1-device" title="Permalink to this headline">¶</a></h3>
5172 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_ECAP1</span></a> (ID = 127)</p>
5173 <p>Following is a mapping of Clocks IDs to function:</p>
5174 <table border="1" class="docutils">
5175 <colgroup>
5176 <col width="27%" />
5177 <col width="44%" />
5178 <col width="29%" />
5179 </colgroup>
5180 <thead valign="bottom">
5181 <tr class="row-odd"><th class="head">Clock ID</th>
5182 <th class="head">Name</th>
5183 <th class="head">Function</th>
5184 </tr>
5185 </thead>
5186 <tbody valign="top">
5187 <tr class="row-even"><td>0</td>
5188 <td>DEV_ECAP1_VBUS_CLK</td>
5189 <td>Input clock</td>
5190 </tr>
5191 </tbody>
5192 </table>
5193 </div>
5194 <div class="section" id="clocks-for-ecap2-device">
5195 <span id="soc-doc-j784s4-public-clks-ecap2"></span><h3>Clocks for ECAP2 Device<a class="headerlink" href="#clocks-for-ecap2-device" title="Permalink to this headline">¶</a></h3>
5196 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_ECAP2</span></a> (ID = 128)</p>
5197 <p>Following is a mapping of Clocks IDs to function:</p>
5198 <table border="1" class="docutils">
5199 <colgroup>
5200 <col width="27%" />
5201 <col width="44%" />
5202 <col width="29%" />
5203 </colgroup>
5204 <thead valign="bottom">
5205 <tr class="row-odd"><th class="head">Clock ID</th>
5206 <th class="head">Name</th>
5207 <th class="head">Function</th>
5208 </tr>
5209 </thead>
5210 <tbody valign="top">
5211 <tr class="row-even"><td>0</td>
5212 <td>DEV_ECAP2_VBUS_CLK</td>
5213 <td>Input clock</td>
5214 </tr>
5215 </tbody>
5216 </table>
5217 </div>
5218 <div class="section" id="clocks-for-elm0-device">
5219 <span id="soc-doc-j784s4-public-clks-elm0"></span><h3>Clocks for ELM0 Device<a class="headerlink" href="#clocks-for-elm0-device" title="Permalink to this headline">¶</a></h3>
5220 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_ELM0</span></a> (ID = 130)</p>
5221 <p>Following is a mapping of Clocks IDs to function:</p>
5222 <table border="1" class="docutils">
5223 <colgroup>
5224 <col width="27%" />
5225 <col width="44%" />
5226 <col width="29%" />
5227 </colgroup>
5228 <thead valign="bottom">
5229 <tr class="row-odd"><th class="head">Clock ID</th>
5230 <th class="head">Name</th>
5231 <th class="head">Function</th>
5232 </tr>
5233 </thead>
5234 <tbody valign="top">
5235 <tr class="row-even"><td>0</td>
5236 <td>DEV_ELM0_VBUSP_CLK</td>
5237 <td>Input clock</td>
5238 </tr>
5239 </tbody>
5240 </table>
5241 </div>
5242 <div class="section" id="clocks-for-emif-data-0-vd-device">
5243 <span id="soc-doc-j784s4-public-clks-emif-data-0-vd"></span><h3>Clocks for EMIF_DATA_0_VD Device<a class="headerlink" href="#clocks-for-emif-data-0-vd-device" title="Permalink to this headline">¶</a></h3>
5244 <p><strong>This device has no defined clocks.</strong></p>
5245 </div>
5246 <div class="section" id="clocks-for-emif-data-1-vd-device">
5247 <span id="soc-doc-j784s4-public-clks-emif-data-1-vd"></span><h3>Clocks for EMIF_DATA_1_VD Device<a class="headerlink" href="#clocks-for-emif-data-1-vd-device" title="Permalink to this headline">¶</a></h3>
5248 <p><strong>This device has no defined clocks.</strong></p>
5249 </div>
5250 <div class="section" id="clocks-for-emif-data-2-vd-device">
5251 <span id="soc-doc-j784s4-public-clks-emif-data-2-vd"></span><h3>Clocks for EMIF_DATA_2_VD Device<a class="headerlink" href="#clocks-for-emif-data-2-vd-device" title="Permalink to this headline">¶</a></h3>
5252 <p><strong>This device has no defined clocks.</strong></p>
5253 </div>
5254 <div class="section" id="clocks-for-emif-data-3-vd-device">
5255 <span id="soc-doc-j784s4-public-clks-emif-data-3-vd"></span><h3>Clocks for EMIF_DATA_3_VD Device<a class="headerlink" href="#clocks-for-emif-data-3-vd-device" title="Permalink to this headline">¶</a></h3>
5256 <p><strong>This device has no defined clocks.</strong></p>
5257 </div>
5258 <div class="section" id="clocks-for-epwm0-device">
5259 <span id="soc-doc-j784s4-public-clks-epwm0"></span><h3>Clocks for EPWM0 Device<a class="headerlink" href="#clocks-for-epwm0-device" title="Permalink to this headline">¶</a></h3>
5260 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_EPWM0</span></a> (ID = 219)</p>
5261 <p>Following is a mapping of Clocks IDs to function:</p>
5262 <table border="1" class="docutils">
5263 <colgroup>
5264 <col width="26%" />
5265 <col width="46%" />
5266 <col width="28%" />
5267 </colgroup>
5268 <thead valign="bottom">
5269 <tr class="row-odd"><th class="head">Clock ID</th>
5270 <th class="head">Name</th>
5271 <th class="head">Function</th>
5272 </tr>
5273 </thead>
5274 <tbody valign="top">
5275 <tr class="row-even"><td>0</td>
5276 <td>DEV_EPWM0_VBUSP_CLK</td>
5277 <td>Input clock</td>
5278 </tr>
5279 </tbody>
5280 </table>
5281 </div>
5282 <div class="section" id="clocks-for-epwm1-device">
5283 <span id="soc-doc-j784s4-public-clks-epwm1"></span><h3>Clocks for EPWM1 Device<a class="headerlink" href="#clocks-for-epwm1-device" title="Permalink to this headline">¶</a></h3>
5284 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_EPWM1</span></a> (ID = 220)</p>
5285 <p>Following is a mapping of Clocks IDs to function:</p>
5286 <table border="1" class="docutils">
5287 <colgroup>
5288 <col width="26%" />
5289 <col width="46%" />
5290 <col width="28%" />
5291 </colgroup>
5292 <thead valign="bottom">
5293 <tr class="row-odd"><th class="head">Clock ID</th>
5294 <th class="head">Name</th>
5295 <th class="head">Function</th>
5296 </tr>
5297 </thead>
5298 <tbody valign="top">
5299 <tr class="row-even"><td>0</td>
5300 <td>DEV_EPWM1_VBUSP_CLK</td>
5301 <td>Input clock</td>
5302 </tr>
5303 </tbody>
5304 </table>
5305 </div>
5306 <div class="section" id="clocks-for-epwm2-device">
5307 <span id="soc-doc-j784s4-public-clks-epwm2"></span><h3>Clocks for EPWM2 Device<a class="headerlink" href="#clocks-for-epwm2-device" title="Permalink to this headline">¶</a></h3>
5308 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_EPWM2</span></a> (ID = 221)</p>
5309 <p>Following is a mapping of Clocks IDs to function:</p>
5310 <table border="1" class="docutils">
5311 <colgroup>
5312 <col width="26%" />
5313 <col width="46%" />
5314 <col width="28%" />
5315 </colgroup>
5316 <thead valign="bottom">
5317 <tr class="row-odd"><th class="head">Clock ID</th>
5318 <th class="head">Name</th>
5319 <th class="head">Function</th>
5320 </tr>
5321 </thead>
5322 <tbody valign="top">
5323 <tr class="row-even"><td>0</td>
5324 <td>DEV_EPWM2_VBUSP_CLK</td>
5325 <td>Input clock</td>
5326 </tr>
5327 </tbody>
5328 </table>
5329 </div>
5330 <div class="section" id="clocks-for-epwm3-device">
5331 <span id="soc-doc-j784s4-public-clks-epwm3"></span><h3>Clocks for EPWM3 Device<a class="headerlink" href="#clocks-for-epwm3-device" title="Permalink to this headline">¶</a></h3>
5332 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_EPWM3</span></a> (ID = 222)</p>
5333 <p>Following is a mapping of Clocks IDs to function:</p>
5334 <table border="1" class="docutils">
5335 <colgroup>
5336 <col width="26%" />
5337 <col width="46%" />
5338 <col width="28%" />
5339 </colgroup>
5340 <thead valign="bottom">
5341 <tr class="row-odd"><th class="head">Clock ID</th>
5342 <th class="head">Name</th>
5343 <th class="head">Function</th>
5344 </tr>
5345 </thead>
5346 <tbody valign="top">
5347 <tr class="row-even"><td>0</td>
5348 <td>DEV_EPWM3_VBUSP_CLK</td>
5349 <td>Input clock</td>
5350 </tr>
5351 </tbody>
5352 </table>
5353 </div>
5354 <div class="section" id="clocks-for-epwm4-device">
5355 <span id="soc-doc-j784s4-public-clks-epwm4"></span><h3>Clocks for EPWM4 Device<a class="headerlink" href="#clocks-for-epwm4-device" title="Permalink to this headline">¶</a></h3>
5356 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_EPWM4</span></a> (ID = 223)</p>
5357 <p>Following is a mapping of Clocks IDs to function:</p>
5358 <table border="1" class="docutils">
5359 <colgroup>
5360 <col width="26%" />
5361 <col width="46%" />
5362 <col width="28%" />
5363 </colgroup>
5364 <thead valign="bottom">
5365 <tr class="row-odd"><th class="head">Clock ID</th>
5366 <th class="head">Name</th>
5367 <th class="head">Function</th>
5368 </tr>
5369 </thead>
5370 <tbody valign="top">
5371 <tr class="row-even"><td>0</td>
5372 <td>DEV_EPWM4_VBUSP_CLK</td>
5373 <td>Input clock</td>
5374 </tr>
5375 </tbody>
5376 </table>
5377 </div>
5378 <div class="section" id="clocks-for-epwm5-device">
5379 <span id="soc-doc-j784s4-public-clks-epwm5"></span><h3>Clocks for EPWM5 Device<a class="headerlink" href="#clocks-for-epwm5-device" title="Permalink to this headline">¶</a></h3>
5380 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_EPWM5</span></a> (ID = 224)</p>
5381 <p>Following is a mapping of Clocks IDs to function:</p>
5382 <table border="1" class="docutils">
5383 <colgroup>
5384 <col width="26%" />
5385 <col width="46%" />
5386 <col width="28%" />
5387 </colgroup>
5388 <thead valign="bottom">
5389 <tr class="row-odd"><th class="head">Clock ID</th>
5390 <th class="head">Name</th>
5391 <th class="head">Function</th>
5392 </tr>
5393 </thead>
5394 <tbody valign="top">
5395 <tr class="row-even"><td>0</td>
5396 <td>DEV_EPWM5_VBUSP_CLK</td>
5397 <td>Input clock</td>
5398 </tr>
5399 </tbody>
5400 </table>
5401 </div>
5402 <div class="section" id="clocks-for-eqep0-device">
5403 <span id="soc-doc-j784s4-public-clks-eqep0"></span><h3>Clocks for EQEP0 Device<a class="headerlink" href="#clocks-for-eqep0-device" title="Permalink to this headline">¶</a></h3>
5404 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_EQEP0</span></a> (ID = 142)</p>
5405 <p>Following is a mapping of Clocks IDs to function:</p>
5406 <table border="1" class="docutils">
5407 <colgroup>
5408 <col width="27%" />
5409 <col width="44%" />
5410 <col width="29%" />
5411 </colgroup>
5412 <thead valign="bottom">
5413 <tr class="row-odd"><th class="head">Clock ID</th>
5414 <th class="head">Name</th>
5415 <th class="head">Function</th>
5416 </tr>
5417 </thead>
5418 <tbody valign="top">
5419 <tr class="row-even"><td>0</td>
5420 <td>DEV_EQEP0_VBUS_CLK</td>
5421 <td>Input clock</td>
5422 </tr>
5423 </tbody>
5424 </table>
5425 </div>
5426 <div class="section" id="clocks-for-eqep1-device">
5427 <span id="soc-doc-j784s4-public-clks-eqep1"></span><h3>Clocks for EQEP1 Device<a class="headerlink" href="#clocks-for-eqep1-device" title="Permalink to this headline">¶</a></h3>
5428 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_EQEP1</span></a> (ID = 143)</p>
5429 <p>Following is a mapping of Clocks IDs to function:</p>
5430 <table border="1" class="docutils">
5431 <colgroup>
5432 <col width="27%" />
5433 <col width="44%" />
5434 <col width="29%" />
5435 </colgroup>
5436 <thead valign="bottom">
5437 <tr class="row-odd"><th class="head">Clock ID</th>
5438 <th class="head">Name</th>
5439 <th class="head">Function</th>
5440 </tr>
5441 </thead>
5442 <tbody valign="top">
5443 <tr class="row-even"><td>0</td>
5444 <td>DEV_EQEP1_VBUS_CLK</td>
5445 <td>Input clock</td>
5446 </tr>
5447 </tbody>
5448 </table>
5449 </div>
5450 <div class="section" id="clocks-for-eqep2-device">
5451 <span id="soc-doc-j784s4-public-clks-eqep2"></span><h3>Clocks for EQEP2 Device<a class="headerlink" href="#clocks-for-eqep2-device" title="Permalink to this headline">¶</a></h3>
5452 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_EQEP2</span></a> (ID = 144)</p>
5453 <p>Following is a mapping of Clocks IDs to function:</p>
5454 <table border="1" class="docutils">
5455 <colgroup>
5456 <col width="27%" />
5457 <col width="44%" />
5458 <col width="29%" />
5459 </colgroup>
5460 <thead valign="bottom">
5461 <tr class="row-odd"><th class="head">Clock ID</th>
5462 <th class="head">Name</th>
5463 <th class="head">Function</th>
5464 </tr>
5465 </thead>
5466 <tbody valign="top">
5467 <tr class="row-even"><td>0</td>
5468 <td>DEV_EQEP2_VBUS_CLK</td>
5469 <td>Input clock</td>
5470 </tr>
5471 </tbody>
5472 </table>
5473 </div>
5474 <div class="section" id="clocks-for-esm0-device">
5475 <span id="soc-doc-j784s4-public-clks-esm0"></span><h3>Clocks for ESM0 Device<a class="headerlink" href="#clocks-for-esm0-device" title="Permalink to this headline">¶</a></h3>
5476 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_ESM0</span></a> (ID = 145)</p>
5477 <p>Following is a mapping of Clocks IDs to function:</p>
5478 <table border="1" class="docutils">
5479 <colgroup>
5480 <col width="31%" />
5481 <col width="36%" />
5482 <col width="33%" />
5483 </colgroup>
5484 <thead valign="bottom">
5485 <tr class="row-odd"><th class="head">Clock ID</th>
5486 <th class="head">Name</th>
5487 <th class="head">Function</th>
5488 </tr>
5489 </thead>
5490 <tbody valign="top">
5491 <tr class="row-even"><td>0</td>
5492 <td>DEV_ESM0_CLK</td>
5493 <td>Input clock</td>
5494 </tr>
5495 </tbody>
5496 </table>
5497 </div>
5498 <div class="section" id="clocks-for-ffi-main-ac-cbass-vd-device">
5499 <span id="soc-doc-j784s4-public-clks-ffi-main-ac-cbass-vd"></span><h3>Clocks for FFI_MAIN_AC_CBASS_VD Device<a class="headerlink" href="#clocks-for-ffi-main-ac-cbass-vd-device" title="Permalink to this headline">¶</a></h3>
5500 <p><strong>This device has no defined clocks.</strong></p>
5501 </div>
5502 <div class="section" id="clocks-for-ffi-main-ac-qm-cbass-vd-device">
5503 <span id="soc-doc-j784s4-public-clks-ffi-main-ac-qm-cbass-vd"></span><h3>Clocks for FFI_MAIN_AC_QM_CBASS_VD Device<a class="headerlink" href="#clocks-for-ffi-main-ac-qm-cbass-vd-device" title="Permalink to this headline">¶</a></h3>
5504 <p><strong>This device has no defined clocks.</strong></p>
5505 </div>
5506 <div class="section" id="clocks-for-ffi-main-hc-cbass-vd-device">
5507 <span id="soc-doc-j784s4-public-clks-ffi-main-hc-cbass-vd"></span><h3>Clocks for FFI_MAIN_HC_CBASS_VD Device<a class="headerlink" href="#clocks-for-ffi-main-hc-cbass-vd-device" title="Permalink to this headline">¶</a></h3>
5508 <p><strong>This device has no defined clocks.</strong></p>
5509 </div>
5510 <div class="section" id="clocks-for-ffi-main-infra-cbass-vd-device">
5511 <span id="soc-doc-j784s4-public-clks-ffi-main-infra-cbass-vd"></span><h3>Clocks for FFI_MAIN_INFRA_CBASS_VD Device<a class="headerlink" href="#clocks-for-ffi-main-infra-cbass-vd-device" title="Permalink to this headline">¶</a></h3>
5512 <p><strong>This device has no defined clocks.</strong></p>
5513 </div>
5514 <div class="section" id="clocks-for-ffi-main-ip-cbass-vd-device">
5515 <span id="soc-doc-j784s4-public-clks-ffi-main-ip-cbass-vd"></span><h3>Clocks for FFI_MAIN_IP_CBASS_VD Device<a class="headerlink" href="#clocks-for-ffi-main-ip-cbass-vd-device" title="Permalink to this headline">¶</a></h3>
5516 <p><strong>This device has no defined clocks.</strong></p>
5517 </div>
5518 <div class="section" id="clocks-for-ffi-main-rc-cbass-vd-device">
5519 <span id="soc-doc-j784s4-public-clks-ffi-main-rc-cbass-vd"></span><h3>Clocks for FFI_MAIN_RC_CBASS_VD Device<a class="headerlink" href="#clocks-for-ffi-main-rc-cbass-vd-device" title="Permalink to this headline">¶</a></h3>
5520 <p><strong>This device has no defined clocks.</strong></p>
5521 </div>
5522 <div class="section" id="clocks-for-gpio0-device">
5523 <span id="soc-doc-j784s4-public-clks-gpio0"></span><h3>Clocks for GPIO0 Device<a class="headerlink" href="#clocks-for-gpio0-device" title="Permalink to this headline">¶</a></h3>
5524 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_GPIO0</span></a> (ID = 163)</p>
5525 <p>Following is a mapping of Clocks IDs to function:</p>
5526 <table border="1" class="docutils">
5527 <colgroup>
5528 <col width="27%" />
5529 <col width="43%" />
5530 <col width="30%" />
5531 </colgroup>
5532 <thead valign="bottom">
5533 <tr class="row-odd"><th class="head">Clock ID</th>
5534 <th class="head">Name</th>
5535 <th class="head">Function</th>
5536 </tr>
5537 </thead>
5538 <tbody valign="top">
5539 <tr class="row-even"><td>0</td>
5540 <td>DEV_GPIO0_MMR_CLK</td>
5541 <td>Input clock</td>
5542 </tr>
5543 </tbody>
5544 </table>
5545 </div>
5546 <div class="section" id="clocks-for-gpio2-device">
5547 <span id="soc-doc-j784s4-public-clks-gpio2"></span><h3>Clocks for GPIO2 Device<a class="headerlink" href="#clocks-for-gpio2-device" title="Permalink to this headline">¶</a></h3>
5548 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_GPIO2</span></a> (ID = 164)</p>
5549 <p>Following is a mapping of Clocks IDs to function:</p>
5550 <table border="1" class="docutils">
5551 <colgroup>
5552 <col width="27%" />
5553 <col width="43%" />
5554 <col width="30%" />
5555 </colgroup>
5556 <thead valign="bottom">
5557 <tr class="row-odd"><th class="head">Clock ID</th>
5558 <th class="head">Name</th>
5559 <th class="head">Function</th>
5560 </tr>
5561 </thead>
5562 <tbody valign="top">
5563 <tr class="row-even"><td>0</td>
5564 <td>DEV_GPIO2_MMR_CLK</td>
5565 <td>Input clock</td>
5566 </tr>
5567 </tbody>
5568 </table>
5569 </div>
5570 <div class="section" id="clocks-for-gpio4-device">
5571 <span id="soc-doc-j784s4-public-clks-gpio4"></span><h3>Clocks for GPIO4 Device<a class="headerlink" href="#clocks-for-gpio4-device" title="Permalink to this headline">¶</a></h3>
5572 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_GPIO4</span></a> (ID = 165)</p>
5573 <p>Following is a mapping of Clocks IDs to function:</p>
5574 <table border="1" class="docutils">
5575 <colgroup>
5576 <col width="27%" />
5577 <col width="43%" />
5578 <col width="30%" />
5579 </colgroup>
5580 <thead valign="bottom">
5581 <tr class="row-odd"><th class="head">Clock ID</th>
5582 <th class="head">Name</th>
5583 <th class="head">Function</th>
5584 </tr>
5585 </thead>
5586 <tbody valign="top">
5587 <tr class="row-even"><td>0</td>
5588 <td>DEV_GPIO4_MMR_CLK</td>
5589 <td>Input clock</td>
5590 </tr>
5591 </tbody>
5592 </table>
5593 </div>
5594 <div class="section" id="clocks-for-gpio6-device">
5595 <span id="soc-doc-j784s4-public-clks-gpio6"></span><h3>Clocks for GPIO6 Device<a class="headerlink" href="#clocks-for-gpio6-device" title="Permalink to this headline">¶</a></h3>
5596 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_GPIO6</span></a> (ID = 166)</p>
5597 <p>Following is a mapping of Clocks IDs to function:</p>
5598 <table border="1" class="docutils">
5599 <colgroup>
5600 <col width="27%" />
5601 <col width="43%" />
5602 <col width="30%" />
5603 </colgroup>
5604 <thead valign="bottom">
5605 <tr class="row-odd"><th class="head">Clock ID</th>
5606 <th class="head">Name</th>
5607 <th class="head">Function</th>
5608 </tr>
5609 </thead>
5610 <tbody valign="top">
5611 <tr class="row-even"><td>0</td>
5612 <td>DEV_GPIO6_MMR_CLK</td>
5613 <td>Input clock</td>
5614 </tr>
5615 </tbody>
5616 </table>
5617 </div>
5618 <div class="section" id="clocks-for-gpiomux-intrtr0-device">
5619 <span id="soc-doc-j784s4-public-clks-gpiomux-intrtr0"></span><h3>Clocks for GPIOMUX_INTRTR0 Device<a class="headerlink" href="#clocks-for-gpiomux-intrtr0-device" title="Permalink to this headline">¶</a></h3>
5620 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_GPIOMUX_INTRTR0</span></a> (ID = 209)</p>
5621 <p>Following is a mapping of Clocks IDs to function:</p>
5622 <table border="1" class="docutils">
5623 <colgroup>
5624 <col width="22%" />
5625 <col width="55%" />
5626 <col width="24%" />
5627 </colgroup>
5628 <thead valign="bottom">
5629 <tr class="row-odd"><th class="head">Clock ID</th>
5630 <th class="head">Name</th>
5631 <th class="head">Function</th>
5632 </tr>
5633 </thead>
5634 <tbody valign="top">
5635 <tr class="row-even"><td>0</td>
5636 <td>DEV_GPIOMUX_INTRTR0_INTR_CLK</td>
5637 <td>Input clock</td>
5638 </tr>
5639 </tbody>
5640 </table>
5641 </div>
5642 <div class="section" id="clocks-for-gpmc0-device">
5643 <span id="soc-doc-j784s4-public-clks-gpmc0"></span><h3>Clocks for GPMC0 Device<a class="headerlink" href="#clocks-for-gpmc0-device" title="Permalink to this headline">¶</a></h3>
5644 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_GPMC0</span></a> (ID = 169)</p>
5645 <p>Following is a mapping of Clocks IDs to function:</p>
5646 <table border="1" class="docutils">
5647 <colgroup>
5648 <col width="9%" />
5649 <col width="53%" />
5650 <col width="37%" />
5651 </colgroup>
5652 <thead valign="bottom">
5653 <tr class="row-odd"><th class="head">Clock ID</th>
5654 <th class="head">Name</th>
5655 <th class="head">Function</th>
5656 </tr>
5657 </thead>
5658 <tbody valign="top">
5659 <tr class="row-even"><td>0</td>
5660 <td>DEV_GPMC0_FUNC_CLK</td>
5661 <td>Input muxed clock</td>
5662 </tr>
5663 <tr class="row-odd"><td>1</td>
5664 <td>DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK</td>
5665 <td>Parent input clock option to DEV_GPMC0_FUNC_CLK</td>
5666 </tr>
5667 <tr class="row-even"><td>2</td>
5668 <td>DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6</td>
5669 <td>Parent input clock option to DEV_GPMC0_FUNC_CLK</td>
5670 </tr>
5671 <tr class="row-odd"><td>3</td>
5672 <td>DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4</td>
5673 <td>Parent input clock option to DEV_GPMC0_FUNC_CLK</td>
5674 </tr>
5675 <tr class="row-even"><td>4</td>
5676 <td>DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4</td>
5677 <td>Parent input clock option to DEV_GPMC0_FUNC_CLK</td>
5678 </tr>
5679 <tr class="row-odd"><td>5</td>
5680 <td>DEV_GPMC0_PI_GPMC_RET_CLK</td>
5681 <td>Input clock</td>
5682 </tr>
5683 <tr class="row-even"><td>6</td>
5684 <td>DEV_GPMC0_PO_GPMC_DEV_CLK</td>
5685 <td>Output clock</td>
5686 </tr>
5687 <tr class="row-odd"><td>7</td>
5688 <td>DEV_GPMC0_VBUSM_CLK</td>
5689 <td>Input clock</td>
5690 </tr>
5691 </tbody>
5692 </table>
5693 </div>
5694 <div class="section" id="clocks-for-gtc0-device">
5695 <span id="soc-doc-j784s4-public-clks-gtc0"></span><h3>Clocks for GTC0 Device<a class="headerlink" href="#clocks-for-gtc0-device" title="Permalink to this headline">¶</a></h3>
5696 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_GTC0</span></a> (ID = 61)</p>
5697 <p>Following is a mapping of Clocks IDs to function:</p>
5698 <table border="1" class="docutils">
5699 <colgroup>
5700 <col width="10%" />
5701 <col width="53%" />
5702 <col width="37%" />
5703 </colgroup>
5704 <thead valign="bottom">
5705 <tr class="row-odd"><th class="head">Clock ID</th>
5706 <th class="head">Name</th>
5707 <th class="head">Function</th>
5708 </tr>
5709 </thead>
5710 <tbody valign="top">
5711 <tr class="row-even"><td>0</td>
5712 <td>DEV_GTC0_GTC_CLK</td>
5713 <td>Input muxed clock</td>
5714 </tr>
5715 <tr class="row-odd"><td>1</td>
5716 <td>DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
5717 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5718 </tr>
5719 <tr class="row-even"><td>2</td>
5720 <td>DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
5721 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5722 </tr>
5723 <tr class="row-odd"><td>3</td>
5724 <td>DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
5725 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5726 </tr>
5727 <tr class="row-even"><td>4</td>
5728 <td>DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
5729 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5730 </tr>
5731 <tr class="row-odd"><td>5</td>
5732 <td>DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
5733 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5734 </tr>
5735 <tr class="row-even"><td>6</td>
5736 <td>DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
5737 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5738 </tr>
5739 <tr class="row-odd"><td>7</td>
5740 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK</td>
5741 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5742 </tr>
5743 <tr class="row-even"><td>8</td>
5744 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK</td>
5745 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5746 </tr>
5747 <tr class="row-odd"><td>9</td>
5748 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK</td>
5749 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5750 </tr>
5751 <tr class="row-even"><td>10</td>
5752 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK</td>
5753 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5754 </tr>
5755 <tr class="row-odd"><td>11</td>
5756 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK</td>
5757 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5758 </tr>
5759 <tr class="row-even"><td>12</td>
5760 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK</td>
5761 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5762 </tr>
5763 <tr class="row-odd"><td>13</td>
5764 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK</td>
5765 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5766 </tr>
5767 <tr class="row-even"><td>14</td>
5768 <td>DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK</td>
5769 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5770 </tr>
5771 <tr class="row-odd"><td>15</td>
5772 <td>DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
5773 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5774 </tr>
5775 <tr class="row-even"><td>16</td>
5776 <td>DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
5777 <td>Parent input clock option to DEV_GTC0_GTC_CLK</td>
5778 </tr>
5779 <tr class="row-odd"><td>17</td>
5780 <td>DEV_GTC0_VBUSP_CLK</td>
5781 <td>Input clock</td>
5782 </tr>
5783 </tbody>
5784 </table>
5785 </div>
5786 <div class="section" id="clocks-for-i2c0-device">
5787 <span id="soc-doc-j784s4-public-clks-i2c0"></span><h3>Clocks for I2C0 Device<a class="headerlink" href="#clocks-for-i2c0-device" title="Permalink to this headline">¶</a></h3>
5788 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_I2C0</span></a> (ID = 270)</p>
5789 <p>Following is a mapping of Clocks IDs to function:</p>
5790 <table border="1" class="docutils">
5791 <colgroup>
5792 <col width="26%" />
5793 <col width="43%" />
5794 <col width="30%" />
5795 </colgroup>
5796 <thead valign="bottom">
5797 <tr class="row-odd"><th class="head">Clock ID</th>
5798 <th class="head">Name</th>
5799 <th class="head">Function</th>
5800 </tr>
5801 </thead>
5802 <tbody valign="top">
5803 <tr class="row-even"><td>0</td>
5804 <td>DEV_I2C0_CLK</td>
5805 <td>Input clock</td>
5806 </tr>
5807 <tr class="row-odd"><td>1</td>
5808 <td>DEV_I2C0_PISCL</td>
5809 <td>Input clock</td>
5810 </tr>
5811 <tr class="row-even"><td>2</td>
5812 <td>DEV_I2C0_PISYS_CLK</td>
5813 <td>Input clock</td>
5814 </tr>
5815 <tr class="row-odd"><td>3</td>
5816 <td>DEV_I2C0_PORSCL</td>
5817 <td>Output clock</td>
5818 </tr>
5819 </tbody>
5820 </table>
5821 </div>
5822 <div class="section" id="clocks-for-i2c1-device">
5823 <span id="soc-doc-j784s4-public-clks-i2c1"></span><h3>Clocks for I2C1 Device<a class="headerlink" href="#clocks-for-i2c1-device" title="Permalink to this headline">¶</a></h3>
5824 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_I2C1</span></a> (ID = 271)</p>
5825 <p>Following is a mapping of Clocks IDs to function:</p>
5826 <table border="1" class="docutils">
5827 <colgroup>
5828 <col width="26%" />
5829 <col width="43%" />
5830 <col width="30%" />
5831 </colgroup>
5832 <thead valign="bottom">
5833 <tr class="row-odd"><th class="head">Clock ID</th>
5834 <th class="head">Name</th>
5835 <th class="head">Function</th>
5836 </tr>
5837 </thead>
5838 <tbody valign="top">
5839 <tr class="row-even"><td>0</td>
5840 <td>DEV_I2C1_CLK</td>
5841 <td>Input clock</td>
5842 </tr>
5843 <tr class="row-odd"><td>1</td>
5844 <td>DEV_I2C1_PISCL</td>
5845 <td>Input clock</td>
5846 </tr>
5847 <tr class="row-even"><td>2</td>
5848 <td>DEV_I2C1_PISYS_CLK</td>
5849 <td>Input clock</td>
5850 </tr>
5851 <tr class="row-odd"><td>3</td>
5852 <td>DEV_I2C1_PORSCL</td>
5853 <td>Output clock</td>
5854 </tr>
5855 </tbody>
5856 </table>
5857 </div>
5858 <div class="section" id="clocks-for-i2c2-device">
5859 <span id="soc-doc-j784s4-public-clks-i2c2"></span><h3>Clocks for I2C2 Device<a class="headerlink" href="#clocks-for-i2c2-device" title="Permalink to this headline">¶</a></h3>
5860 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_I2C2</span></a> (ID = 272)</p>
5861 <p>Following is a mapping of Clocks IDs to function:</p>
5862 <table border="1" class="docutils">
5863 <colgroup>
5864 <col width="26%" />
5865 <col width="43%" />
5866 <col width="30%" />
5867 </colgroup>
5868 <thead valign="bottom">
5869 <tr class="row-odd"><th class="head">Clock ID</th>
5870 <th class="head">Name</th>
5871 <th class="head">Function</th>
5872 </tr>
5873 </thead>
5874 <tbody valign="top">
5875 <tr class="row-even"><td>0</td>
5876 <td>DEV_I2C2_CLK</td>
5877 <td>Input clock</td>
5878 </tr>
5879 <tr class="row-odd"><td>1</td>
5880 <td>DEV_I2C2_PISCL</td>
5881 <td>Input clock</td>
5882 </tr>
5883 <tr class="row-even"><td>2</td>
5884 <td>DEV_I2C2_PISYS_CLK</td>
5885 <td>Input clock</td>
5886 </tr>
5887 <tr class="row-odd"><td>3</td>
5888 <td>DEV_I2C2_PORSCL</td>
5889 <td>Output clock</td>
5890 </tr>
5891 </tbody>
5892 </table>
5893 </div>
5894 <div class="section" id="clocks-for-i2c3-device">
5895 <span id="soc-doc-j784s4-public-clks-i2c3"></span><h3>Clocks for I2C3 Device<a class="headerlink" href="#clocks-for-i2c3-device" title="Permalink to this headline">¶</a></h3>
5896 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_I2C3</span></a> (ID = 273)</p>
5897 <p>Following is a mapping of Clocks IDs to function:</p>
5898 <table border="1" class="docutils">
5899 <colgroup>
5900 <col width="26%" />
5901 <col width="43%" />
5902 <col width="30%" />
5903 </colgroup>
5904 <thead valign="bottom">
5905 <tr class="row-odd"><th class="head">Clock ID</th>
5906 <th class="head">Name</th>
5907 <th class="head">Function</th>
5908 </tr>
5909 </thead>
5910 <tbody valign="top">
5911 <tr class="row-even"><td>0</td>
5912 <td>DEV_I2C3_CLK</td>
5913 <td>Input clock</td>
5914 </tr>
5915 <tr class="row-odd"><td>1</td>
5916 <td>DEV_I2C3_PISCL</td>
5917 <td>Input clock</td>
5918 </tr>
5919 <tr class="row-even"><td>2</td>
5920 <td>DEV_I2C3_PISYS_CLK</td>
5921 <td>Input clock</td>
5922 </tr>
5923 <tr class="row-odd"><td>3</td>
5924 <td>DEV_I2C3_PORSCL</td>
5925 <td>Output clock</td>
5926 </tr>
5927 </tbody>
5928 </table>
5929 </div>
5930 <div class="section" id="clocks-for-i2c4-device">
5931 <span id="soc-doc-j784s4-public-clks-i2c4"></span><h3>Clocks for I2C4 Device<a class="headerlink" href="#clocks-for-i2c4-device" title="Permalink to this headline">¶</a></h3>
5932 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_I2C4</span></a> (ID = 274)</p>
5933 <p>Following is a mapping of Clocks IDs to function:</p>
5934 <table border="1" class="docutils">
5935 <colgroup>
5936 <col width="26%" />
5937 <col width="43%" />
5938 <col width="30%" />
5939 </colgroup>
5940 <thead valign="bottom">
5941 <tr class="row-odd"><th class="head">Clock ID</th>
5942 <th class="head">Name</th>
5943 <th class="head">Function</th>
5944 </tr>
5945 </thead>
5946 <tbody valign="top">
5947 <tr class="row-even"><td>0</td>
5948 <td>DEV_I2C4_CLK</td>
5949 <td>Input clock</td>
5950 </tr>
5951 <tr class="row-odd"><td>1</td>
5952 <td>DEV_I2C4_PISCL</td>
5953 <td>Input clock</td>
5954 </tr>
5955 <tr class="row-even"><td>2</td>
5956 <td>DEV_I2C4_PISYS_CLK</td>
5957 <td>Input clock</td>
5958 </tr>
5959 <tr class="row-odd"><td>3</td>
5960 <td>DEV_I2C4_PORSCL</td>
5961 <td>Output clock</td>
5962 </tr>
5963 </tbody>
5964 </table>
5965 </div>
5966 <div class="section" id="clocks-for-i2c5-device">
5967 <span id="soc-doc-j784s4-public-clks-i2c5"></span><h3>Clocks for I2C5 Device<a class="headerlink" href="#clocks-for-i2c5-device" title="Permalink to this headline">¶</a></h3>
5968 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_I2C5</span></a> (ID = 275)</p>
5969 <p>Following is a mapping of Clocks IDs to function:</p>
5970 <table border="1" class="docutils">
5971 <colgroup>
5972 <col width="26%" />
5973 <col width="43%" />
5974 <col width="30%" />
5975 </colgroup>
5976 <thead valign="bottom">
5977 <tr class="row-odd"><th class="head">Clock ID</th>
5978 <th class="head">Name</th>
5979 <th class="head">Function</th>
5980 </tr>
5981 </thead>
5982 <tbody valign="top">
5983 <tr class="row-even"><td>0</td>
5984 <td>DEV_I2C5_CLK</td>
5985 <td>Input clock</td>
5986 </tr>
5987 <tr class="row-odd"><td>1</td>
5988 <td>DEV_I2C5_PISCL</td>
5989 <td>Input clock</td>
5990 </tr>
5991 <tr class="row-even"><td>2</td>
5992 <td>DEV_I2C5_PISYS_CLK</td>
5993 <td>Input clock</td>
5994 </tr>
5995 <tr class="row-odd"><td>3</td>
5996 <td>DEV_I2C5_PORSCL</td>
5997 <td>Output clock</td>
5998 </tr>
5999 </tbody>
6000 </table>
6001 </div>
6002 <div class="section" id="clocks-for-i2c6-device">
6003 <span id="soc-doc-j784s4-public-clks-i2c6"></span><h3>Clocks for I2C6 Device<a class="headerlink" href="#clocks-for-i2c6-device" title="Permalink to this headline">¶</a></h3>
6004 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_I2C6</span></a> (ID = 276)</p>
6005 <p>Following is a mapping of Clocks IDs to function:</p>
6006 <table border="1" class="docutils">
6007 <colgroup>
6008 <col width="26%" />
6009 <col width="43%" />
6010 <col width="30%" />
6011 </colgroup>
6012 <thead valign="bottom">
6013 <tr class="row-odd"><th class="head">Clock ID</th>
6014 <th class="head">Name</th>
6015 <th class="head">Function</th>
6016 </tr>
6017 </thead>
6018 <tbody valign="top">
6019 <tr class="row-even"><td>0</td>
6020 <td>DEV_I2C6_CLK</td>
6021 <td>Input clock</td>
6022 </tr>
6023 <tr class="row-odd"><td>1</td>
6024 <td>DEV_I2C6_PISCL</td>
6025 <td>Input clock</td>
6026 </tr>
6027 <tr class="row-even"><td>2</td>
6028 <td>DEV_I2C6_PISYS_CLK</td>
6029 <td>Input clock</td>
6030 </tr>
6031 <tr class="row-odd"><td>3</td>
6032 <td>DEV_I2C6_PORSCL</td>
6033 <td>Output clock</td>
6034 </tr>
6035 </tbody>
6036 </table>
6037 </div>
6038 <div class="section" id="clocks-for-j7aep-gpu-bxs464-wrap0-device">
6039 <span id="soc-doc-j784s4-public-clks-j7aep-gpu-bxs464-wrap0"></span><h3>Clocks for J7AEP_GPU_BXS464_WRAP0 Device<a class="headerlink" href="#clocks-for-j7aep-gpu-bxs464-wrap0-device" title="Permalink to this headline">¶</a></h3>
6040 <p><strong>This device has no defined clocks.</strong></p>
6041 </div>
6042 <div class="section" id="clocks-for-j7aep-gpu-bxs464-wrap0-dft-embed-pbist-0-device">
6043 <span id="soc-doc-j784s4-public-clks-j7aep-gpu-bxs464-wrap0-dft-embed-pbist-0"></span><h3>Clocks for J7AEP_GPU_BXS464_WRAP0_DFT_EMBED_PBIST_0 Device<a class="headerlink" href="#clocks-for-j7aep-gpu-bxs464-wrap0-dft-embed-pbist-0-device" title="Permalink to this headline">¶</a></h3>
6044 <p><strong>This device has no defined clocks.</strong></p>
6045 </div>
6046 <div class="section" id="clocks-for-j7aep-gpu-bxs464-wrap0-gpucore-0-device">
6047 <span id="soc-doc-j784s4-public-clks-j7aep-gpu-bxs464-wrap0-gpucore-0"></span><h3>Clocks for J7AEP_GPU_BXS464_WRAP0_GPUCORE_0 Device<a class="headerlink" href="#clocks-for-j7aep-gpu-bxs464-wrap0-gpucore-0-device" title="Permalink to this headline">¶</a></h3>
6048 <p><strong>This device has no defined clocks.</strong></p>
6049 </div>
6050 <div class="section" id="clocks-for-j7aep-gpu-bxs464-wrap0-gpu-ss-0-device">
6051 <span id="soc-doc-j784s4-public-clks-j7aep-gpu-bxs464-wrap0-gpu-ss-0"></span><h3>Clocks for J7AEP_GPU_BXS464_WRAP0_GPU_SS_0 Device<a class="headerlink" href="#clocks-for-j7aep-gpu-bxs464-wrap0-gpu-ss-0-device" title="Permalink to this headline">¶</a></h3>
6052 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0</span></a> (ID = 181)</p>
6053 <p>Following is a mapping of Clocks IDs to function:</p>
6054 <table border="1" class="docutils">
6055 <colgroup>
6056 <col width="16%" />
6057 <col width="67%" />
6058 <col width="17%" />
6059 </colgroup>
6060 <thead valign="bottom">
6061 <tr class="row-odd"><th class="head">Clock ID</th>
6062 <th class="head">Name</th>
6063 <th class="head">Function</th>
6064 </tr>
6065 </thead>
6066 <tbody valign="top">
6067 <tr class="row-even"><td>1</td>
6068 <td>DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_GPU_PLL_CLK</td>
6069 <td>Input clock</td>
6070 </tr>
6071 <tr class="row-odd"><td>4</td>
6072 <td>DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_PLL_CTRL_CLK</td>
6073 <td>Input clock</td>
6074 </tr>
6075 </tbody>
6076 </table>
6077 </div>
6078 <div class="section" id="clocks-for-j7am-32-64-atb-funnel0-device">
6079 <span id="soc-doc-j784s4-public-clks-j7am-32-64-atb-funnel0"></span><h3>Clocks for J7AM_32_64_ATB_FUNNEL0 Device<a class="headerlink" href="#clocks-for-j7am-32-64-atb-funnel0-device" title="Permalink to this headline">¶</a></h3>
6080 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_J7AM_32_64_ATB_FUNNEL0</span></a> (ID = 183)</p>
6081 <p>Following is a mapping of Clocks IDs to function:</p>
6082 <table border="1" class="docutils">
6083 <colgroup>
6084 <col width="20%" />
6085 <col width="59%" />
6086 <col width="21%" />
6087 </colgroup>
6088 <thead valign="bottom">
6089 <tr class="row-odd"><th class="head">Clock ID</th>
6090 <th class="head">Name</th>
6091 <th class="head">Function</th>
6092 </tr>
6093 </thead>
6094 <tbody valign="top">
6095 <tr class="row-even"><td>0</td>
6096 <td>DEV_J7AM_32_64_ATB_FUNNEL0_DBG_CLK</td>
6097 <td>Input clock</td>
6098 </tr>
6099 </tbody>
6100 </table>
6101 </div>
6102 <div class="section" id="clocks-for-j7am-32-64-atb-funnel1-device">
6103 <span id="soc-doc-j784s4-public-clks-j7am-32-64-atb-funnel1"></span><h3>Clocks for J7AM_32_64_ATB_FUNNEL1 Device<a class="headerlink" href="#clocks-for-j7am-32-64-atb-funnel1-device" title="Permalink to this headline">¶</a></h3>
6104 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_J7AM_32_64_ATB_FUNNEL1</span></a> (ID = 184)</p>
6105 <p>Following is a mapping of Clocks IDs to function:</p>
6106 <table border="1" class="docutils">
6107 <colgroup>
6108 <col width="20%" />
6109 <col width="59%" />
6110 <col width="21%" />
6111 </colgroup>
6112 <thead valign="bottom">
6113 <tr class="row-odd"><th class="head">Clock ID</th>
6114 <th class="head">Name</th>
6115 <th class="head">Function</th>
6116 </tr>
6117 </thead>
6118 <tbody valign="top">
6119 <tr class="row-even"><td>0</td>
6120 <td>DEV_J7AM_32_64_ATB_FUNNEL1_DBG_CLK</td>
6121 <td>Input clock</td>
6122 </tr>
6123 </tbody>
6124 </table>
6125 </div>
6126 <div class="section" id="clocks-for-j7am-32-64-atb-funnel2-device">
6127 <span id="soc-doc-j784s4-public-clks-j7am-32-64-atb-funnel2"></span><h3>Clocks for J7AM_32_64_ATB_FUNNEL2 Device<a class="headerlink" href="#clocks-for-j7am-32-64-atb-funnel2-device" title="Permalink to this headline">¶</a></h3>
6128 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_J7AM_32_64_ATB_FUNNEL2</span></a> (ID = 185)</p>
6129 <p>Following is a mapping of Clocks IDs to function:</p>
6130 <table border="1" class="docutils">
6131 <colgroup>
6132 <col width="20%" />
6133 <col width="59%" />
6134 <col width="21%" />
6135 </colgroup>
6136 <thead valign="bottom">
6137 <tr class="row-odd"><th class="head">Clock ID</th>
6138 <th class="head">Name</th>
6139 <th class="head">Function</th>
6140 </tr>
6141 </thead>
6142 <tbody valign="top">
6143 <tr class="row-even"><td>0</td>
6144 <td>DEV_J7AM_32_64_ATB_FUNNEL2_DBG_CLK</td>
6145 <td>Input clock</td>
6146 </tr>
6147 </tbody>
6148 </table>
6149 </div>
6150 <div class="section" id="clocks-for-j7am-bolt-pgd0-device">
6151 <span id="soc-doc-j784s4-public-clks-j7am-bolt-pgd0"></span><h3>Clocks for J7AM_BOLT_PGD0 Device<a class="headerlink" href="#clocks-for-j7am-bolt-pgd0-device" title="Permalink to this headline">¶</a></h3>
6152 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_J7AM_BOLT_PGD0</span></a> (ID = 187)</p>
6153 <p>Following is a mapping of Clocks IDs to function:</p>
6154 <table border="1" class="docutils">
6155 <colgroup>
6156 <col width="20%" />
6157 <col width="58%" />
6158 <col width="22%" />
6159 </colgroup>
6160 <thead valign="bottom">
6161 <tr class="row-odd"><th class="head">Clock ID</th>
6162 <th class="head">Name</th>
6163 <th class="head">Function</th>
6164 </tr>
6165 </thead>
6166 <tbody valign="top">
6167 <tr class="row-even"><td>0</td>
6168 <td>DEV_J7AM_BOLT_PGD0_WKUP_OSC0_CLK</td>
6169 <td>Input clock</td>
6170 </tr>
6171 </tbody>
6172 </table>
6173 </div>
6174 <div class="section" id="clocks-for-j7am-bolt-psc-wrap0-device">
6175 <span id="soc-doc-j784s4-public-clks-j7am-bolt-psc-wrap0"></span><h3>Clocks for J7AM_BOLT_PSC_WRAP0 Device<a class="headerlink" href="#clocks-for-j7am-bolt-psc-wrap0-device" title="Permalink to this headline">¶</a></h3>
6176 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_J7AM_BOLT_PSC_WRAP0</span></a> (ID = 188)</p>
6177 <p>Following is a mapping of Clocks IDs to function:</p>
6178 <table border="1" class="docutils">
6179 <colgroup>
6180 <col width="20%" />
6181 <col width="58%" />
6182 <col width="22%" />
6183 </colgroup>
6184 <thead valign="bottom">
6185 <tr class="row-odd"><th class="head">Clock ID</th>
6186 <th class="head">Name</th>
6187 <th class="head">Function</th>
6188 </tr>
6189 </thead>
6190 <tbody valign="top">
6191 <tr class="row-even"><td>0</td>
6192 <td>DEV_J7AM_BOLT_PSC_WRAP0_CLK</td>
6193 <td>Input clock</td>
6194 </tr>
6195 <tr class="row-odd"><td>1</td>
6196 <td>DEV_J7AM_BOLT_PSC_WRAP0_SLOW_CLK</td>
6197 <td>Input clock</td>
6198 </tr>
6199 </tbody>
6200 </table>
6201 </div>
6202 <div class="section" id="clocks-for-j7am-hwa-atb-funnel0-device">
6203 <span id="soc-doc-j784s4-public-clks-j7am-hwa-atb-funnel0"></span><h3>Clocks for J7AM_HWA_ATB_FUNNEL0 Device<a class="headerlink" href="#clocks-for-j7am-hwa-atb-funnel0-device" title="Permalink to this headline">¶</a></h3>
6204 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_J7AM_HWA_ATB_FUNNEL0</span></a> (ID = 197)</p>
6205 <p>Following is a mapping of Clocks IDs to function:</p>
6206 <table border="1" class="docutils">
6207 <colgroup>
6208 <col width="20%" />
6209 <col width="58%" />
6210 <col width="22%" />
6211 </colgroup>
6212 <thead valign="bottom">
6213 <tr class="row-odd"><th class="head">Clock ID</th>
6214 <th class="head">Name</th>
6215 <th class="head">Function</th>
6216 </tr>
6217 </thead>
6218 <tbody valign="top">
6219 <tr class="row-even"><td>0</td>
6220 <td>DEV_J7AM_HWA_ATB_FUNNEL0_DBG_CLK</td>
6221 <td>Input clock</td>
6222 </tr>
6223 </tbody>
6224 </table>
6225 </div>
6226 <div class="section" id="clocks-for-j7am-main-16ff0-device">
6227 <span id="soc-doc-j784s4-public-clks-j7am-main-16ff0"></span><h3>Clocks for J7AM_MAIN_16FF0 Device<a class="headerlink" href="#clocks-for-j7am-main-16ff0-device" title="Permalink to this headline">¶</a></h3>
6228 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_J7AM_MAIN_16FF0</span></a> (ID = 199)</p>
6229 <p>Following is a mapping of Clocks IDs to function:</p>
6230 <table border="1" class="docutils">
6231 <colgroup>
6232 <col width="20%" />
6233 <col width="58%" />
6234 <col width="22%" />
6235 </colgroup>
6236 <thead valign="bottom">
6237 <tr class="row-odd"><th class="head">Clock ID</th>
6238 <th class="head">Name</th>
6239 <th class="head">Function</th>
6240 </tr>
6241 </thead>
6242 <tbody valign="top">
6243 <tr class="row-even"><td>0</td>
6244 <td>DEV_J7AM_MAIN_16FF0_WKUP_OSC0_CLK</td>
6245 <td>Input clock</td>
6246 </tr>
6247 </tbody>
6248 </table>
6249 </div>
6250 <div class="section" id="clocks-for-j7am-pulsar-atb-funnel0-device">
6251 <span id="soc-doc-j784s4-public-clks-j7am-pulsar-atb-funnel0"></span><h3>Clocks for J7AM_PULSAR_ATB_FUNNEL0 Device<a class="headerlink" href="#clocks-for-j7am-pulsar-atb-funnel0-device" title="Permalink to this headline">¶</a></h3>
6252 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_J7AM_PULSAR_ATB_FUNNEL0</span></a> (ID = 206)</p>
6253 <p>Following is a mapping of Clocks IDs to function:</p>
6254 <table border="1" class="docutils">
6255 <colgroup>
6256 <col width="19%" />
6257 <col width="60%" />
6258 <col width="21%" />
6259 </colgroup>
6260 <thead valign="bottom">
6261 <tr class="row-odd"><th class="head">Clock ID</th>
6262 <th class="head">Name</th>
6263 <th class="head">Function</th>
6264 </tr>
6265 </thead>
6266 <tbody valign="top">
6267 <tr class="row-even"><td>0</td>
6268 <td>DEV_J7AM_PULSAR_ATB_FUNNEL0_DBG_CLK</td>
6269 <td>Input clock</td>
6270 </tr>
6271 </tbody>
6272 </table>
6273 </div>
6274 <div class="section" id="clocks-for-led0-device">
6275 <span id="soc-doc-j784s4-public-clks-led0"></span><h3>Clocks for LED0 Device<a class="headerlink" href="#clocks-for-led0-device" title="Permalink to this headline">¶</a></h3>
6276 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_LED0</span></a> (ID = 172)</p>
6277 <p>Following is a mapping of Clocks IDs to function:</p>
6278 <table border="1" class="docutils">
6279 <colgroup>
6280 <col width="27%" />
6281 <col width="43%" />
6282 <col width="30%" />
6283 </colgroup>
6284 <thead valign="bottom">
6285 <tr class="row-odd"><th class="head">Clock ID</th>
6286 <th class="head">Name</th>
6287 <th class="head">Function</th>
6288 </tr>
6289 </thead>
6290 <tbody valign="top">
6291 <tr class="row-even"><td>0</td>
6292 <td>DEV_LED0_LED_CLK</td>
6293 <td>Input clock</td>
6294 </tr>
6295 <tr class="row-odd"><td>1</td>
6296 <td>DEV_LED0_VBUS_CLK</td>
6297 <td>Input clock</td>
6298 </tr>
6299 </tbody>
6300 </table>
6301 </div>
6302 <div class="section" id="clocks-for-main2mcu-lvl-intrtr0-device">
6303 <span id="soc-doc-j784s4-public-clks-main2mcu-lvl-intrtr0"></span><h3>Clocks for MAIN2MCU_LVL_INTRTR0 Device<a class="headerlink" href="#clocks-for-main2mcu-lvl-intrtr0-device" title="Permalink to this headline">¶</a></h3>
6304 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MAIN2MCU_LVL_INTRTR0</span></a> (ID = 173)</p>
6305 <p>Following is a mapping of Clocks IDs to function:</p>
6306 <table border="1" class="docutils">
6307 <colgroup>
6308 <col width="20%" />
6309 <col width="58%" />
6310 <col width="22%" />
6311 </colgroup>
6312 <thead valign="bottom">
6313 <tr class="row-odd"><th class="head">Clock ID</th>
6314 <th class="head">Name</th>
6315 <th class="head">Function</th>
6316 </tr>
6317 </thead>
6318 <tbody valign="top">
6319 <tr class="row-even"><td>0</td>
6320 <td>DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK</td>
6321 <td>Input clock</td>
6322 </tr>
6323 </tbody>
6324 </table>
6325 </div>
6326 <div class="section" id="clocks-for-main2mcu-pls-intrtr0-device">
6327 <span id="soc-doc-j784s4-public-clks-main2mcu-pls-intrtr0"></span><h3>Clocks for MAIN2MCU_PLS_INTRTR0 Device<a class="headerlink" href="#clocks-for-main2mcu-pls-intrtr0-device" title="Permalink to this headline">¶</a></h3>
6328 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MAIN2MCU_PLS_INTRTR0</span></a> (ID = 174)</p>
6329 <p>Following is a mapping of Clocks IDs to function:</p>
6330 <table border="1" class="docutils">
6331 <colgroup>
6332 <col width="20%" />
6333 <col width="58%" />
6334 <col width="22%" />
6335 </colgroup>
6336 <thead valign="bottom">
6337 <tr class="row-odd"><th class="head">Clock ID</th>
6338 <th class="head">Name</th>
6339 <th class="head">Function</th>
6340 </tr>
6341 </thead>
6342 <tbody valign="top">
6343 <tr class="row-even"><td>0</td>
6344 <td>DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK</td>
6345 <td>Input clock</td>
6346 </tr>
6347 </tbody>
6348 </table>
6349 </div>
6350 <div class="section" id="clocks-for-main2wkupmcu-vd-device">
6351 <span id="soc-doc-j784s4-public-clks-main2wkupmcu-vd"></span><h3>Clocks for MAIN2WKUPMCU_VD Device<a class="headerlink" href="#clocks-for-main2wkupmcu-vd-device" title="Permalink to this headline">¶</a></h3>
6352 <p><strong>This device has no defined clocks.</strong></p>
6353 </div>
6354 <div class="section" id="clocks-for-mcan0-device">
6355 <span id="soc-doc-j784s4-public-clks-mcan0"></span><h3>Clocks for MCAN0 Device<a class="headerlink" href="#clocks-for-mcan0-device" title="Permalink to this headline">¶</a></h3>
6356 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN0</span></a> (ID = 245)</p>
6357 <p>Following is a mapping of Clocks IDs to function:</p>
6358 <table border="1" class="docutils">
6359 <colgroup>
6360 <col width="9%" />
6361 <col width="50%" />
6362 <col width="41%" />
6363 </colgroup>
6364 <thead valign="bottom">
6365 <tr class="row-odd"><th class="head">Clock ID</th>
6366 <th class="head">Name</th>
6367 <th class="head">Function</th>
6368 </tr>
6369 </thead>
6370 <tbody valign="top">
6371 <tr class="row-even"><td>0</td>
6372 <td>DEV_MCAN0_MCANSS_CAN_RXD</td>
6373 <td>Input clock</td>
6374 </tr>
6375 <tr class="row-odd"><td>1</td>
6376 <td>DEV_MCAN0_MCANSS_CCLK_CLK</td>
6377 <td>Input muxed clock</td>
6378 </tr>
6379 <tr class="row-even"><td>2</td>
6380 <td>DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6381 <td>Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK</td>
6382 </tr>
6383 <tr class="row-odd"><td>3</td>
6384 <td>DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6385 <td>Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK</td>
6386 </tr>
6387 <tr class="row-even"><td>4</td>
6388 <td>DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6389 <td>Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK</td>
6390 </tr>
6391 <tr class="row-odd"><td>5</td>
6392 <td>DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6393 <td>Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK</td>
6394 </tr>
6395 <tr class="row-even"><td>6</td>
6396 <td>DEV_MCAN0_MCANSS_HCLK_CLK</td>
6397 <td>Input clock</td>
6398 </tr>
6399 </tbody>
6400 </table>
6401 </div>
6402 <div class="section" id="clocks-for-mcan1-device">
6403 <span id="soc-doc-j784s4-public-clks-mcan1"></span><h3>Clocks for MCAN1 Device<a class="headerlink" href="#clocks-for-mcan1-device" title="Permalink to this headline">¶</a></h3>
6404 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN1</span></a> (ID = 246)</p>
6405 <p>Following is a mapping of Clocks IDs to function:</p>
6406 <table border="1" class="docutils">
6407 <colgroup>
6408 <col width="9%" />
6409 <col width="50%" />
6410 <col width="41%" />
6411 </colgroup>
6412 <thead valign="bottom">
6413 <tr class="row-odd"><th class="head">Clock ID</th>
6414 <th class="head">Name</th>
6415 <th class="head">Function</th>
6416 </tr>
6417 </thead>
6418 <tbody valign="top">
6419 <tr class="row-even"><td>0</td>
6420 <td>DEV_MCAN1_MCANSS_CAN_RXD</td>
6421 <td>Input clock</td>
6422 </tr>
6423 <tr class="row-odd"><td>1</td>
6424 <td>DEV_MCAN1_MCANSS_CCLK_CLK</td>
6425 <td>Input muxed clock</td>
6426 </tr>
6427 <tr class="row-even"><td>2</td>
6428 <td>DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6429 <td>Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK</td>
6430 </tr>
6431 <tr class="row-odd"><td>3</td>
6432 <td>DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6433 <td>Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK</td>
6434 </tr>
6435 <tr class="row-even"><td>4</td>
6436 <td>DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6437 <td>Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK</td>
6438 </tr>
6439 <tr class="row-odd"><td>5</td>
6440 <td>DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6441 <td>Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK</td>
6442 </tr>
6443 <tr class="row-even"><td>6</td>
6444 <td>DEV_MCAN1_MCANSS_HCLK_CLK</td>
6445 <td>Input clock</td>
6446 </tr>
6447 </tbody>
6448 </table>
6449 </div>
6450 <div class="section" id="clocks-for-mcan10-device">
6451 <span id="soc-doc-j784s4-public-clks-mcan10"></span><h3>Clocks for MCAN10 Device<a class="headerlink" href="#clocks-for-mcan10-device" title="Permalink to this headline">¶</a></h3>
6452 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN10</span></a> (ID = 255)</p>
6453 <p>Following is a mapping of Clocks IDs to function:</p>
6454 <table border="1" class="docutils">
6455 <colgroup>
6456 <col width="9%" />
6457 <col width="50%" />
6458 <col width="41%" />
6459 </colgroup>
6460 <thead valign="bottom">
6461 <tr class="row-odd"><th class="head">Clock ID</th>
6462 <th class="head">Name</th>
6463 <th class="head">Function</th>
6464 </tr>
6465 </thead>
6466 <tbody valign="top">
6467 <tr class="row-even"><td>0</td>
6468 <td>DEV_MCAN10_MCANSS_CAN_RXD</td>
6469 <td>Input clock</td>
6470 </tr>
6471 <tr class="row-odd"><td>1</td>
6472 <td>DEV_MCAN10_MCANSS_CCLK_CLK</td>
6473 <td>Input muxed clock</td>
6474 </tr>
6475 <tr class="row-even"><td>2</td>
6476 <td>DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6477 <td>Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK</td>
6478 </tr>
6479 <tr class="row-odd"><td>3</td>
6480 <td>DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6481 <td>Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK</td>
6482 </tr>
6483 <tr class="row-even"><td>4</td>
6484 <td>DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6485 <td>Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK</td>
6486 </tr>
6487 <tr class="row-odd"><td>5</td>
6488 <td>DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6489 <td>Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK</td>
6490 </tr>
6491 <tr class="row-even"><td>6</td>
6492 <td>DEV_MCAN10_MCANSS_HCLK_CLK</td>
6493 <td>Input clock</td>
6494 </tr>
6495 </tbody>
6496 </table>
6497 </div>
6498 <div class="section" id="clocks-for-mcan11-device">
6499 <span id="soc-doc-j784s4-public-clks-mcan11"></span><h3>Clocks for MCAN11 Device<a class="headerlink" href="#clocks-for-mcan11-device" title="Permalink to this headline">¶</a></h3>
6500 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN11</span></a> (ID = 256)</p>
6501 <p>Following is a mapping of Clocks IDs to function:</p>
6502 <table border="1" class="docutils">
6503 <colgroup>
6504 <col width="9%" />
6505 <col width="50%" />
6506 <col width="41%" />
6507 </colgroup>
6508 <thead valign="bottom">
6509 <tr class="row-odd"><th class="head">Clock ID</th>
6510 <th class="head">Name</th>
6511 <th class="head">Function</th>
6512 </tr>
6513 </thead>
6514 <tbody valign="top">
6515 <tr class="row-even"><td>0</td>
6516 <td>DEV_MCAN11_MCANSS_CAN_RXD</td>
6517 <td>Input clock</td>
6518 </tr>
6519 <tr class="row-odd"><td>1</td>
6520 <td>DEV_MCAN11_MCANSS_CCLK_CLK</td>
6521 <td>Input muxed clock</td>
6522 </tr>
6523 <tr class="row-even"><td>2</td>
6524 <td>DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6525 <td>Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK</td>
6526 </tr>
6527 <tr class="row-odd"><td>3</td>
6528 <td>DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6529 <td>Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK</td>
6530 </tr>
6531 <tr class="row-even"><td>4</td>
6532 <td>DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6533 <td>Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK</td>
6534 </tr>
6535 <tr class="row-odd"><td>5</td>
6536 <td>DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6537 <td>Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK</td>
6538 </tr>
6539 <tr class="row-even"><td>6</td>
6540 <td>DEV_MCAN11_MCANSS_HCLK_CLK</td>
6541 <td>Input clock</td>
6542 </tr>
6543 </tbody>
6544 </table>
6545 </div>
6546 <div class="section" id="clocks-for-mcan12-device">
6547 <span id="soc-doc-j784s4-public-clks-mcan12"></span><h3>Clocks for MCAN12 Device<a class="headerlink" href="#clocks-for-mcan12-device" title="Permalink to this headline">¶</a></h3>
6548 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN12</span></a> (ID = 257)</p>
6549 <p>Following is a mapping of Clocks IDs to function:</p>
6550 <table border="1" class="docutils">
6551 <colgroup>
6552 <col width="9%" />
6553 <col width="50%" />
6554 <col width="41%" />
6555 </colgroup>
6556 <thead valign="bottom">
6557 <tr class="row-odd"><th class="head">Clock ID</th>
6558 <th class="head">Name</th>
6559 <th class="head">Function</th>
6560 </tr>
6561 </thead>
6562 <tbody valign="top">
6563 <tr class="row-even"><td>0</td>
6564 <td>DEV_MCAN12_MCANSS_CAN_RXD</td>
6565 <td>Input clock</td>
6566 </tr>
6567 <tr class="row-odd"><td>1</td>
6568 <td>DEV_MCAN12_MCANSS_CCLK_CLK</td>
6569 <td>Input muxed clock</td>
6570 </tr>
6571 <tr class="row-even"><td>2</td>
6572 <td>DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6573 <td>Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK</td>
6574 </tr>
6575 <tr class="row-odd"><td>3</td>
6576 <td>DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6577 <td>Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK</td>
6578 </tr>
6579 <tr class="row-even"><td>4</td>
6580 <td>DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6581 <td>Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK</td>
6582 </tr>
6583 <tr class="row-odd"><td>5</td>
6584 <td>DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6585 <td>Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK</td>
6586 </tr>
6587 <tr class="row-even"><td>6</td>
6588 <td>DEV_MCAN12_MCANSS_HCLK_CLK</td>
6589 <td>Input clock</td>
6590 </tr>
6591 </tbody>
6592 </table>
6593 </div>
6594 <div class="section" id="clocks-for-mcan13-device">
6595 <span id="soc-doc-j784s4-public-clks-mcan13"></span><h3>Clocks for MCAN13 Device<a class="headerlink" href="#clocks-for-mcan13-device" title="Permalink to this headline">¶</a></h3>
6596 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN13</span></a> (ID = 258)</p>
6597 <p>Following is a mapping of Clocks IDs to function:</p>
6598 <table border="1" class="docutils">
6599 <colgroup>
6600 <col width="9%" />
6601 <col width="50%" />
6602 <col width="41%" />
6603 </colgroup>
6604 <thead valign="bottom">
6605 <tr class="row-odd"><th class="head">Clock ID</th>
6606 <th class="head">Name</th>
6607 <th class="head">Function</th>
6608 </tr>
6609 </thead>
6610 <tbody valign="top">
6611 <tr class="row-even"><td>0</td>
6612 <td>DEV_MCAN13_MCANSS_CAN_RXD</td>
6613 <td>Input clock</td>
6614 </tr>
6615 <tr class="row-odd"><td>1</td>
6616 <td>DEV_MCAN13_MCANSS_CCLK_CLK</td>
6617 <td>Input muxed clock</td>
6618 </tr>
6619 <tr class="row-even"><td>2</td>
6620 <td>DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6621 <td>Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK</td>
6622 </tr>
6623 <tr class="row-odd"><td>3</td>
6624 <td>DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6625 <td>Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK</td>
6626 </tr>
6627 <tr class="row-even"><td>4</td>
6628 <td>DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6629 <td>Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK</td>
6630 </tr>
6631 <tr class="row-odd"><td>5</td>
6632 <td>DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6633 <td>Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK</td>
6634 </tr>
6635 <tr class="row-even"><td>6</td>
6636 <td>DEV_MCAN13_MCANSS_HCLK_CLK</td>
6637 <td>Input clock</td>
6638 </tr>
6639 </tbody>
6640 </table>
6641 </div>
6642 <div class="section" id="clocks-for-mcan14-device">
6643 <span id="soc-doc-j784s4-public-clks-mcan14"></span><h3>Clocks for MCAN14 Device<a class="headerlink" href="#clocks-for-mcan14-device" title="Permalink to this headline">¶</a></h3>
6644 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN14</span></a> (ID = 259)</p>
6645 <p>Following is a mapping of Clocks IDs to function:</p>
6646 <table border="1" class="docutils">
6647 <colgroup>
6648 <col width="9%" />
6649 <col width="50%" />
6650 <col width="41%" />
6651 </colgroup>
6652 <thead valign="bottom">
6653 <tr class="row-odd"><th class="head">Clock ID</th>
6654 <th class="head">Name</th>
6655 <th class="head">Function</th>
6656 </tr>
6657 </thead>
6658 <tbody valign="top">
6659 <tr class="row-even"><td>0</td>
6660 <td>DEV_MCAN14_MCANSS_CAN_RXD</td>
6661 <td>Input clock</td>
6662 </tr>
6663 <tr class="row-odd"><td>1</td>
6664 <td>DEV_MCAN14_MCANSS_CCLK_CLK</td>
6665 <td>Input muxed clock</td>
6666 </tr>
6667 <tr class="row-even"><td>2</td>
6668 <td>DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6669 <td>Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK</td>
6670 </tr>
6671 <tr class="row-odd"><td>3</td>
6672 <td>DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6673 <td>Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK</td>
6674 </tr>
6675 <tr class="row-even"><td>4</td>
6676 <td>DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6677 <td>Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK</td>
6678 </tr>
6679 <tr class="row-odd"><td>5</td>
6680 <td>DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6681 <td>Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK</td>
6682 </tr>
6683 <tr class="row-even"><td>6</td>
6684 <td>DEV_MCAN14_MCANSS_HCLK_CLK</td>
6685 <td>Input clock</td>
6686 </tr>
6687 </tbody>
6688 </table>
6689 </div>
6690 <div class="section" id="clocks-for-mcan15-device">
6691 <span id="soc-doc-j784s4-public-clks-mcan15"></span><h3>Clocks for MCAN15 Device<a class="headerlink" href="#clocks-for-mcan15-device" title="Permalink to this headline">¶</a></h3>
6692 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN15</span></a> (ID = 260)</p>
6693 <p>Following is a mapping of Clocks IDs to function:</p>
6694 <table border="1" class="docutils">
6695 <colgroup>
6696 <col width="9%" />
6697 <col width="50%" />
6698 <col width="41%" />
6699 </colgroup>
6700 <thead valign="bottom">
6701 <tr class="row-odd"><th class="head">Clock ID</th>
6702 <th class="head">Name</th>
6703 <th class="head">Function</th>
6704 </tr>
6705 </thead>
6706 <tbody valign="top">
6707 <tr class="row-even"><td>0</td>
6708 <td>DEV_MCAN15_MCANSS_CAN_RXD</td>
6709 <td>Input clock</td>
6710 </tr>
6711 <tr class="row-odd"><td>1</td>
6712 <td>DEV_MCAN15_MCANSS_CCLK_CLK</td>
6713 <td>Input muxed clock</td>
6714 </tr>
6715 <tr class="row-even"><td>2</td>
6716 <td>DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6717 <td>Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK</td>
6718 </tr>
6719 <tr class="row-odd"><td>3</td>
6720 <td>DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6721 <td>Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK</td>
6722 </tr>
6723 <tr class="row-even"><td>4</td>
6724 <td>DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6725 <td>Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK</td>
6726 </tr>
6727 <tr class="row-odd"><td>5</td>
6728 <td>DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6729 <td>Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK</td>
6730 </tr>
6731 <tr class="row-even"><td>6</td>
6732 <td>DEV_MCAN15_MCANSS_HCLK_CLK</td>
6733 <td>Input clock</td>
6734 </tr>
6735 </tbody>
6736 </table>
6737 </div>
6738 <div class="section" id="clocks-for-mcan16-device">
6739 <span id="soc-doc-j784s4-public-clks-mcan16"></span><h3>Clocks for MCAN16 Device<a class="headerlink" href="#clocks-for-mcan16-device" title="Permalink to this headline">¶</a></h3>
6740 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN16</span></a> (ID = 261)</p>
6741 <p>Following is a mapping of Clocks IDs to function:</p>
6742 <table border="1" class="docutils">
6743 <colgroup>
6744 <col width="9%" />
6745 <col width="50%" />
6746 <col width="41%" />
6747 </colgroup>
6748 <thead valign="bottom">
6749 <tr class="row-odd"><th class="head">Clock ID</th>
6750 <th class="head">Name</th>
6751 <th class="head">Function</th>
6752 </tr>
6753 </thead>
6754 <tbody valign="top">
6755 <tr class="row-even"><td>0</td>
6756 <td>DEV_MCAN16_MCANSS_CAN_RXD</td>
6757 <td>Input clock</td>
6758 </tr>
6759 <tr class="row-odd"><td>1</td>
6760 <td>DEV_MCAN16_MCANSS_CCLK_CLK</td>
6761 <td>Input muxed clock</td>
6762 </tr>
6763 <tr class="row-even"><td>2</td>
6764 <td>DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6765 <td>Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK</td>
6766 </tr>
6767 <tr class="row-odd"><td>3</td>
6768 <td>DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6769 <td>Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK</td>
6770 </tr>
6771 <tr class="row-even"><td>4</td>
6772 <td>DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6773 <td>Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK</td>
6774 </tr>
6775 <tr class="row-odd"><td>5</td>
6776 <td>DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6777 <td>Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK</td>
6778 </tr>
6779 <tr class="row-even"><td>6</td>
6780 <td>DEV_MCAN16_MCANSS_HCLK_CLK</td>
6781 <td>Input clock</td>
6782 </tr>
6783 </tbody>
6784 </table>
6785 </div>
6786 <div class="section" id="clocks-for-mcan17-device">
6787 <span id="soc-doc-j784s4-public-clks-mcan17"></span><h3>Clocks for MCAN17 Device<a class="headerlink" href="#clocks-for-mcan17-device" title="Permalink to this headline">¶</a></h3>
6788 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN17</span></a> (ID = 262)</p>
6789 <p>Following is a mapping of Clocks IDs to function:</p>
6790 <table border="1" class="docutils">
6791 <colgroup>
6792 <col width="9%" />
6793 <col width="50%" />
6794 <col width="41%" />
6795 </colgroup>
6796 <thead valign="bottom">
6797 <tr class="row-odd"><th class="head">Clock ID</th>
6798 <th class="head">Name</th>
6799 <th class="head">Function</th>
6800 </tr>
6801 </thead>
6802 <tbody valign="top">
6803 <tr class="row-even"><td>0</td>
6804 <td>DEV_MCAN17_MCANSS_CAN_RXD</td>
6805 <td>Input clock</td>
6806 </tr>
6807 <tr class="row-odd"><td>1</td>
6808 <td>DEV_MCAN17_MCANSS_CCLK_CLK</td>
6809 <td>Input muxed clock</td>
6810 </tr>
6811 <tr class="row-even"><td>2</td>
6812 <td>DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6813 <td>Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK</td>
6814 </tr>
6815 <tr class="row-odd"><td>3</td>
6816 <td>DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6817 <td>Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK</td>
6818 </tr>
6819 <tr class="row-even"><td>4</td>
6820 <td>DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6821 <td>Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK</td>
6822 </tr>
6823 <tr class="row-odd"><td>5</td>
6824 <td>DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6825 <td>Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK</td>
6826 </tr>
6827 <tr class="row-even"><td>6</td>
6828 <td>DEV_MCAN17_MCANSS_HCLK_CLK</td>
6829 <td>Input clock</td>
6830 </tr>
6831 </tbody>
6832 </table>
6833 </div>
6834 <div class="section" id="clocks-for-mcan2-device">
6835 <span id="soc-doc-j784s4-public-clks-mcan2"></span><h3>Clocks for MCAN2 Device<a class="headerlink" href="#clocks-for-mcan2-device" title="Permalink to this headline">¶</a></h3>
6836 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN2</span></a> (ID = 247)</p>
6837 <p>Following is a mapping of Clocks IDs to function:</p>
6838 <table border="1" class="docutils">
6839 <colgroup>
6840 <col width="9%" />
6841 <col width="50%" />
6842 <col width="41%" />
6843 </colgroup>
6844 <thead valign="bottom">
6845 <tr class="row-odd"><th class="head">Clock ID</th>
6846 <th class="head">Name</th>
6847 <th class="head">Function</th>
6848 </tr>
6849 </thead>
6850 <tbody valign="top">
6851 <tr class="row-even"><td>0</td>
6852 <td>DEV_MCAN2_MCANSS_CAN_RXD</td>
6853 <td>Input clock</td>
6854 </tr>
6855 <tr class="row-odd"><td>1</td>
6856 <td>DEV_MCAN2_MCANSS_CCLK_CLK</td>
6857 <td>Input muxed clock</td>
6858 </tr>
6859 <tr class="row-even"><td>2</td>
6860 <td>DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6861 <td>Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK</td>
6862 </tr>
6863 <tr class="row-odd"><td>3</td>
6864 <td>DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6865 <td>Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK</td>
6866 </tr>
6867 <tr class="row-even"><td>4</td>
6868 <td>DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6869 <td>Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK</td>
6870 </tr>
6871 <tr class="row-odd"><td>5</td>
6872 <td>DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6873 <td>Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK</td>
6874 </tr>
6875 <tr class="row-even"><td>6</td>
6876 <td>DEV_MCAN2_MCANSS_HCLK_CLK</td>
6877 <td>Input clock</td>
6878 </tr>
6879 </tbody>
6880 </table>
6881 </div>
6882 <div class="section" id="clocks-for-mcan3-device">
6883 <span id="soc-doc-j784s4-public-clks-mcan3"></span><h3>Clocks for MCAN3 Device<a class="headerlink" href="#clocks-for-mcan3-device" title="Permalink to this headline">¶</a></h3>
6884 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN3</span></a> (ID = 248)</p>
6885 <p>Following is a mapping of Clocks IDs to function:</p>
6886 <table border="1" class="docutils">
6887 <colgroup>
6888 <col width="9%" />
6889 <col width="50%" />
6890 <col width="41%" />
6891 </colgroup>
6892 <thead valign="bottom">
6893 <tr class="row-odd"><th class="head">Clock ID</th>
6894 <th class="head">Name</th>
6895 <th class="head">Function</th>
6896 </tr>
6897 </thead>
6898 <tbody valign="top">
6899 <tr class="row-even"><td>0</td>
6900 <td>DEV_MCAN3_MCANSS_CAN_RXD</td>
6901 <td>Input clock</td>
6902 </tr>
6903 <tr class="row-odd"><td>1</td>
6904 <td>DEV_MCAN3_MCANSS_CCLK_CLK</td>
6905 <td>Input muxed clock</td>
6906 </tr>
6907 <tr class="row-even"><td>2</td>
6908 <td>DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6909 <td>Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK</td>
6910 </tr>
6911 <tr class="row-odd"><td>3</td>
6912 <td>DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6913 <td>Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK</td>
6914 </tr>
6915 <tr class="row-even"><td>4</td>
6916 <td>DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6917 <td>Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK</td>
6918 </tr>
6919 <tr class="row-odd"><td>5</td>
6920 <td>DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6921 <td>Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK</td>
6922 </tr>
6923 <tr class="row-even"><td>6</td>
6924 <td>DEV_MCAN3_MCANSS_HCLK_CLK</td>
6925 <td>Input clock</td>
6926 </tr>
6927 </tbody>
6928 </table>
6929 </div>
6930 <div class="section" id="clocks-for-mcan4-device">
6931 <span id="soc-doc-j784s4-public-clks-mcan4"></span><h3>Clocks for MCAN4 Device<a class="headerlink" href="#clocks-for-mcan4-device" title="Permalink to this headline">¶</a></h3>
6932 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN4</span></a> (ID = 249)</p>
6933 <p>Following is a mapping of Clocks IDs to function:</p>
6934 <table border="1" class="docutils">
6935 <colgroup>
6936 <col width="9%" />
6937 <col width="50%" />
6938 <col width="41%" />
6939 </colgroup>
6940 <thead valign="bottom">
6941 <tr class="row-odd"><th class="head">Clock ID</th>
6942 <th class="head">Name</th>
6943 <th class="head">Function</th>
6944 </tr>
6945 </thead>
6946 <tbody valign="top">
6947 <tr class="row-even"><td>0</td>
6948 <td>DEV_MCAN4_MCANSS_CAN_RXD</td>
6949 <td>Input clock</td>
6950 </tr>
6951 <tr class="row-odd"><td>1</td>
6952 <td>DEV_MCAN4_MCANSS_CCLK_CLK</td>
6953 <td>Input muxed clock</td>
6954 </tr>
6955 <tr class="row-even"><td>2</td>
6956 <td>DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
6957 <td>Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK</td>
6958 </tr>
6959 <tr class="row-odd"><td>3</td>
6960 <td>DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
6961 <td>Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK</td>
6962 </tr>
6963 <tr class="row-even"><td>4</td>
6964 <td>DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
6965 <td>Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK</td>
6966 </tr>
6967 <tr class="row-odd"><td>5</td>
6968 <td>DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
6969 <td>Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK</td>
6970 </tr>
6971 <tr class="row-even"><td>6</td>
6972 <td>DEV_MCAN4_MCANSS_HCLK_CLK</td>
6973 <td>Input clock</td>
6974 </tr>
6975 </tbody>
6976 </table>
6977 </div>
6978 <div class="section" id="clocks-for-mcan5-device">
6979 <span id="soc-doc-j784s4-public-clks-mcan5"></span><h3>Clocks for MCAN5 Device<a class="headerlink" href="#clocks-for-mcan5-device" title="Permalink to this headline">¶</a></h3>
6980 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN5</span></a> (ID = 250)</p>
6981 <p>Following is a mapping of Clocks IDs to function:</p>
6982 <table border="1" class="docutils">
6983 <colgroup>
6984 <col width="9%" />
6985 <col width="50%" />
6986 <col width="41%" />
6987 </colgroup>
6988 <thead valign="bottom">
6989 <tr class="row-odd"><th class="head">Clock ID</th>
6990 <th class="head">Name</th>
6991 <th class="head">Function</th>
6992 </tr>
6993 </thead>
6994 <tbody valign="top">
6995 <tr class="row-even"><td>0</td>
6996 <td>DEV_MCAN5_MCANSS_CAN_RXD</td>
6997 <td>Input clock</td>
6998 </tr>
6999 <tr class="row-odd"><td>1</td>
7000 <td>DEV_MCAN5_MCANSS_CCLK_CLK</td>
7001 <td>Input muxed clock</td>
7002 </tr>
7003 <tr class="row-even"><td>2</td>
7004 <td>DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
7005 <td>Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK</td>
7006 </tr>
7007 <tr class="row-odd"><td>3</td>
7008 <td>DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
7009 <td>Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK</td>
7010 </tr>
7011 <tr class="row-even"><td>4</td>
7012 <td>DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7013 <td>Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK</td>
7014 </tr>
7015 <tr class="row-odd"><td>5</td>
7016 <td>DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7017 <td>Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK</td>
7018 </tr>
7019 <tr class="row-even"><td>6</td>
7020 <td>DEV_MCAN5_MCANSS_HCLK_CLK</td>
7021 <td>Input clock</td>
7022 </tr>
7023 </tbody>
7024 </table>
7025 </div>
7026 <div class="section" id="clocks-for-mcan6-device">
7027 <span id="soc-doc-j784s4-public-clks-mcan6"></span><h3>Clocks for MCAN6 Device<a class="headerlink" href="#clocks-for-mcan6-device" title="Permalink to this headline">¶</a></h3>
7028 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN6</span></a> (ID = 251)</p>
7029 <p>Following is a mapping of Clocks IDs to function:</p>
7030 <table border="1" class="docutils">
7031 <colgroup>
7032 <col width="9%" />
7033 <col width="50%" />
7034 <col width="41%" />
7035 </colgroup>
7036 <thead valign="bottom">
7037 <tr class="row-odd"><th class="head">Clock ID</th>
7038 <th class="head">Name</th>
7039 <th class="head">Function</th>
7040 </tr>
7041 </thead>
7042 <tbody valign="top">
7043 <tr class="row-even"><td>0</td>
7044 <td>DEV_MCAN6_MCANSS_CAN_RXD</td>
7045 <td>Input clock</td>
7046 </tr>
7047 <tr class="row-odd"><td>1</td>
7048 <td>DEV_MCAN6_MCANSS_CCLK_CLK</td>
7049 <td>Input muxed clock</td>
7050 </tr>
7051 <tr class="row-even"><td>2</td>
7052 <td>DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
7053 <td>Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK</td>
7054 </tr>
7055 <tr class="row-odd"><td>3</td>
7056 <td>DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
7057 <td>Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK</td>
7058 </tr>
7059 <tr class="row-even"><td>4</td>
7060 <td>DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7061 <td>Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK</td>
7062 </tr>
7063 <tr class="row-odd"><td>5</td>
7064 <td>DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7065 <td>Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK</td>
7066 </tr>
7067 <tr class="row-even"><td>6</td>
7068 <td>DEV_MCAN6_MCANSS_HCLK_CLK</td>
7069 <td>Input clock</td>
7070 </tr>
7071 </tbody>
7072 </table>
7073 </div>
7074 <div class="section" id="clocks-for-mcan7-device">
7075 <span id="soc-doc-j784s4-public-clks-mcan7"></span><h3>Clocks for MCAN7 Device<a class="headerlink" href="#clocks-for-mcan7-device" title="Permalink to this headline">¶</a></h3>
7076 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN7</span></a> (ID = 252)</p>
7077 <p>Following is a mapping of Clocks IDs to function:</p>
7078 <table border="1" class="docutils">
7079 <colgroup>
7080 <col width="9%" />
7081 <col width="50%" />
7082 <col width="41%" />
7083 </colgroup>
7084 <thead valign="bottom">
7085 <tr class="row-odd"><th class="head">Clock ID</th>
7086 <th class="head">Name</th>
7087 <th class="head">Function</th>
7088 </tr>
7089 </thead>
7090 <tbody valign="top">
7091 <tr class="row-even"><td>0</td>
7092 <td>DEV_MCAN7_MCANSS_CAN_RXD</td>
7093 <td>Input clock</td>
7094 </tr>
7095 <tr class="row-odd"><td>1</td>
7096 <td>DEV_MCAN7_MCANSS_CCLK_CLK</td>
7097 <td>Input muxed clock</td>
7098 </tr>
7099 <tr class="row-even"><td>2</td>
7100 <td>DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
7101 <td>Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK</td>
7102 </tr>
7103 <tr class="row-odd"><td>3</td>
7104 <td>DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
7105 <td>Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK</td>
7106 </tr>
7107 <tr class="row-even"><td>4</td>
7108 <td>DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7109 <td>Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK</td>
7110 </tr>
7111 <tr class="row-odd"><td>5</td>
7112 <td>DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7113 <td>Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK</td>
7114 </tr>
7115 <tr class="row-even"><td>6</td>
7116 <td>DEV_MCAN7_MCANSS_HCLK_CLK</td>
7117 <td>Input clock</td>
7118 </tr>
7119 </tbody>
7120 </table>
7121 </div>
7122 <div class="section" id="clocks-for-mcan8-device">
7123 <span id="soc-doc-j784s4-public-clks-mcan8"></span><h3>Clocks for MCAN8 Device<a class="headerlink" href="#clocks-for-mcan8-device" title="Permalink to this headline">¶</a></h3>
7124 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN8</span></a> (ID = 253)</p>
7125 <p>Following is a mapping of Clocks IDs to function:</p>
7126 <table border="1" class="docutils">
7127 <colgroup>
7128 <col width="9%" />
7129 <col width="50%" />
7130 <col width="41%" />
7131 </colgroup>
7132 <thead valign="bottom">
7133 <tr class="row-odd"><th class="head">Clock ID</th>
7134 <th class="head">Name</th>
7135 <th class="head">Function</th>
7136 </tr>
7137 </thead>
7138 <tbody valign="top">
7139 <tr class="row-even"><td>0</td>
7140 <td>DEV_MCAN8_MCANSS_CAN_RXD</td>
7141 <td>Input clock</td>
7142 </tr>
7143 <tr class="row-odd"><td>1</td>
7144 <td>DEV_MCAN8_MCANSS_CCLK_CLK</td>
7145 <td>Input muxed clock</td>
7146 </tr>
7147 <tr class="row-even"><td>2</td>
7148 <td>DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
7149 <td>Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK</td>
7150 </tr>
7151 <tr class="row-odd"><td>3</td>
7152 <td>DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
7153 <td>Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK</td>
7154 </tr>
7155 <tr class="row-even"><td>4</td>
7156 <td>DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7157 <td>Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK</td>
7158 </tr>
7159 <tr class="row-odd"><td>5</td>
7160 <td>DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7161 <td>Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK</td>
7162 </tr>
7163 <tr class="row-even"><td>6</td>
7164 <td>DEV_MCAN8_MCANSS_HCLK_CLK</td>
7165 <td>Input clock</td>
7166 </tr>
7167 </tbody>
7168 </table>
7169 </div>
7170 <div class="section" id="clocks-for-mcan9-device">
7171 <span id="soc-doc-j784s4-public-clks-mcan9"></span><h3>Clocks for MCAN9 Device<a class="headerlink" href="#clocks-for-mcan9-device" title="Permalink to this headline">¶</a></h3>
7172 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCAN9</span></a> (ID = 254)</p>
7173 <p>Following is a mapping of Clocks IDs to function:</p>
7174 <table border="1" class="docutils">
7175 <colgroup>
7176 <col width="9%" />
7177 <col width="50%" />
7178 <col width="41%" />
7179 </colgroup>
7180 <thead valign="bottom">
7181 <tr class="row-odd"><th class="head">Clock ID</th>
7182 <th class="head">Name</th>
7183 <th class="head">Function</th>
7184 </tr>
7185 </thead>
7186 <tbody valign="top">
7187 <tr class="row-even"><td>0</td>
7188 <td>DEV_MCAN9_MCANSS_CAN_RXD</td>
7189 <td>Input clock</td>
7190 </tr>
7191 <tr class="row-odd"><td>1</td>
7192 <td>DEV_MCAN9_MCANSS_CCLK_CLK</td>
7193 <td>Input muxed clock</td>
7194 </tr>
7195 <tr class="row-even"><td>2</td>
7196 <td>DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK</td>
7197 <td>Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK</td>
7198 </tr>
7199 <tr class="row-odd"><td>3</td>
7200 <td>DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
7201 <td>Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK</td>
7202 </tr>
7203 <tr class="row-even"><td>4</td>
7204 <td>DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7205 <td>Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK</td>
7206 </tr>
7207 <tr class="row-odd"><td>5</td>
7208 <td>DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7209 <td>Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK</td>
7210 </tr>
7211 <tr class="row-even"><td>6</td>
7212 <td>DEV_MCAN9_MCANSS_HCLK_CLK</td>
7213 <td>Input clock</td>
7214 </tr>
7215 </tbody>
7216 </table>
7217 </div>
7218 <div class="section" id="clocks-for-mcasp0-device">
7219 <span id="soc-doc-j784s4-public-clks-mcasp0"></span><h3>Clocks for MCASP0 Device<a class="headerlink" href="#clocks-for-mcasp0-device" title="Permalink to this headline">¶</a></h3>
7220 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCASP0</span></a> (ID = 265)</p>
7221 <p>Following is a mapping of Clocks IDs to function:</p>
7222 <table border="1" class="docutils">
7223 <colgroup>
7224 <col width="9%" />
7225 <col width="50%" />
7226 <col width="41%" />
7227 </colgroup>
7228 <thead valign="bottom">
7229 <tr class="row-odd"><th class="head">Clock ID</th>
7230 <th class="head">Name</th>
7231 <th class="head">Function</th>
7232 </tr>
7233 </thead>
7234 <tbody valign="top">
7235 <tr class="row-even"><td>0</td>
7236 <td>DEV_MCASP0_AUX_CLK</td>
7237 <td>Input muxed clock</td>
7238 </tr>
7239 <tr class="row-odd"><td>1</td>
7240 <td>DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
7241 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7242 </tr>
7243 <tr class="row-even"><td>2</td>
7244 <td>DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
7245 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7246 </tr>
7247 <tr class="row-odd"><td>5</td>
7248 <td>DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7249 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7250 </tr>
7251 <tr class="row-even"><td>6</td>
7252 <td>DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7253 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7254 </tr>
7255 <tr class="row-odd"><td>7</td>
7256 <td>DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7257 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7258 </tr>
7259 <tr class="row-even"><td>8</td>
7260 <td>DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7261 <td>Parent input clock option to DEV_MCASP0_AUX_CLK</td>
7262 </tr>
7263 <tr class="row-odd"><td>9</td>
7264 <td>DEV_MCASP0_MCASP_ACLKR_PIN</td>
7265 <td>Input clock</td>
7266 </tr>
7267 <tr class="row-even"><td>10</td>
7268 <td>DEV_MCASP0_MCASP_ACLKR_POUT</td>
7269 <td>Output clock</td>
7270 </tr>
7271 <tr class="row-odd"><td>11</td>
7272 <td>DEV_MCASP0_MCASP_ACLKX_PIN</td>
7273 <td>Input clock</td>
7274 </tr>
7275 <tr class="row-even"><td>12</td>
7276 <td>DEV_MCASP0_MCASP_ACLKX_POUT</td>
7277 <td>Output clock</td>
7278 </tr>
7279 <tr class="row-odd"><td>13</td>
7280 <td>DEV_MCASP0_MCASP_AFSR_POUT</td>
7281 <td>Output clock</td>
7282 </tr>
7283 <tr class="row-even"><td>14</td>
7284 <td>DEV_MCASP0_MCASP_AFSX_POUT</td>
7285 <td>Output clock</td>
7286 </tr>
7287 <tr class="row-odd"><td>15</td>
7288 <td>DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7289 <td>Input muxed clock</td>
7290 </tr>
7291 <tr class="row-even"><td>16</td>
7292 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7293 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7294 </tr>
7295 <tr class="row-odd"><td>17</td>
7296 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7297 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7298 </tr>
7299 <tr class="row-even"><td>18</td>
7300 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
7301 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7302 </tr>
7303 <tr class="row-odd"><td>19</td>
7304 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
7305 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7306 </tr>
7307 <tr class="row-even"><td>24</td>
7308 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7309 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7310 </tr>
7311 <tr class="row-odd"><td>25</td>
7312 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7313 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7314 </tr>
7315 <tr class="row-even"><td>26</td>
7316 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7317 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7318 </tr>
7319 <tr class="row-odd"><td>27</td>
7320 <td>DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7321 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN</td>
7322 </tr>
7323 <tr class="row-even"><td>32</td>
7324 <td>DEV_MCASP0_MCASP_AHCLKR_POUT</td>
7325 <td>Output clock</td>
7326 </tr>
7327 <tr class="row-odd"><td>33</td>
7328 <td>DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7329 <td>Input muxed clock</td>
7330 </tr>
7331 <tr class="row-even"><td>34</td>
7332 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7333 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7334 </tr>
7335 <tr class="row-odd"><td>35</td>
7336 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7337 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7338 </tr>
7339 <tr class="row-even"><td>36</td>
7340 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
7341 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7342 </tr>
7343 <tr class="row-odd"><td>37</td>
7344 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
7345 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7346 </tr>
7347 <tr class="row-even"><td>42</td>
7348 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7349 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7350 </tr>
7351 <tr class="row-odd"><td>43</td>
7352 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7353 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7354 </tr>
7355 <tr class="row-even"><td>44</td>
7356 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7357 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7358 </tr>
7359 <tr class="row-odd"><td>45</td>
7360 <td>DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7361 <td>Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN</td>
7362 </tr>
7363 <tr class="row-even"><td>50</td>
7364 <td>DEV_MCASP0_MCASP_AHCLKX_POUT</td>
7365 <td>Output clock</td>
7366 </tr>
7367 <tr class="row-odd"><td>51</td>
7368 <td>DEV_MCASP0_VBUSP_CLK</td>
7369 <td>Input clock</td>
7370 </tr>
7371 </tbody>
7372 </table>
7373 </div>
7374 <div class="section" id="clocks-for-mcasp1-device">
7375 <span id="soc-doc-j784s4-public-clks-mcasp1"></span><h3>Clocks for MCASP1 Device<a class="headerlink" href="#clocks-for-mcasp1-device" title="Permalink to this headline">¶</a></h3>
7376 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCASP1</span></a> (ID = 266)</p>
7377 <p>Following is a mapping of Clocks IDs to function:</p>
7378 <table border="1" class="docutils">
7379 <colgroup>
7380 <col width="9%" />
7381 <col width="50%" />
7382 <col width="41%" />
7383 </colgroup>
7384 <thead valign="bottom">
7385 <tr class="row-odd"><th class="head">Clock ID</th>
7386 <th class="head">Name</th>
7387 <th class="head">Function</th>
7388 </tr>
7389 </thead>
7390 <tbody valign="top">
7391 <tr class="row-even"><td>0</td>
7392 <td>DEV_MCASP1_AUX_CLK</td>
7393 <td>Input muxed clock</td>
7394 </tr>
7395 <tr class="row-odd"><td>1</td>
7396 <td>DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
7397 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7398 </tr>
7399 <tr class="row-even"><td>2</td>
7400 <td>DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
7401 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7402 </tr>
7403 <tr class="row-odd"><td>5</td>
7404 <td>DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7405 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7406 </tr>
7407 <tr class="row-even"><td>6</td>
7408 <td>DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7409 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7410 </tr>
7411 <tr class="row-odd"><td>7</td>
7412 <td>DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7413 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7414 </tr>
7415 <tr class="row-even"><td>8</td>
7416 <td>DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7417 <td>Parent input clock option to DEV_MCASP1_AUX_CLK</td>
7418 </tr>
7419 <tr class="row-odd"><td>9</td>
7420 <td>DEV_MCASP1_MCASP_ACLKR_PIN</td>
7421 <td>Input clock</td>
7422 </tr>
7423 <tr class="row-even"><td>10</td>
7424 <td>DEV_MCASP1_MCASP_ACLKR_POUT</td>
7425 <td>Output clock</td>
7426 </tr>
7427 <tr class="row-odd"><td>11</td>
7428 <td>DEV_MCASP1_MCASP_ACLKX_PIN</td>
7429 <td>Input clock</td>
7430 </tr>
7431 <tr class="row-even"><td>12</td>
7432 <td>DEV_MCASP1_MCASP_ACLKX_POUT</td>
7433 <td>Output clock</td>
7434 </tr>
7435 <tr class="row-odd"><td>13</td>
7436 <td>DEV_MCASP1_MCASP_AFSR_POUT</td>
7437 <td>Output clock</td>
7438 </tr>
7439 <tr class="row-even"><td>14</td>
7440 <td>DEV_MCASP1_MCASP_AFSX_POUT</td>
7441 <td>Output clock</td>
7442 </tr>
7443 <tr class="row-odd"><td>15</td>
7444 <td>DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7445 <td>Input muxed clock</td>
7446 </tr>
7447 <tr class="row-even"><td>16</td>
7448 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7449 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7450 </tr>
7451 <tr class="row-odd"><td>17</td>
7452 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7453 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7454 </tr>
7455 <tr class="row-even"><td>18</td>
7456 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
7457 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7458 </tr>
7459 <tr class="row-odd"><td>19</td>
7460 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
7461 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7462 </tr>
7463 <tr class="row-even"><td>24</td>
7464 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7465 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7466 </tr>
7467 <tr class="row-odd"><td>25</td>
7468 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7469 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7470 </tr>
7471 <tr class="row-even"><td>26</td>
7472 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7473 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7474 </tr>
7475 <tr class="row-odd"><td>27</td>
7476 <td>DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7477 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN</td>
7478 </tr>
7479 <tr class="row-even"><td>32</td>
7480 <td>DEV_MCASP1_MCASP_AHCLKR_POUT</td>
7481 <td>Output clock</td>
7482 </tr>
7483 <tr class="row-odd"><td>33</td>
7484 <td>DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7485 <td>Input muxed clock</td>
7486 </tr>
7487 <tr class="row-even"><td>34</td>
7488 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7489 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7490 </tr>
7491 <tr class="row-odd"><td>35</td>
7492 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7493 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7494 </tr>
7495 <tr class="row-even"><td>36</td>
7496 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
7497 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7498 </tr>
7499 <tr class="row-odd"><td>37</td>
7500 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
7501 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7502 </tr>
7503 <tr class="row-even"><td>42</td>
7504 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7505 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7506 </tr>
7507 <tr class="row-odd"><td>43</td>
7508 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7509 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7510 </tr>
7511 <tr class="row-even"><td>44</td>
7512 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7513 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7514 </tr>
7515 <tr class="row-odd"><td>45</td>
7516 <td>DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7517 <td>Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN</td>
7518 </tr>
7519 <tr class="row-even"><td>50</td>
7520 <td>DEV_MCASP1_MCASP_AHCLKX_POUT</td>
7521 <td>Output clock</td>
7522 </tr>
7523 <tr class="row-odd"><td>51</td>
7524 <td>DEV_MCASP1_VBUSP_CLK</td>
7525 <td>Input clock</td>
7526 </tr>
7527 </tbody>
7528 </table>
7529 </div>
7530 <div class="section" id="clocks-for-mcasp2-device">
7531 <span id="soc-doc-j784s4-public-clks-mcasp2"></span><h3>Clocks for MCASP2 Device<a class="headerlink" href="#clocks-for-mcasp2-device" title="Permalink to this headline">¶</a></h3>
7532 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCASP2</span></a> (ID = 267)</p>
7533 <p>Following is a mapping of Clocks IDs to function:</p>
7534 <table border="1" class="docutils">
7535 <colgroup>
7536 <col width="9%" />
7537 <col width="50%" />
7538 <col width="41%" />
7539 </colgroup>
7540 <thead valign="bottom">
7541 <tr class="row-odd"><th class="head">Clock ID</th>
7542 <th class="head">Name</th>
7543 <th class="head">Function</th>
7544 </tr>
7545 </thead>
7546 <tbody valign="top">
7547 <tr class="row-even"><td>0</td>
7548 <td>DEV_MCASP2_AUX_CLK</td>
7549 <td>Input muxed clock</td>
7550 </tr>
7551 <tr class="row-odd"><td>1</td>
7552 <td>DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
7553 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
7554 </tr>
7555 <tr class="row-even"><td>2</td>
7556 <td>DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
7557 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
7558 </tr>
7559 <tr class="row-odd"><td>5</td>
7560 <td>DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7561 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
7562 </tr>
7563 <tr class="row-even"><td>6</td>
7564 <td>DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7565 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
7566 </tr>
7567 <tr class="row-odd"><td>7</td>
7568 <td>DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7569 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
7570 </tr>
7571 <tr class="row-even"><td>8</td>
7572 <td>DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7573 <td>Parent input clock option to DEV_MCASP2_AUX_CLK</td>
7574 </tr>
7575 <tr class="row-odd"><td>9</td>
7576 <td>DEV_MCASP2_MCASP_ACLKR_PIN</td>
7577 <td>Input clock</td>
7578 </tr>
7579 <tr class="row-even"><td>10</td>
7580 <td>DEV_MCASP2_MCASP_ACLKR_POUT</td>
7581 <td>Output clock</td>
7582 </tr>
7583 <tr class="row-odd"><td>11</td>
7584 <td>DEV_MCASP2_MCASP_ACLKX_PIN</td>
7585 <td>Input clock</td>
7586 </tr>
7587 <tr class="row-even"><td>12</td>
7588 <td>DEV_MCASP2_MCASP_ACLKX_POUT</td>
7589 <td>Output clock</td>
7590 </tr>
7591 <tr class="row-odd"><td>13</td>
7592 <td>DEV_MCASP2_MCASP_AFSR_POUT</td>
7593 <td>Output clock</td>
7594 </tr>
7595 <tr class="row-even"><td>14</td>
7596 <td>DEV_MCASP2_MCASP_AFSX_POUT</td>
7597 <td>Output clock</td>
7598 </tr>
7599 <tr class="row-odd"><td>15</td>
7600 <td>DEV_MCASP2_MCASP_AHCLKR_PIN</td>
7601 <td>Input muxed clock</td>
7602 </tr>
7603 <tr class="row-even"><td>16</td>
7604 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7605 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
7606 </tr>
7607 <tr class="row-odd"><td>17</td>
7608 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7609 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
7610 </tr>
7611 <tr class="row-even"><td>18</td>
7612 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
7613 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
7614 </tr>
7615 <tr class="row-odd"><td>19</td>
7616 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
7617 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
7618 </tr>
7619 <tr class="row-even"><td>24</td>
7620 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7621 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
7622 </tr>
7623 <tr class="row-odd"><td>25</td>
7624 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7625 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
7626 </tr>
7627 <tr class="row-even"><td>26</td>
7628 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7629 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
7630 </tr>
7631 <tr class="row-odd"><td>27</td>
7632 <td>DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7633 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN</td>
7634 </tr>
7635 <tr class="row-even"><td>32</td>
7636 <td>DEV_MCASP2_MCASP_AHCLKR_POUT</td>
7637 <td>Output clock</td>
7638 </tr>
7639 <tr class="row-odd"><td>33</td>
7640 <td>DEV_MCASP2_MCASP_AHCLKX_PIN</td>
7641 <td>Input muxed clock</td>
7642 </tr>
7643 <tr class="row-even"><td>34</td>
7644 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7645 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
7646 </tr>
7647 <tr class="row-odd"><td>35</td>
7648 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7649 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
7650 </tr>
7651 <tr class="row-even"><td>36</td>
7652 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
7653 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
7654 </tr>
7655 <tr class="row-odd"><td>37</td>
7656 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
7657 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
7658 </tr>
7659 <tr class="row-even"><td>42</td>
7660 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7661 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
7662 </tr>
7663 <tr class="row-odd"><td>43</td>
7664 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7665 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
7666 </tr>
7667 <tr class="row-even"><td>44</td>
7668 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7669 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
7670 </tr>
7671 <tr class="row-odd"><td>45</td>
7672 <td>DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7673 <td>Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN</td>
7674 </tr>
7675 <tr class="row-even"><td>50</td>
7676 <td>DEV_MCASP2_MCASP_AHCLKX_POUT</td>
7677 <td>Output clock</td>
7678 </tr>
7679 <tr class="row-odd"><td>51</td>
7680 <td>DEV_MCASP2_VBUSP_CLK</td>
7681 <td>Input clock</td>
7682 </tr>
7683 </tbody>
7684 </table>
7685 </div>
7686 <div class="section" id="clocks-for-mcasp3-device">
7687 <span id="soc-doc-j784s4-public-clks-mcasp3"></span><h3>Clocks for MCASP3 Device<a class="headerlink" href="#clocks-for-mcasp3-device" title="Permalink to this headline">¶</a></h3>
7688 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCASP3</span></a> (ID = 268)</p>
7689 <p>Following is a mapping of Clocks IDs to function:</p>
7690 <table border="1" class="docutils">
7691 <colgroup>
7692 <col width="9%" />
7693 <col width="50%" />
7694 <col width="41%" />
7695 </colgroup>
7696 <thead valign="bottom">
7697 <tr class="row-odd"><th class="head">Clock ID</th>
7698 <th class="head">Name</th>
7699 <th class="head">Function</th>
7700 </tr>
7701 </thead>
7702 <tbody valign="top">
7703 <tr class="row-even"><td>0</td>
7704 <td>DEV_MCASP3_AUX_CLK</td>
7705 <td>Input muxed clock</td>
7706 </tr>
7707 <tr class="row-odd"><td>1</td>
7708 <td>DEV_MCASP3_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
7709 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
7710 </tr>
7711 <tr class="row-even"><td>2</td>
7712 <td>DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
7713 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
7714 </tr>
7715 <tr class="row-odd"><td>5</td>
7716 <td>DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7717 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
7718 </tr>
7719 <tr class="row-even"><td>6</td>
7720 <td>DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7721 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
7722 </tr>
7723 <tr class="row-odd"><td>7</td>
7724 <td>DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7725 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
7726 </tr>
7727 <tr class="row-even"><td>8</td>
7728 <td>DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7729 <td>Parent input clock option to DEV_MCASP3_AUX_CLK</td>
7730 </tr>
7731 <tr class="row-odd"><td>9</td>
7732 <td>DEV_MCASP3_MCASP_ACLKR_PIN</td>
7733 <td>Input clock</td>
7734 </tr>
7735 <tr class="row-even"><td>10</td>
7736 <td>DEV_MCASP3_MCASP_ACLKR_POUT</td>
7737 <td>Output clock</td>
7738 </tr>
7739 <tr class="row-odd"><td>11</td>
7740 <td>DEV_MCASP3_MCASP_ACLKX_PIN</td>
7741 <td>Input clock</td>
7742 </tr>
7743 <tr class="row-even"><td>12</td>
7744 <td>DEV_MCASP3_MCASP_ACLKX_POUT</td>
7745 <td>Output clock</td>
7746 </tr>
7747 <tr class="row-odd"><td>13</td>
7748 <td>DEV_MCASP3_MCASP_AFSR_POUT</td>
7749 <td>Output clock</td>
7750 </tr>
7751 <tr class="row-even"><td>14</td>
7752 <td>DEV_MCASP3_MCASP_AFSX_POUT</td>
7753 <td>Output clock</td>
7754 </tr>
7755 <tr class="row-odd"><td>15</td>
7756 <td>DEV_MCASP3_MCASP_AHCLKR_PIN</td>
7757 <td>Input muxed clock</td>
7758 </tr>
7759 <tr class="row-even"><td>16</td>
7760 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7761 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
7762 </tr>
7763 <tr class="row-odd"><td>17</td>
7764 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7765 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
7766 </tr>
7767 <tr class="row-even"><td>18</td>
7768 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
7769 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
7770 </tr>
7771 <tr class="row-odd"><td>19</td>
7772 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
7773 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
7774 </tr>
7775 <tr class="row-even"><td>24</td>
7776 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7777 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
7778 </tr>
7779 <tr class="row-odd"><td>25</td>
7780 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7781 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
7782 </tr>
7783 <tr class="row-even"><td>26</td>
7784 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7785 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
7786 </tr>
7787 <tr class="row-odd"><td>27</td>
7788 <td>DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7789 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN</td>
7790 </tr>
7791 <tr class="row-even"><td>32</td>
7792 <td>DEV_MCASP3_MCASP_AHCLKR_POUT</td>
7793 <td>Output clock</td>
7794 </tr>
7795 <tr class="row-odd"><td>33</td>
7796 <td>DEV_MCASP3_MCASP_AHCLKX_PIN</td>
7797 <td>Input muxed clock</td>
7798 </tr>
7799 <tr class="row-even"><td>34</td>
7800 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7801 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
7802 </tr>
7803 <tr class="row-odd"><td>35</td>
7804 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7805 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
7806 </tr>
7807 <tr class="row-even"><td>36</td>
7808 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
7809 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
7810 </tr>
7811 <tr class="row-odd"><td>37</td>
7812 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
7813 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
7814 </tr>
7815 <tr class="row-even"><td>42</td>
7816 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7817 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
7818 </tr>
7819 <tr class="row-odd"><td>43</td>
7820 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7821 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
7822 </tr>
7823 <tr class="row-even"><td>44</td>
7824 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7825 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
7826 </tr>
7827 <tr class="row-odd"><td>45</td>
7828 <td>DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7829 <td>Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN</td>
7830 </tr>
7831 <tr class="row-even"><td>50</td>
7832 <td>DEV_MCASP3_MCASP_AHCLKX_POUT</td>
7833 <td>Output clock</td>
7834 </tr>
7835 <tr class="row-odd"><td>51</td>
7836 <td>DEV_MCASP3_VBUSP_CLK</td>
7837 <td>Input clock</td>
7838 </tr>
7839 </tbody>
7840 </table>
7841 </div>
7842 <div class="section" id="clocks-for-mcasp4-device">
7843 <span id="soc-doc-j784s4-public-clks-mcasp4"></span><h3>Clocks for MCASP4 Device<a class="headerlink" href="#clocks-for-mcasp4-device" title="Permalink to this headline">¶</a></h3>
7844 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCASP4</span></a> (ID = 269)</p>
7845 <p>Following is a mapping of Clocks IDs to function:</p>
7846 <table border="1" class="docutils">
7847 <colgroup>
7848 <col width="9%" />
7849 <col width="50%" />
7850 <col width="41%" />
7851 </colgroup>
7852 <thead valign="bottom">
7853 <tr class="row-odd"><th class="head">Clock ID</th>
7854 <th class="head">Name</th>
7855 <th class="head">Function</th>
7856 </tr>
7857 </thead>
7858 <tbody valign="top">
7859 <tr class="row-even"><td>0</td>
7860 <td>DEV_MCASP4_AUX_CLK</td>
7861 <td>Input muxed clock</td>
7862 </tr>
7863 <tr class="row-odd"><td>1</td>
7864 <td>DEV_MCASP4_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK</td>
7865 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
7866 </tr>
7867 <tr class="row-even"><td>2</td>
7868 <td>DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
7869 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
7870 </tr>
7871 <tr class="row-odd"><td>5</td>
7872 <td>DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7873 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
7874 </tr>
7875 <tr class="row-even"><td>6</td>
7876 <td>DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7877 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
7878 </tr>
7879 <tr class="row-odd"><td>7</td>
7880 <td>DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7881 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
7882 </tr>
7883 <tr class="row-even"><td>8</td>
7884 <td>DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7885 <td>Parent input clock option to DEV_MCASP4_AUX_CLK</td>
7886 </tr>
7887 <tr class="row-odd"><td>9</td>
7888 <td>DEV_MCASP4_MCASP_ACLKR_PIN</td>
7889 <td>Input clock</td>
7890 </tr>
7891 <tr class="row-even"><td>10</td>
7892 <td>DEV_MCASP4_MCASP_ACLKR_POUT</td>
7893 <td>Output clock</td>
7894 </tr>
7895 <tr class="row-odd"><td>11</td>
7896 <td>DEV_MCASP4_MCASP_ACLKX_PIN</td>
7897 <td>Input clock</td>
7898 </tr>
7899 <tr class="row-even"><td>12</td>
7900 <td>DEV_MCASP4_MCASP_ACLKX_POUT</td>
7901 <td>Output clock</td>
7902 </tr>
7903 <tr class="row-odd"><td>13</td>
7904 <td>DEV_MCASP4_MCASP_AFSR_POUT</td>
7905 <td>Output clock</td>
7906 </tr>
7907 <tr class="row-even"><td>14</td>
7908 <td>DEV_MCASP4_MCASP_AFSX_POUT</td>
7909 <td>Output clock</td>
7910 </tr>
7911 <tr class="row-odd"><td>15</td>
7912 <td>DEV_MCASP4_MCASP_AHCLKR_PIN</td>
7913 <td>Input muxed clock</td>
7914 </tr>
7915 <tr class="row-even"><td>16</td>
7916 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7917 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
7918 </tr>
7919 <tr class="row-odd"><td>17</td>
7920 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7921 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
7922 </tr>
7923 <tr class="row-even"><td>18</td>
7924 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
7925 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
7926 </tr>
7927 <tr class="row-odd"><td>19</td>
7928 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
7929 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
7930 </tr>
7931 <tr class="row-even"><td>24</td>
7932 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7933 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
7934 </tr>
7935 <tr class="row-odd"><td>25</td>
7936 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7937 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
7938 </tr>
7939 <tr class="row-even"><td>26</td>
7940 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7941 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
7942 </tr>
7943 <tr class="row-odd"><td>27</td>
7944 <td>DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7945 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN</td>
7946 </tr>
7947 <tr class="row-even"><td>32</td>
7948 <td>DEV_MCASP4_MCASP_AHCLKR_POUT</td>
7949 <td>Output clock</td>
7950 </tr>
7951 <tr class="row-odd"><td>33</td>
7952 <td>DEV_MCASP4_MCASP_AHCLKX_PIN</td>
7953 <td>Input muxed clock</td>
7954 </tr>
7955 <tr class="row-even"><td>34</td>
7956 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
7957 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
7958 </tr>
7959 <tr class="row-odd"><td>35</td>
7960 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
7961 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
7962 </tr>
7963 <tr class="row-even"><td>36</td>
7964 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT</td>
7965 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
7966 </tr>
7967 <tr class="row-odd"><td>37</td>
7968 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT</td>
7969 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
7970 </tr>
7971 <tr class="row-even"><td>42</td>
7972 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT</td>
7973 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
7974 </tr>
7975 <tr class="row-odd"><td>43</td>
7976 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1</td>
7977 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
7978 </tr>
7979 <tr class="row-even"><td>44</td>
7980 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2</td>
7981 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
7982 </tr>
7983 <tr class="row-odd"><td>45</td>
7984 <td>DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3</td>
7985 <td>Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN</td>
7986 </tr>
7987 <tr class="row-even"><td>50</td>
7988 <td>DEV_MCASP4_MCASP_AHCLKX_POUT</td>
7989 <td>Output clock</td>
7990 </tr>
7991 <tr class="row-odd"><td>51</td>
7992 <td>DEV_MCASP4_VBUSP_CLK</td>
7993 <td>Input clock</td>
7994 </tr>
7995 </tbody>
7996 </table>
7997 </div>
7998 <div class="section" id="clocks-for-mcspi0-device">
7999 <span id="soc-doc-j784s4-public-clks-mcspi0"></span><h3>Clocks for MCSPI0 Device<a class="headerlink" href="#clocks-for-mcspi0-device" title="Permalink to this headline">¶</a></h3>
8000 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCSPI0</span></a> (ID = 376)</p>
8001 <p>Following is a mapping of Clocks IDs to function:</p>
8002 <table border="1" class="docutils">
8003 <colgroup>
8004 <col width="9%" />
8005 <col width="47%" />
8006 <col width="44%" />
8007 </colgroup>
8008 <thead valign="bottom">
8009 <tr class="row-odd"><th class="head">Clock ID</th>
8010 <th class="head">Name</th>
8011 <th class="head">Function</th>
8012 </tr>
8013 </thead>
8014 <tbody valign="top">
8015 <tr class="row-even"><td>0</td>
8016 <td>DEV_MCSPI0_CLKSPIREF_CLK</td>
8017 <td>Input clock</td>
8018 </tr>
8019 <tr class="row-odd"><td>1</td>
8020 <td>DEV_MCSPI0_IO_CLKSPII_CLK</td>
8021 <td>Input muxed clock</td>
8022 </tr>
8023 <tr class="row-even"><td>2</td>
8024 <td>DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT</td>
8025 <td>Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK</td>
8026 </tr>
8027 <tr class="row-odd"><td>3</td>
8028 <td>DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK</td>
8029 <td>Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK</td>
8030 </tr>
8031 <tr class="row-even"><td>4</td>
8032 <td>DEV_MCSPI0_IO_CLKSPIO_CLK</td>
8033 <td>Output clock</td>
8034 </tr>
8035 <tr class="row-odd"><td>5</td>
8036 <td>DEV_MCSPI0_VBUSP_CLK</td>
8037 <td>Input clock</td>
8038 </tr>
8039 </tbody>
8040 </table>
8041 </div>
8042 <div class="section" id="clocks-for-mcspi1-device">
8043 <span id="soc-doc-j784s4-public-clks-mcspi1"></span><h3>Clocks for MCSPI1 Device<a class="headerlink" href="#clocks-for-mcspi1-device" title="Permalink to this headline">¶</a></h3>
8044 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCSPI1</span></a> (ID = 377)</p>
8045 <p>Following is a mapping of Clocks IDs to function:</p>
8046 <table border="1" class="docutils">
8047 <colgroup>
8048 <col width="9%" />
8049 <col width="47%" />
8050 <col width="44%" />
8051 </colgroup>
8052 <thead valign="bottom">
8053 <tr class="row-odd"><th class="head">Clock ID</th>
8054 <th class="head">Name</th>
8055 <th class="head">Function</th>
8056 </tr>
8057 </thead>
8058 <tbody valign="top">
8059 <tr class="row-even"><td>0</td>
8060 <td>DEV_MCSPI1_CLKSPIREF_CLK</td>
8061 <td>Input clock</td>
8062 </tr>
8063 <tr class="row-odd"><td>1</td>
8064 <td>DEV_MCSPI1_IO_CLKSPII_CLK</td>
8065 <td>Input muxed clock</td>
8066 </tr>
8067 <tr class="row-even"><td>2</td>
8068 <td>DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT</td>
8069 <td>Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK</td>
8070 </tr>
8071 <tr class="row-odd"><td>3</td>
8072 <td>DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK</td>
8073 <td>Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK</td>
8074 </tr>
8075 <tr class="row-even"><td>4</td>
8076 <td>DEV_MCSPI1_IO_CLKSPIO_CLK</td>
8077 <td>Output clock</td>
8078 </tr>
8079 <tr class="row-odd"><td>5</td>
8080 <td>DEV_MCSPI1_VBUSP_CLK</td>
8081 <td>Input clock</td>
8082 </tr>
8083 </tbody>
8084 </table>
8085 </div>
8086 <div class="section" id="clocks-for-mcspi2-device">
8087 <span id="soc-doc-j784s4-public-clks-mcspi2"></span><h3>Clocks for MCSPI2 Device<a class="headerlink" href="#clocks-for-mcspi2-device" title="Permalink to this headline">¶</a></h3>
8088 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCSPI2</span></a> (ID = 378)</p>
8089 <p>Following is a mapping of Clocks IDs to function:</p>
8090 <table border="1" class="docutils">
8091 <colgroup>
8092 <col width="9%" />
8093 <col width="47%" />
8094 <col width="44%" />
8095 </colgroup>
8096 <thead valign="bottom">
8097 <tr class="row-odd"><th class="head">Clock ID</th>
8098 <th class="head">Name</th>
8099 <th class="head">Function</th>
8100 </tr>
8101 </thead>
8102 <tbody valign="top">
8103 <tr class="row-even"><td>0</td>
8104 <td>DEV_MCSPI2_CLKSPIREF_CLK</td>
8105 <td>Input clock</td>
8106 </tr>
8107 <tr class="row-odd"><td>1</td>
8108 <td>DEV_MCSPI2_IO_CLKSPII_CLK</td>
8109 <td>Input muxed clock</td>
8110 </tr>
8111 <tr class="row-even"><td>2</td>
8112 <td>DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT</td>
8113 <td>Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK</td>
8114 </tr>
8115 <tr class="row-odd"><td>3</td>
8116 <td>DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK</td>
8117 <td>Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK</td>
8118 </tr>
8119 <tr class="row-even"><td>4</td>
8120 <td>DEV_MCSPI2_IO_CLKSPIO_CLK</td>
8121 <td>Output clock</td>
8122 </tr>
8123 <tr class="row-odd"><td>5</td>
8124 <td>DEV_MCSPI2_VBUSP_CLK</td>
8125 <td>Input clock</td>
8126 </tr>
8127 </tbody>
8128 </table>
8129 </div>
8130 <div class="section" id="clocks-for-mcspi3-device">
8131 <span id="soc-doc-j784s4-public-clks-mcspi3"></span><h3>Clocks for MCSPI3 Device<a class="headerlink" href="#clocks-for-mcspi3-device" title="Permalink to this headline">¶</a></h3>
8132 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCSPI3</span></a> (ID = 379)</p>
8133 <p>Following is a mapping of Clocks IDs to function:</p>
8134 <table border="1" class="docutils">
8135 <colgroup>
8136 <col width="9%" />
8137 <col width="47%" />
8138 <col width="44%" />
8139 </colgroup>
8140 <thead valign="bottom">
8141 <tr class="row-odd"><th class="head">Clock ID</th>
8142 <th class="head">Name</th>
8143 <th class="head">Function</th>
8144 </tr>
8145 </thead>
8146 <tbody valign="top">
8147 <tr class="row-even"><td>0</td>
8148 <td>DEV_MCSPI3_CLKSPIREF_CLK</td>
8149 <td>Input clock</td>
8150 </tr>
8151 <tr class="row-odd"><td>1</td>
8152 <td>DEV_MCSPI3_IO_CLKSPII_CLK</td>
8153 <td>Input muxed clock</td>
8154 </tr>
8155 <tr class="row-even"><td>2</td>
8156 <td>DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK</td>
8157 <td>Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK</td>
8158 </tr>
8159 <tr class="row-odd"><td>3</td>
8160 <td>DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI3_CLK_LPBK_MUX_OUT0</td>
8161 <td>Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK</td>
8162 </tr>
8163 <tr class="row-even"><td>4</td>
8164 <td>DEV_MCSPI3_IO_CLKSPIO_CLK</td>
8165 <td>Output clock</td>
8166 </tr>
8167 <tr class="row-odd"><td>5</td>
8168 <td>DEV_MCSPI3_VBUSP_CLK</td>
8169 <td>Input clock</td>
8170 </tr>
8171 </tbody>
8172 </table>
8173 </div>
8174 <div class="section" id="clocks-for-mcspi4-device">
8175 <span id="soc-doc-j784s4-public-clks-mcspi4"></span><h3>Clocks for MCSPI4 Device<a class="headerlink" href="#clocks-for-mcspi4-device" title="Permalink to this headline">¶</a></h3>
8176 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCSPI4</span></a> (ID = 380)</p>
8177 <p>Following is a mapping of Clocks IDs to function:</p>
8178 <table border="1" class="docutils">
8179 <colgroup>
8180 <col width="23%" />
8181 <col width="51%" />
8182 <col width="26%" />
8183 </colgroup>
8184 <thead valign="bottom">
8185 <tr class="row-odd"><th class="head">Clock ID</th>
8186 <th class="head">Name</th>
8187 <th class="head">Function</th>
8188 </tr>
8189 </thead>
8190 <tbody valign="top">
8191 <tr class="row-even"><td>0</td>
8192 <td>DEV_MCSPI4_CLKSPIREF_CLK</td>
8193 <td>Input clock</td>
8194 </tr>
8195 <tr class="row-odd"><td>1</td>
8196 <td>DEV_MCSPI4_IO_CLKSPII_CLK</td>
8197 <td>Input clock</td>
8198 </tr>
8199 <tr class="row-even"><td>2</td>
8200 <td>DEV_MCSPI4_IO_CLKSPIO_CLK</td>
8201 <td>Output clock</td>
8202 </tr>
8203 <tr class="row-odd"><td>3</td>
8204 <td>DEV_MCSPI4_VBUSP_CLK</td>
8205 <td>Input clock</td>
8206 </tr>
8207 </tbody>
8208 </table>
8209 </div>
8210 <div class="section" id="clocks-for-mcspi5-device">
8211 <span id="soc-doc-j784s4-public-clks-mcspi5"></span><h3>Clocks for MCSPI5 Device<a class="headerlink" href="#clocks-for-mcspi5-device" title="Permalink to this headline">¶</a></h3>
8212 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCSPI5</span></a> (ID = 381)</p>
8213 <p>Following is a mapping of Clocks IDs to function:</p>
8214 <table border="1" class="docutils">
8215 <colgroup>
8216 <col width="9%" />
8217 <col width="47%" />
8218 <col width="44%" />
8219 </colgroup>
8220 <thead valign="bottom">
8221 <tr class="row-odd"><th class="head">Clock ID</th>
8222 <th class="head">Name</th>
8223 <th class="head">Function</th>
8224 </tr>
8225 </thead>
8226 <tbody valign="top">
8227 <tr class="row-even"><td>0</td>
8228 <td>DEV_MCSPI5_CLKSPIREF_CLK</td>
8229 <td>Input clock</td>
8230 </tr>
8231 <tr class="row-odd"><td>1</td>
8232 <td>DEV_MCSPI5_IO_CLKSPII_CLK</td>
8233 <td>Input muxed clock</td>
8234 </tr>
8235 <tr class="row-even"><td>2</td>
8236 <td>DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI5_CLK_OUT</td>
8237 <td>Parent input clock option to DEV_MCSPI5_IO_CLKSPII_CLK</td>
8238 </tr>
8239 <tr class="row-odd"><td>3</td>
8240 <td>DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_SPI_MAIN_5_IO_CLKSPIO_CLK</td>
8241 <td>Parent input clock option to DEV_MCSPI5_IO_CLKSPII_CLK</td>
8242 </tr>
8243 <tr class="row-even"><td>4</td>
8244 <td>DEV_MCSPI5_IO_CLKSPIO_CLK</td>
8245 <td>Output clock</td>
8246 </tr>
8247 <tr class="row-odd"><td>5</td>
8248 <td>DEV_MCSPI5_VBUSP_CLK</td>
8249 <td>Input clock</td>
8250 </tr>
8251 </tbody>
8252 </table>
8253 </div>
8254 <div class="section" id="clocks-for-mcspi6-device">
8255 <span id="soc-doc-j784s4-public-clks-mcspi6"></span><h3>Clocks for MCSPI6 Device<a class="headerlink" href="#clocks-for-mcspi6-device" title="Permalink to this headline">¶</a></h3>
8256 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCSPI6</span></a> (ID = 382)</p>
8257 <p>Following is a mapping of Clocks IDs to function:</p>
8258 <table border="1" class="docutils">
8259 <colgroup>
8260 <col width="9%" />
8261 <col width="47%" />
8262 <col width="44%" />
8263 </colgroup>
8264 <thead valign="bottom">
8265 <tr class="row-odd"><th class="head">Clock ID</th>
8266 <th class="head">Name</th>
8267 <th class="head">Function</th>
8268 </tr>
8269 </thead>
8270 <tbody valign="top">
8271 <tr class="row-even"><td>0</td>
8272 <td>DEV_MCSPI6_CLKSPIREF_CLK</td>
8273 <td>Input clock</td>
8274 </tr>
8275 <tr class="row-odd"><td>1</td>
8276 <td>DEV_MCSPI6_IO_CLKSPII_CLK</td>
8277 <td>Input muxed clock</td>
8278 </tr>
8279 <tr class="row-even"><td>2</td>
8280 <td>DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI6_CLK_OUT</td>
8281 <td>Parent input clock option to DEV_MCSPI6_IO_CLKSPII_CLK</td>
8282 </tr>
8283 <tr class="row-odd"><td>3</td>
8284 <td>DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_SPI_MAIN_6_IO_CLKSPIO_CLK</td>
8285 <td>Parent input clock option to DEV_MCSPI6_IO_CLKSPII_CLK</td>
8286 </tr>
8287 <tr class="row-even"><td>4</td>
8288 <td>DEV_MCSPI6_IO_CLKSPIO_CLK</td>
8289 <td>Output clock</td>
8290 </tr>
8291 <tr class="row-odd"><td>5</td>
8292 <td>DEV_MCSPI6_VBUSP_CLK</td>
8293 <td>Input clock</td>
8294 </tr>
8295 </tbody>
8296 </table>
8297 </div>
8298 <div class="section" id="clocks-for-mcspi7-device">
8299 <span id="soc-doc-j784s4-public-clks-mcspi7"></span><h3>Clocks for MCSPI7 Device<a class="headerlink" href="#clocks-for-mcspi7-device" title="Permalink to this headline">¶</a></h3>
8300 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCSPI7</span></a> (ID = 383)</p>
8301 <p>Following is a mapping of Clocks IDs to function:</p>
8302 <table border="1" class="docutils">
8303 <colgroup>
8304 <col width="9%" />
8305 <col width="47%" />
8306 <col width="44%" />
8307 </colgroup>
8308 <thead valign="bottom">
8309 <tr class="row-odd"><th class="head">Clock ID</th>
8310 <th class="head">Name</th>
8311 <th class="head">Function</th>
8312 </tr>
8313 </thead>
8314 <tbody valign="top">
8315 <tr class="row-even"><td>0</td>
8316 <td>DEV_MCSPI7_CLKSPIREF_CLK</td>
8317 <td>Input clock</td>
8318 </tr>
8319 <tr class="row-odd"><td>1</td>
8320 <td>DEV_MCSPI7_IO_CLKSPII_CLK</td>
8321 <td>Input muxed clock</td>
8322 </tr>
8323 <tr class="row-even"><td>2</td>
8324 <td>DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI7_CLK_OUT</td>
8325 <td>Parent input clock option to DEV_MCSPI7_IO_CLKSPII_CLK</td>
8326 </tr>
8327 <tr class="row-odd"><td>3</td>
8328 <td>DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_SPI_MAIN_7_IO_CLKSPIO_CLK</td>
8329 <td>Parent input clock option to DEV_MCSPI7_IO_CLKSPII_CLK</td>
8330 </tr>
8331 <tr class="row-even"><td>4</td>
8332 <td>DEV_MCSPI7_IO_CLKSPIO_CLK</td>
8333 <td>Output clock</td>
8334 </tr>
8335 <tr class="row-odd"><td>5</td>
8336 <td>DEV_MCSPI7_VBUSP_CLK</td>
8337 <td>Input clock</td>
8338 </tr>
8339 </tbody>
8340 </table>
8341 </div>
8342 <div class="section" id="clocks-for-mcu-adc12fc-16ffc0-device">
8343 <span id="soc-doc-j784s4-public-clks-mcu-adc12fc-16ffc0"></span><h3>Clocks for MCU_ADC12FC_16FFC0 Device<a class="headerlink" href="#clocks-for-mcu-adc12fc-16ffc0-device" title="Permalink to this headline">¶</a></h3>
8344 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_ADC12FC_16FFC0</span></a> (ID = 0)</p>
8345 <p>Following is a mapping of Clocks IDs to function:</p>
8346 <table border="1" class="docutils">
8347 <colgroup>
8348 <col width="8%" />
8349 <col width="50%" />
8350 <col width="42%" />
8351 </colgroup>
8352 <thead valign="bottom">
8353 <tr class="row-odd"><th class="head">Clock ID</th>
8354 <th class="head">Name</th>
8355 <th class="head">Function</th>
8356 </tr>
8357 </thead>
8358 <tbody valign="top">
8359 <tr class="row-even"><td>0</td>
8360 <td>DEV_MCU_ADC12FC_16FFC0_ADC_CLK</td>
8361 <td>Input muxed clock</td>
8362 </tr>
8363 <tr class="row-odd"><td>1</td>
8364 <td>DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8365 <td>Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK</td>
8366 </tr>
8367 <tr class="row-even"><td>2</td>
8368 <td>DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK</td>
8369 <td>Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK</td>
8370 </tr>
8371 <tr class="row-odd"><td>3</td>
8372 <td>DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK</td>
8373 <td>Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK</td>
8374 </tr>
8375 <tr class="row-even"><td>4</td>
8376 <td>DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
8377 <td>Parent input clock option to DEV_MCU_ADC12FC_16FFC0_ADC_CLK</td>
8378 </tr>
8379 <tr class="row-odd"><td>5</td>
8380 <td>DEV_MCU_ADC12FC_16FFC0_SYS_CLK</td>
8381 <td>Input clock</td>
8382 </tr>
8383 <tr class="row-even"><td>6</td>
8384 <td>DEV_MCU_ADC12FC_16FFC0_VBUS_CLK</td>
8385 <td>Input clock</td>
8386 </tr>
8387 </tbody>
8388 </table>
8389 </div>
8390 <div class="section" id="clocks-for-mcu-adc12fc-16ffc1-device">
8391 <span id="soc-doc-j784s4-public-clks-mcu-adc12fc-16ffc1"></span><h3>Clocks for MCU_ADC12FC_16FFC1 Device<a class="headerlink" href="#clocks-for-mcu-adc12fc-16ffc1-device" title="Permalink to this headline">¶</a></h3>
8392 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_ADC12FC_16FFC1</span></a> (ID = 1)</p>
8393 <p>Following is a mapping of Clocks IDs to function:</p>
8394 <table border="1" class="docutils">
8395 <colgroup>
8396 <col width="8%" />
8397 <col width="50%" />
8398 <col width="42%" />
8399 </colgroup>
8400 <thead valign="bottom">
8401 <tr class="row-odd"><th class="head">Clock ID</th>
8402 <th class="head">Name</th>
8403 <th class="head">Function</th>
8404 </tr>
8405 </thead>
8406 <tbody valign="top">
8407 <tr class="row-even"><td>0</td>
8408 <td>DEV_MCU_ADC12FC_16FFC1_ADC_CLK</td>
8409 <td>Input muxed clock</td>
8410 </tr>
8411 <tr class="row-odd"><td>1</td>
8412 <td>DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
8413 <td>Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK</td>
8414 </tr>
8415 <tr class="row-even"><td>2</td>
8416 <td>DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK</td>
8417 <td>Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK</td>
8418 </tr>
8419 <tr class="row-odd"><td>3</td>
8420 <td>DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK</td>
8421 <td>Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK</td>
8422 </tr>
8423 <tr class="row-even"><td>4</td>
8424 <td>DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
8425 <td>Parent input clock option to DEV_MCU_ADC12FC_16FFC1_ADC_CLK</td>
8426 </tr>
8427 <tr class="row-odd"><td>5</td>
8428 <td>DEV_MCU_ADC12FC_16FFC1_SYS_CLK</td>
8429 <td>Input clock</td>
8430 </tr>
8431 <tr class="row-even"><td>6</td>
8432 <td>DEV_MCU_ADC12FC_16FFC1_VBUS_CLK</td>
8433 <td>Input clock</td>
8434 </tr>
8435 </tbody>
8436 </table>
8437 </div>
8438 <div class="section" id="clocks-for-mcu-cpsw0-device">
8439 <span id="soc-doc-j784s4-public-clks-mcu-cpsw0"></span><h3>Clocks for MCU_CPSW0 Device<a class="headerlink" href="#clocks-for-mcu-cpsw0-device" title="Permalink to this headline">¶</a></h3>
8440 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_CPSW0</span></a> (ID = 63)</p>
8441 <p>Following is a mapping of Clocks IDs to function:</p>
8442 <table border="1" class="docutils">
8443 <colgroup>
8444 <col width="8%" />
8445 <col width="53%" />
8446 <col width="39%" />
8447 </colgroup>
8448 <thead valign="bottom">
8449 <tr class="row-odd"><th class="head">Clock ID</th>
8450 <th class="head">Name</th>
8451 <th class="head">Function</th>
8452 </tr>
8453 </thead>
8454 <tbody valign="top">
8455 <tr class="row-even"><td>0</td>
8456 <td>DEV_MCU_CPSW0_CPPI_CLK_CLK</td>
8457 <td>Input clock</td>
8458 </tr>
8459 <tr class="row-odd"><td>1</td>
8460 <td>DEV_MCU_CPSW0_CPTS_GENF0</td>
8461 <td>Output clock</td>
8462 </tr>
8463 <tr class="row-even"><td>3</td>
8464 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8465 <td>Input muxed clock</td>
8466 </tr>
8467 <tr class="row-odd"><td>4</td>
8468 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
8469 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8470 </tr>
8471 <tr class="row-even"><td>5</td>
8472 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
8473 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8474 </tr>
8475 <tr class="row-odd"><td>6</td>
8476 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
8477 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8478 </tr>
8479 <tr class="row-even"><td>7</td>
8480 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
8481 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8482 </tr>
8483 <tr class="row-odd"><td>8</td>
8484 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
8485 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8486 </tr>
8487 <tr class="row-even"><td>9</td>
8488 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
8489 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8490 </tr>
8491 <tr class="row-odd"><td>10</td>
8492 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK</td>
8493 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8494 </tr>
8495 <tr class="row-even"><td>11</td>
8496 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK</td>
8497 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8498 </tr>
8499 <tr class="row-odd"><td>12</td>
8500 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK</td>
8501 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8502 </tr>
8503 <tr class="row-even"><td>13</td>
8504 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK</td>
8505 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8506 </tr>
8507 <tr class="row-odd"><td>14</td>
8508 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK</td>
8509 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8510 </tr>
8511 <tr class="row-even"><td>15</td>
8512 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK</td>
8513 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8514 </tr>
8515 <tr class="row-odd"><td>16</td>
8516 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK</td>
8517 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8518 </tr>
8519 <tr class="row-even"><td>17</td>
8520 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK</td>
8521 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8522 </tr>
8523 <tr class="row-odd"><td>18</td>
8524 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
8525 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8526 </tr>
8527 <tr class="row-even"><td>19</td>
8528 <td>DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2</td>
8529 <td>Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK</td>
8530 </tr>
8531 <tr class="row-odd"><td>20</td>
8532 <td>DEV_MCU_CPSW0_GMII1_MR_CLK</td>
8533 <td>Input clock</td>
8534 </tr>
8535 <tr class="row-even"><td>21</td>
8536 <td>DEV_MCU_CPSW0_GMII1_MT_CLK</td>
8537 <td>Input clock</td>
8538 </tr>
8539 <tr class="row-odd"><td>22</td>
8540 <td>DEV_MCU_CPSW0_GMII_RFT_CLK</td>
8541 <td>Input clock</td>
8542 </tr>
8543 <tr class="row-even"><td>23</td>
8544 <td>DEV_MCU_CPSW0_MDIO_MDCLK_O</td>
8545 <td>Output clock</td>
8546 </tr>
8547 <tr class="row-odd"><td>24</td>
8548 <td>DEV_MCU_CPSW0_RGMII1_RXC_I</td>
8549 <td>Input clock</td>
8550 </tr>
8551 <tr class="row-even"><td>26</td>
8552 <td>DEV_MCU_CPSW0_RGMII1_TXC_O</td>
8553 <td>Output clock</td>
8554 </tr>
8555 <tr class="row-odd"><td>27</td>
8556 <td>DEV_MCU_CPSW0_RGMII_MHZ_250_CLK</td>
8557 <td>Input clock</td>
8558 </tr>
8559 <tr class="row-even"><td>28</td>
8560 <td>DEV_MCU_CPSW0_RGMII_MHZ_50_CLK</td>
8561 <td>Input clock</td>
8562 </tr>
8563 <tr class="row-odd"><td>29</td>
8564 <td>DEV_MCU_CPSW0_RGMII_MHZ_5_CLK</td>
8565 <td>Input clock</td>
8566 </tr>
8567 <tr class="row-even"><td>30</td>
8568 <td>DEV_MCU_CPSW0_RMII_MHZ_50_CLK</td>
8569 <td>Input clock</td>
8570 </tr>
8571 </tbody>
8572 </table>
8573 </div>
8574 <div class="section" id="clocks-for-mcu-cpt2-aggr0-device">
8575 <span id="soc-doc-j784s4-public-clks-mcu-cpt2-aggr0"></span><h3>Clocks for MCU_CPT2_AGGR0 Device<a class="headerlink" href="#clocks-for-mcu-cpt2-aggr0-device" title="Permalink to this headline">¶</a></h3>
8576 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_CPT2_AGGR0</span></a> (ID = 71)</p>
8577 <p>Following is a mapping of Clocks IDs to function:</p>
8578 <table border="1" class="docutils">
8579 <colgroup>
8580 <col width="22%" />
8581 <col width="54%" />
8582 <col width="24%" />
8583 </colgroup>
8584 <thead valign="bottom">
8585 <tr class="row-odd"><th class="head">Clock ID</th>
8586 <th class="head">Name</th>
8587 <th class="head">Function</th>
8588 </tr>
8589 </thead>
8590 <tbody valign="top">
8591 <tr class="row-even"><td>0</td>
8592 <td>DEV_MCU_CPT2_AGGR0_VCLK_CLK</td>
8593 <td>Input clock</td>
8594 </tr>
8595 </tbody>
8596 </table>
8597 </div>
8598 <div class="section" id="clocks-for-mcu-dcc0-device">
8599 <span id="soc-doc-j784s4-public-clks-mcu-dcc0"></span><h3>Clocks for MCU_DCC0 Device<a class="headerlink" href="#clocks-for-mcu-dcc0-device" title="Permalink to this headline">¶</a></h3>
8600 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_DCC0</span></a> (ID = 88)</p>
8601 <p>Following is a mapping of Clocks IDs to function:</p>
8602 <table border="1" class="docutils">
8603 <colgroup>
8604 <col width="22%" />
8605 <col width="55%" />
8606 <col width="24%" />
8607 </colgroup>
8608 <thead valign="bottom">
8609 <tr class="row-odd"><th class="head">Clock ID</th>
8610 <th class="head">Name</th>
8611 <th class="head">Function</th>
8612 </tr>
8613 </thead>
8614 <tbody valign="top">
8615 <tr class="row-even"><td>0</td>
8616 <td>DEV_MCU_DCC0_DCC_CLKSRC0_CLK</td>
8617 <td>Input clock</td>
8618 </tr>
8619 <tr class="row-odd"><td>1</td>
8620 <td>DEV_MCU_DCC0_DCC_CLKSRC1_CLK</td>
8621 <td>Input clock</td>
8622 </tr>
8623 <tr class="row-even"><td>2</td>
8624 <td>DEV_MCU_DCC0_DCC_CLKSRC2_CLK</td>
8625 <td>Input clock</td>
8626 </tr>
8627 <tr class="row-odd"><td>3</td>
8628 <td>DEV_MCU_DCC0_DCC_CLKSRC3_CLK</td>
8629 <td>Input clock</td>
8630 </tr>
8631 <tr class="row-even"><td>4</td>
8632 <td>DEV_MCU_DCC0_DCC_CLKSRC4_CLK</td>
8633 <td>Input clock</td>
8634 </tr>
8635 <tr class="row-odd"><td>5</td>
8636 <td>DEV_MCU_DCC0_DCC_CLKSRC5_CLK</td>
8637 <td>Input clock</td>
8638 </tr>
8639 <tr class="row-even"><td>6</td>
8640 <td>DEV_MCU_DCC0_DCC_CLKSRC6_CLK</td>
8641 <td>Input clock</td>
8642 </tr>
8643 <tr class="row-odd"><td>7</td>
8644 <td>DEV_MCU_DCC0_DCC_CLKSRC7_CLK</td>
8645 <td>Input clock</td>
8646 </tr>
8647 <tr class="row-even"><td>8</td>
8648 <td>DEV_MCU_DCC0_DCC_INPUT00_CLK</td>
8649 <td>Input clock</td>
8650 </tr>
8651 <tr class="row-odd"><td>9</td>
8652 <td>DEV_MCU_DCC0_DCC_INPUT01_CLK</td>
8653 <td>Input clock</td>
8654 </tr>
8655 <tr class="row-even"><td>10</td>
8656 <td>DEV_MCU_DCC0_DCC_INPUT02_CLK</td>
8657 <td>Input clock</td>
8658 </tr>
8659 <tr class="row-odd"><td>11</td>
8660 <td>DEV_MCU_DCC0_DCC_INPUT10_CLK</td>
8661 <td>Input clock</td>
8662 </tr>
8663 <tr class="row-even"><td>12</td>
8664 <td>DEV_MCU_DCC0_VBUS_CLK</td>
8665 <td>Input clock</td>
8666 </tr>
8667 </tbody>
8668 </table>
8669 </div>
8670 <div class="section" id="clocks-for-mcu-dcc1-device">
8671 <span id="soc-doc-j784s4-public-clks-mcu-dcc1"></span><h3>Clocks for MCU_DCC1 Device<a class="headerlink" href="#clocks-for-mcu-dcc1-device" title="Permalink to this headline">¶</a></h3>
8672 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_DCC1</span></a> (ID = 89)</p>
8673 <p>Following is a mapping of Clocks IDs to function:</p>
8674 <table border="1" class="docutils">
8675 <colgroup>
8676 <col width="22%" />
8677 <col width="55%" />
8678 <col width="24%" />
8679 </colgroup>
8680 <thead valign="bottom">
8681 <tr class="row-odd"><th class="head">Clock ID</th>
8682 <th class="head">Name</th>
8683 <th class="head">Function</th>
8684 </tr>
8685 </thead>
8686 <tbody valign="top">
8687 <tr class="row-even"><td>0</td>
8688 <td>DEV_MCU_DCC1_DCC_CLKSRC0_CLK</td>
8689 <td>Input clock</td>
8690 </tr>
8691 <tr class="row-odd"><td>1</td>
8692 <td>DEV_MCU_DCC1_DCC_CLKSRC1_CLK</td>
8693 <td>Input clock</td>
8694 </tr>
8695 <tr class="row-even"><td>2</td>
8696 <td>DEV_MCU_DCC1_DCC_CLKSRC2_CLK</td>
8697 <td>Input clock</td>
8698 </tr>
8699 <tr class="row-odd"><td>3</td>
8700 <td>DEV_MCU_DCC1_DCC_CLKSRC3_CLK</td>
8701 <td>Input clock</td>
8702 </tr>
8703 <tr class="row-even"><td>4</td>
8704 <td>DEV_MCU_DCC1_DCC_CLKSRC4_CLK</td>
8705 <td>Input clock</td>
8706 </tr>
8707 <tr class="row-odd"><td>5</td>
8708 <td>DEV_MCU_DCC1_DCC_CLKSRC5_CLK</td>
8709 <td>Input clock</td>
8710 </tr>
8711 <tr class="row-even"><td>6</td>
8712 <td>DEV_MCU_DCC1_DCC_CLKSRC6_CLK</td>
8713 <td>Input clock</td>
8714 </tr>
8715 <tr class="row-odd"><td>7</td>
8716 <td>DEV_MCU_DCC1_DCC_CLKSRC7_CLK</td>
8717 <td>Input clock</td>
8718 </tr>
8719 <tr class="row-even"><td>8</td>
8720 <td>DEV_MCU_DCC1_DCC_INPUT00_CLK</td>
8721 <td>Input clock</td>
8722 </tr>
8723 <tr class="row-odd"><td>9</td>
8724 <td>DEV_MCU_DCC1_DCC_INPUT01_CLK</td>
8725 <td>Input clock</td>
8726 </tr>
8727 <tr class="row-even"><td>10</td>
8728 <td>DEV_MCU_DCC1_DCC_INPUT02_CLK</td>
8729 <td>Input clock</td>
8730 </tr>
8731 <tr class="row-odd"><td>11</td>
8732 <td>DEV_MCU_DCC1_DCC_INPUT10_CLK</td>
8733 <td>Input clock</td>
8734 </tr>
8735 <tr class="row-even"><td>12</td>
8736 <td>DEV_MCU_DCC1_VBUS_CLK</td>
8737 <td>Input clock</td>
8738 </tr>
8739 </tbody>
8740 </table>
8741 </div>
8742 <div class="section" id="clocks-for-mcu-dcc2-device">
8743 <span id="soc-doc-j784s4-public-clks-mcu-dcc2"></span><h3>Clocks for MCU_DCC2 Device<a class="headerlink" href="#clocks-for-mcu-dcc2-device" title="Permalink to this headline">¶</a></h3>
8744 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_DCC2</span></a> (ID = 90)</p>
8745 <p>Following is a mapping of Clocks IDs to function:</p>
8746 <table border="1" class="docutils">
8747 <colgroup>
8748 <col width="22%" />
8749 <col width="55%" />
8750 <col width="24%" />
8751 </colgroup>
8752 <thead valign="bottom">
8753 <tr class="row-odd"><th class="head">Clock ID</th>
8754 <th class="head">Name</th>
8755 <th class="head">Function</th>
8756 </tr>
8757 </thead>
8758 <tbody valign="top">
8759 <tr class="row-even"><td>0</td>
8760 <td>DEV_MCU_DCC2_DCC_CLKSRC0_CLK</td>
8761 <td>Input clock</td>
8762 </tr>
8763 <tr class="row-odd"><td>1</td>
8764 <td>DEV_MCU_DCC2_DCC_CLKSRC1_CLK</td>
8765 <td>Input clock</td>
8766 </tr>
8767 <tr class="row-even"><td>2</td>
8768 <td>DEV_MCU_DCC2_DCC_CLKSRC2_CLK</td>
8769 <td>Input clock</td>
8770 </tr>
8771 <tr class="row-odd"><td>3</td>
8772 <td>DEV_MCU_DCC2_DCC_CLKSRC3_CLK</td>
8773 <td>Input clock</td>
8774 </tr>
8775 <tr class="row-even"><td>4</td>
8776 <td>DEV_MCU_DCC2_DCC_CLKSRC4_CLK</td>
8777 <td>Input clock</td>
8778 </tr>
8779 <tr class="row-odd"><td>6</td>
8780 <td>DEV_MCU_DCC2_DCC_CLKSRC6_CLK</td>
8781 <td>Input clock</td>
8782 </tr>
8783 <tr class="row-even"><td>7</td>
8784 <td>DEV_MCU_DCC2_DCC_CLKSRC7_CLK</td>
8785 <td>Input clock</td>
8786 </tr>
8787 <tr class="row-odd"><td>8</td>
8788 <td>DEV_MCU_DCC2_DCC_INPUT00_CLK</td>
8789 <td>Input clock</td>
8790 </tr>
8791 <tr class="row-even"><td>9</td>
8792 <td>DEV_MCU_DCC2_DCC_INPUT01_CLK</td>
8793 <td>Input clock</td>
8794 </tr>
8795 <tr class="row-odd"><td>10</td>
8796 <td>DEV_MCU_DCC2_DCC_INPUT02_CLK</td>
8797 <td>Input clock</td>
8798 </tr>
8799 <tr class="row-even"><td>11</td>
8800 <td>DEV_MCU_DCC2_DCC_INPUT10_CLK</td>
8801 <td>Input clock</td>
8802 </tr>
8803 <tr class="row-odd"><td>12</td>
8804 <td>DEV_MCU_DCC2_VBUS_CLK</td>
8805 <td>Input clock</td>
8806 </tr>
8807 </tbody>
8808 </table>
8809 </div>
8810 <div class="section" id="clocks-for-mcu-esm0-device">
8811 <span id="soc-doc-j784s4-public-clks-mcu-esm0"></span><h3>Clocks for MCU_ESM0 Device<a class="headerlink" href="#clocks-for-mcu-esm0-device" title="Permalink to this headline">¶</a></h3>
8812 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_ESM0</span></a> (ID = 148)</p>
8813 <p>Following is a mapping of Clocks IDs to function:</p>
8814 <table border="1" class="docutils">
8815 <colgroup>
8816 <col width="28%" />
8817 <col width="42%" />
8818 <col width="30%" />
8819 </colgroup>
8820 <thead valign="bottom">
8821 <tr class="row-odd"><th class="head">Clock ID</th>
8822 <th class="head">Name</th>
8823 <th class="head">Function</th>
8824 </tr>
8825 </thead>
8826 <tbody valign="top">
8827 <tr class="row-even"><td>0</td>
8828 <td>DEV_MCU_ESM0_CLK</td>
8829 <td>Input clock</td>
8830 </tr>
8831 </tbody>
8832 </table>
8833 </div>
8834 <div class="section" id="clocks-for-mcu-fss0-device">
8835 <span id="soc-doc-j784s4-public-clks-mcu-fss0"></span><h3>Clocks for MCU_FSS0 Device<a class="headerlink" href="#clocks-for-mcu-fss0-device" title="Permalink to this headline">¶</a></h3>
8836 <p><strong>This device has no defined clocks.</strong></p>
8837 </div>
8838 <div class="section" id="clocks-for-mcu-fss0-fsas-0-device">
8839 <span id="soc-doc-j784s4-public-clks-mcu-fss0-fsas-0"></span><h3>Clocks for MCU_FSS0_FSAS_0 Device<a class="headerlink" href="#clocks-for-mcu-fss0-fsas-0-device" title="Permalink to this headline">¶</a></h3>
8840 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_FSS0_FSAS_0</span></a> (ID = 158)</p>
8841 <p>Following is a mapping of Clocks IDs to function:</p>
8842 <table border="1" class="docutils">
8843 <colgroup>
8844 <col width="24%" />
8845 <col width="51%" />
8846 <col width="25%" />
8847 </colgroup>
8848 <thead valign="bottom">
8849 <tr class="row-odd"><th class="head">Clock ID</th>
8850 <th class="head">Name</th>
8851 <th class="head">Function</th>
8852 </tr>
8853 </thead>
8854 <tbody valign="top">
8855 <tr class="row-even"><td>0</td>
8856 <td>DEV_MCU_FSS0_FSAS_0_GCLK</td>
8857 <td>Input clock</td>
8858 </tr>
8859 </tbody>
8860 </table>
8861 </div>
8862 <div class="section" id="clocks-for-mcu-fss0-hyperbus1p0-0-device">
8863 <span id="soc-doc-j784s4-public-clks-mcu-fss0-hyperbus1p0-0"></span><h3>Clocks for MCU_FSS0_HYPERBUS1P0_0 Device<a class="headerlink" href="#clocks-for-mcu-fss0-hyperbus1p0-0-device" title="Permalink to this headline">¶</a></h3>
8864 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_FSS0_HYPERBUS1P0_0</span></a> (ID = 160)</p>
8865 <p>Following is a mapping of Clocks IDs to function:</p>
8866 <table border="1" class="docutils">
8867 <colgroup>
8868 <col width="17%" />
8869 <col width="64%" />
8870 <col width="19%" />
8871 </colgroup>
8872 <thead valign="bottom">
8873 <tr class="row-odd"><th class="head">Clock ID</th>
8874 <th class="head">Name</th>
8875 <th class="head">Function</th>
8876 </tr>
8877 </thead>
8878 <tbody valign="top">
8879 <tr class="row-even"><td>0</td>
8880 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK</td>
8881 <td>Input clock</td>
8882 </tr>
8883 <tr class="row-odd"><td>2</td>
8884 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK</td>
8885 <td>Input clock</td>
8886 </tr>
8887 <tr class="row-even"><td>4</td>
8888 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK</td>
8889 <td>Input clock</td>
8890 </tr>
8891 <tr class="row-odd"><td>6</td>
8892 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK</td>
8893 <td>Input clock</td>
8894 </tr>
8895 <tr class="row-even"><td>8</td>
8896 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK</td>
8897 <td>Input clock</td>
8898 </tr>
8899 <tr class="row-odd"><td>10</td>
8900 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N</td>
8901 <td>Output clock</td>
8902 </tr>
8903 <tr class="row-even"><td>11</td>
8904 <td>DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P</td>
8905 <td>Output clock</td>
8906 </tr>
8907 </tbody>
8908 </table>
8909 </div>
8910 <div class="section" id="clocks-for-mcu-fss0-ospi-0-device">
8911 <span id="soc-doc-j784s4-public-clks-mcu-fss0-ospi-0"></span><h3>Clocks for MCU_FSS0_OSPI_0 Device<a class="headerlink" href="#clocks-for-mcu-fss0-ospi-0-device" title="Permalink to this headline">¶</a></h3>
8912 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_FSS0_OSPI_0</span></a> (ID = 161)</p>
8913 <p>Following is a mapping of Clocks IDs to function:</p>
8914 <table border="1" class="docutils">
8915 <colgroup>
8916 <col width="8%" />
8917 <col width="50%" />
8918 <col width="42%" />
8919 </colgroup>
8920 <thead valign="bottom">
8921 <tr class="row-odd"><th class="head">Clock ID</th>
8922 <th class="head">Name</th>
8923 <th class="head">Function</th>
8924 </tr>
8925 </thead>
8926 <tbody valign="top">
8927 <tr class="row-even"><td>0</td>
8928 <td>DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK</td>
8929 <td>Input clock</td>
8930 </tr>
8931 <tr class="row-odd"><td>1</td>
8932 <td>DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK</td>
8933 <td>Input clock</td>
8934 </tr>
8935 <tr class="row-even"><td>2</td>
8936 <td>DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK</td>
8937 <td>Input muxed clock</td>
8938 </tr>
8939 <tr class="row-odd"><td>3</td>
8940 <td>DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT</td>
8941 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK</td>
8942 </tr>
8943 <tr class="row-even"><td>4</td>
8944 <td>DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK</td>
8945 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK</td>
8946 </tr>
8947 <tr class="row-odd"><td>5</td>
8948 <td>DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK</td>
8949 <td>Output clock</td>
8950 </tr>
8951 <tr class="row-even"><td>6</td>
8952 <td>DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK</td>
8953 <td>Input clock</td>
8954 </tr>
8955 <tr class="row-odd"><td>7</td>
8956 <td>DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK</td>
8957 <td>Input muxed clock</td>
8958 </tr>
8959 <tr class="row-even"><td>8</td>
8960 <td>DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK</td>
8961 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK</td>
8962 </tr>
8963 <tr class="row-odd"><td>9</td>
8964 <td>DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK</td>
8965 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK</td>
8966 </tr>
8967 </tbody>
8968 </table>
8969 </div>
8970 <div class="section" id="clocks-for-mcu-fss0-ospi-1-device">
8971 <span id="soc-doc-j784s4-public-clks-mcu-fss0-ospi-1"></span><h3>Clocks for MCU_FSS0_OSPI_1 Device<a class="headerlink" href="#clocks-for-mcu-fss0-ospi-1-device" title="Permalink to this headline">¶</a></h3>
8972 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_FSS0_OSPI_1</span></a> (ID = 162)</p>
8973 <p>Following is a mapping of Clocks IDs to function:</p>
8974 <table border="1" class="docutils">
8975 <colgroup>
8976 <col width="8%" />
8977 <col width="50%" />
8978 <col width="42%" />
8979 </colgroup>
8980 <thead valign="bottom">
8981 <tr class="row-odd"><th class="head">Clock ID</th>
8982 <th class="head">Name</th>
8983 <th class="head">Function</th>
8984 </tr>
8985 </thead>
8986 <tbody valign="top">
8987 <tr class="row-even"><td>0</td>
8988 <td>DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK</td>
8989 <td>Input clock</td>
8990 </tr>
8991 <tr class="row-odd"><td>1</td>
8992 <td>DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK</td>
8993 <td>Input clock</td>
8994 </tr>
8995 <tr class="row-even"><td>2</td>
8996 <td>DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK</td>
8997 <td>Input muxed clock</td>
8998 </tr>
8999 <tr class="row-odd"><td>3</td>
9000 <td>DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT</td>
9001 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK</td>
9002 </tr>
9003 <tr class="row-even"><td>4</td>
9004 <td>DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK</td>
9005 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK</td>
9006 </tr>
9007 <tr class="row-odd"><td>5</td>
9008 <td>DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK</td>
9009 <td>Output clock</td>
9010 </tr>
9011 <tr class="row-even"><td>6</td>
9012 <td>DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK</td>
9013 <td>Input clock</td>
9014 </tr>
9015 <tr class="row-odd"><td>7</td>
9016 <td>DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK</td>
9017 <td>Input muxed clock</td>
9018 </tr>
9019 <tr class="row-even"><td>8</td>
9020 <td>DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK</td>
9021 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK</td>
9022 </tr>
9023 <tr class="row-odd"><td>9</td>
9024 <td>DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK</td>
9025 <td>Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK</td>
9026 </tr>
9027 </tbody>
9028 </table>
9029 </div>
9030 <div class="section" id="clocks-for-mcu-i2c0-device">
9031 <span id="soc-doc-j784s4-public-clks-mcu-i2c0"></span><h3>Clocks for MCU_I2C0 Device<a class="headerlink" href="#clocks-for-mcu-i2c0-device" title="Permalink to this headline">¶</a></h3>
9032 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_I2C0</span></a> (ID = 277)</p>
9033 <p>Following is a mapping of Clocks IDs to function:</p>
9034 <table border="1" class="docutils">
9035 <colgroup>
9036 <col width="24%" />
9037 <col width="48%" />
9038 <col width="28%" />
9039 </colgroup>
9040 <thead valign="bottom">
9041 <tr class="row-odd"><th class="head">Clock ID</th>
9042 <th class="head">Name</th>
9043 <th class="head">Function</th>
9044 </tr>
9045 </thead>
9046 <tbody valign="top">
9047 <tr class="row-even"><td>0</td>
9048 <td>DEV_MCU_I2C0_CLK</td>
9049 <td>Input clock</td>
9050 </tr>
9051 <tr class="row-odd"><td>1</td>
9052 <td>DEV_MCU_I2C0_PISCL</td>
9053 <td>Input clock</td>
9054 </tr>
9055 <tr class="row-even"><td>2</td>
9056 <td>DEV_MCU_I2C0_PISYS_CLK</td>
9057 <td>Input clock</td>
9058 </tr>
9059 <tr class="row-odd"><td>3</td>
9060 <td>DEV_MCU_I2C0_PORSCL</td>
9061 <td>Output clock</td>
9062 </tr>
9063 </tbody>
9064 </table>
9065 </div>
9066 <div class="section" id="clocks-for-mcu-i2c1-device">
9067 <span id="soc-doc-j784s4-public-clks-mcu-i2c1"></span><h3>Clocks for MCU_I2C1 Device<a class="headerlink" href="#clocks-for-mcu-i2c1-device" title="Permalink to this headline">¶</a></h3>
9068 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_I2C1</span></a> (ID = 278)</p>
9069 <p>Following is a mapping of Clocks IDs to function:</p>
9070 <table border="1" class="docutils">
9071 <colgroup>
9072 <col width="24%" />
9073 <col width="48%" />
9074 <col width="28%" />
9075 </colgroup>
9076 <thead valign="bottom">
9077 <tr class="row-odd"><th class="head">Clock ID</th>
9078 <th class="head">Name</th>
9079 <th class="head">Function</th>
9080 </tr>
9081 </thead>
9082 <tbody valign="top">
9083 <tr class="row-even"><td>0</td>
9084 <td>DEV_MCU_I2C1_CLK</td>
9085 <td>Input clock</td>
9086 </tr>
9087 <tr class="row-odd"><td>1</td>
9088 <td>DEV_MCU_I2C1_PISCL</td>
9089 <td>Input clock</td>
9090 </tr>
9091 <tr class="row-even"><td>2</td>
9092 <td>DEV_MCU_I2C1_PISYS_CLK</td>
9093 <td>Input clock</td>
9094 </tr>
9095 <tr class="row-odd"><td>3</td>
9096 <td>DEV_MCU_I2C1_PORSCL</td>
9097 <td>Output clock</td>
9098 </tr>
9099 </tbody>
9100 </table>
9101 </div>
9102 <div class="section" id="clocks-for-mcu-i3c0-device">
9103 <span id="soc-doc-j784s4-public-clks-mcu-i3c0"></span><h3>Clocks for MCU_I3C0 Device<a class="headerlink" href="#clocks-for-mcu-i3c0-device" title="Permalink to this headline">¶</a></h3>
9104 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_I3C0</span></a> (ID = 170)</p>
9105 <p>Following is a mapping of Clocks IDs to function:</p>
9106 <table border="1" class="docutils">
9107 <colgroup>
9108 <col width="23%" />
9109 <col width="51%" />
9110 <col width="26%" />
9111 </colgroup>
9112 <thead valign="bottom">
9113 <tr class="row-odd"><th class="head">Clock ID</th>
9114 <th class="head">Name</th>
9115 <th class="head">Function</th>
9116 </tr>
9117 </thead>
9118 <tbody valign="top">
9119 <tr class="row-even"><td>0</td>
9120 <td>DEV_MCU_I3C0_I3C_PCLK_CLK</td>
9121 <td>Input clock</td>
9122 </tr>
9123 <tr class="row-odd"><td>1</td>
9124 <td>DEV_MCU_I3C0_I3C_SCL_DI</td>
9125 <td>Input clock</td>
9126 </tr>
9127 <tr class="row-even"><td>2</td>
9128 <td>DEV_MCU_I3C0_I3C_SCL_DO</td>
9129 <td>Output clock</td>
9130 </tr>
9131 <tr class="row-odd"><td>3</td>
9132 <td>DEV_MCU_I3C0_I3C_SCLK_CLK</td>
9133 <td>Input clock</td>
9134 </tr>
9135 <tr class="row-even"><td>4</td>
9136 <td>DEV_MCU_I3C0_I3C_SDA_DI</td>
9137 <td>Input clock</td>
9138 </tr>
9139 </tbody>
9140 </table>
9141 </div>
9142 <div class="section" id="clocks-for-mcu-i3c1-device">
9143 <span id="soc-doc-j784s4-public-clks-mcu-i3c1"></span><h3>Clocks for MCU_I3C1 Device<a class="headerlink" href="#clocks-for-mcu-i3c1-device" title="Permalink to this headline">¶</a></h3>
9144 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_I3C1</span></a> (ID = 171)</p>
9145 <p>Following is a mapping of Clocks IDs to function:</p>
9146 <table border="1" class="docutils">
9147 <colgroup>
9148 <col width="23%" />
9149 <col width="52%" />
9150 <col width="25%" />
9151 </colgroup>
9152 <thead valign="bottom">
9153 <tr class="row-odd"><th class="head">Clock ID</th>
9154 <th class="head">Name</th>
9155 <th class="head">Function</th>
9156 </tr>
9157 </thead>
9158 <tbody valign="top">
9159 <tr class="row-even"><td>0</td>
9160 <td>DEV_MCU_I3C1_I3C_PCLK_CLK</td>
9161 <td>Input clock</td>
9162 </tr>
9163 <tr class="row-odd"><td>3</td>
9164 <td>DEV_MCU_I3C1_I3C_SCLK_CLK</td>
9165 <td>Input clock</td>
9166 </tr>
9167 </tbody>
9168 </table>
9169 </div>
9170 <div class="section" id="clocks-for-mcu-mcan0-device">
9171 <span id="soc-doc-j784s4-public-clks-mcu-mcan0"></span><h3>Clocks for MCU_MCAN0 Device<a class="headerlink" href="#clocks-for-mcu-mcan0-device" title="Permalink to this headline">¶</a></h3>
9172 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_MCAN0</span></a> (ID = 263)</p>
9173 <p>Following is a mapping of Clocks IDs to function:</p>
9174 <table border="1" class="docutils">
9175 <colgroup>
9176 <col width="8%" />
9177 <col width="50%" />
9178 <col width="42%" />
9179 </colgroup>
9180 <thead valign="bottom">
9181 <tr class="row-odd"><th class="head">Clock ID</th>
9182 <th class="head">Name</th>
9183 <th class="head">Function</th>
9184 </tr>
9185 </thead>
9186 <tbody valign="top">
9187 <tr class="row-even"><td>0</td>
9188 <td>DEV_MCU_MCAN0_MCANSS_CAN_RXD</td>
9189 <td>Input clock</td>
9190 </tr>
9191 <tr class="row-odd"><td>1</td>
9192 <td>DEV_MCU_MCAN0_MCANSS_CCLK_CLK</td>
9193 <td>Input muxed clock</td>
9194 </tr>
9195 <tr class="row-even"><td>2</td>
9196 <td>DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK</td>
9197 <td>Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK</td>
9198 </tr>
9199 <tr class="row-odd"><td>3</td>
9200 <td>DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
9201 <td>Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK</td>
9202 </tr>
9203 <tr class="row-even"><td>4</td>
9204 <td>DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK</td>
9205 <td>Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK</td>
9206 </tr>
9207 <tr class="row-odd"><td>5</td>
9208 <td>DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9209 <td>Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK</td>
9210 </tr>
9211 <tr class="row-even"><td>6</td>
9212 <td>DEV_MCU_MCAN0_MCANSS_HCLK_CLK</td>
9213 <td>Input clock</td>
9214 </tr>
9215 </tbody>
9216 </table>
9217 </div>
9218 <div class="section" id="clocks-for-mcu-mcan1-device">
9219 <span id="soc-doc-j784s4-public-clks-mcu-mcan1"></span><h3>Clocks for MCU_MCAN1 Device<a class="headerlink" href="#clocks-for-mcu-mcan1-device" title="Permalink to this headline">¶</a></h3>
9220 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_MCAN1</span></a> (ID = 264)</p>
9221 <p>Following is a mapping of Clocks IDs to function:</p>
9222 <table border="1" class="docutils">
9223 <colgroup>
9224 <col width="8%" />
9225 <col width="50%" />
9226 <col width="42%" />
9227 </colgroup>
9228 <thead valign="bottom">
9229 <tr class="row-odd"><th class="head">Clock ID</th>
9230 <th class="head">Name</th>
9231 <th class="head">Function</th>
9232 </tr>
9233 </thead>
9234 <tbody valign="top">
9235 <tr class="row-even"><td>0</td>
9236 <td>DEV_MCU_MCAN1_MCANSS_CAN_RXD</td>
9237 <td>Input clock</td>
9238 </tr>
9239 <tr class="row-odd"><td>1</td>
9240 <td>DEV_MCU_MCAN1_MCANSS_CCLK_CLK</td>
9241 <td>Input muxed clock</td>
9242 </tr>
9243 <tr class="row-even"><td>2</td>
9244 <td>DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK</td>
9245 <td>Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK</td>
9246 </tr>
9247 <tr class="row-odd"><td>3</td>
9248 <td>DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
9249 <td>Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK</td>
9250 </tr>
9251 <tr class="row-even"><td>4</td>
9252 <td>DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK</td>
9253 <td>Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK</td>
9254 </tr>
9255 <tr class="row-odd"><td>5</td>
9256 <td>DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9257 <td>Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK</td>
9258 </tr>
9259 <tr class="row-even"><td>6</td>
9260 <td>DEV_MCU_MCAN1_MCANSS_HCLK_CLK</td>
9261 <td>Input clock</td>
9262 </tr>
9263 </tbody>
9264 </table>
9265 </div>
9266 <div class="section" id="clocks-for-mcu-mcspi0-device">
9267 <span id="soc-doc-j784s4-public-clks-mcu-mcspi0"></span><h3>Clocks for MCU_MCSPI0 Device<a class="headerlink" href="#clocks-for-mcu-mcspi0-device" title="Permalink to this headline">¶</a></h3>
9268 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_MCSPI0</span></a> (ID = 384)</p>
9269 <p>Following is a mapping of Clocks IDs to function:</p>
9270 <table border="1" class="docutils">
9271 <colgroup>
9272 <col width="9%" />
9273 <col width="47%" />
9274 <col width="44%" />
9275 </colgroup>
9276 <thead valign="bottom">
9277 <tr class="row-odd"><th class="head">Clock ID</th>
9278 <th class="head">Name</th>
9279 <th class="head">Function</th>
9280 </tr>
9281 </thead>
9282 <tbody valign="top">
9283 <tr class="row-even"><td>0</td>
9284 <td>DEV_MCU_MCSPI0_CLKSPIREF_CLK</td>
9285 <td>Input clock</td>
9286 </tr>
9287 <tr class="row-odd"><td>1</td>
9288 <td>DEV_MCU_MCSPI0_IO_CLKSPII_CLK</td>
9289 <td>Input muxed clock</td>
9290 </tr>
9291 <tr class="row-even"><td>2</td>
9292 <td>DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT</td>
9293 <td>Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK</td>
9294 </tr>
9295 <tr class="row-odd"><td>3</td>
9296 <td>DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK</td>
9297 <td>Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK</td>
9298 </tr>
9299 <tr class="row-even"><td>4</td>
9300 <td>DEV_MCU_MCSPI0_IO_CLKSPIO_CLK</td>
9301 <td>Output clock</td>
9302 </tr>
9303 <tr class="row-odd"><td>5</td>
9304 <td>DEV_MCU_MCSPI0_VBUSP_CLK</td>
9305 <td>Input clock</td>
9306 </tr>
9307 </tbody>
9308 </table>
9309 </div>
9310 <div class="section" id="clocks-for-mcu-mcspi1-device">
9311 <span id="soc-doc-j784s4-public-clks-mcu-mcspi1"></span><h3>Clocks for MCU_MCSPI1 Device<a class="headerlink" href="#clocks-for-mcu-mcspi1-device" title="Permalink to this headline">¶</a></h3>
9312 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_MCSPI1</span></a> (ID = 385)</p>
9313 <p>Following is a mapping of Clocks IDs to function:</p>
9314 <table border="1" class="docutils">
9315 <colgroup>
9316 <col width="9%" />
9317 <col width="47%" />
9318 <col width="44%" />
9319 </colgroup>
9320 <thead valign="bottom">
9321 <tr class="row-odd"><th class="head">Clock ID</th>
9322 <th class="head">Name</th>
9323 <th class="head">Function</th>
9324 </tr>
9325 </thead>
9326 <tbody valign="top">
9327 <tr class="row-even"><td>0</td>
9328 <td>DEV_MCU_MCSPI1_CLKSPIREF_CLK</td>
9329 <td>Input clock</td>
9330 </tr>
9331 <tr class="row-odd"><td>1</td>
9332 <td>DEV_MCU_MCSPI1_IO_CLKSPII_CLK</td>
9333 <td>Input muxed clock</td>
9334 </tr>
9335 <tr class="row-even"><td>2</td>
9336 <td>DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK</td>
9337 <td>Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK</td>
9338 </tr>
9339 <tr class="row-odd"><td>3</td>
9340 <td>DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_MCU_SPI1_CLK_LPBK_MUX_OUT0</td>
9341 <td>Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK</td>
9342 </tr>
9343 <tr class="row-even"><td>4</td>
9344 <td>DEV_MCU_MCSPI1_IO_CLKSPIO_CLK</td>
9345 <td>Output clock</td>
9346 </tr>
9347 <tr class="row-odd"><td>5</td>
9348 <td>DEV_MCU_MCSPI1_VBUSP_CLK</td>
9349 <td>Input clock</td>
9350 </tr>
9351 </tbody>
9352 </table>
9353 </div>
9354 <div class="section" id="clocks-for-mcu-mcspi2-device">
9355 <span id="soc-doc-j784s4-public-clks-mcu-mcspi2"></span><h3>Clocks for MCU_MCSPI2 Device<a class="headerlink" href="#clocks-for-mcu-mcspi2-device" title="Permalink to this headline">¶</a></h3>
9356 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_MCSPI2</span></a> (ID = 386)</p>
9357 <p>Following is a mapping of Clocks IDs to function:</p>
9358 <table border="1" class="docutils">
9359 <colgroup>
9360 <col width="21%" />
9361 <col width="54%" />
9362 <col width="25%" />
9363 </colgroup>
9364 <thead valign="bottom">
9365 <tr class="row-odd"><th class="head">Clock ID</th>
9366 <th class="head">Name</th>
9367 <th class="head">Function</th>
9368 </tr>
9369 </thead>
9370 <tbody valign="top">
9371 <tr class="row-even"><td>0</td>
9372 <td>DEV_MCU_MCSPI2_CLKSPIREF_CLK</td>
9373 <td>Input clock</td>
9374 </tr>
9375 <tr class="row-odd"><td>1</td>
9376 <td>DEV_MCU_MCSPI2_IO_CLKSPII_CLK</td>
9377 <td>Input clock</td>
9378 </tr>
9379 <tr class="row-even"><td>2</td>
9380 <td>DEV_MCU_MCSPI2_IO_CLKSPIO_CLK</td>
9381 <td>Output clock</td>
9382 </tr>
9383 <tr class="row-odd"><td>3</td>
9384 <td>DEV_MCU_MCSPI2_VBUSP_CLK</td>
9385 <td>Input clock</td>
9386 </tr>
9387 </tbody>
9388 </table>
9389 </div>
9390 <div class="section" id="clocks-for-mcu-navss0-device">
9391 <span id="soc-doc-j784s4-public-clks-mcu-navss0"></span><h3>Clocks for MCU_NAVSS0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-device" title="Permalink to this headline">¶</a></h3>
9392 <p><strong>This device has no defined clocks.</strong></p>
9393 </div>
9394 <div class="section" id="clocks-for-mcu-navss0-intr-router-0-device">
9395 <span id="soc-doc-j784s4-public-clks-mcu-navss0-intr-router-0"></span><h3>Clocks for MCU_NAVSS0_INTR_ROUTER_0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-intr-router-0-device" title="Permalink to this headline">¶</a></h3>
9396 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_NAVSS0_INTR_ROUTER_0</span></a> (ID = 324)</p>
9397 <p>Following is a mapping of Clocks IDs to function:</p>
9398 <table border="1" class="docutils">
9399 <colgroup>
9400 <col width="19%" />
9401 <col width="61%" />
9402 <col width="20%" />
9403 </colgroup>
9404 <thead valign="bottom">
9405 <tr class="row-odd"><th class="head">Clock ID</th>
9406 <th class="head">Name</th>
9407 <th class="head">Function</th>
9408 </tr>
9409 </thead>
9410 <tbody valign="top">
9411 <tr class="row-even"><td>0</td>
9412 <td>DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK</td>
9413 <td>Input clock</td>
9414 </tr>
9415 </tbody>
9416 </table>
9417 </div>
9418 <div class="section" id="clocks-for-mcu-navss0-mcrc-0-device">
9419 <span id="soc-doc-j784s4-public-clks-mcu-navss0-mcrc-0"></span><h3>Clocks for MCU_NAVSS0_MCRC_0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-mcrc-0-device" title="Permalink to this headline">¶</a></h3>
9420 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_NAVSS0_MCRC_0</span></a> (ID = 325)</p>
9421 <p>Following is a mapping of Clocks IDs to function:</p>
9422 <table border="1" class="docutils">
9423 <colgroup>
9424 <col width="23%" />
9425 <col width="52%" />
9426 <col width="25%" />
9427 </colgroup>
9428 <thead valign="bottom">
9429 <tr class="row-odd"><th class="head">Clock ID</th>
9430 <th class="head">Name</th>
9431 <th class="head">Function</th>
9432 </tr>
9433 </thead>
9434 <tbody valign="top">
9435 <tr class="row-even"><td>0</td>
9436 <td>DEV_MCU_NAVSS0_MCRC_0_CLK</td>
9437 <td>Input clock</td>
9438 </tr>
9439 </tbody>
9440 </table>
9441 </div>
9442 <div class="section" id="clocks-for-mcu-navss0-modss-device">
9443 <span id="soc-doc-j784s4-public-clks-mcu-navss0-modss"></span><h3>Clocks for MCU_NAVSS0_MODSS Device<a class="headerlink" href="#clocks-for-mcu-navss0-modss-device" title="Permalink to this headline">¶</a></h3>
9444 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_NAVSS0_MODSS</span></a> (ID = 326)</p>
9445 <p>Following is a mapping of Clocks IDs to function:</p>
9446 <table border="1" class="docutils">
9447 <colgroup>
9448 <col width="22%" />
9449 <col width="54%" />
9450 <col width="24%" />
9451 </colgroup>
9452 <thead valign="bottom">
9453 <tr class="row-odd"><th class="head">Clock ID</th>
9454 <th class="head">Name</th>
9455 <th class="head">Function</th>
9456 </tr>
9457 </thead>
9458 <tbody valign="top">
9459 <tr class="row-even"><td>0</td>
9460 <td>DEV_MCU_NAVSS0_MODSS_VD2CLK</td>
9461 <td>Input clock</td>
9462 </tr>
9463 </tbody>
9464 </table>
9465 </div>
9466 <div class="section" id="clocks-for-mcu-navss0-proxy0-device">
9467 <span id="soc-doc-j784s4-public-clks-mcu-navss0-proxy0"></span><h3>Clocks for MCU_NAVSS0_PROXY0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-proxy0-device" title="Permalink to this headline">¶</a></h3>
9468 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_NAVSS0_PROXY0</span></a> (ID = 327)</p>
9469 <p>Following is a mapping of Clocks IDs to function:</p>
9470 <table border="1" class="docutils">
9471 <colgroup>
9472 <col width="21%" />
9473 <col width="55%" />
9474 <col width="23%" />
9475 </colgroup>
9476 <thead valign="bottom">
9477 <tr class="row-odd"><th class="head">Clock ID</th>
9478 <th class="head">Name</th>
9479 <th class="head">Function</th>
9480 </tr>
9481 </thead>
9482 <tbody valign="top">
9483 <tr class="row-even"><td>0</td>
9484 <td>DEV_MCU_NAVSS0_PROXY0_CLK_CLK</td>
9485 <td>Input clock</td>
9486 </tr>
9487 </tbody>
9488 </table>
9489 </div>
9490 <div class="section" id="clocks-for-mcu-navss0-ringacc0-device">
9491 <span id="soc-doc-j784s4-public-clks-mcu-navss0-ringacc0"></span><h3>Clocks for MCU_NAVSS0_RINGACC0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-ringacc0-device" title="Permalink to this headline">¶</a></h3>
9492 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_NAVSS0_RINGACC0</span></a> (ID = 328)</p>
9493 <p>Following is a mapping of Clocks IDs to function:</p>
9494 <table border="1" class="docutils">
9495 <colgroup>
9496 <col width="21%" />
9497 <col width="57%" />
9498 <col width="22%" />
9499 </colgroup>
9500 <thead valign="bottom">
9501 <tr class="row-odd"><th class="head">Clock ID</th>
9502 <th class="head">Name</th>
9503 <th class="head">Function</th>
9504 </tr>
9505 </thead>
9506 <tbody valign="top">
9507 <tr class="row-even"><td>0</td>
9508 <td>DEV_MCU_NAVSS0_RINGACC0_SYS_CLK</td>
9509 <td>Input clock</td>
9510 </tr>
9511 </tbody>
9512 </table>
9513 </div>
9514 <div class="section" id="clocks-for-mcu-navss0-udmap-0-device">
9515 <span id="soc-doc-j784s4-public-clks-mcu-navss0-udmap-0"></span><h3>Clocks for MCU_NAVSS0_UDMAP_0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-udmap-0-device" title="Permalink to this headline">¶</a></h3>
9516 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_NAVSS0_UDMAP_0</span></a> (ID = 329)</p>
9517 <p>Following is a mapping of Clocks IDs to function:</p>
9518 <table border="1" class="docutils">
9519 <colgroup>
9520 <col width="21%" />
9521 <col width="56%" />
9522 <col width="23%" />
9523 </colgroup>
9524 <thead valign="bottom">
9525 <tr class="row-odd"><th class="head">Clock ID</th>
9526 <th class="head">Name</th>
9527 <th class="head">Function</th>
9528 </tr>
9529 </thead>
9530 <tbody valign="top">
9531 <tr class="row-even"><td>0</td>
9532 <td>DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK</td>
9533 <td>Input clock</td>
9534 </tr>
9535 </tbody>
9536 </table>
9537 </div>
9538 <div class="section" id="clocks-for-mcu-navss0-udmass-device">
9539 <span id="soc-doc-j784s4-public-clks-mcu-navss0-udmass"></span><h3>Clocks for MCU_NAVSS0_UDMASS Device<a class="headerlink" href="#clocks-for-mcu-navss0-udmass-device" title="Permalink to this headline">¶</a></h3>
9540 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_NAVSS0_UDMASS</span></a> (ID = 330)</p>
9541 <p>Following is a mapping of Clocks IDs to function:</p>
9542 <table border="1" class="docutils">
9543 <colgroup>
9544 <col width="22%" />
9545 <col width="55%" />
9546 <col width="24%" />
9547 </colgroup>
9548 <thead valign="bottom">
9549 <tr class="row-odd"><th class="head">Clock ID</th>
9550 <th class="head">Name</th>
9551 <th class="head">Function</th>
9552 </tr>
9553 </thead>
9554 <tbody valign="top">
9555 <tr class="row-even"><td>0</td>
9556 <td>DEV_MCU_NAVSS0_UDMASS_VD2CLK</td>
9557 <td>Input clock</td>
9558 </tr>
9559 </tbody>
9560 </table>
9561 </div>
9562 <div class="section" id="clocks-for-mcu-navss0-udmass-inta-0-device">
9563 <span id="soc-doc-j784s4-public-clks-mcu-navss0-udmass-inta-0"></span><h3>Clocks for MCU_NAVSS0_UDMASS_INTA_0 Device<a class="headerlink" href="#clocks-for-mcu-navss0-udmass-inta-0-device" title="Permalink to this headline">¶</a></h3>
9564 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0</span></a> (ID = 331)</p>
9565 <p>Following is a mapping of Clocks IDs to function:</p>
9566 <table border="1" class="docutils">
9567 <colgroup>
9568 <col width="19%" />
9569 <col width="60%" />
9570 <col width="21%" />
9571 </colgroup>
9572 <thead valign="bottom">
9573 <tr class="row-odd"><th class="head">Clock ID</th>
9574 <th class="head">Name</th>
9575 <th class="head">Function</th>
9576 </tr>
9577 </thead>
9578 <tbody valign="top">
9579 <tr class="row-even"><td>0</td>
9580 <td>DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK</td>
9581 <td>Input clock</td>
9582 </tr>
9583 </tbody>
9584 </table>
9585 </div>
9586 <div class="section" id="clocks-for-mcu-pbist0-device">
9587 <span id="soc-doc-j784s4-public-clks-mcu-pbist0"></span><h3>Clocks for MCU_PBIST0 Device<a class="headerlink" href="#clocks-for-mcu-pbist0-device" title="Permalink to this headline">¶</a></h3>
9588 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_PBIST0</span></a> (ID = 238)</p>
9589 <p>Following is a mapping of Clocks IDs to function:</p>
9590 <table border="1" class="docutils">
9591 <colgroup>
9592 <col width="24%" />
9593 <col width="50%" />
9594 <col width="26%" />
9595 </colgroup>
9596 <thead valign="bottom">
9597 <tr class="row-odd"><th class="head">Clock ID</th>
9598 <th class="head">Name</th>
9599 <th class="head">Function</th>
9600 </tr>
9601 </thead>
9602 <tbody valign="top">
9603 <tr class="row-even"><td>0</td>
9604 <td>DEV_MCU_PBIST0_CLK1_CLK</td>
9605 <td>Input clock</td>
9606 </tr>
9607 <tr class="row-odd"><td>1</td>
9608 <td>DEV_MCU_PBIST0_CLK2_CLK</td>
9609 <td>Input clock</td>
9610 </tr>
9611 <tr class="row-even"><td>2</td>
9612 <td>DEV_MCU_PBIST0_CLK3_CLK</td>
9613 <td>Input clock</td>
9614 </tr>
9615 <tr class="row-odd"><td>3</td>
9616 <td>DEV_MCU_PBIST0_CLK4_CLK</td>
9617 <td>Input clock</td>
9618 </tr>
9619 <tr class="row-even"><td>4</td>
9620 <td>DEV_MCU_PBIST0_CLK5_CLK</td>
9621 <td>Input clock</td>
9622 </tr>
9623 <tr class="row-odd"><td>5</td>
9624 <td>DEV_MCU_PBIST0_CLK6_CLK</td>
9625 <td>Input clock</td>
9626 </tr>
9627 <tr class="row-even"><td>6</td>
9628 <td>DEV_MCU_PBIST0_CLK7_CLK</td>
9629 <td>Input clock</td>
9630 </tr>
9631 <tr class="row-odd"><td>7</td>
9632 <td>DEV_MCU_PBIST0_CLK8_CLK</td>
9633 <td>Input clock</td>
9634 </tr>
9635 </tbody>
9636 </table>
9637 </div>
9638 <div class="section" id="clocks-for-mcu-pbist1-device">
9639 <span id="soc-doc-j784s4-public-clks-mcu-pbist1"></span><h3>Clocks for MCU_PBIST1 Device<a class="headerlink" href="#clocks-for-mcu-pbist1-device" title="Permalink to this headline">¶</a></h3>
9640 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_PBIST1</span></a> (ID = 239)</p>
9641 <p>Following is a mapping of Clocks IDs to function:</p>
9642 <table border="1" class="docutils">
9643 <colgroup>
9644 <col width="24%" />
9645 <col width="50%" />
9646 <col width="26%" />
9647 </colgroup>
9648 <thead valign="bottom">
9649 <tr class="row-odd"><th class="head">Clock ID</th>
9650 <th class="head">Name</th>
9651 <th class="head">Function</th>
9652 </tr>
9653 </thead>
9654 <tbody valign="top">
9655 <tr class="row-even"><td>0</td>
9656 <td>DEV_MCU_PBIST1_CLK1_CLK</td>
9657 <td>Input clock</td>
9658 </tr>
9659 <tr class="row-odd"><td>1</td>
9660 <td>DEV_MCU_PBIST1_CLK2_CLK</td>
9661 <td>Input clock</td>
9662 </tr>
9663 <tr class="row-even"><td>2</td>
9664 <td>DEV_MCU_PBIST1_CLK3_CLK</td>
9665 <td>Input clock</td>
9666 </tr>
9667 <tr class="row-odd"><td>3</td>
9668 <td>DEV_MCU_PBIST1_CLK4_CLK</td>
9669 <td>Input clock</td>
9670 </tr>
9671 <tr class="row-even"><td>4</td>
9672 <td>DEV_MCU_PBIST1_CLK5_CLK</td>
9673 <td>Input clock</td>
9674 </tr>
9675 <tr class="row-odd"><td>5</td>
9676 <td>DEV_MCU_PBIST1_CLK6_CLK</td>
9677 <td>Input clock</td>
9678 </tr>
9679 <tr class="row-even"><td>6</td>
9680 <td>DEV_MCU_PBIST1_CLK7_CLK</td>
9681 <td>Input clock</td>
9682 </tr>
9683 <tr class="row-odd"><td>7</td>
9684 <td>DEV_MCU_PBIST1_CLK8_CLK</td>
9685 <td>Input clock</td>
9686 </tr>
9687 </tbody>
9688 </table>
9689 </div>
9690 <div class="section" id="clocks-for-mcu-pbist2-device">
9691 <span id="soc-doc-j784s4-public-clks-mcu-pbist2"></span><h3>Clocks for MCU_PBIST2 Device<a class="headerlink" href="#clocks-for-mcu-pbist2-device" title="Permalink to this headline">¶</a></h3>
9692 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_PBIST2</span></a> (ID = 240)</p>
9693 <p>Following is a mapping of Clocks IDs to function:</p>
9694 <table border="1" class="docutils">
9695 <colgroup>
9696 <col width="24%" />
9697 <col width="50%" />
9698 <col width="26%" />
9699 </colgroup>
9700 <thead valign="bottom">
9701 <tr class="row-odd"><th class="head">Clock ID</th>
9702 <th class="head">Name</th>
9703 <th class="head">Function</th>
9704 </tr>
9705 </thead>
9706 <tbody valign="top">
9707 <tr class="row-even"><td>7</td>
9708 <td>DEV_MCU_PBIST2_CLK8_CLK</td>
9709 <td>Input clock</td>
9710 </tr>
9711 </tbody>
9712 </table>
9713 </div>
9714 <div class="section" id="clocks-for-mcu-r5fss0-device">
9715 <span id="soc-doc-j784s4-public-clks-mcu-r5fss0"></span><h3>Clocks for MCU_R5FSS0 Device<a class="headerlink" href="#clocks-for-mcu-r5fss0-device" title="Permalink to this headline">¶</a></h3>
9716 <p><strong>This device has no defined clocks.</strong></p>
9717 </div>
9718 <div class="section" id="clocks-for-mcu-r5fss0-core0-device">
9719 <span id="soc-doc-j784s4-public-clks-mcu-r5fss0-core0"></span><h3>Clocks for MCU_R5FSS0_CORE0 Device<a class="headerlink" href="#clocks-for-mcu-r5fss0-core0-device" title="Permalink to this headline">¶</a></h3>
9720 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_R5FSS0_CORE0</span></a> (ID = 346)</p>
9721 <p>Following is a mapping of Clocks IDs to function:</p>
9722 <table border="1" class="docutils">
9723 <colgroup>
9724 <col width="8%" />
9725 <col width="53%" />
9726 <col width="39%" />
9727 </colgroup>
9728 <thead valign="bottom">
9729 <tr class="row-odd"><th class="head">Clock ID</th>
9730 <th class="head">Name</th>
9731 <th class="head">Function</th>
9732 </tr>
9733 </thead>
9734 <tbody valign="top">
9735 <tr class="row-even"><td>0</td>
9736 <td>DEV_MCU_R5FSS0_CORE0_CPU_CLK</td>
9737 <td>Input muxed clock</td>
9738 </tr>
9739 <tr class="row-odd"><td>1</td>
9740 <td>DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK</td>
9741 <td>Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK</td>
9742 </tr>
9743 <tr class="row-even"><td>2</td>
9744 <td>DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3</td>
9745 <td>Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK</td>
9746 </tr>
9747 <tr class="row-odd"><td>3</td>
9748 <td>DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK</td>
9749 <td>Input clock</td>
9750 </tr>
9751 <tr class="row-even"><td>4</td>
9752 <td>DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE</td>
9753 <td>Input clock</td>
9754 </tr>
9755 </tbody>
9756 </table>
9757 </div>
9758 <div class="section" id="clocks-for-mcu-r5fss0-core1-device">
9759 <span id="soc-doc-j784s4-public-clks-mcu-r5fss0-core1"></span><h3>Clocks for MCU_R5FSS0_CORE1 Device<a class="headerlink" href="#clocks-for-mcu-r5fss0-core1-device" title="Permalink to this headline">¶</a></h3>
9760 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_R5FSS0_CORE1</span></a> (ID = 347)</p>
9761 <p>Following is a mapping of Clocks IDs to function:</p>
9762 <table border="1" class="docutils">
9763 <colgroup>
9764 <col width="8%" />
9765 <col width="53%" />
9766 <col width="39%" />
9767 </colgroup>
9768 <thead valign="bottom">
9769 <tr class="row-odd"><th class="head">Clock ID</th>
9770 <th class="head">Name</th>
9771 <th class="head">Function</th>
9772 </tr>
9773 </thead>
9774 <tbody valign="top">
9775 <tr class="row-even"><td>0</td>
9776 <td>DEV_MCU_R5FSS0_CORE1_CPU_CLK</td>
9777 <td>Input muxed clock</td>
9778 </tr>
9779 <tr class="row-odd"><td>1</td>
9780 <td>DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK</td>
9781 <td>Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK</td>
9782 </tr>
9783 <tr class="row-even"><td>2</td>
9784 <td>DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3</td>
9785 <td>Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK</td>
9786 </tr>
9787 <tr class="row-odd"><td>3</td>
9788 <td>DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK</td>
9789 <td>Input clock</td>
9790 </tr>
9791 <tr class="row-even"><td>4</td>
9792 <td>DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE</td>
9793 <td>Input clock</td>
9794 </tr>
9795 </tbody>
9796 </table>
9797 </div>
9798 <div class="section" id="clocks-for-mcu-rti0-device">
9799 <span id="soc-doc-j784s4-public-clks-mcu-rti0"></span><h3>Clocks for MCU_RTI0 Device<a class="headerlink" href="#clocks-for-mcu-rti0-device" title="Permalink to this headline">¶</a></h3>
9800 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_RTI0</span></a> (ID = 367)</p>
9801 <p>Following is a mapping of Clocks IDs to function:</p>
9802 <table border="1" class="docutils">
9803 <colgroup>
9804 <col width="9%" />
9805 <col width="54%" />
9806 <col width="37%" />
9807 </colgroup>
9808 <thead valign="bottom">
9809 <tr class="row-odd"><th class="head">Clock ID</th>
9810 <th class="head">Name</th>
9811 <th class="head">Function</th>
9812 </tr>
9813 </thead>
9814 <tbody valign="top">
9815 <tr class="row-even"><td>0</td>
9816 <td>DEV_MCU_RTI0_RTI_CLK</td>
9817 <td>Input muxed clock</td>
9818 </tr>
9819 <tr class="row-odd"><td>1</td>
9820 <td>DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9821 <td>Parent input clock option to DEV_MCU_RTI0_RTI_CLK</td>
9822 </tr>
9823 <tr class="row-even"><td>2</td>
9824 <td>DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
9825 <td>Parent input clock option to DEV_MCU_RTI0_RTI_CLK</td>
9826 </tr>
9827 <tr class="row-odd"><td>3</td>
9828 <td>DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
9829 <td>Parent input clock option to DEV_MCU_RTI0_RTI_CLK</td>
9830 </tr>
9831 <tr class="row-even"><td>4</td>
9832 <td>DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
9833 <td>Parent input clock option to DEV_MCU_RTI0_RTI_CLK</td>
9834 </tr>
9835 <tr class="row-odd"><td>9</td>
9836 <td>DEV_MCU_RTI0_VBUSP_CLK</td>
9837 <td>Input clock</td>
9838 </tr>
9839 </tbody>
9840 </table>
9841 </div>
9842 <div class="section" id="clocks-for-mcu-rti1-device">
9843 <span id="soc-doc-j784s4-public-clks-mcu-rti1"></span><h3>Clocks for MCU_RTI1 Device<a class="headerlink" href="#clocks-for-mcu-rti1-device" title="Permalink to this headline">¶</a></h3>
9844 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_RTI1</span></a> (ID = 368)</p>
9845 <p>Following is a mapping of Clocks IDs to function:</p>
9846 <table border="1" class="docutils">
9847 <colgroup>
9848 <col width="9%" />
9849 <col width="54%" />
9850 <col width="37%" />
9851 </colgroup>
9852 <thead valign="bottom">
9853 <tr class="row-odd"><th class="head">Clock ID</th>
9854 <th class="head">Name</th>
9855 <th class="head">Function</th>
9856 </tr>
9857 </thead>
9858 <tbody valign="top">
9859 <tr class="row-even"><td>0</td>
9860 <td>DEV_MCU_RTI1_RTI_CLK</td>
9861 <td>Input muxed clock</td>
9862 </tr>
9863 <tr class="row-odd"><td>1</td>
9864 <td>DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9865 <td>Parent input clock option to DEV_MCU_RTI1_RTI_CLK</td>
9866 </tr>
9867 <tr class="row-even"><td>2</td>
9868 <td>DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
9869 <td>Parent input clock option to DEV_MCU_RTI1_RTI_CLK</td>
9870 </tr>
9871 <tr class="row-odd"><td>3</td>
9872 <td>DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
9873 <td>Parent input clock option to DEV_MCU_RTI1_RTI_CLK</td>
9874 </tr>
9875 <tr class="row-even"><td>4</td>
9876 <td>DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
9877 <td>Parent input clock option to DEV_MCU_RTI1_RTI_CLK</td>
9878 </tr>
9879 <tr class="row-odd"><td>9</td>
9880 <td>DEV_MCU_RTI1_VBUSP_CLK</td>
9881 <td>Input clock</td>
9882 </tr>
9883 </tbody>
9884 </table>
9885 </div>
9886 <div class="section" id="clocks-for-mcu-timer0-device">
9887 <span id="soc-doc-j784s4-public-clks-mcu-timer0"></span><h3>Clocks for MCU_TIMER0 Device<a class="headerlink" href="#clocks-for-mcu-timer0-device" title="Permalink to this headline">¶</a></h3>
9888 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_TIMER0</span></a> (ID = 35)</p>
9889 <p>Following is a mapping of Clocks IDs to function:</p>
9890 <table border="1" class="docutils">
9891 <colgroup>
9892 <col width="8%" />
9893 <col width="54%" />
9894 <col width="39%" />
9895 </colgroup>
9896 <thead valign="bottom">
9897 <tr class="row-odd"><th class="head">Clock ID</th>
9898 <th class="head">Name</th>
9899 <th class="head">Function</th>
9900 </tr>
9901 </thead>
9902 <tbody valign="top">
9903 <tr class="row-even"><td>0</td>
9904 <td>DEV_MCU_TIMER0_TIMER_HCLK_CLK</td>
9905 <td>Input clock</td>
9906 </tr>
9907 <tr class="row-odd"><td>1</td>
9908 <td>DEV_MCU_TIMER0_TIMER_PWM</td>
9909 <td>Output clock</td>
9910 </tr>
9911 <tr class="row-even"><td>2</td>
9912 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
9913 <td>Input muxed clock</td>
9914 </tr>
9915 <tr class="row-odd"><td>3</td>
9916 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
9917 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
9918 </tr>
9919 <tr class="row-even"><td>4</td>
9920 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16</td>
9921 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
9922 </tr>
9923 <tr class="row-odd"><td>5</td>
9924 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
9925 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
9926 </tr>
9927 <tr class="row-even"><td>6</td>
9928 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK</td>
9929 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
9930 </tr>
9931 <tr class="row-odd"><td>7</td>
9932 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
9933 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
9934 </tr>
9935 <tr class="row-even"><td>8</td>
9936 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
9937 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
9938 </tr>
9939 <tr class="row-odd"><td>9</td>
9940 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0</td>
9941 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
9942 </tr>
9943 <tr class="row-even"><td>10</td>
9944 <td>DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
9945 <td>Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK</td>
9946 </tr>
9947 </tbody>
9948 </table>
9949 </div>
9950 <div class="section" id="clocks-for-mcu-timer1-device">
9951 <span id="soc-doc-j784s4-public-clks-mcu-timer1"></span><h3>Clocks for MCU_TIMER1 Device<a class="headerlink" href="#clocks-for-mcu-timer1-device" title="Permalink to this headline">¶</a></h3>
9952 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_TIMER1</span></a> (ID = 117)</p>
9953 <p>Following is a mapping of Clocks IDs to function:</p>
9954 <table border="1" class="docutils">
9955 <colgroup>
9956 <col width="9%" />
9957 <col width="49%" />
9958 <col width="43%" />
9959 </colgroup>
9960 <thead valign="bottom">
9961 <tr class="row-odd"><th class="head">Clock ID</th>
9962 <th class="head">Name</th>
9963 <th class="head">Function</th>
9964 </tr>
9965 </thead>
9966 <tbody valign="top">
9967 <tr class="row-even"><td>0</td>
9968 <td>DEV_MCU_TIMER1_TIMER_HCLK_CLK</td>
9969 <td>Input clock</td>
9970 </tr>
9971 <tr class="row-odd"><td>2</td>
9972 <td>DEV_MCU_TIMER1_TIMER_TCLK_CLK</td>
9973 <td>Input muxed clock</td>
9974 </tr>
9975 <tr class="row-even"><td>3</td>
9976 <td>DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1</td>
9977 <td>Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK</td>
9978 </tr>
9979 <tr class="row-odd"><td>4</td>
9980 <td>DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM</td>
9981 <td>Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK</td>
9982 </tr>
9983 </tbody>
9984 </table>
9985 </div>
9986 <div class="section" id="clocks-for-mcu-timer2-device">
9987 <span id="soc-doc-j784s4-public-clks-mcu-timer2"></span><h3>Clocks for MCU_TIMER2 Device<a class="headerlink" href="#clocks-for-mcu-timer2-device" title="Permalink to this headline">¶</a></h3>
9988 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_TIMER2</span></a> (ID = 118)</p>
9989 <p>Following is a mapping of Clocks IDs to function:</p>
9990 <table border="1" class="docutils">
9991 <colgroup>
9992 <col width="8%" />
9993 <col width="54%" />
9994 <col width="39%" />
9995 </colgroup>
9996 <thead valign="bottom">
9997 <tr class="row-odd"><th class="head">Clock ID</th>
9998 <th class="head">Name</th>
9999 <th class="head">Function</th>
10000 </tr>
10001 </thead>
10002 <tbody valign="top">
10003 <tr class="row-even"><td>0</td>
10004 <td>DEV_MCU_TIMER2_TIMER_HCLK_CLK</td>
10005 <td>Input clock</td>
10006 </tr>
10007 <tr class="row-odd"><td>1</td>
10008 <td>DEV_MCU_TIMER2_TIMER_PWM</td>
10009 <td>Output clock</td>
10010 </tr>
10011 <tr class="row-even"><td>2</td>
10012 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
10013 <td>Input muxed clock</td>
10014 </tr>
10015 <tr class="row-odd"><td>3</td>
10016 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
10017 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
10018 </tr>
10019 <tr class="row-even"><td>4</td>
10020 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16</td>
10021 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
10022 </tr>
10023 <tr class="row-odd"><td>5</td>
10024 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
10025 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
10026 </tr>
10027 <tr class="row-even"><td>6</td>
10028 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK</td>
10029 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
10030 </tr>
10031 <tr class="row-odd"><td>7</td>
10032 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
10033 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
10034 </tr>
10035 <tr class="row-even"><td>8</td>
10036 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
10037 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
10038 </tr>
10039 <tr class="row-odd"><td>9</td>
10040 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0</td>
10041 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
10042 </tr>
10043 <tr class="row-even"><td>10</td>
10044 <td>DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
10045 <td>Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK</td>
10046 </tr>
10047 </tbody>
10048 </table>
10049 </div>
10050 <div class="section" id="clocks-for-mcu-timer3-device">
10051 <span id="soc-doc-j784s4-public-clks-mcu-timer3"></span><h3>Clocks for MCU_TIMER3 Device<a class="headerlink" href="#clocks-for-mcu-timer3-device" title="Permalink to this headline">¶</a></h3>
10052 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_TIMER3</span></a> (ID = 119)</p>
10053 <p>Following is a mapping of Clocks IDs to function:</p>
10054 <table border="1" class="docutils">
10055 <colgroup>
10056 <col width="9%" />
10057 <col width="49%" />
10058 <col width="43%" />
10059 </colgroup>
10060 <thead valign="bottom">
10061 <tr class="row-odd"><th class="head">Clock ID</th>
10062 <th class="head">Name</th>
10063 <th class="head">Function</th>
10064 </tr>
10065 </thead>
10066 <tbody valign="top">
10067 <tr class="row-even"><td>0</td>
10068 <td>DEV_MCU_TIMER3_TIMER_HCLK_CLK</td>
10069 <td>Input clock</td>
10070 </tr>
10071 <tr class="row-odd"><td>2</td>
10072 <td>DEV_MCU_TIMER3_TIMER_TCLK_CLK</td>
10073 <td>Input muxed clock</td>
10074 </tr>
10075 <tr class="row-even"><td>3</td>
10076 <td>DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3</td>
10077 <td>Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK</td>
10078 </tr>
10079 <tr class="row-odd"><td>4</td>
10080 <td>DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM</td>
10081 <td>Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK</td>
10082 </tr>
10083 </tbody>
10084 </table>
10085 </div>
10086 <div class="section" id="clocks-for-mcu-timer4-device">
10087 <span id="soc-doc-j784s4-public-clks-mcu-timer4"></span><h3>Clocks for MCU_TIMER4 Device<a class="headerlink" href="#clocks-for-mcu-timer4-device" title="Permalink to this headline">¶</a></h3>
10088 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_TIMER4</span></a> (ID = 120)</p>
10089 <p>Following is a mapping of Clocks IDs to function:</p>
10090 <table border="1" class="docutils">
10091 <colgroup>
10092 <col width="8%" />
10093 <col width="54%" />
10094 <col width="39%" />
10095 </colgroup>
10096 <thead valign="bottom">
10097 <tr class="row-odd"><th class="head">Clock ID</th>
10098 <th class="head">Name</th>
10099 <th class="head">Function</th>
10100 </tr>
10101 </thead>
10102 <tbody valign="top">
10103 <tr class="row-even"><td>0</td>
10104 <td>DEV_MCU_TIMER4_TIMER_HCLK_CLK</td>
10105 <td>Input clock</td>
10106 </tr>
10107 <tr class="row-odd"><td>1</td>
10108 <td>DEV_MCU_TIMER4_TIMER_PWM</td>
10109 <td>Output clock</td>
10110 </tr>
10111 <tr class="row-even"><td>2</td>
10112 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
10113 <td>Input muxed clock</td>
10114 </tr>
10115 <tr class="row-odd"><td>3</td>
10116 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
10117 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
10118 </tr>
10119 <tr class="row-even"><td>4</td>
10120 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16</td>
10121 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
10122 </tr>
10123 <tr class="row-odd"><td>5</td>
10124 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
10125 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
10126 </tr>
10127 <tr class="row-even"><td>6</td>
10128 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK</td>
10129 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
10130 </tr>
10131 <tr class="row-odd"><td>7</td>
10132 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
10133 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
10134 </tr>
10135 <tr class="row-even"><td>8</td>
10136 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
10137 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
10138 </tr>
10139 <tr class="row-odd"><td>9</td>
10140 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0</td>
10141 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
10142 </tr>
10143 <tr class="row-even"><td>10</td>
10144 <td>DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
10145 <td>Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK</td>
10146 </tr>
10147 </tbody>
10148 </table>
10149 </div>
10150 <div class="section" id="clocks-for-mcu-timer5-device">
10151 <span id="soc-doc-j784s4-public-clks-mcu-timer5"></span><h3>Clocks for MCU_TIMER5 Device<a class="headerlink" href="#clocks-for-mcu-timer5-device" title="Permalink to this headline">¶</a></h3>
10152 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_TIMER5</span></a> (ID = 121)</p>
10153 <p>Following is a mapping of Clocks IDs to function:</p>
10154 <table border="1" class="docutils">
10155 <colgroup>
10156 <col width="9%" />
10157 <col width="49%" />
10158 <col width="43%" />
10159 </colgroup>
10160 <thead valign="bottom">
10161 <tr class="row-odd"><th class="head">Clock ID</th>
10162 <th class="head">Name</th>
10163 <th class="head">Function</th>
10164 </tr>
10165 </thead>
10166 <tbody valign="top">
10167 <tr class="row-even"><td>0</td>
10168 <td>DEV_MCU_TIMER5_TIMER_HCLK_CLK</td>
10169 <td>Input clock</td>
10170 </tr>
10171 <tr class="row-odd"><td>2</td>
10172 <td>DEV_MCU_TIMER5_TIMER_TCLK_CLK</td>
10173 <td>Input muxed clock</td>
10174 </tr>
10175 <tr class="row-even"><td>3</td>
10176 <td>DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5</td>
10177 <td>Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK</td>
10178 </tr>
10179 <tr class="row-odd"><td>4</td>
10180 <td>DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM</td>
10181 <td>Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK</td>
10182 </tr>
10183 </tbody>
10184 </table>
10185 </div>
10186 <div class="section" id="clocks-for-mcu-timer6-device">
10187 <span id="soc-doc-j784s4-public-clks-mcu-timer6"></span><h3>Clocks for MCU_TIMER6 Device<a class="headerlink" href="#clocks-for-mcu-timer6-device" title="Permalink to this headline">¶</a></h3>
10188 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_TIMER6</span></a> (ID = 122)</p>
10189 <p>Following is a mapping of Clocks IDs to function:</p>
10190 <table border="1" class="docutils">
10191 <colgroup>
10192 <col width="8%" />
10193 <col width="54%" />
10194 <col width="39%" />
10195 </colgroup>
10196 <thead valign="bottom">
10197 <tr class="row-odd"><th class="head">Clock ID</th>
10198 <th class="head">Name</th>
10199 <th class="head">Function</th>
10200 </tr>
10201 </thead>
10202 <tbody valign="top">
10203 <tr class="row-even"><td>0</td>
10204 <td>DEV_MCU_TIMER6_TIMER_HCLK_CLK</td>
10205 <td>Input clock</td>
10206 </tr>
10207 <tr class="row-odd"><td>1</td>
10208 <td>DEV_MCU_TIMER6_TIMER_PWM</td>
10209 <td>Output clock</td>
10210 </tr>
10211 <tr class="row-even"><td>2</td>
10212 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
10213 <td>Input muxed clock</td>
10214 </tr>
10215 <tr class="row-odd"><td>3</td>
10216 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
10217 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
10218 </tr>
10219 <tr class="row-even"><td>4</td>
10220 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16</td>
10221 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
10222 </tr>
10223 <tr class="row-odd"><td>5</td>
10224 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
10225 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
10226 </tr>
10227 <tr class="row-even"><td>6</td>
10228 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK</td>
10229 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
10230 </tr>
10231 <tr class="row-odd"><td>7</td>
10232 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
10233 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
10234 </tr>
10235 <tr class="row-even"><td>8</td>
10236 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
10237 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
10238 </tr>
10239 <tr class="row-odd"><td>9</td>
10240 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0</td>
10241 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
10242 </tr>
10243 <tr class="row-even"><td>10</td>
10244 <td>DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
10245 <td>Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK</td>
10246 </tr>
10247 </tbody>
10248 </table>
10249 </div>
10250 <div class="section" id="clocks-for-mcu-timer7-device">
10251 <span id="soc-doc-j784s4-public-clks-mcu-timer7"></span><h3>Clocks for MCU_TIMER7 Device<a class="headerlink" href="#clocks-for-mcu-timer7-device" title="Permalink to this headline">¶</a></h3>
10252 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_TIMER7</span></a> (ID = 123)</p>
10253 <p>Following is a mapping of Clocks IDs to function:</p>
10254 <table border="1" class="docutils">
10255 <colgroup>
10256 <col width="9%" />
10257 <col width="49%" />
10258 <col width="43%" />
10259 </colgroup>
10260 <thead valign="bottom">
10261 <tr class="row-odd"><th class="head">Clock ID</th>
10262 <th class="head">Name</th>
10263 <th class="head">Function</th>
10264 </tr>
10265 </thead>
10266 <tbody valign="top">
10267 <tr class="row-even"><td>0</td>
10268 <td>DEV_MCU_TIMER7_TIMER_HCLK_CLK</td>
10269 <td>Input clock</td>
10270 </tr>
10271 <tr class="row-odd"><td>2</td>
10272 <td>DEV_MCU_TIMER7_TIMER_TCLK_CLK</td>
10273 <td>Input muxed clock</td>
10274 </tr>
10275 <tr class="row-even"><td>3</td>
10276 <td>DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7</td>
10277 <td>Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK</td>
10278 </tr>
10279 <tr class="row-odd"><td>4</td>
10280 <td>DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM</td>
10281 <td>Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK</td>
10282 </tr>
10283 </tbody>
10284 </table>
10285 </div>
10286 <div class="section" id="clocks-for-mcu-timer8-device">
10287 <span id="soc-doc-j784s4-public-clks-mcu-timer8"></span><h3>Clocks for MCU_TIMER8 Device<a class="headerlink" href="#clocks-for-mcu-timer8-device" title="Permalink to this headline">¶</a></h3>
10288 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_TIMER8</span></a> (ID = 124)</p>
10289 <p>Following is a mapping of Clocks IDs to function:</p>
10290 <table border="1" class="docutils">
10291 <colgroup>
10292 <col width="8%" />
10293 <col width="54%" />
10294 <col width="39%" />
10295 </colgroup>
10296 <thead valign="bottom">
10297 <tr class="row-odd"><th class="head">Clock ID</th>
10298 <th class="head">Name</th>
10299 <th class="head">Function</th>
10300 </tr>
10301 </thead>
10302 <tbody valign="top">
10303 <tr class="row-even"><td>0</td>
10304 <td>DEV_MCU_TIMER8_TIMER_HCLK_CLK</td>
10305 <td>Input clock</td>
10306 </tr>
10307 <tr class="row-odd"><td>1</td>
10308 <td>DEV_MCU_TIMER8_TIMER_PWM</td>
10309 <td>Output clock</td>
10310 </tr>
10311 <tr class="row-even"><td>2</td>
10312 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
10313 <td>Input muxed clock</td>
10314 </tr>
10315 <tr class="row-odd"><td>3</td>
10316 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
10317 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
10318 </tr>
10319 <tr class="row-even"><td>4</td>
10320 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16</td>
10321 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
10322 </tr>
10323 <tr class="row-odd"><td>5</td>
10324 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
10325 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
10326 </tr>
10327 <tr class="row-even"><td>6</td>
10328 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK</td>
10329 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
10330 </tr>
10331 <tr class="row-odd"><td>7</td>
10332 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
10333 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
10334 </tr>
10335 <tr class="row-even"><td>8</td>
10336 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
10337 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
10338 </tr>
10339 <tr class="row-odd"><td>9</td>
10340 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0</td>
10341 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
10342 </tr>
10343 <tr class="row-even"><td>10</td>
10344 <td>DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
10345 <td>Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK</td>
10346 </tr>
10347 </tbody>
10348 </table>
10349 </div>
10350 <div class="section" id="clocks-for-mcu-timer9-device">
10351 <span id="soc-doc-j784s4-public-clks-mcu-timer9"></span><h3>Clocks for MCU_TIMER9 Device<a class="headerlink" href="#clocks-for-mcu-timer9-device" title="Permalink to this headline">¶</a></h3>
10352 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_TIMER9</span></a> (ID = 125)</p>
10353 <p>Following is a mapping of Clocks IDs to function:</p>
10354 <table border="1" class="docutils">
10355 <colgroup>
10356 <col width="9%" />
10357 <col width="49%" />
10358 <col width="43%" />
10359 </colgroup>
10360 <thead valign="bottom">
10361 <tr class="row-odd"><th class="head">Clock ID</th>
10362 <th class="head">Name</th>
10363 <th class="head">Function</th>
10364 </tr>
10365 </thead>
10366 <tbody valign="top">
10367 <tr class="row-even"><td>0</td>
10368 <td>DEV_MCU_TIMER9_TIMER_HCLK_CLK</td>
10369 <td>Input clock</td>
10370 </tr>
10371 <tr class="row-odd"><td>2</td>
10372 <td>DEV_MCU_TIMER9_TIMER_TCLK_CLK</td>
10373 <td>Input muxed clock</td>
10374 </tr>
10375 <tr class="row-even"><td>3</td>
10376 <td>DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9</td>
10377 <td>Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK</td>
10378 </tr>
10379 <tr class="row-odd"><td>4</td>
10380 <td>DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM</td>
10381 <td>Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK</td>
10382 </tr>
10383 </tbody>
10384 </table>
10385 </div>
10386 <div class="section" id="clocks-for-mcu-uart0-device">
10387 <span id="soc-doc-j784s4-public-clks-mcu-uart0"></span><h3>Clocks for MCU_UART0 Device<a class="headerlink" href="#clocks-for-mcu-uart0-device" title="Permalink to this headline">¶</a></h3>
10388 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MCU_UART0</span></a> (ID = 149)</p>
10389 <p>Following is a mapping of Clocks IDs to function:</p>
10390 <table border="1" class="docutils">
10391 <colgroup>
10392 <col width="9%" />
10393 <col width="51%" />
10394 <col width="40%" />
10395 </colgroup>
10396 <thead valign="bottom">
10397 <tr class="row-odd"><th class="head">Clock ID</th>
10398 <th class="head">Name</th>
10399 <th class="head">Function</th>
10400 </tr>
10401 </thead>
10402 <tbody valign="top">
10403 <tr class="row-even"><td>0</td>
10404 <td>DEV_MCU_UART0_FCLK_CLK</td>
10405 <td>Input muxed clock</td>
10406 </tr>
10407 <tr class="row-odd"><td>1</td>
10408 <td>DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK</td>
10409 <td>Parent input clock option to DEV_MCU_UART0_FCLK_CLK</td>
10410 </tr>
10411 <tr class="row-even"><td>2</td>
10412 <td>DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK</td>
10413 <td>Parent input clock option to DEV_MCU_UART0_FCLK_CLK</td>
10414 </tr>
10415 <tr class="row-odd"><td>5</td>
10416 <td>DEV_MCU_UART0_VBUSP_CLK</td>
10417 <td>Input clock</td>
10418 </tr>
10419 </tbody>
10420 </table>
10421 </div>
10422 <div class="section" id="clocks-for-mmcsd0-device">
10423 <span id="soc-doc-j784s4-public-clks-mmcsd0"></span><h3>Clocks for MMCSD0 Device<a class="headerlink" href="#clocks-for-mmcsd0-device" title="Permalink to this headline">¶</a></h3>
10424 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MMCSD0</span></a> (ID = 140)</p>
10425 <p>Following is a mapping of Clocks IDs to function:</p>
10426 <table border="1" class="docutils">
10427 <colgroup>
10428 <col width="9%" />
10429 <col width="50%" />
10430 <col width="41%" />
10431 </colgroup>
10432 <thead valign="bottom">
10433 <tr class="row-odd"><th class="head">Clock ID</th>
10434 <th class="head">Name</th>
10435 <th class="head">Function</th>
10436 </tr>
10437 </thead>
10438 <tbody valign="top">
10439 <tr class="row-even"><td>1</td>
10440 <td>DEV_MMCSD0_EMMCSS_VBUS_CLK</td>
10441 <td>Input clock</td>
10442 </tr>
10443 <tr class="row-odd"><td>2</td>
10444 <td>DEV_MMCSD0_EMMCSS_XIN_CLK</td>
10445 <td>Input muxed clock</td>
10446 </tr>
10447 <tr class="row-even"><td>3</td>
10448 <td>DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK</td>
10449 <td>Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK</td>
10450 </tr>
10451 <tr class="row-odd"><td>4</td>
10452 <td>DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK</td>
10453 <td>Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK</td>
10454 </tr>
10455 <tr class="row-even"><td>5</td>
10456 <td>DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
10457 <td>Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK</td>
10458 </tr>
10459 <tr class="row-odd"><td>6</td>
10460 <td>DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK</td>
10461 <td>Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK</td>
10462 </tr>
10463 </tbody>
10464 </table>
10465 </div>
10466 <div class="section" id="clocks-for-mmcsd1-device">
10467 <span id="soc-doc-j784s4-public-clks-mmcsd1"></span><h3>Clocks for MMCSD1 Device<a class="headerlink" href="#clocks-for-mmcsd1-device" title="Permalink to this headline">¶</a></h3>
10468 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_MMCSD1</span></a> (ID = 141)</p>
10469 <p>Following is a mapping of Clocks IDs to function:</p>
10470 <table border="1" class="docutils">
10471 <colgroup>
10472 <col width="9%" />
10473 <col width="50%" />
10474 <col width="41%" />
10475 </colgroup>
10476 <thead valign="bottom">
10477 <tr class="row-odd"><th class="head">Clock ID</th>
10478 <th class="head">Name</th>
10479 <th class="head">Function</th>
10480 </tr>
10481 </thead>
10482 <tbody valign="top">
10483 <tr class="row-even"><td>0</td>
10484 <td>DEV_MMCSD1_EMMCSDSS_IO_CLK_I</td>
10485 <td>Input clock</td>
10486 </tr>
10487 <tr class="row-odd"><td>1</td>
10488 <td>DEV_MMCSD1_EMMCSDSS_IO_CLK_O</td>
10489 <td>Output clock</td>
10490 </tr>
10491 <tr class="row-even"><td>3</td>
10492 <td>DEV_MMCSD1_EMMCSDSS_VBUS_CLK</td>
10493 <td>Input clock</td>
10494 </tr>
10495 <tr class="row-odd"><td>4</td>
10496 <td>DEV_MMCSD1_EMMCSDSS_XIN_CLK</td>
10497 <td>Input muxed clock</td>
10498 </tr>
10499 <tr class="row-even"><td>5</td>
10500 <td>DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK</td>
10501 <td>Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK</td>
10502 </tr>
10503 <tr class="row-odd"><td>6</td>
10504 <td>DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK</td>
10505 <td>Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK</td>
10506 </tr>
10507 <tr class="row-even"><td>7</td>
10508 <td>DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK</td>
10509 <td>Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK</td>
10510 </tr>
10511 <tr class="row-odd"><td>8</td>
10512 <td>DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK</td>
10513 <td>Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK</td>
10514 </tr>
10515 </tbody>
10516 </table>
10517 </div>
10518 <div class="section" id="clocks-for-navss0-device">
10519 <span id="soc-doc-j784s4-public-clks-navss0"></span><h3>Clocks for NAVSS0 Device<a class="headerlink" href="#clocks-for-navss0-device" title="Permalink to this headline">¶</a></h3>
10520 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0</span></a> (ID = 280)</p>
10521 <p>Following is a mapping of Clocks IDs to function:</p>
10522 <table border="1" class="docutils">
10523 <colgroup>
10524 <col width="24%" />
10525 <col width="48%" />
10526 <col width="28%" />
10527 </colgroup>
10528 <thead valign="bottom">
10529 <tr class="row-odd"><th class="head">Clock ID</th>
10530 <th class="head">Name</th>
10531 <th class="head">Function</th>
10532 </tr>
10533 </thead>
10534 <tbody valign="top">
10535 <tr class="row-even"><td>0</td>
10536 <td>DEV_NAVSS0_CPTS0_GENF2</td>
10537 <td>Output clock</td>
10538 </tr>
10539 <tr class="row-odd"><td>1</td>
10540 <td>DEV_NAVSS0_CPTS0_GENF3</td>
10541 <td>Output clock</td>
10542 </tr>
10543 </tbody>
10544 </table>
10545 </div>
10546 <div class="section" id="clocks-for-navss0-bcdma-0-device">
10547 <span id="soc-doc-j784s4-public-clks-navss0-bcdma-0"></span><h3>Clocks for NAVSS0_BCDMA_0 Device<a class="headerlink" href="#clocks-for-navss0-bcdma-0-device" title="Permalink to this headline">¶</a></h3>
10548 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_BCDMA_0</span></a> (ID = 281)</p>
10549 <p>Following is a mapping of Clocks IDs to function:</p>
10550 <table border="1" class="docutils">
10551 <colgroup>
10552 <col width="24%" />
10553 <col width="49%" />
10554 <col width="27%" />
10555 </colgroup>
10556 <thead valign="bottom">
10557 <tr class="row-odd"><th class="head">Clock ID</th>
10558 <th class="head">Name</th>
10559 <th class="head">Function</th>
10560 </tr>
10561 </thead>
10562 <tbody valign="top">
10563 <tr class="row-even"><td>0</td>
10564 <td>DEV_NAVSS0_BCDMA_0_CLK</td>
10565 <td>Input clock</td>
10566 </tr>
10567 </tbody>
10568 </table>
10569 </div>
10570 <div class="section" id="clocks-for-navss0-cpts-0-device">
10571 <span id="soc-doc-j784s4-public-clks-navss0-cpts-0"></span><h3>Clocks for NAVSS0_CPTS_0 Device<a class="headerlink" href="#clocks-for-navss0-cpts-0-device" title="Permalink to this headline">¶</a></h3>
10572 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_CPTS_0</span></a> (ID = 282)</p>
10573 <p>Following is a mapping of Clocks IDs to function:</p>
10574 <table border="1" class="docutils">
10575 <colgroup>
10576 <col width="9%" />
10577 <col width="53%" />
10578 <col width="38%" />
10579 </colgroup>
10580 <thead valign="bottom">
10581 <tr class="row-odd"><th class="head">Clock ID</th>
10582 <th class="head">Name</th>
10583 <th class="head">Function</th>
10584 </tr>
10585 </thead>
10586 <tbody valign="top">
10587 <tr class="row-even"><td>0</td>
10588 <td>DEV_NAVSS0_CPTS_0_RCLK</td>
10589 <td>Input muxed clock</td>
10590 </tr>
10591 <tr class="row-odd"><td>1</td>
10592 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
10593 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10594 </tr>
10595 <tr class="row-even"><td>2</td>
10596 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
10597 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10598 </tr>
10599 <tr class="row-odd"><td>3</td>
10600 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
10601 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10602 </tr>
10603 <tr class="row-even"><td>4</td>
10604 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
10605 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10606 </tr>
10607 <tr class="row-odd"><td>5</td>
10608 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
10609 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10610 </tr>
10611 <tr class="row-even"><td>6</td>
10612 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
10613 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10614 </tr>
10615 <tr class="row-odd"><td>7</td>
10616 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK</td>
10617 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10618 </tr>
10619 <tr class="row-even"><td>8</td>
10620 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK</td>
10621 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10622 </tr>
10623 <tr class="row-odd"><td>9</td>
10624 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK</td>
10625 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10626 </tr>
10627 <tr class="row-even"><td>10</td>
10628 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK</td>
10629 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10630 </tr>
10631 <tr class="row-odd"><td>11</td>
10632 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK</td>
10633 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10634 </tr>
10635 <tr class="row-even"><td>12</td>
10636 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK</td>
10637 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10638 </tr>
10639 <tr class="row-odd"><td>13</td>
10640 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK</td>
10641 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10642 </tr>
10643 <tr class="row-even"><td>14</td>
10644 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK</td>
10645 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10646 </tr>
10647 <tr class="row-odd"><td>15</td>
10648 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
10649 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10650 </tr>
10651 <tr class="row-even"><td>16</td>
10652 <td>DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
10653 <td>Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK</td>
10654 </tr>
10655 <tr class="row-odd"><td>17</td>
10656 <td>DEV_NAVSS0_CPTS_0_TS_GENF0</td>
10657 <td>Output clock</td>
10658 </tr>
10659 <tr class="row-even"><td>18</td>
10660 <td>DEV_NAVSS0_CPTS_0_TS_GENF1</td>
10661 <td>Output clock</td>
10662 </tr>
10663 <tr class="row-odd"><td>21</td>
10664 <td>DEV_NAVSS0_CPTS_0_VBUSP_GCLK</td>
10665 <td>Input clock</td>
10666 </tr>
10667 </tbody>
10668 </table>
10669 </div>
10670 <div class="section" id="clocks-for-navss0-intr-0-device">
10671 <span id="soc-doc-j784s4-public-clks-navss0-intr-0"></span><h3>Clocks for NAVSS0_INTR_0 Device<a class="headerlink" href="#clocks-for-navss0-intr-0-device" title="Permalink to this headline">¶</a></h3>
10672 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_INTR_0</span></a> (ID = 283)</p>
10673 <p>Following is a mapping of Clocks IDs to function:</p>
10674 <table border="1" class="docutils">
10675 <colgroup>
10676 <col width="23%" />
10677 <col width="53%" />
10678 <col width="25%" />
10679 </colgroup>
10680 <thead valign="bottom">
10681 <tr class="row-odd"><th class="head">Clock ID</th>
10682 <th class="head">Name</th>
10683 <th class="head">Function</th>
10684 </tr>
10685 </thead>
10686 <tbody valign="top">
10687 <tr class="row-even"><td>0</td>
10688 <td>DEV_NAVSS0_INTR_0_INTR_CLK</td>
10689 <td>Input clock</td>
10690 </tr>
10691 </tbody>
10692 </table>
10693 </div>
10694 <div class="section" id="clocks-for-navss0-mailbox1-0-device">
10695 <span id="soc-doc-j784s4-public-clks-navss0-mailbox1-0"></span><h3>Clocks for NAVSS0_MAILBOX1_0 Device<a class="headerlink" href="#clocks-for-navss0-mailbox1-0-device" title="Permalink to this headline">¶</a></h3>
10696 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX1_0</span></a> (ID = 284)</p>
10697 <p>Following is a mapping of Clocks IDs to function:</p>
10698 <table border="1" class="docutils">
10699 <colgroup>
10700 <col width="21%" />
10701 <col width="56%" />
10702 <col width="23%" />
10703 </colgroup>
10704 <thead valign="bottom">
10705 <tr class="row-odd"><th class="head">Clock ID</th>
10706 <th class="head">Name</th>
10707 <th class="head">Function</th>
10708 </tr>
10709 </thead>
10710 <tbody valign="top">
10711 <tr class="row-even"><td>0</td>
10712 <td>DEV_NAVSS0_MAILBOX1_0_VCLK_CLK</td>
10713 <td>Input clock</td>
10714 </tr>
10715 </tbody>
10716 </table>
10717 </div>
10718 <div class="section" id="clocks-for-navss0-mailbox1-1-device">
10719 <span id="soc-doc-j784s4-public-clks-navss0-mailbox1-1"></span><h3>Clocks for NAVSS0_MAILBOX1_1 Device<a class="headerlink" href="#clocks-for-navss0-mailbox1-1-device" title="Permalink to this headline">¶</a></h3>
10720 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX1_1</span></a> (ID = 285)</p>
10721 <p>Following is a mapping of Clocks IDs to function:</p>
10722 <table border="1" class="docutils">
10723 <colgroup>
10724 <col width="21%" />
10725 <col width="56%" />
10726 <col width="23%" />
10727 </colgroup>
10728 <thead valign="bottom">
10729 <tr class="row-odd"><th class="head">Clock ID</th>
10730 <th class="head">Name</th>
10731 <th class="head">Function</th>
10732 </tr>
10733 </thead>
10734 <tbody valign="top">
10735 <tr class="row-even"><td>0</td>
10736 <td>DEV_NAVSS0_MAILBOX1_1_VCLK_CLK</td>
10737 <td>Input clock</td>
10738 </tr>
10739 </tbody>
10740 </table>
10741 </div>
10742 <div class="section" id="clocks-for-navss0-mailbox1-10-device">
10743 <span id="soc-doc-j784s4-public-clks-navss0-mailbox1-10"></span><h3>Clocks for NAVSS0_MAILBOX1_10 Device<a class="headerlink" href="#clocks-for-navss0-mailbox1-10-device" title="Permalink to this headline">¶</a></h3>
10744 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX1_10</span></a> (ID = 294)</p>
10745 <p>Following is a mapping of Clocks IDs to function:</p>
10746 <table border="1" class="docutils">
10747 <colgroup>
10748 <col width="21%" />
10749 <col width="57%" />
10750 <col width="22%" />
10751 </colgroup>
10752 <thead valign="bottom">
10753 <tr class="row-odd"><th class="head">Clock ID</th>
10754 <th class="head">Name</th>
10755 <th class="head">Function</th>
10756 </tr>
10757 </thead>
10758 <tbody valign="top">
10759 <tr class="row-even"><td>0</td>
10760 <td>DEV_NAVSS0_MAILBOX1_10_VCLK_CLK</td>
10761 <td>Input clock</td>
10762 </tr>
10763 </tbody>
10764 </table>
10765 </div>
10766 <div class="section" id="clocks-for-navss0-mailbox1-11-device">
10767 <span id="soc-doc-j784s4-public-clks-navss0-mailbox1-11"></span><h3>Clocks for NAVSS0_MAILBOX1_11 Device<a class="headerlink" href="#clocks-for-navss0-mailbox1-11-device" title="Permalink to this headline">¶</a></h3>
10768 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX1_11</span></a> (ID = 295)</p>
10769 <p>Following is a mapping of Clocks IDs to function:</p>
10770 <table border="1" class="docutils">
10771 <colgroup>
10772 <col width="21%" />
10773 <col width="57%" />
10774 <col width="22%" />
10775 </colgroup>
10776 <thead valign="bottom">
10777 <tr class="row-odd"><th class="head">Clock ID</th>
10778 <th class="head">Name</th>
10779 <th class="head">Function</th>
10780 </tr>
10781 </thead>
10782 <tbody valign="top">
10783 <tr class="row-even"><td>0</td>
10784 <td>DEV_NAVSS0_MAILBOX1_11_VCLK_CLK</td>
10785 <td>Input clock</td>
10786 </tr>
10787 </tbody>
10788 </table>
10789 </div>
10790 <div class="section" id="clocks-for-navss0-mailbox1-2-device">
10791 <span id="soc-doc-j784s4-public-clks-navss0-mailbox1-2"></span><h3>Clocks for NAVSS0_MAILBOX1_2 Device<a class="headerlink" href="#clocks-for-navss0-mailbox1-2-device" title="Permalink to this headline">¶</a></h3>
10792 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX1_2</span></a> (ID = 286)</p>
10793 <p>Following is a mapping of Clocks IDs to function:</p>
10794 <table border="1" class="docutils">
10795 <colgroup>
10796 <col width="21%" />
10797 <col width="56%" />
10798 <col width="23%" />
10799 </colgroup>
10800 <thead valign="bottom">
10801 <tr class="row-odd"><th class="head">Clock ID</th>
10802 <th class="head">Name</th>
10803 <th class="head">Function</th>
10804 </tr>
10805 </thead>
10806 <tbody valign="top">
10807 <tr class="row-even"><td>0</td>
10808 <td>DEV_NAVSS0_MAILBOX1_2_VCLK_CLK</td>
10809 <td>Input clock</td>
10810 </tr>
10811 </tbody>
10812 </table>
10813 </div>
10814 <div class="section" id="clocks-for-navss0-mailbox1-3-device">
10815 <span id="soc-doc-j784s4-public-clks-navss0-mailbox1-3"></span><h3>Clocks for NAVSS0_MAILBOX1_3 Device<a class="headerlink" href="#clocks-for-navss0-mailbox1-3-device" title="Permalink to this headline">¶</a></h3>
10816 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX1_3</span></a> (ID = 287)</p>
10817 <p>Following is a mapping of Clocks IDs to function:</p>
10818 <table border="1" class="docutils">
10819 <colgroup>
10820 <col width="21%" />
10821 <col width="56%" />
10822 <col width="23%" />
10823 </colgroup>
10824 <thead valign="bottom">
10825 <tr class="row-odd"><th class="head">Clock ID</th>
10826 <th class="head">Name</th>
10827 <th class="head">Function</th>
10828 </tr>
10829 </thead>
10830 <tbody valign="top">
10831 <tr class="row-even"><td>0</td>
10832 <td>DEV_NAVSS0_MAILBOX1_3_VCLK_CLK</td>
10833 <td>Input clock</td>
10834 </tr>
10835 </tbody>
10836 </table>
10837 </div>
10838 <div class="section" id="clocks-for-navss0-mailbox1-4-device">
10839 <span id="soc-doc-j784s4-public-clks-navss0-mailbox1-4"></span><h3>Clocks for NAVSS0_MAILBOX1_4 Device<a class="headerlink" href="#clocks-for-navss0-mailbox1-4-device" title="Permalink to this headline">¶</a></h3>
10840 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX1_4</span></a> (ID = 288)</p>
10841 <p>Following is a mapping of Clocks IDs to function:</p>
10842 <table border="1" class="docutils">
10843 <colgroup>
10844 <col width="21%" />
10845 <col width="56%" />
10846 <col width="23%" />
10847 </colgroup>
10848 <thead valign="bottom">
10849 <tr class="row-odd"><th class="head">Clock ID</th>
10850 <th class="head">Name</th>
10851 <th class="head">Function</th>
10852 </tr>
10853 </thead>
10854 <tbody valign="top">
10855 <tr class="row-even"><td>0</td>
10856 <td>DEV_NAVSS0_MAILBOX1_4_VCLK_CLK</td>
10857 <td>Input clock</td>
10858 </tr>
10859 </tbody>
10860 </table>
10861 </div>
10862 <div class="section" id="clocks-for-navss0-mailbox1-5-device">
10863 <span id="soc-doc-j784s4-public-clks-navss0-mailbox1-5"></span><h3>Clocks for NAVSS0_MAILBOX1_5 Device<a class="headerlink" href="#clocks-for-navss0-mailbox1-5-device" title="Permalink to this headline">¶</a></h3>
10864 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX1_5</span></a> (ID = 289)</p>
10865 <p>Following is a mapping of Clocks IDs to function:</p>
10866 <table border="1" class="docutils">
10867 <colgroup>
10868 <col width="21%" />
10869 <col width="56%" />
10870 <col width="23%" />
10871 </colgroup>
10872 <thead valign="bottom">
10873 <tr class="row-odd"><th class="head">Clock ID</th>
10874 <th class="head">Name</th>
10875 <th class="head">Function</th>
10876 </tr>
10877 </thead>
10878 <tbody valign="top">
10879 <tr class="row-even"><td>0</td>
10880 <td>DEV_NAVSS0_MAILBOX1_5_VCLK_CLK</td>
10881 <td>Input clock</td>
10882 </tr>
10883 </tbody>
10884 </table>
10885 </div>
10886 <div class="section" id="clocks-for-navss0-mailbox1-6-device">
10887 <span id="soc-doc-j784s4-public-clks-navss0-mailbox1-6"></span><h3>Clocks for NAVSS0_MAILBOX1_6 Device<a class="headerlink" href="#clocks-for-navss0-mailbox1-6-device" title="Permalink to this headline">¶</a></h3>
10888 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX1_6</span></a> (ID = 290)</p>
10889 <p>Following is a mapping of Clocks IDs to function:</p>
10890 <table border="1" class="docutils">
10891 <colgroup>
10892 <col width="21%" />
10893 <col width="56%" />
10894 <col width="23%" />
10895 </colgroup>
10896 <thead valign="bottom">
10897 <tr class="row-odd"><th class="head">Clock ID</th>
10898 <th class="head">Name</th>
10899 <th class="head">Function</th>
10900 </tr>
10901 </thead>
10902 <tbody valign="top">
10903 <tr class="row-even"><td>0</td>
10904 <td>DEV_NAVSS0_MAILBOX1_6_VCLK_CLK</td>
10905 <td>Input clock</td>
10906 </tr>
10907 </tbody>
10908 </table>
10909 </div>
10910 <div class="section" id="clocks-for-navss0-mailbox1-7-device">
10911 <span id="soc-doc-j784s4-public-clks-navss0-mailbox1-7"></span><h3>Clocks for NAVSS0_MAILBOX1_7 Device<a class="headerlink" href="#clocks-for-navss0-mailbox1-7-device" title="Permalink to this headline">¶</a></h3>
10912 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX1_7</span></a> (ID = 291)</p>
10913 <p>Following is a mapping of Clocks IDs to function:</p>
10914 <table border="1" class="docutils">
10915 <colgroup>
10916 <col width="21%" />
10917 <col width="56%" />
10918 <col width="23%" />
10919 </colgroup>
10920 <thead valign="bottom">
10921 <tr class="row-odd"><th class="head">Clock ID</th>
10922 <th class="head">Name</th>
10923 <th class="head">Function</th>
10924 </tr>
10925 </thead>
10926 <tbody valign="top">
10927 <tr class="row-even"><td>0</td>
10928 <td>DEV_NAVSS0_MAILBOX1_7_VCLK_CLK</td>
10929 <td>Input clock</td>
10930 </tr>
10931 </tbody>
10932 </table>
10933 </div>
10934 <div class="section" id="clocks-for-navss0-mailbox1-8-device">
10935 <span id="soc-doc-j784s4-public-clks-navss0-mailbox1-8"></span><h3>Clocks for NAVSS0_MAILBOX1_8 Device<a class="headerlink" href="#clocks-for-navss0-mailbox1-8-device" title="Permalink to this headline">¶</a></h3>
10936 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX1_8</span></a> (ID = 292)</p>
10937 <p>Following is a mapping of Clocks IDs to function:</p>
10938 <table border="1" class="docutils">
10939 <colgroup>
10940 <col width="21%" />
10941 <col width="56%" />
10942 <col width="23%" />
10943 </colgroup>
10944 <thead valign="bottom">
10945 <tr class="row-odd"><th class="head">Clock ID</th>
10946 <th class="head">Name</th>
10947 <th class="head">Function</th>
10948 </tr>
10949 </thead>
10950 <tbody valign="top">
10951 <tr class="row-even"><td>0</td>
10952 <td>DEV_NAVSS0_MAILBOX1_8_VCLK_CLK</td>
10953 <td>Input clock</td>
10954 </tr>
10955 </tbody>
10956 </table>
10957 </div>
10958 <div class="section" id="clocks-for-navss0-mailbox1-9-device">
10959 <span id="soc-doc-j784s4-public-clks-navss0-mailbox1-9"></span><h3>Clocks for NAVSS0_MAILBOX1_9 Device<a class="headerlink" href="#clocks-for-navss0-mailbox1-9-device" title="Permalink to this headline">¶</a></h3>
10960 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX1_9</span></a> (ID = 293)</p>
10961 <p>Following is a mapping of Clocks IDs to function:</p>
10962 <table border="1" class="docutils">
10963 <colgroup>
10964 <col width="21%" />
10965 <col width="56%" />
10966 <col width="23%" />
10967 </colgroup>
10968 <thead valign="bottom">
10969 <tr class="row-odd"><th class="head">Clock ID</th>
10970 <th class="head">Name</th>
10971 <th class="head">Function</th>
10972 </tr>
10973 </thead>
10974 <tbody valign="top">
10975 <tr class="row-even"><td>0</td>
10976 <td>DEV_NAVSS0_MAILBOX1_9_VCLK_CLK</td>
10977 <td>Input clock</td>
10978 </tr>
10979 </tbody>
10980 </table>
10981 </div>
10982 <div class="section" id="clocks-for-navss0-mailbox-0-device">
10983 <span id="soc-doc-j784s4-public-clks-navss0-mailbox-0"></span><h3>Clocks for NAVSS0_MAILBOX_0 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-0-device" title="Permalink to this headline">¶</a></h3>
10984 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX_0</span></a> (ID = 296)</p>
10985 <p>Following is a mapping of Clocks IDs to function:</p>
10986 <table border="1" class="docutils">
10987 <colgroup>
10988 <col width="21%" />
10989 <col width="55%" />
10990 <col width="23%" />
10991 </colgroup>
10992 <thead valign="bottom">
10993 <tr class="row-odd"><th class="head">Clock ID</th>
10994 <th class="head">Name</th>
10995 <th class="head">Function</th>
10996 </tr>
10997 </thead>
10998 <tbody valign="top">
10999 <tr class="row-even"><td>0</td>
11000 <td>DEV_NAVSS0_MAILBOX_0_VCLK_CLK</td>
11001 <td>Input clock</td>
11002 </tr>
11003 </tbody>
11004 </table>
11005 </div>
11006 <div class="section" id="clocks-for-navss0-mailbox-1-device">
11007 <span id="soc-doc-j784s4-public-clks-navss0-mailbox-1"></span><h3>Clocks for NAVSS0_MAILBOX_1 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-1-device" title="Permalink to this headline">¶</a></h3>
11008 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX_1</span></a> (ID = 297)</p>
11009 <p>Following is a mapping of Clocks IDs to function:</p>
11010 <table border="1" class="docutils">
11011 <colgroup>
11012 <col width="21%" />
11013 <col width="55%" />
11014 <col width="23%" />
11015 </colgroup>
11016 <thead valign="bottom">
11017 <tr class="row-odd"><th class="head">Clock ID</th>
11018 <th class="head">Name</th>
11019 <th class="head">Function</th>
11020 </tr>
11021 </thead>
11022 <tbody valign="top">
11023 <tr class="row-even"><td>0</td>
11024 <td>DEV_NAVSS0_MAILBOX_1_VCLK_CLK</td>
11025 <td>Input clock</td>
11026 </tr>
11027 </tbody>
11028 </table>
11029 </div>
11030 <div class="section" id="clocks-for-navss0-mailbox-10-device">
11031 <span id="soc-doc-j784s4-public-clks-navss0-mailbox-10"></span><h3>Clocks for NAVSS0_MAILBOX_10 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-10-device" title="Permalink to this headline">¶</a></h3>
11032 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX_10</span></a> (ID = 306)</p>
11033 <p>Following is a mapping of Clocks IDs to function:</p>
11034 <table border="1" class="docutils">
11035 <colgroup>
11036 <col width="21%" />
11037 <col width="56%" />
11038 <col width="23%" />
11039 </colgroup>
11040 <thead valign="bottom">
11041 <tr class="row-odd"><th class="head">Clock ID</th>
11042 <th class="head">Name</th>
11043 <th class="head">Function</th>
11044 </tr>
11045 </thead>
11046 <tbody valign="top">
11047 <tr class="row-even"><td>0</td>
11048 <td>DEV_NAVSS0_MAILBOX_10_VCLK_CLK</td>
11049 <td>Input clock</td>
11050 </tr>
11051 </tbody>
11052 </table>
11053 </div>
11054 <div class="section" id="clocks-for-navss0-mailbox-11-device">
11055 <span id="soc-doc-j784s4-public-clks-navss0-mailbox-11"></span><h3>Clocks for NAVSS0_MAILBOX_11 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-11-device" title="Permalink to this headline">¶</a></h3>
11056 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX_11</span></a> (ID = 307)</p>
11057 <p>Following is a mapping of Clocks IDs to function:</p>
11058 <table border="1" class="docutils">
11059 <colgroup>
11060 <col width="21%" />
11061 <col width="56%" />
11062 <col width="23%" />
11063 </colgroup>
11064 <thead valign="bottom">
11065 <tr class="row-odd"><th class="head">Clock ID</th>
11066 <th class="head">Name</th>
11067 <th class="head">Function</th>
11068 </tr>
11069 </thead>
11070 <tbody valign="top">
11071 <tr class="row-even"><td>0</td>
11072 <td>DEV_NAVSS0_MAILBOX_11_VCLK_CLK</td>
11073 <td>Input clock</td>
11074 </tr>
11075 </tbody>
11076 </table>
11077 </div>
11078 <div class="section" id="clocks-for-navss0-mailbox-2-device">
11079 <span id="soc-doc-j784s4-public-clks-navss0-mailbox-2"></span><h3>Clocks for NAVSS0_MAILBOX_2 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-2-device" title="Permalink to this headline">¶</a></h3>
11080 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX_2</span></a> (ID = 298)</p>
11081 <p>Following is a mapping of Clocks IDs to function:</p>
11082 <table border="1" class="docutils">
11083 <colgroup>
11084 <col width="21%" />
11085 <col width="55%" />
11086 <col width="23%" />
11087 </colgroup>
11088 <thead valign="bottom">
11089 <tr class="row-odd"><th class="head">Clock ID</th>
11090 <th class="head">Name</th>
11091 <th class="head">Function</th>
11092 </tr>
11093 </thead>
11094 <tbody valign="top">
11095 <tr class="row-even"><td>0</td>
11096 <td>DEV_NAVSS0_MAILBOX_2_VCLK_CLK</td>
11097 <td>Input clock</td>
11098 </tr>
11099 </tbody>
11100 </table>
11101 </div>
11102 <div class="section" id="clocks-for-navss0-mailbox-3-device">
11103 <span id="soc-doc-j784s4-public-clks-navss0-mailbox-3"></span><h3>Clocks for NAVSS0_MAILBOX_3 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-3-device" title="Permalink to this headline">¶</a></h3>
11104 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX_3</span></a> (ID = 299)</p>
11105 <p>Following is a mapping of Clocks IDs to function:</p>
11106 <table border="1" class="docutils">
11107 <colgroup>
11108 <col width="21%" />
11109 <col width="55%" />
11110 <col width="23%" />
11111 </colgroup>
11112 <thead valign="bottom">
11113 <tr class="row-odd"><th class="head">Clock ID</th>
11114 <th class="head">Name</th>
11115 <th class="head">Function</th>
11116 </tr>
11117 </thead>
11118 <tbody valign="top">
11119 <tr class="row-even"><td>0</td>
11120 <td>DEV_NAVSS0_MAILBOX_3_VCLK_CLK</td>
11121 <td>Input clock</td>
11122 </tr>
11123 </tbody>
11124 </table>
11125 </div>
11126 <div class="section" id="clocks-for-navss0-mailbox-4-device">
11127 <span id="soc-doc-j784s4-public-clks-navss0-mailbox-4"></span><h3>Clocks for NAVSS0_MAILBOX_4 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-4-device" title="Permalink to this headline">¶</a></h3>
11128 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX_4</span></a> (ID = 300)</p>
11129 <p>Following is a mapping of Clocks IDs to function:</p>
11130 <table border="1" class="docutils">
11131 <colgroup>
11132 <col width="21%" />
11133 <col width="55%" />
11134 <col width="23%" />
11135 </colgroup>
11136 <thead valign="bottom">
11137 <tr class="row-odd"><th class="head">Clock ID</th>
11138 <th class="head">Name</th>
11139 <th class="head">Function</th>
11140 </tr>
11141 </thead>
11142 <tbody valign="top">
11143 <tr class="row-even"><td>0</td>
11144 <td>DEV_NAVSS0_MAILBOX_4_VCLK_CLK</td>
11145 <td>Input clock</td>
11146 </tr>
11147 </tbody>
11148 </table>
11149 </div>
11150 <div class="section" id="clocks-for-navss0-mailbox-5-device">
11151 <span id="soc-doc-j784s4-public-clks-navss0-mailbox-5"></span><h3>Clocks for NAVSS0_MAILBOX_5 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-5-device" title="Permalink to this headline">¶</a></h3>
11152 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX_5</span></a> (ID = 301)</p>
11153 <p>Following is a mapping of Clocks IDs to function:</p>
11154 <table border="1" class="docutils">
11155 <colgroup>
11156 <col width="21%" />
11157 <col width="55%" />
11158 <col width="23%" />
11159 </colgroup>
11160 <thead valign="bottom">
11161 <tr class="row-odd"><th class="head">Clock ID</th>
11162 <th class="head">Name</th>
11163 <th class="head">Function</th>
11164 </tr>
11165 </thead>
11166 <tbody valign="top">
11167 <tr class="row-even"><td>0</td>
11168 <td>DEV_NAVSS0_MAILBOX_5_VCLK_CLK</td>
11169 <td>Input clock</td>
11170 </tr>
11171 </tbody>
11172 </table>
11173 </div>
11174 <div class="section" id="clocks-for-navss0-mailbox-6-device">
11175 <span id="soc-doc-j784s4-public-clks-navss0-mailbox-6"></span><h3>Clocks for NAVSS0_MAILBOX_6 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-6-device" title="Permalink to this headline">¶</a></h3>
11176 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX_6</span></a> (ID = 302)</p>
11177 <p>Following is a mapping of Clocks IDs to function:</p>
11178 <table border="1" class="docutils">
11179 <colgroup>
11180 <col width="21%" />
11181 <col width="55%" />
11182 <col width="23%" />
11183 </colgroup>
11184 <thead valign="bottom">
11185 <tr class="row-odd"><th class="head">Clock ID</th>
11186 <th class="head">Name</th>
11187 <th class="head">Function</th>
11188 </tr>
11189 </thead>
11190 <tbody valign="top">
11191 <tr class="row-even"><td>0</td>
11192 <td>DEV_NAVSS0_MAILBOX_6_VCLK_CLK</td>
11193 <td>Input clock</td>
11194 </tr>
11195 </tbody>
11196 </table>
11197 </div>
11198 <div class="section" id="clocks-for-navss0-mailbox-7-device">
11199 <span id="soc-doc-j784s4-public-clks-navss0-mailbox-7"></span><h3>Clocks for NAVSS0_MAILBOX_7 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-7-device" title="Permalink to this headline">¶</a></h3>
11200 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX_7</span></a> (ID = 303)</p>
11201 <p>Following is a mapping of Clocks IDs to function:</p>
11202 <table border="1" class="docutils">
11203 <colgroup>
11204 <col width="21%" />
11205 <col width="55%" />
11206 <col width="23%" />
11207 </colgroup>
11208 <thead valign="bottom">
11209 <tr class="row-odd"><th class="head">Clock ID</th>
11210 <th class="head">Name</th>
11211 <th class="head">Function</th>
11212 </tr>
11213 </thead>
11214 <tbody valign="top">
11215 <tr class="row-even"><td>0</td>
11216 <td>DEV_NAVSS0_MAILBOX_7_VCLK_CLK</td>
11217 <td>Input clock</td>
11218 </tr>
11219 </tbody>
11220 </table>
11221 </div>
11222 <div class="section" id="clocks-for-navss0-mailbox-8-device">
11223 <span id="soc-doc-j784s4-public-clks-navss0-mailbox-8"></span><h3>Clocks for NAVSS0_MAILBOX_8 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-8-device" title="Permalink to this headline">¶</a></h3>
11224 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX_8</span></a> (ID = 304)</p>
11225 <p>Following is a mapping of Clocks IDs to function:</p>
11226 <table border="1" class="docutils">
11227 <colgroup>
11228 <col width="21%" />
11229 <col width="55%" />
11230 <col width="23%" />
11231 </colgroup>
11232 <thead valign="bottom">
11233 <tr class="row-odd"><th class="head">Clock ID</th>
11234 <th class="head">Name</th>
11235 <th class="head">Function</th>
11236 </tr>
11237 </thead>
11238 <tbody valign="top">
11239 <tr class="row-even"><td>0</td>
11240 <td>DEV_NAVSS0_MAILBOX_8_VCLK_CLK</td>
11241 <td>Input clock</td>
11242 </tr>
11243 </tbody>
11244 </table>
11245 </div>
11246 <div class="section" id="clocks-for-navss0-mailbox-9-device">
11247 <span id="soc-doc-j784s4-public-clks-navss0-mailbox-9"></span><h3>Clocks for NAVSS0_MAILBOX_9 Device<a class="headerlink" href="#clocks-for-navss0-mailbox-9-device" title="Permalink to this headline">¶</a></h3>
11248 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MAILBOX_9</span></a> (ID = 305)</p>
11249 <p>Following is a mapping of Clocks IDs to function:</p>
11250 <table border="1" class="docutils">
11251 <colgroup>
11252 <col width="21%" />
11253 <col width="55%" />
11254 <col width="23%" />
11255 </colgroup>
11256 <thead valign="bottom">
11257 <tr class="row-odd"><th class="head">Clock ID</th>
11258 <th class="head">Name</th>
11259 <th class="head">Function</th>
11260 </tr>
11261 </thead>
11262 <tbody valign="top">
11263 <tr class="row-even"><td>0</td>
11264 <td>DEV_NAVSS0_MAILBOX_9_VCLK_CLK</td>
11265 <td>Input clock</td>
11266 </tr>
11267 </tbody>
11268 </table>
11269 </div>
11270 <div class="section" id="clocks-for-navss0-mcrc-0-device">
11271 <span id="soc-doc-j784s4-public-clks-navss0-mcrc-0"></span><h3>Clocks for NAVSS0_MCRC_0 Device<a class="headerlink" href="#clocks-for-navss0-mcrc-0-device" title="Permalink to this headline">¶</a></h3>
11272 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MCRC_0</span></a> (ID = 308)</p>
11273 <p>Following is a mapping of Clocks IDs to function:</p>
11274 <table border="1" class="docutils">
11275 <colgroup>
11276 <col width="25%" />
11277 <col width="48%" />
11278 <col width="27%" />
11279 </colgroup>
11280 <thead valign="bottom">
11281 <tr class="row-odd"><th class="head">Clock ID</th>
11282 <th class="head">Name</th>
11283 <th class="head">Function</th>
11284 </tr>
11285 </thead>
11286 <tbody valign="top">
11287 <tr class="row-even"><td>0</td>
11288 <td>DEV_NAVSS0_MCRC_0_CLK</td>
11289 <td>Input clock</td>
11290 </tr>
11291 </tbody>
11292 </table>
11293 </div>
11294 <div class="section" id="clocks-for-navss0-modss-device">
11295 <span id="soc-doc-j784s4-public-clks-navss0-modss"></span><h3>Clocks for NAVSS0_MODSS Device<a class="headerlink" href="#clocks-for-navss0-modss-device" title="Permalink to this headline">¶</a></h3>
11296 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MODSS</span></a> (ID = 309)</p>
11297 <p>Following is a mapping of Clocks IDs to function:</p>
11298 <table border="1" class="docutils">
11299 <colgroup>
11300 <col width="24%" />
11301 <col width="50%" />
11302 <col width="26%" />
11303 </colgroup>
11304 <thead valign="bottom">
11305 <tr class="row-odd"><th class="head">Clock ID</th>
11306 <th class="head">Name</th>
11307 <th class="head">Function</th>
11308 </tr>
11309 </thead>
11310 <tbody valign="top">
11311 <tr class="row-even"><td>0</td>
11312 <td>DEV_NAVSS0_MODSS_VD2CLK</td>
11313 <td>Input clock</td>
11314 </tr>
11315 </tbody>
11316 </table>
11317 </div>
11318 <div class="section" id="clocks-for-navss0-modss-inta-0-device">
11319 <span id="soc-doc-j784s4-public-clks-navss0-modss-inta-0"></span><h3>Clocks for NAVSS0_MODSS_INTA_0 Device<a class="headerlink" href="#clocks-for-navss0-modss-inta-0-device" title="Permalink to this headline">¶</a></h3>
11320 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MODSS_INTA_0</span></a> (ID = 310)</p>
11321 <p>Following is a mapping of Clocks IDs to function:</p>
11322 <table border="1" class="docutils">
11323 <colgroup>
11324 <col width="21%" />
11325 <col width="57%" />
11326 <col width="22%" />
11327 </colgroup>
11328 <thead valign="bottom">
11329 <tr class="row-odd"><th class="head">Clock ID</th>
11330 <th class="head">Name</th>
11331 <th class="head">Function</th>
11332 </tr>
11333 </thead>
11334 <tbody valign="top">
11335 <tr class="row-even"><td>0</td>
11336 <td>DEV_NAVSS0_MODSS_INTA_0_SYS_CLK</td>
11337 <td>Input clock</td>
11338 </tr>
11339 </tbody>
11340 </table>
11341 </div>
11342 <div class="section" id="clocks-for-navss0-modss-inta-1-device">
11343 <span id="soc-doc-j784s4-public-clks-navss0-modss-inta-1"></span><h3>Clocks for NAVSS0_MODSS_INTA_1 Device<a class="headerlink" href="#clocks-for-navss0-modss-inta-1-device" title="Permalink to this headline">¶</a></h3>
11344 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_MODSS_INTA_1</span></a> (ID = 311)</p>
11345 <p>Following is a mapping of Clocks IDs to function:</p>
11346 <table border="1" class="docutils">
11347 <colgroup>
11348 <col width="21%" />
11349 <col width="57%" />
11350 <col width="22%" />
11351 </colgroup>
11352 <thead valign="bottom">
11353 <tr class="row-odd"><th class="head">Clock ID</th>
11354 <th class="head">Name</th>
11355 <th class="head">Function</th>
11356 </tr>
11357 </thead>
11358 <tbody valign="top">
11359 <tr class="row-even"><td>0</td>
11360 <td>DEV_NAVSS0_MODSS_INTA_1_SYS_CLK</td>
11361 <td>Input clock</td>
11362 </tr>
11363 </tbody>
11364 </table>
11365 </div>
11366 <div class="section" id="clocks-for-navss0-proxy-0-device">
11367 <span id="soc-doc-j784s4-public-clks-navss0-proxy-0"></span><h3>Clocks for NAVSS0_PROXY_0 Device<a class="headerlink" href="#clocks-for-navss0-proxy-0-device" title="Permalink to this headline">¶</a></h3>
11368 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_PROXY_0</span></a> (ID = 312)</p>
11369 <p>Following is a mapping of Clocks IDs to function:</p>
11370 <table border="1" class="docutils">
11371 <colgroup>
11372 <col width="23%" />
11373 <col width="53%" />
11374 <col width="25%" />
11375 </colgroup>
11376 <thead valign="bottom">
11377 <tr class="row-odd"><th class="head">Clock ID</th>
11378 <th class="head">Name</th>
11379 <th class="head">Function</th>
11380 </tr>
11381 </thead>
11382 <tbody valign="top">
11383 <tr class="row-even"><td>0</td>
11384 <td>DEV_NAVSS0_PROXY_0_CLK_CLK</td>
11385 <td>Input clock</td>
11386 </tr>
11387 </tbody>
11388 </table>
11389 </div>
11390 <div class="section" id="clocks-for-navss0-pvu-0-device">
11391 <span id="soc-doc-j784s4-public-clks-navss0-pvu-0"></span><h3>Clocks for NAVSS0_PVU_0 Device<a class="headerlink" href="#clocks-for-navss0-pvu-0-device" title="Permalink to this headline">¶</a></h3>
11392 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_PVU_0</span></a> (ID = 313)</p>
11393 <p>Following is a mapping of Clocks IDs to function:</p>
11394 <table border="1" class="docutils">
11395 <colgroup>
11396 <col width="24%" />
11397 <col width="51%" />
11398 <col width="25%" />
11399 </colgroup>
11400 <thead valign="bottom">
11401 <tr class="row-odd"><th class="head">Clock ID</th>
11402 <th class="head">Name</th>
11403 <th class="head">Function</th>
11404 </tr>
11405 </thead>
11406 <tbody valign="top">
11407 <tr class="row-even"><td>0</td>
11408 <td>DEV_NAVSS0_PVU_0_CLK_CLK</td>
11409 <td>Input clock</td>
11410 </tr>
11411 </tbody>
11412 </table>
11413 </div>
11414 <div class="section" id="clocks-for-navss0-pvu-1-device">
11415 <span id="soc-doc-j784s4-public-clks-navss0-pvu-1"></span><h3>Clocks for NAVSS0_PVU_1 Device<a class="headerlink" href="#clocks-for-navss0-pvu-1-device" title="Permalink to this headline">¶</a></h3>
11416 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_PVU_1</span></a> (ID = 314)</p>
11417 <p>Following is a mapping of Clocks IDs to function:</p>
11418 <table border="1" class="docutils">
11419 <colgroup>
11420 <col width="24%" />
11421 <col width="51%" />
11422 <col width="25%" />
11423 </colgroup>
11424 <thead valign="bottom">
11425 <tr class="row-odd"><th class="head">Clock ID</th>
11426 <th class="head">Name</th>
11427 <th class="head">Function</th>
11428 </tr>
11429 </thead>
11430 <tbody valign="top">
11431 <tr class="row-even"><td>0</td>
11432 <td>DEV_NAVSS0_PVU_1_CLK_CLK</td>
11433 <td>Input clock</td>
11434 </tr>
11435 </tbody>
11436 </table>
11437 </div>
11438 <div class="section" id="clocks-for-navss0-ringacc-0-device">
11439 <span id="soc-doc-j784s4-public-clks-navss0-ringacc-0"></span><h3>Clocks for NAVSS0_RINGACC_0 Device<a class="headerlink" href="#clocks-for-navss0-ringacc-0-device" title="Permalink to this headline">¶</a></h3>
11440 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_RINGACC_0</span></a> (ID = 315)</p>
11441 <p>Following is a mapping of Clocks IDs to function:</p>
11442 <table border="1" class="docutils">
11443 <colgroup>
11444 <col width="22%" />
11445 <col width="55%" />
11446 <col width="24%" />
11447 </colgroup>
11448 <thead valign="bottom">
11449 <tr class="row-odd"><th class="head">Clock ID</th>
11450 <th class="head">Name</th>
11451 <th class="head">Function</th>
11452 </tr>
11453 </thead>
11454 <tbody valign="top">
11455 <tr class="row-even"><td>0</td>
11456 <td>DEV_NAVSS0_RINGACC_0_SYS_CLK</td>
11457 <td>Input clock</td>
11458 </tr>
11459 </tbody>
11460 </table>
11461 </div>
11462 <div class="section" id="clocks-for-navss0-spinlock-0-device">
11463 <span id="soc-doc-j784s4-public-clks-navss0-spinlock-0"></span><h3>Clocks for NAVSS0_SPINLOCK_0 Device<a class="headerlink" href="#clocks-for-navss0-spinlock-0-device" title="Permalink to this headline">¶</a></h3>
11464 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_SPINLOCK_0</span></a> (ID = 316)</p>
11465 <p>Following is a mapping of Clocks IDs to function:</p>
11466 <table border="1" class="docutils">
11467 <colgroup>
11468 <col width="23%" />
11469 <col width="52%" />
11470 <col width="25%" />
11471 </colgroup>
11472 <thead valign="bottom">
11473 <tr class="row-odd"><th class="head">Clock ID</th>
11474 <th class="head">Name</th>
11475 <th class="head">Function</th>
11476 </tr>
11477 </thead>
11478 <tbody valign="top">
11479 <tr class="row-even"><td>0</td>
11480 <td>DEV_NAVSS0_SPINLOCK_0_CLK</td>
11481 <td>Input clock</td>
11482 </tr>
11483 </tbody>
11484 </table>
11485 </div>
11486 <div class="section" id="clocks-for-navss0-timermgr-0-device">
11487 <span id="soc-doc-j784s4-public-clks-navss0-timermgr-0"></span><h3>Clocks for NAVSS0_TIMERMGR_0 Device<a class="headerlink" href="#clocks-for-navss0-timermgr-0-device" title="Permalink to this headline">¶</a></h3>
11488 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_TIMERMGR_0</span></a> (ID = 317)</p>
11489 <p>Following is a mapping of Clocks IDs to function:</p>
11490 <table border="1" class="docutils">
11491 <colgroup>
11492 <col width="20%" />
11493 <col width="59%" />
11494 <col width="21%" />
11495 </colgroup>
11496 <thead valign="bottom">
11497 <tr class="row-odd"><th class="head">Clock ID</th>
11498 <th class="head">Name</th>
11499 <th class="head">Function</th>
11500 </tr>
11501 </thead>
11502 <tbody valign="top">
11503 <tr class="row-even"><td>0</td>
11504 <td>DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT</td>
11505 <td>Input clock</td>
11506 </tr>
11507 <tr class="row-odd"><td>1</td>
11508 <td>DEV_NAVSS0_TIMERMGR_0_VCLK_CLK</td>
11509 <td>Input clock</td>
11510 </tr>
11511 </tbody>
11512 </table>
11513 </div>
11514 <div class="section" id="clocks-for-navss0-timermgr-1-device">
11515 <span id="soc-doc-j784s4-public-clks-navss0-timermgr-1"></span><h3>Clocks for NAVSS0_TIMERMGR_1 Device<a class="headerlink" href="#clocks-for-navss0-timermgr-1-device" title="Permalink to this headline">¶</a></h3>
11516 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_TIMERMGR_1</span></a> (ID = 318)</p>
11517 <p>Following is a mapping of Clocks IDs to function:</p>
11518 <table border="1" class="docutils">
11519 <colgroup>
11520 <col width="20%" />
11521 <col width="59%" />
11522 <col width="21%" />
11523 </colgroup>
11524 <thead valign="bottom">
11525 <tr class="row-odd"><th class="head">Clock ID</th>
11526 <th class="head">Name</th>
11527 <th class="head">Function</th>
11528 </tr>
11529 </thead>
11530 <tbody valign="top">
11531 <tr class="row-even"><td>0</td>
11532 <td>DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT</td>
11533 <td>Input clock</td>
11534 </tr>
11535 <tr class="row-odd"><td>1</td>
11536 <td>DEV_NAVSS0_TIMERMGR_1_VCLK_CLK</td>
11537 <td>Input clock</td>
11538 </tr>
11539 </tbody>
11540 </table>
11541 </div>
11542 <div class="section" id="clocks-for-navss0-udmap-0-device">
11543 <span id="soc-doc-j784s4-public-clks-navss0-udmap-0"></span><h3>Clocks for NAVSS0_UDMAP_0 Device<a class="headerlink" href="#clocks-for-navss0-udmap-0-device" title="Permalink to this headline">¶</a></h3>
11544 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_UDMAP_0</span></a> (ID = 319)</p>
11545 <p>Following is a mapping of Clocks IDs to function:</p>
11546 <table border="1" class="docutils">
11547 <colgroup>
11548 <col width="23%" />
11549 <col width="53%" />
11550 <col width="25%" />
11551 </colgroup>
11552 <thead valign="bottom">
11553 <tr class="row-odd"><th class="head">Clock ID</th>
11554 <th class="head">Name</th>
11555 <th class="head">Function</th>
11556 </tr>
11557 </thead>
11558 <tbody valign="top">
11559 <tr class="row-even"><td>0</td>
11560 <td>DEV_NAVSS0_UDMAP_0_SYS_CLK</td>
11561 <td>Input clock</td>
11562 </tr>
11563 </tbody>
11564 </table>
11565 </div>
11566 <div class="section" id="clocks-for-navss0-udmass-device">
11567 <span id="soc-doc-j784s4-public-clks-navss0-udmass"></span><h3>Clocks for NAVSS0_UDMASS Device<a class="headerlink" href="#clocks-for-navss0-udmass-device" title="Permalink to this headline">¶</a></h3>
11568 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_UDMASS</span></a> (ID = 320)</p>
11569 <p>Following is a mapping of Clocks IDs to function:</p>
11570 <table border="1" class="docutils">
11571 <colgroup>
11572 <col width="24%" />
11573 <col width="51%" />
11574 <col width="25%" />
11575 </colgroup>
11576 <thead valign="bottom">
11577 <tr class="row-odd"><th class="head">Clock ID</th>
11578 <th class="head">Name</th>
11579 <th class="head">Function</th>
11580 </tr>
11581 </thead>
11582 <tbody valign="top">
11583 <tr class="row-even"><td>0</td>
11584 <td>DEV_NAVSS0_UDMASS_VD2CLK</td>
11585 <td>Input clock</td>
11586 </tr>
11587 </tbody>
11588 </table>
11589 </div>
11590 <div class="section" id="clocks-for-navss0-udmass-inta-0-device">
11591 <span id="soc-doc-j784s4-public-clks-navss0-udmass-inta-0"></span><h3>Clocks for NAVSS0_UDMASS_INTA_0 Device<a class="headerlink" href="#clocks-for-navss0-udmass-inta-0-device" title="Permalink to this headline">¶</a></h3>
11592 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_UDMASS_INTA_0</span></a> (ID = 321)</p>
11593 <p>Following is a mapping of Clocks IDs to function:</p>
11594 <table border="1" class="docutils">
11595 <colgroup>
11596 <col width="20%" />
11597 <col width="58%" />
11598 <col width="22%" />
11599 </colgroup>
11600 <thead valign="bottom">
11601 <tr class="row-odd"><th class="head">Clock ID</th>
11602 <th class="head">Name</th>
11603 <th class="head">Function</th>
11604 </tr>
11605 </thead>
11606 <tbody valign="top">
11607 <tr class="row-even"><td>0</td>
11608 <td>DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK</td>
11609 <td>Input clock</td>
11610 </tr>
11611 </tbody>
11612 </table>
11613 </div>
11614 <div class="section" id="clocks-for-navss0-virtss-device">
11615 <span id="soc-doc-j784s4-public-clks-navss0-virtss"></span><h3>Clocks for NAVSS0_VIRTSS Device<a class="headerlink" href="#clocks-for-navss0-virtss-device" title="Permalink to this headline">¶</a></h3>
11616 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_NAVSS0_VIRTSS</span></a> (ID = 322)</p>
11617 <p>Following is a mapping of Clocks IDs to function:</p>
11618 <table border="1" class="docutils">
11619 <colgroup>
11620 <col width="24%" />
11621 <col width="51%" />
11622 <col width="25%" />
11623 </colgroup>
11624 <thead valign="bottom">
11625 <tr class="row-odd"><th class="head">Clock ID</th>
11626 <th class="head">Name</th>
11627 <th class="head">Function</th>
11628 </tr>
11629 </thead>
11630 <tbody valign="top">
11631 <tr class="row-even"><td>0</td>
11632 <td>DEV_NAVSS0_VIRTSS_VD2CLK</td>
11633 <td>Input clock</td>
11634 </tr>
11635 </tbody>
11636 </table>
11637 </div>
11638 <div class="section" id="clocks-for-pbist0-device">
11639 <span id="soc-doc-j784s4-public-clks-pbist0"></span><h3>Clocks for PBIST0 Device<a class="headerlink" href="#clocks-for-pbist0-device" title="Permalink to this headline">¶</a></h3>
11640 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PBIST0</span></a> (ID = 232)</p>
11641 <p>Following is a mapping of Clocks IDs to function:</p>
11642 <table border="1" class="docutils">
11643 <colgroup>
11644 <col width="26%" />
11645 <col width="46%" />
11646 <col width="28%" />
11647 </colgroup>
11648 <thead valign="bottom">
11649 <tr class="row-odd"><th class="head">Clock ID</th>
11650 <th class="head">Name</th>
11651 <th class="head">Function</th>
11652 </tr>
11653 </thead>
11654 <tbody valign="top">
11655 <tr class="row-even"><td>7</td>
11656 <td>DEV_PBIST0_CLK8_CLK</td>
11657 <td>Input clock</td>
11658 </tr>
11659 </tbody>
11660 </table>
11661 </div>
11662 <div class="section" id="clocks-for-pbist1-device">
11663 <span id="soc-doc-j784s4-public-clks-pbist1"></span><h3>Clocks for PBIST1 Device<a class="headerlink" href="#clocks-for-pbist1-device" title="Permalink to this headline">¶</a></h3>
11664 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PBIST1</span></a> (ID = 233)</p>
11665 <p>Following is a mapping of Clocks IDs to function:</p>
11666 <table border="1" class="docutils">
11667 <colgroup>
11668 <col width="26%" />
11669 <col width="46%" />
11670 <col width="28%" />
11671 </colgroup>
11672 <thead valign="bottom">
11673 <tr class="row-odd"><th class="head">Clock ID</th>
11674 <th class="head">Name</th>
11675 <th class="head">Function</th>
11676 </tr>
11677 </thead>
11678 <tbody valign="top">
11679 <tr class="row-even"><td>7</td>
11680 <td>DEV_PBIST1_CLK8_CLK</td>
11681 <td>Input clock</td>
11682 </tr>
11683 </tbody>
11684 </table>
11685 </div>
11686 <div class="section" id="clocks-for-pbist10-device">
11687 <span id="soc-doc-j784s4-public-clks-pbist10"></span><h3>Clocks for PBIST10 Device<a class="headerlink" href="#clocks-for-pbist10-device" title="Permalink to this headline">¶</a></h3>
11688 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PBIST10</span></a> (ID = 236)</p>
11689 <p>Following is a mapping of Clocks IDs to function:</p>
11690 <table border="1" class="docutils">
11691 <colgroup>
11692 <col width="26%" />
11693 <col width="47%" />
11694 <col width="28%" />
11695 </colgroup>
11696 <thead valign="bottom">
11697 <tr class="row-odd"><th class="head">Clock ID</th>
11698 <th class="head">Name</th>
11699 <th class="head">Function</th>
11700 </tr>
11701 </thead>
11702 <tbody valign="top">
11703 <tr class="row-even"><td>7</td>
11704 <td>DEV_PBIST10_CLK8_CLK</td>
11705 <td>Input clock</td>
11706 </tr>
11707 </tbody>
11708 </table>
11709 </div>
11710 <div class="section" id="clocks-for-pbist11-device">
11711 <span id="soc-doc-j784s4-public-clks-pbist11"></span><h3>Clocks for PBIST11 Device<a class="headerlink" href="#clocks-for-pbist11-device" title="Permalink to this headline">¶</a></h3>
11712 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PBIST11</span></a> (ID = 227)</p>
11713 <p>Following is a mapping of Clocks IDs to function:</p>
11714 <table border="1" class="docutils">
11715 <colgroup>
11716 <col width="26%" />
11717 <col width="47%" />
11718 <col width="28%" />
11719 </colgroup>
11720 <thead valign="bottom">
11721 <tr class="row-odd"><th class="head">Clock ID</th>
11722 <th class="head">Name</th>
11723 <th class="head">Function</th>
11724 </tr>
11725 </thead>
11726 <tbody valign="top">
11727 <tr class="row-even"><td>6</td>
11728 <td>DEV_PBIST11_CLK7_CLK</td>
11729 <td>Input clock</td>
11730 </tr>
11731 </tbody>
11732 </table>
11733 </div>
11734 <div class="section" id="clocks-for-pbist13-device">
11735 <span id="soc-doc-j784s4-public-clks-pbist13"></span><h3>Clocks for PBIST13 Device<a class="headerlink" href="#clocks-for-pbist13-device" title="Permalink to this headline">¶</a></h3>
11736 <p><strong>This device has no defined clocks.</strong></p>
11737 </div>
11738 <div class="section" id="clocks-for-pbist14-device">
11739 <span id="soc-doc-j784s4-public-clks-pbist14"></span><h3>Clocks for PBIST14 Device<a class="headerlink" href="#clocks-for-pbist14-device" title="Permalink to this headline">¶</a></h3>
11740 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PBIST14</span></a> (ID = 237)</p>
11741 <p>Following is a mapping of Clocks IDs to function:</p>
11742 <table border="1" class="docutils">
11743 <colgroup>
11744 <col width="26%" />
11745 <col width="47%" />
11746 <col width="28%" />
11747 </colgroup>
11748 <thead valign="bottom">
11749 <tr class="row-odd"><th class="head">Clock ID</th>
11750 <th class="head">Name</th>
11751 <th class="head">Function</th>
11752 </tr>
11753 </thead>
11754 <tbody valign="top">
11755 <tr class="row-even"><td>7</td>
11756 <td>DEV_PBIST14_CLK8_CLK</td>
11757 <td>Input clock</td>
11758 </tr>
11759 </tbody>
11760 </table>
11761 </div>
11762 <div class="section" id="clocks-for-pbist15-device">
11763 <span id="soc-doc-j784s4-public-clks-pbist15"></span><h3>Clocks for PBIST15 Device<a class="headerlink" href="#clocks-for-pbist15-device" title="Permalink to this headline">¶</a></h3>
11764 <p><strong>This device has no defined clocks.</strong></p>
11765 </div>
11766 <div class="section" id="clocks-for-pbist2-device">
11767 <span id="soc-doc-j784s4-public-clks-pbist2"></span><h3>Clocks for PBIST2 Device<a class="headerlink" href="#clocks-for-pbist2-device" title="Permalink to this headline">¶</a></h3>
11768 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PBIST2</span></a> (ID = 235)</p>
11769 <p>Following is a mapping of Clocks IDs to function:</p>
11770 <table border="1" class="docutils">
11771 <colgroup>
11772 <col width="26%" />
11773 <col width="46%" />
11774 <col width="28%" />
11775 </colgroup>
11776 <thead valign="bottom">
11777 <tr class="row-odd"><th class="head">Clock ID</th>
11778 <th class="head">Name</th>
11779 <th class="head">Function</th>
11780 </tr>
11781 </thead>
11782 <tbody valign="top">
11783 <tr class="row-even"><td>7</td>
11784 <td>DEV_PBIST2_CLK8_CLK</td>
11785 <td>Input clock</td>
11786 </tr>
11787 </tbody>
11788 </table>
11789 </div>
11790 <div class="section" id="clocks-for-pbist3-device">
11791 <span id="soc-doc-j784s4-public-clks-pbist3"></span><h3>Clocks for PBIST3 Device<a class="headerlink" href="#clocks-for-pbist3-device" title="Permalink to this headline">¶</a></h3>
11792 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PBIST3</span></a> (ID = 231)</p>
11793 <p>Following is a mapping of Clocks IDs to function:</p>
11794 <table border="1" class="docutils">
11795 <colgroup>
11796 <col width="26%" />
11797 <col width="46%" />
11798 <col width="28%" />
11799 </colgroup>
11800 <thead valign="bottom">
11801 <tr class="row-odd"><th class="head">Clock ID</th>
11802 <th class="head">Name</th>
11803 <th class="head">Function</th>
11804 </tr>
11805 </thead>
11806 <tbody valign="top">
11807 <tr class="row-even"><td>7</td>
11808 <td>DEV_PBIST3_CLK8_CLK</td>
11809 <td>Input clock</td>
11810 </tr>
11811 </tbody>
11812 </table>
11813 </div>
11814 <div class="section" id="clocks-for-pbist4-device">
11815 <span id="soc-doc-j784s4-public-clks-pbist4"></span><h3>Clocks for PBIST4 Device<a class="headerlink" href="#clocks-for-pbist4-device" title="Permalink to this headline">¶</a></h3>
11816 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PBIST4</span></a> (ID = 234)</p>
11817 <p>Following is a mapping of Clocks IDs to function:</p>
11818 <table border="1" class="docutils">
11819 <colgroup>
11820 <col width="26%" />
11821 <col width="46%" />
11822 <col width="28%" />
11823 </colgroup>
11824 <thead valign="bottom">
11825 <tr class="row-odd"><th class="head">Clock ID</th>
11826 <th class="head">Name</th>
11827 <th class="head">Function</th>
11828 </tr>
11829 </thead>
11830 <tbody valign="top">
11831 <tr class="row-even"><td>7</td>
11832 <td>DEV_PBIST4_CLK8_CLK</td>
11833 <td>Input clock</td>
11834 </tr>
11835 </tbody>
11836 </table>
11837 </div>
11838 <div class="section" id="clocks-for-pbist5-device">
11839 <span id="soc-doc-j784s4-public-clks-pbist5"></span><h3>Clocks for PBIST5 Device<a class="headerlink" href="#clocks-for-pbist5-device" title="Permalink to this headline">¶</a></h3>
11840 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PBIST5</span></a> (ID = 226)</p>
11841 <p>Following is a mapping of Clocks IDs to function:</p>
11842 <table border="1" class="docutils">
11843 <colgroup>
11844 <col width="26%" />
11845 <col width="46%" />
11846 <col width="28%" />
11847 </colgroup>
11848 <thead valign="bottom">
11849 <tr class="row-odd"><th class="head">Clock ID</th>
11850 <th class="head">Name</th>
11851 <th class="head">Function</th>
11852 </tr>
11853 </thead>
11854 <tbody valign="top">
11855 <tr class="row-even"><td>7</td>
11856 <td>DEV_PBIST5_CLK8_CLK</td>
11857 <td>Input clock</td>
11858 </tr>
11859 </tbody>
11860 </table>
11861 </div>
11862 <div class="section" id="clocks-for-pbist7-device">
11863 <span id="soc-doc-j784s4-public-clks-pbist7"></span><h3>Clocks for PBIST7 Device<a class="headerlink" href="#clocks-for-pbist7-device" title="Permalink to this headline">¶</a></h3>
11864 <p><strong>This device has no defined clocks.</strong></p>
11865 </div>
11866 <div class="section" id="clocks-for-pbist8-device">
11867 <span id="soc-doc-j784s4-public-clks-pbist8"></span><h3>Clocks for PBIST8 Device<a class="headerlink" href="#clocks-for-pbist8-device" title="Permalink to this headline">¶</a></h3>
11868 <p><strong>This device has no defined clocks.</strong></p>
11869 </div>
11870 <div class="section" id="clocks-for-pcie0-device">
11871 <span id="soc-doc-j784s4-public-clks-pcie0"></span><h3>Clocks for PCIE0 Device<a class="headerlink" href="#clocks-for-pcie0-device" title="Permalink to this headline">¶</a></h3>
11872 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PCIE0</span></a> (ID = 332)</p>
11873 <p>Following is a mapping of Clocks IDs to function:</p>
11874 <table border="1" class="docutils">
11875 <colgroup>
11876 <col width="8%" />
11877 <col width="53%" />
11878 <col width="39%" />
11879 </colgroup>
11880 <thead valign="bottom">
11881 <tr class="row-odd"><th class="head">Clock ID</th>
11882 <th class="head">Name</th>
11883 <th class="head">Function</th>
11884 </tr>
11885 </thead>
11886 <tbody valign="top">
11887 <tr class="row-even"><td>0</td>
11888 <td>DEV_PCIE0_PCIE_CBA_CLK</td>
11889 <td>Input clock</td>
11890 </tr>
11891 <tr class="row-odd"><td>2</td>
11892 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11893 <td>Input muxed clock</td>
11894 </tr>
11895 <tr class="row-even"><td>3</td>
11896 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
11897 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11898 </tr>
11899 <tr class="row-odd"><td>4</td>
11900 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
11901 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11902 </tr>
11903 <tr class="row-even"><td>5</td>
11904 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
11905 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11906 </tr>
11907 <tr class="row-odd"><td>6</td>
11908 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
11909 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11910 </tr>
11911 <tr class="row-even"><td>7</td>
11912 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
11913 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11914 </tr>
11915 <tr class="row-odd"><td>8</td>
11916 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
11917 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11918 </tr>
11919 <tr class="row-even"><td>9</td>
11920 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK</td>
11921 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11922 </tr>
11923 <tr class="row-odd"><td>10</td>
11924 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK</td>
11925 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11926 </tr>
11927 <tr class="row-even"><td>11</td>
11928 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK</td>
11929 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11930 </tr>
11931 <tr class="row-odd"><td>12</td>
11932 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK</td>
11933 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11934 </tr>
11935 <tr class="row-even"><td>13</td>
11936 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK</td>
11937 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11938 </tr>
11939 <tr class="row-odd"><td>14</td>
11940 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK</td>
11941 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11942 </tr>
11943 <tr class="row-even"><td>15</td>
11944 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK</td>
11945 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11946 </tr>
11947 <tr class="row-odd"><td>16</td>
11948 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK</td>
11949 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11950 </tr>
11951 <tr class="row-even"><td>17</td>
11952 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
11953 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11954 </tr>
11955 <tr class="row-odd"><td>18</td>
11956 <td>DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
11957 <td>Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK</td>
11958 </tr>
11959 <tr class="row-even"><td>19</td>
11960 <td>DEV_PCIE0_PCIE_LANE0_REFCLK</td>
11961 <td>Input clock</td>
11962 </tr>
11963 <tr class="row-odd"><td>20</td>
11964 <td>DEV_PCIE0_PCIE_LANE0_RXCLK</td>
11965 <td>Input clock</td>
11966 </tr>
11967 <tr class="row-even"><td>21</td>
11968 <td>DEV_PCIE0_PCIE_LANE0_RXFCLK</td>
11969 <td>Input clock</td>
11970 </tr>
11971 <tr class="row-odd"><td>22</td>
11972 <td>DEV_PCIE0_PCIE_LANE0_TXCLK</td>
11973 <td>Output clock</td>
11974 </tr>
11975 <tr class="row-even"><td>23</td>
11976 <td>DEV_PCIE0_PCIE_LANE0_TXFCLK</td>
11977 <td>Input clock</td>
11978 </tr>
11979 <tr class="row-odd"><td>24</td>
11980 <td>DEV_PCIE0_PCIE_LANE0_TXMCLK</td>
11981 <td>Input clock</td>
11982 </tr>
11983 <tr class="row-even"><td>25</td>
11984 <td>DEV_PCIE0_PCIE_LANE1_REFCLK</td>
11985 <td>Input clock</td>
11986 </tr>
11987 <tr class="row-odd"><td>26</td>
11988 <td>DEV_PCIE0_PCIE_LANE1_RXCLK</td>
11989 <td>Input clock</td>
11990 </tr>
11991 <tr class="row-even"><td>27</td>
11992 <td>DEV_PCIE0_PCIE_LANE1_RXFCLK</td>
11993 <td>Input clock</td>
11994 </tr>
11995 <tr class="row-odd"><td>28</td>
11996 <td>DEV_PCIE0_PCIE_LANE1_TXCLK</td>
11997 <td>Output clock</td>
11998 </tr>
11999 <tr class="row-even"><td>29</td>
12000 <td>DEV_PCIE0_PCIE_LANE1_TXFCLK</td>
12001 <td>Input clock</td>
12002 </tr>
12003 <tr class="row-odd"><td>30</td>
12004 <td>DEV_PCIE0_PCIE_LANE1_TXMCLK</td>
12005 <td>Input clock</td>
12006 </tr>
12007 <tr class="row-even"><td>31</td>
12008 <td>DEV_PCIE0_PCIE_LANE2_REFCLK</td>
12009 <td>Input clock</td>
12010 </tr>
12011 <tr class="row-odd"><td>32</td>
12012 <td>DEV_PCIE0_PCIE_LANE2_RXCLK</td>
12013 <td>Input clock</td>
12014 </tr>
12015 <tr class="row-even"><td>33</td>
12016 <td>DEV_PCIE0_PCIE_LANE2_RXFCLK</td>
12017 <td>Input clock</td>
12018 </tr>
12019 <tr class="row-odd"><td>34</td>
12020 <td>DEV_PCIE0_PCIE_LANE2_TXCLK</td>
12021 <td>Output clock</td>
12022 </tr>
12023 <tr class="row-even"><td>35</td>
12024 <td>DEV_PCIE0_PCIE_LANE2_TXFCLK</td>
12025 <td>Input clock</td>
12026 </tr>
12027 <tr class="row-odd"><td>36</td>
12028 <td>DEV_PCIE0_PCIE_LANE2_TXMCLK</td>
12029 <td>Input clock</td>
12030 </tr>
12031 <tr class="row-even"><td>37</td>
12032 <td>DEV_PCIE0_PCIE_LANE3_REFCLK</td>
12033 <td>Input clock</td>
12034 </tr>
12035 <tr class="row-odd"><td>38</td>
12036 <td>DEV_PCIE0_PCIE_LANE3_RXCLK</td>
12037 <td>Input clock</td>
12038 </tr>
12039 <tr class="row-even"><td>39</td>
12040 <td>DEV_PCIE0_PCIE_LANE3_RXFCLK</td>
12041 <td>Input clock</td>
12042 </tr>
12043 <tr class="row-odd"><td>40</td>
12044 <td>DEV_PCIE0_PCIE_LANE3_TXCLK</td>
12045 <td>Output clock</td>
12046 </tr>
12047 <tr class="row-even"><td>41</td>
12048 <td>DEV_PCIE0_PCIE_LANE3_TXFCLK</td>
12049 <td>Input clock</td>
12050 </tr>
12051 <tr class="row-odd"><td>42</td>
12052 <td>DEV_PCIE0_PCIE_LANE3_TXMCLK</td>
12053 <td>Input clock</td>
12054 </tr>
12055 <tr class="row-even"><td>43</td>
12056 <td>DEV_PCIE0_PCIE_PM_CLK</td>
12057 <td>Input clock</td>
12058 </tr>
12059 </tbody>
12060 </table>
12061 </div>
12062 <div class="section" id="clocks-for-pcie1-device">
12063 <span id="soc-doc-j784s4-public-clks-pcie1"></span><h3>Clocks for PCIE1 Device<a class="headerlink" href="#clocks-for-pcie1-device" title="Permalink to this headline">¶</a></h3>
12064 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PCIE1</span></a> (ID = 333)</p>
12065 <p>Following is a mapping of Clocks IDs to function:</p>
12066 <table border="1" class="docutils">
12067 <colgroup>
12068 <col width="8%" />
12069 <col width="53%" />
12070 <col width="39%" />
12071 </colgroup>
12072 <thead valign="bottom">
12073 <tr class="row-odd"><th class="head">Clock ID</th>
12074 <th class="head">Name</th>
12075 <th class="head">Function</th>
12076 </tr>
12077 </thead>
12078 <tbody valign="top">
12079 <tr class="row-even"><td>0</td>
12080 <td>DEV_PCIE1_PCIE_CBA_CLK</td>
12081 <td>Input clock</td>
12082 </tr>
12083 <tr class="row-odd"><td>2</td>
12084 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12085 <td>Input muxed clock</td>
12086 </tr>
12087 <tr class="row-even"><td>3</td>
12088 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
12089 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12090 </tr>
12091 <tr class="row-odd"><td>4</td>
12092 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
12093 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12094 </tr>
12095 <tr class="row-even"><td>5</td>
12096 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
12097 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12098 </tr>
12099 <tr class="row-odd"><td>6</td>
12100 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
12101 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12102 </tr>
12103 <tr class="row-even"><td>7</td>
12104 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
12105 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12106 </tr>
12107 <tr class="row-odd"><td>8</td>
12108 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
12109 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12110 </tr>
12111 <tr class="row-even"><td>9</td>
12112 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK</td>
12113 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12114 </tr>
12115 <tr class="row-odd"><td>10</td>
12116 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK</td>
12117 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12118 </tr>
12119 <tr class="row-even"><td>11</td>
12120 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK</td>
12121 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12122 </tr>
12123 <tr class="row-odd"><td>12</td>
12124 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK</td>
12125 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12126 </tr>
12127 <tr class="row-even"><td>13</td>
12128 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK</td>
12129 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12130 </tr>
12131 <tr class="row-odd"><td>14</td>
12132 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK</td>
12133 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12134 </tr>
12135 <tr class="row-even"><td>15</td>
12136 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK</td>
12137 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12138 </tr>
12139 <tr class="row-odd"><td>16</td>
12140 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK</td>
12141 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12142 </tr>
12143 <tr class="row-even"><td>17</td>
12144 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
12145 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12146 </tr>
12147 <tr class="row-odd"><td>18</td>
12148 <td>DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
12149 <td>Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK</td>
12150 </tr>
12151 <tr class="row-even"><td>19</td>
12152 <td>DEV_PCIE1_PCIE_LANE0_REFCLK</td>
12153 <td>Input clock</td>
12154 </tr>
12155 <tr class="row-odd"><td>20</td>
12156 <td>DEV_PCIE1_PCIE_LANE0_RXCLK</td>
12157 <td>Input clock</td>
12158 </tr>
12159 <tr class="row-even"><td>21</td>
12160 <td>DEV_PCIE1_PCIE_LANE0_RXFCLK</td>
12161 <td>Input clock</td>
12162 </tr>
12163 <tr class="row-odd"><td>22</td>
12164 <td>DEV_PCIE1_PCIE_LANE0_TXCLK</td>
12165 <td>Output clock</td>
12166 </tr>
12167 <tr class="row-even"><td>23</td>
12168 <td>DEV_PCIE1_PCIE_LANE0_TXFCLK</td>
12169 <td>Input clock</td>
12170 </tr>
12171 <tr class="row-odd"><td>24</td>
12172 <td>DEV_PCIE1_PCIE_LANE0_TXMCLK</td>
12173 <td>Input clock</td>
12174 </tr>
12175 <tr class="row-even"><td>25</td>
12176 <td>DEV_PCIE1_PCIE_LANE1_REFCLK</td>
12177 <td>Input clock</td>
12178 </tr>
12179 <tr class="row-odd"><td>26</td>
12180 <td>DEV_PCIE1_PCIE_LANE1_RXCLK</td>
12181 <td>Input clock</td>
12182 </tr>
12183 <tr class="row-even"><td>27</td>
12184 <td>DEV_PCIE1_PCIE_LANE1_RXFCLK</td>
12185 <td>Input clock</td>
12186 </tr>
12187 <tr class="row-odd"><td>28</td>
12188 <td>DEV_PCIE1_PCIE_LANE1_TXCLK</td>
12189 <td>Output clock</td>
12190 </tr>
12191 <tr class="row-even"><td>29</td>
12192 <td>DEV_PCIE1_PCIE_LANE1_TXFCLK</td>
12193 <td>Input clock</td>
12194 </tr>
12195 <tr class="row-odd"><td>30</td>
12196 <td>DEV_PCIE1_PCIE_LANE1_TXMCLK</td>
12197 <td>Input clock</td>
12198 </tr>
12199 <tr class="row-even"><td>31</td>
12200 <td>DEV_PCIE1_PCIE_LANE2_REFCLK</td>
12201 <td>Input clock</td>
12202 </tr>
12203 <tr class="row-odd"><td>32</td>
12204 <td>DEV_PCIE1_PCIE_LANE2_RXCLK</td>
12205 <td>Input clock</td>
12206 </tr>
12207 <tr class="row-even"><td>33</td>
12208 <td>DEV_PCIE1_PCIE_LANE2_RXFCLK</td>
12209 <td>Input clock</td>
12210 </tr>
12211 <tr class="row-odd"><td>34</td>
12212 <td>DEV_PCIE1_PCIE_LANE2_TXCLK</td>
12213 <td>Output clock</td>
12214 </tr>
12215 <tr class="row-even"><td>35</td>
12216 <td>DEV_PCIE1_PCIE_LANE2_TXFCLK</td>
12217 <td>Input clock</td>
12218 </tr>
12219 <tr class="row-odd"><td>36</td>
12220 <td>DEV_PCIE1_PCIE_LANE2_TXMCLK</td>
12221 <td>Input clock</td>
12222 </tr>
12223 <tr class="row-even"><td>37</td>
12224 <td>DEV_PCIE1_PCIE_LANE3_REFCLK</td>
12225 <td>Input clock</td>
12226 </tr>
12227 <tr class="row-odd"><td>38</td>
12228 <td>DEV_PCIE1_PCIE_LANE3_RXCLK</td>
12229 <td>Input clock</td>
12230 </tr>
12231 <tr class="row-even"><td>39</td>
12232 <td>DEV_PCIE1_PCIE_LANE3_RXFCLK</td>
12233 <td>Input clock</td>
12234 </tr>
12235 <tr class="row-odd"><td>40</td>
12236 <td>DEV_PCIE1_PCIE_LANE3_TXCLK</td>
12237 <td>Output clock</td>
12238 </tr>
12239 <tr class="row-even"><td>41</td>
12240 <td>DEV_PCIE1_PCIE_LANE3_TXFCLK</td>
12241 <td>Input clock</td>
12242 </tr>
12243 <tr class="row-odd"><td>42</td>
12244 <td>DEV_PCIE1_PCIE_LANE3_TXMCLK</td>
12245 <td>Input clock</td>
12246 </tr>
12247 <tr class="row-even"><td>43</td>
12248 <td>DEV_PCIE1_PCIE_PM_CLK</td>
12249 <td>Input clock</td>
12250 </tr>
12251 </tbody>
12252 </table>
12253 </div>
12254 <div class="section" id="clocks-for-pcie2-device">
12255 <span id="soc-doc-j784s4-public-clks-pcie2"></span><h3>Clocks for PCIE2 Device<a class="headerlink" href="#clocks-for-pcie2-device" title="Permalink to this headline">¶</a></h3>
12256 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PCIE2</span></a> (ID = 334)</p>
12257 <p>Following is a mapping of Clocks IDs to function:</p>
12258 <table border="1" class="docutils">
12259 <colgroup>
12260 <col width="8%" />
12261 <col width="53%" />
12262 <col width="39%" />
12263 </colgroup>
12264 <thead valign="bottom">
12265 <tr class="row-odd"><th class="head">Clock ID</th>
12266 <th class="head">Name</th>
12267 <th class="head">Function</th>
12268 </tr>
12269 </thead>
12270 <tbody valign="top">
12271 <tr class="row-even"><td>0</td>
12272 <td>DEV_PCIE2_PCIE_CBA_CLK</td>
12273 <td>Input clock</td>
12274 </tr>
12275 <tr class="row-odd"><td>2</td>
12276 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12277 <td>Input muxed clock</td>
12278 </tr>
12279 <tr class="row-even"><td>3</td>
12280 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
12281 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12282 </tr>
12283 <tr class="row-odd"><td>4</td>
12284 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
12285 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12286 </tr>
12287 <tr class="row-even"><td>5</td>
12288 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
12289 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12290 </tr>
12291 <tr class="row-odd"><td>6</td>
12292 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
12293 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12294 </tr>
12295 <tr class="row-even"><td>7</td>
12296 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
12297 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12298 </tr>
12299 <tr class="row-odd"><td>8</td>
12300 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
12301 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12302 </tr>
12303 <tr class="row-even"><td>9</td>
12304 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK</td>
12305 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12306 </tr>
12307 <tr class="row-odd"><td>10</td>
12308 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK</td>
12309 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12310 </tr>
12311 <tr class="row-even"><td>11</td>
12312 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK</td>
12313 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12314 </tr>
12315 <tr class="row-odd"><td>12</td>
12316 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK</td>
12317 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12318 </tr>
12319 <tr class="row-even"><td>13</td>
12320 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK</td>
12321 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12322 </tr>
12323 <tr class="row-odd"><td>14</td>
12324 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK</td>
12325 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12326 </tr>
12327 <tr class="row-even"><td>15</td>
12328 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK</td>
12329 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12330 </tr>
12331 <tr class="row-odd"><td>16</td>
12332 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK</td>
12333 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12334 </tr>
12335 <tr class="row-even"><td>17</td>
12336 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
12337 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12338 </tr>
12339 <tr class="row-odd"><td>18</td>
12340 <td>DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
12341 <td>Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK</td>
12342 </tr>
12343 <tr class="row-even"><td>19</td>
12344 <td>DEV_PCIE2_PCIE_LANE0_REFCLK</td>
12345 <td>Input clock</td>
12346 </tr>
12347 <tr class="row-odd"><td>20</td>
12348 <td>DEV_PCIE2_PCIE_LANE0_RXCLK</td>
12349 <td>Input clock</td>
12350 </tr>
12351 <tr class="row-even"><td>21</td>
12352 <td>DEV_PCIE2_PCIE_LANE0_RXFCLK</td>
12353 <td>Input clock</td>
12354 </tr>
12355 <tr class="row-odd"><td>22</td>
12356 <td>DEV_PCIE2_PCIE_LANE0_TXCLK</td>
12357 <td>Output clock</td>
12358 </tr>
12359 <tr class="row-even"><td>23</td>
12360 <td>DEV_PCIE2_PCIE_LANE0_TXFCLK</td>
12361 <td>Input clock</td>
12362 </tr>
12363 <tr class="row-odd"><td>24</td>
12364 <td>DEV_PCIE2_PCIE_LANE0_TXMCLK</td>
12365 <td>Input clock</td>
12366 </tr>
12367 <tr class="row-even"><td>25</td>
12368 <td>DEV_PCIE2_PCIE_LANE1_REFCLK</td>
12369 <td>Input clock</td>
12370 </tr>
12371 <tr class="row-odd"><td>26</td>
12372 <td>DEV_PCIE2_PCIE_LANE1_RXCLK</td>
12373 <td>Input clock</td>
12374 </tr>
12375 <tr class="row-even"><td>27</td>
12376 <td>DEV_PCIE2_PCIE_LANE1_RXFCLK</td>
12377 <td>Input clock</td>
12378 </tr>
12379 <tr class="row-odd"><td>28</td>
12380 <td>DEV_PCIE2_PCIE_LANE1_TXCLK</td>
12381 <td>Output clock</td>
12382 </tr>
12383 <tr class="row-even"><td>29</td>
12384 <td>DEV_PCIE2_PCIE_LANE1_TXFCLK</td>
12385 <td>Input clock</td>
12386 </tr>
12387 <tr class="row-odd"><td>30</td>
12388 <td>DEV_PCIE2_PCIE_LANE1_TXMCLK</td>
12389 <td>Input clock</td>
12390 </tr>
12391 <tr class="row-even"><td>43</td>
12392 <td>DEV_PCIE2_PCIE_PM_CLK</td>
12393 <td>Input clock</td>
12394 </tr>
12395 </tbody>
12396 </table>
12397 </div>
12398 <div class="section" id="clocks-for-pcie3-device">
12399 <span id="soc-doc-j784s4-public-clks-pcie3"></span><h3>Clocks for PCIE3 Device<a class="headerlink" href="#clocks-for-pcie3-device" title="Permalink to this headline">¶</a></h3>
12400 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PCIE3</span></a> (ID = 335)</p>
12401 <p>Following is a mapping of Clocks IDs to function:</p>
12402 <table border="1" class="docutils">
12403 <colgroup>
12404 <col width="8%" />
12405 <col width="53%" />
12406 <col width="39%" />
12407 </colgroup>
12408 <thead valign="bottom">
12409 <tr class="row-odd"><th class="head">Clock ID</th>
12410 <th class="head">Name</th>
12411 <th class="head">Function</th>
12412 </tr>
12413 </thead>
12414 <tbody valign="top">
12415 <tr class="row-even"><td>0</td>
12416 <td>DEV_PCIE3_PCIE_CBA_CLK</td>
12417 <td>Input clock</td>
12418 </tr>
12419 <tr class="row-odd"><td>2</td>
12420 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12421 <td>Input muxed clock</td>
12422 </tr>
12423 <tr class="row-even"><td>3</td>
12424 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK</td>
12425 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12426 </tr>
12427 <tr class="row-odd"><td>4</td>
12428 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK</td>
12429 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12430 </tr>
12431 <tr class="row-even"><td>5</td>
12432 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT</td>
12433 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12434 </tr>
12435 <tr class="row-odd"><td>6</td>
12436 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
12437 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12438 </tr>
12439 <tr class="row-even"><td>7</td>
12440 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
12441 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12442 </tr>
12443 <tr class="row-odd"><td>8</td>
12444 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
12445 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12446 </tr>
12447 <tr class="row-even"><td>9</td>
12448 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN0_TXMCLK</td>
12449 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12450 </tr>
12451 <tr class="row-odd"><td>10</td>
12452 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN1_TXMCLK</td>
12453 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12454 </tr>
12455 <tr class="row-even"><td>11</td>
12456 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN2_TXMCLK</td>
12457 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12458 </tr>
12459 <tr class="row-odd"><td>12</td>
12460 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP2_LN3_TXMCLK</td>
12461 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12462 </tr>
12463 <tr class="row-even"><td>13</td>
12464 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN0_TXMCLK</td>
12465 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12466 </tr>
12467 <tr class="row-odd"><td>14</td>
12468 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP2_LN1_TXMCLK</td>
12469 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12470 </tr>
12471 <tr class="row-even"><td>15</td>
12472 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP1_LN2_TXMCLK</td>
12473 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12474 </tr>
12475 <tr class="row-odd"><td>16</td>
12476 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT3_MAIN_1_IP3_LN2_TXMCLK</td>
12477 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12478 </tr>
12479 <tr class="row-even"><td>17</td>
12480 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK</td>
12481 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12482 </tr>
12483 <tr class="row-odd"><td>18</td>
12484 <td>DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK</td>
12485 <td>Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK</td>
12486 </tr>
12487 <tr class="row-even"><td>19</td>
12488 <td>DEV_PCIE3_PCIE_LANE0_REFCLK</td>
12489 <td>Input clock</td>
12490 </tr>
12491 <tr class="row-odd"><td>20</td>
12492 <td>DEV_PCIE3_PCIE_LANE0_RXCLK</td>
12493 <td>Input clock</td>
12494 </tr>
12495 <tr class="row-even"><td>21</td>
12496 <td>DEV_PCIE3_PCIE_LANE0_RXFCLK</td>
12497 <td>Input clock</td>
12498 </tr>
12499 <tr class="row-odd"><td>22</td>
12500 <td>DEV_PCIE3_PCIE_LANE0_TXCLK</td>
12501 <td>Output clock</td>
12502 </tr>
12503 <tr class="row-even"><td>23</td>
12504 <td>DEV_PCIE3_PCIE_LANE0_TXFCLK</td>
12505 <td>Input clock</td>
12506 </tr>
12507 <tr class="row-odd"><td>24</td>
12508 <td>DEV_PCIE3_PCIE_LANE0_TXMCLK</td>
12509 <td>Input clock</td>
12510 </tr>
12511 <tr class="row-even"><td>25</td>
12512 <td>DEV_PCIE3_PCIE_LANE1_REFCLK</td>
12513 <td>Input clock</td>
12514 </tr>
12515 <tr class="row-odd"><td>26</td>
12516 <td>DEV_PCIE3_PCIE_LANE1_RXCLK</td>
12517 <td>Input clock</td>
12518 </tr>
12519 <tr class="row-even"><td>27</td>
12520 <td>DEV_PCIE3_PCIE_LANE1_RXFCLK</td>
12521 <td>Input clock</td>
12522 </tr>
12523 <tr class="row-odd"><td>28</td>
12524 <td>DEV_PCIE3_PCIE_LANE1_TXCLK</td>
12525 <td>Output clock</td>
12526 </tr>
12527 <tr class="row-even"><td>29</td>
12528 <td>DEV_PCIE3_PCIE_LANE1_TXFCLK</td>
12529 <td>Input clock</td>
12530 </tr>
12531 <tr class="row-odd"><td>30</td>
12532 <td>DEV_PCIE3_PCIE_LANE1_TXMCLK</td>
12533 <td>Input clock</td>
12534 </tr>
12535 <tr class="row-even"><td>43</td>
12536 <td>DEV_PCIE3_PCIE_PM_CLK</td>
12537 <td>Input clock</td>
12538 </tr>
12539 </tbody>
12540 </table>
12541 </div>
12542 <div class="section" id="clocks-for-psc0-device">
12543 <span id="soc-doc-j784s4-public-clks-psc0"></span><h3>Clocks for PSC0 Device<a class="headerlink" href="#clocks-for-psc0-device" title="Permalink to this headline">¶</a></h3>
12544 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_PSC0</span></a> (ID = 201)</p>
12545 <p>Following is a mapping of Clocks IDs to function:</p>
12546 <table border="1" class="docutils">
12547 <colgroup>
12548 <col width="27%" />
12549 <col width="43%" />
12550 <col width="30%" />
12551 </colgroup>
12552 <thead valign="bottom">
12553 <tr class="row-odd"><th class="head">Clock ID</th>
12554 <th class="head">Name</th>
12555 <th class="head">Function</th>
12556 </tr>
12557 </thead>
12558 <tbody valign="top">
12559 <tr class="row-even"><td>0</td>
12560 <td>DEV_PSC0_CLK</td>
12561 <td>Input clock</td>
12562 </tr>
12563 <tr class="row-odd"><td>1</td>
12564 <td>DEV_PSC0_SLOW_CLK</td>
12565 <td>Input clock</td>
12566 </tr>
12567 </tbody>
12568 </table>
12569 </div>
12570 <div class="section" id="clocks-for-r5fss0-device">
12571 <span id="soc-doc-j784s4-public-clks-r5fss0"></span><h3>Clocks for R5FSS0 Device<a class="headerlink" href="#clocks-for-r5fss0-device" title="Permalink to this headline">¶</a></h3>
12572 <p><strong>This device has no defined clocks.</strong></p>
12573 </div>
12574 <div class="section" id="clocks-for-r5fss0-core0-device">
12575 <span id="soc-doc-j784s4-public-clks-r5fss0-core0"></span><h3>Clocks for R5FSS0_CORE0 Device<a class="headerlink" href="#clocks-for-r5fss0-core0-device" title="Permalink to this headline">¶</a></h3>
12576 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_R5FSS0_CORE0</span></a> (ID = 339)</p>
12577 <p>Following is a mapping of Clocks IDs to function:</p>
12578 <table border="1" class="docutils">
12579 <colgroup>
12580 <col width="21%" />
12581 <col width="56%" />
12582 <col width="23%" />
12583 </colgroup>
12584 <thead valign="bottom">
12585 <tr class="row-odd"><th class="head">Clock ID</th>
12586 <th class="head">Name</th>
12587 <th class="head">Function</th>
12588 </tr>
12589 </thead>
12590 <tbody valign="top">
12591 <tr class="row-even"><td>0</td>
12592 <td>DEV_R5FSS0_CORE0_CPU_CLK</td>
12593 <td>Input clock</td>
12594 </tr>
12595 <tr class="row-odd"><td>1</td>
12596 <td>DEV_R5FSS0_CORE0_INTERFACE_CLK</td>
12597 <td>Input clock</td>
12598 </tr>
12599 </tbody>
12600 </table>
12601 </div>
12602 <div class="section" id="clocks-for-r5fss0-core1-device">
12603 <span id="soc-doc-j784s4-public-clks-r5fss0-core1"></span><h3>Clocks for R5FSS0_CORE1 Device<a class="headerlink" href="#clocks-for-r5fss0-core1-device" title="Permalink to this headline">¶</a></h3>
12604 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_R5FSS0_CORE1</span></a> (ID = 340)</p>
12605 <p>Following is a mapping of Clocks IDs to function:</p>
12606 <table border="1" class="docutils">
12607 <colgroup>
12608 <col width="21%" />
12609 <col width="56%" />
12610 <col width="23%" />
12611 </colgroup>
12612 <thead valign="bottom">
12613 <tr class="row-odd"><th class="head">Clock ID</th>
12614 <th class="head">Name</th>
12615 <th class="head">Function</th>
12616 </tr>
12617 </thead>
12618 <tbody valign="top">
12619 <tr class="row-even"><td>0</td>
12620 <td>DEV_R5FSS0_CORE1_CPU_CLK</td>
12621 <td>Input clock</td>
12622 </tr>
12623 <tr class="row-odd"><td>1</td>
12624 <td>DEV_R5FSS0_CORE1_INTERFACE_CLK</td>
12625 <td>Input clock</td>
12626 </tr>
12627 </tbody>
12628 </table>
12629 </div>
12630 <div class="section" id="clocks-for-r5fss1-device">
12631 <span id="soc-doc-j784s4-public-clks-r5fss1"></span><h3>Clocks for R5FSS1 Device<a class="headerlink" href="#clocks-for-r5fss1-device" title="Permalink to this headline">¶</a></h3>
12632 <p><strong>This device has no defined clocks.</strong></p>
12633 </div>
12634 <div class="section" id="clocks-for-r5fss1-core0-device">
12635 <span id="soc-doc-j784s4-public-clks-r5fss1-core0"></span><h3>Clocks for R5FSS1_CORE0 Device<a class="headerlink" href="#clocks-for-r5fss1-core0-device" title="Permalink to this headline">¶</a></h3>
12636 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_R5FSS1_CORE0</span></a> (ID = 341)</p>
12637 <p>Following is a mapping of Clocks IDs to function:</p>
12638 <table border="1" class="docutils">
12639 <colgroup>
12640 <col width="21%" />
12641 <col width="56%" />
12642 <col width="23%" />
12643 </colgroup>
12644 <thead valign="bottom">
12645 <tr class="row-odd"><th class="head">Clock ID</th>
12646 <th class="head">Name</th>
12647 <th class="head">Function</th>
12648 </tr>
12649 </thead>
12650 <tbody valign="top">
12651 <tr class="row-even"><td>0</td>
12652 <td>DEV_R5FSS1_CORE0_CPU_CLK</td>
12653 <td>Input clock</td>
12654 </tr>
12655 <tr class="row-odd"><td>1</td>
12656 <td>DEV_R5FSS1_CORE0_INTERFACE_CLK</td>
12657 <td>Input clock</td>
12658 </tr>
12659 </tbody>
12660 </table>
12661 </div>
12662 <div class="section" id="clocks-for-r5fss1-core1-device">
12663 <span id="soc-doc-j784s4-public-clks-r5fss1-core1"></span><h3>Clocks for R5FSS1_CORE1 Device<a class="headerlink" href="#clocks-for-r5fss1-core1-device" title="Permalink to this headline">¶</a></h3>
12664 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_R5FSS1_CORE1</span></a> (ID = 342)</p>
12665 <p>Following is a mapping of Clocks IDs to function:</p>
12666 <table border="1" class="docutils">
12667 <colgroup>
12668 <col width="21%" />
12669 <col width="56%" />
12670 <col width="23%" />
12671 </colgroup>
12672 <thead valign="bottom">
12673 <tr class="row-odd"><th class="head">Clock ID</th>
12674 <th class="head">Name</th>
12675 <th class="head">Function</th>
12676 </tr>
12677 </thead>
12678 <tbody valign="top">
12679 <tr class="row-even"><td>0</td>
12680 <td>DEV_R5FSS1_CORE1_CPU_CLK</td>
12681 <td>Input clock</td>
12682 </tr>
12683 <tr class="row-odd"><td>1</td>
12684 <td>DEV_R5FSS1_CORE1_INTERFACE_CLK</td>
12685 <td>Input clock</td>
12686 </tr>
12687 </tbody>
12688 </table>
12689 </div>
12690 <div class="section" id="clocks-for-r5fss2-device">
12691 <span id="soc-doc-j784s4-public-clks-r5fss2"></span><h3>Clocks for R5FSS2 Device<a class="headerlink" href="#clocks-for-r5fss2-device" title="Permalink to this headline">¶</a></h3>
12692 <p><strong>This device has no defined clocks.</strong></p>
12693 </div>
12694 <div class="section" id="clocks-for-r5fss2-core0-device">
12695 <span id="soc-doc-j784s4-public-clks-r5fss2-core0"></span><h3>Clocks for R5FSS2_CORE0 Device<a class="headerlink" href="#clocks-for-r5fss2-core0-device" title="Permalink to this headline">¶</a></h3>
12696 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_R5FSS2_CORE0</span></a> (ID = 343)</p>
12697 <p>Following is a mapping of Clocks IDs to function:</p>
12698 <table border="1" class="docutils">
12699 <colgroup>
12700 <col width="21%" />
12701 <col width="56%" />
12702 <col width="23%" />
12703 </colgroup>
12704 <thead valign="bottom">
12705 <tr class="row-odd"><th class="head">Clock ID</th>
12706 <th class="head">Name</th>
12707 <th class="head">Function</th>
12708 </tr>
12709 </thead>
12710 <tbody valign="top">
12711 <tr class="row-even"><td>0</td>
12712 <td>DEV_R5FSS2_CORE0_CPU_CLK</td>
12713 <td>Input clock</td>
12714 </tr>
12715 <tr class="row-odd"><td>1</td>
12716 <td>DEV_R5FSS2_CORE0_INTERFACE_CLK</td>
12717 <td>Input clock</td>
12718 </tr>
12719 </tbody>
12720 </table>
12721 </div>
12722 <div class="section" id="clocks-for-r5fss2-core1-device">
12723 <span id="soc-doc-j784s4-public-clks-r5fss2-core1"></span><h3>Clocks for R5FSS2_CORE1 Device<a class="headerlink" href="#clocks-for-r5fss2-core1-device" title="Permalink to this headline">¶</a></h3>
12724 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_R5FSS2_CORE1</span></a> (ID = 344)</p>
12725 <p>Following is a mapping of Clocks IDs to function:</p>
12726 <table border="1" class="docutils">
12727 <colgroup>
12728 <col width="21%" />
12729 <col width="56%" />
12730 <col width="23%" />
12731 </colgroup>
12732 <thead valign="bottom">
12733 <tr class="row-odd"><th class="head">Clock ID</th>
12734 <th class="head">Name</th>
12735 <th class="head">Function</th>
12736 </tr>
12737 </thead>
12738 <tbody valign="top">
12739 <tr class="row-even"><td>0</td>
12740 <td>DEV_R5FSS2_CORE1_CPU_CLK</td>
12741 <td>Input clock</td>
12742 </tr>
12743 <tr class="row-odd"><td>1</td>
12744 <td>DEV_R5FSS2_CORE1_INTERFACE_CLK</td>
12745 <td>Input clock</td>
12746 </tr>
12747 </tbody>
12748 </table>
12749 </div>
12750 <div class="section" id="clocks-for-rti0-device">
12751 <span id="soc-doc-j784s4-public-clks-rti0"></span><h3>Clocks for RTI0 Device<a class="headerlink" href="#clocks-for-rti0-device" title="Permalink to this headline">¶</a></h3>
12752 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI0</span></a> (ID = 348)</p>
12753 <p>Following is a mapping of Clocks IDs to function:</p>
12754 <table border="1" class="docutils">
12755 <colgroup>
12756 <col width="9%" />
12757 <col width="54%" />
12758 <col width="36%" />
12759 </colgroup>
12760 <thead valign="bottom">
12761 <tr class="row-odd"><th class="head">Clock ID</th>
12762 <th class="head">Name</th>
12763 <th class="head">Function</th>
12764 </tr>
12765 </thead>
12766 <tbody valign="top">
12767 <tr class="row-even"><td>0</td>
12768 <td>DEV_RTI0_RTI_CLK</td>
12769 <td>Input muxed clock</td>
12770 </tr>
12771 <tr class="row-odd"><td>1</td>
12772 <td>DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
12773 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
12774 </tr>
12775 <tr class="row-even"><td>2</td>
12776 <td>DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
12777 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
12778 </tr>
12779 <tr class="row-odd"><td>3</td>
12780 <td>DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
12781 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
12782 </tr>
12783 <tr class="row-even"><td>4</td>
12784 <td>DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
12785 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
12786 </tr>
12787 <tr class="row-odd"><td>5</td>
12788 <td>DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
12789 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
12790 </tr>
12791 <tr class="row-even"><td>6</td>
12792 <td>DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
12793 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
12794 </tr>
12795 <tr class="row-odd"><td>7</td>
12796 <td>DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
12797 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
12798 </tr>
12799 <tr class="row-even"><td>8</td>
12800 <td>DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
12801 <td>Parent input clock option to DEV_RTI0_RTI_CLK</td>
12802 </tr>
12803 <tr class="row-odd"><td>9</td>
12804 <td>DEV_RTI0_VBUSP_CLK</td>
12805 <td>Input clock</td>
12806 </tr>
12807 </tbody>
12808 </table>
12809 </div>
12810 <div class="section" id="clocks-for-rti1-device">
12811 <span id="soc-doc-j784s4-public-clks-rti1"></span><h3>Clocks for RTI1 Device<a class="headerlink" href="#clocks-for-rti1-device" title="Permalink to this headline">¶</a></h3>
12812 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI1</span></a> (ID = 349)</p>
12813 <p>Following is a mapping of Clocks IDs to function:</p>
12814 <table border="1" class="docutils">
12815 <colgroup>
12816 <col width="9%" />
12817 <col width="54%" />
12818 <col width="36%" />
12819 </colgroup>
12820 <thead valign="bottom">
12821 <tr class="row-odd"><th class="head">Clock ID</th>
12822 <th class="head">Name</th>
12823 <th class="head">Function</th>
12824 </tr>
12825 </thead>
12826 <tbody valign="top">
12827 <tr class="row-even"><td>0</td>
12828 <td>DEV_RTI1_RTI_CLK</td>
12829 <td>Input muxed clock</td>
12830 </tr>
12831 <tr class="row-odd"><td>1</td>
12832 <td>DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
12833 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
12834 </tr>
12835 <tr class="row-even"><td>2</td>
12836 <td>DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
12837 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
12838 </tr>
12839 <tr class="row-odd"><td>3</td>
12840 <td>DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
12841 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
12842 </tr>
12843 <tr class="row-even"><td>4</td>
12844 <td>DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
12845 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
12846 </tr>
12847 <tr class="row-odd"><td>5</td>
12848 <td>DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
12849 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
12850 </tr>
12851 <tr class="row-even"><td>6</td>
12852 <td>DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
12853 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
12854 </tr>
12855 <tr class="row-odd"><td>7</td>
12856 <td>DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
12857 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
12858 </tr>
12859 <tr class="row-even"><td>8</td>
12860 <td>DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
12861 <td>Parent input clock option to DEV_RTI1_RTI_CLK</td>
12862 </tr>
12863 <tr class="row-odd"><td>9</td>
12864 <td>DEV_RTI1_VBUSP_CLK</td>
12865 <td>Input clock</td>
12866 </tr>
12867 </tbody>
12868 </table>
12869 </div>
12870 <div class="section" id="clocks-for-rti15-device">
12871 <span id="soc-doc-j784s4-public-clks-rti15"></span><h3>Clocks for RTI15 Device<a class="headerlink" href="#clocks-for-rti15-device" title="Permalink to this headline">¶</a></h3>
12872 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI15</span></a> (ID = 360)</p>
12873 <p>Following is a mapping of Clocks IDs to function:</p>
12874 <table border="1" class="docutils">
12875 <colgroup>
12876 <col width="9%" />
12877 <col width="54%" />
12878 <col width="37%" />
12879 </colgroup>
12880 <thead valign="bottom">
12881 <tr class="row-odd"><th class="head">Clock ID</th>
12882 <th class="head">Name</th>
12883 <th class="head">Function</th>
12884 </tr>
12885 </thead>
12886 <tbody valign="top">
12887 <tr class="row-even"><td>0</td>
12888 <td>DEV_RTI15_RTI_CLK</td>
12889 <td>Input muxed clock</td>
12890 </tr>
12891 <tr class="row-odd"><td>1</td>
12892 <td>DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
12893 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
12894 </tr>
12895 <tr class="row-even"><td>2</td>
12896 <td>DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
12897 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
12898 </tr>
12899 <tr class="row-odd"><td>3</td>
12900 <td>DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
12901 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
12902 </tr>
12903 <tr class="row-even"><td>4</td>
12904 <td>DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
12905 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
12906 </tr>
12907 <tr class="row-odd"><td>5</td>
12908 <td>DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
12909 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
12910 </tr>
12911 <tr class="row-even"><td>6</td>
12912 <td>DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
12913 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
12914 </tr>
12915 <tr class="row-odd"><td>7</td>
12916 <td>DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
12917 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
12918 </tr>
12919 <tr class="row-even"><td>8</td>
12920 <td>DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
12921 <td>Parent input clock option to DEV_RTI15_RTI_CLK</td>
12922 </tr>
12923 <tr class="row-odd"><td>9</td>
12924 <td>DEV_RTI15_VBUSP_CLK</td>
12925 <td>Input clock</td>
12926 </tr>
12927 </tbody>
12928 </table>
12929 </div>
12930 <div class="section" id="clocks-for-rti16-device">
12931 <span id="soc-doc-j784s4-public-clks-rti16"></span><h3>Clocks for RTI16 Device<a class="headerlink" href="#clocks-for-rti16-device" title="Permalink to this headline">¶</a></h3>
12932 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI16</span></a> (ID = 356)</p>
12933 <p>Following is a mapping of Clocks IDs to function:</p>
12934 <table border="1" class="docutils">
12935 <colgroup>
12936 <col width="9%" />
12937 <col width="54%" />
12938 <col width="37%" />
12939 </colgroup>
12940 <thead valign="bottom">
12941 <tr class="row-odd"><th class="head">Clock ID</th>
12942 <th class="head">Name</th>
12943 <th class="head">Function</th>
12944 </tr>
12945 </thead>
12946 <tbody valign="top">
12947 <tr class="row-even"><td>0</td>
12948 <td>DEV_RTI16_RTI_CLK</td>
12949 <td>Input muxed clock</td>
12950 </tr>
12951 <tr class="row-odd"><td>1</td>
12952 <td>DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
12953 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
12954 </tr>
12955 <tr class="row-even"><td>2</td>
12956 <td>DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
12957 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
12958 </tr>
12959 <tr class="row-odd"><td>3</td>
12960 <td>DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
12961 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
12962 </tr>
12963 <tr class="row-even"><td>4</td>
12964 <td>DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
12965 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
12966 </tr>
12967 <tr class="row-odd"><td>5</td>
12968 <td>DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
12969 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
12970 </tr>
12971 <tr class="row-even"><td>6</td>
12972 <td>DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
12973 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
12974 </tr>
12975 <tr class="row-odd"><td>7</td>
12976 <td>DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
12977 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
12978 </tr>
12979 <tr class="row-even"><td>8</td>
12980 <td>DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
12981 <td>Parent input clock option to DEV_RTI16_RTI_CLK</td>
12982 </tr>
12983 <tr class="row-odd"><td>9</td>
12984 <td>DEV_RTI16_VBUSP_CLK</td>
12985 <td>Input clock</td>
12986 </tr>
12987 </tbody>
12988 </table>
12989 </div>
12990 <div class="section" id="clocks-for-rti17-device">
12991 <span id="soc-doc-j784s4-public-clks-rti17"></span><h3>Clocks for RTI17 Device<a class="headerlink" href="#clocks-for-rti17-device" title="Permalink to this headline">¶</a></h3>
12992 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI17</span></a> (ID = 357)</p>
12993 <p>Following is a mapping of Clocks IDs to function:</p>
12994 <table border="1" class="docutils">
12995 <colgroup>
12996 <col width="9%" />
12997 <col width="54%" />
12998 <col width="37%" />
12999 </colgroup>
13000 <thead valign="bottom">
13001 <tr class="row-odd"><th class="head">Clock ID</th>
13002 <th class="head">Name</th>
13003 <th class="head">Function</th>
13004 </tr>
13005 </thead>
13006 <tbody valign="top">
13007 <tr class="row-even"><td>0</td>
13008 <td>DEV_RTI17_RTI_CLK</td>
13009 <td>Input muxed clock</td>
13010 </tr>
13011 <tr class="row-odd"><td>1</td>
13012 <td>DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13013 <td>Parent input clock option to DEV_RTI17_RTI_CLK</td>
13014 </tr>
13015 <tr class="row-even"><td>2</td>
13016 <td>DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13017 <td>Parent input clock option to DEV_RTI17_RTI_CLK</td>
13018 </tr>
13019 <tr class="row-odd"><td>3</td>
13020 <td>DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13021 <td>Parent input clock option to DEV_RTI17_RTI_CLK</td>
13022 </tr>
13023 <tr class="row-even"><td>4</td>
13024 <td>DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13025 <td>Parent input clock option to DEV_RTI17_RTI_CLK</td>
13026 </tr>
13027 <tr class="row-odd"><td>5</td>
13028 <td>DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13029 <td>Parent input clock option to DEV_RTI17_RTI_CLK</td>
13030 </tr>
13031 <tr class="row-even"><td>6</td>
13032 <td>DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13033 <td>Parent input clock option to DEV_RTI17_RTI_CLK</td>
13034 </tr>
13035 <tr class="row-odd"><td>7</td>
13036 <td>DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13037 <td>Parent input clock option to DEV_RTI17_RTI_CLK</td>
13038 </tr>
13039 <tr class="row-even"><td>8</td>
13040 <td>DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13041 <td>Parent input clock option to DEV_RTI17_RTI_CLK</td>
13042 </tr>
13043 <tr class="row-odd"><td>9</td>
13044 <td>DEV_RTI17_VBUSP_CLK</td>
13045 <td>Input clock</td>
13046 </tr>
13047 </tbody>
13048 </table>
13049 </div>
13050 <div class="section" id="clocks-for-rti18-device">
13051 <span id="soc-doc-j784s4-public-clks-rti18"></span><h3>Clocks for RTI18 Device<a class="headerlink" href="#clocks-for-rti18-device" title="Permalink to this headline">¶</a></h3>
13052 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI18</span></a> (ID = 358)</p>
13053 <p>Following is a mapping of Clocks IDs to function:</p>
13054 <table border="1" class="docutils">
13055 <colgroup>
13056 <col width="9%" />
13057 <col width="54%" />
13058 <col width="37%" />
13059 </colgroup>
13060 <thead valign="bottom">
13061 <tr class="row-odd"><th class="head">Clock ID</th>
13062 <th class="head">Name</th>
13063 <th class="head">Function</th>
13064 </tr>
13065 </thead>
13066 <tbody valign="top">
13067 <tr class="row-even"><td>0</td>
13068 <td>DEV_RTI18_RTI_CLK</td>
13069 <td>Input muxed clock</td>
13070 </tr>
13071 <tr class="row-odd"><td>1</td>
13072 <td>DEV_RTI18_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13073 <td>Parent input clock option to DEV_RTI18_RTI_CLK</td>
13074 </tr>
13075 <tr class="row-even"><td>2</td>
13076 <td>DEV_RTI18_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13077 <td>Parent input clock option to DEV_RTI18_RTI_CLK</td>
13078 </tr>
13079 <tr class="row-odd"><td>3</td>
13080 <td>DEV_RTI18_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13081 <td>Parent input clock option to DEV_RTI18_RTI_CLK</td>
13082 </tr>
13083 <tr class="row-even"><td>4</td>
13084 <td>DEV_RTI18_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13085 <td>Parent input clock option to DEV_RTI18_RTI_CLK</td>
13086 </tr>
13087 <tr class="row-odd"><td>5</td>
13088 <td>DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13089 <td>Parent input clock option to DEV_RTI18_RTI_CLK</td>
13090 </tr>
13091 <tr class="row-even"><td>6</td>
13092 <td>DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13093 <td>Parent input clock option to DEV_RTI18_RTI_CLK</td>
13094 </tr>
13095 <tr class="row-odd"><td>7</td>
13096 <td>DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13097 <td>Parent input clock option to DEV_RTI18_RTI_CLK</td>
13098 </tr>
13099 <tr class="row-even"><td>8</td>
13100 <td>DEV_RTI18_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13101 <td>Parent input clock option to DEV_RTI18_RTI_CLK</td>
13102 </tr>
13103 <tr class="row-odd"><td>9</td>
13104 <td>DEV_RTI18_VBUSP_CLK</td>
13105 <td>Input clock</td>
13106 </tr>
13107 </tbody>
13108 </table>
13109 </div>
13110 <div class="section" id="clocks-for-rti19-device">
13111 <span id="soc-doc-j784s4-public-clks-rti19"></span><h3>Clocks for RTI19 Device<a class="headerlink" href="#clocks-for-rti19-device" title="Permalink to this headline">¶</a></h3>
13112 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI19</span></a> (ID = 359)</p>
13113 <p>Following is a mapping of Clocks IDs to function:</p>
13114 <table border="1" class="docutils">
13115 <colgroup>
13116 <col width="9%" />
13117 <col width="54%" />
13118 <col width="37%" />
13119 </colgroup>
13120 <thead valign="bottom">
13121 <tr class="row-odd"><th class="head">Clock ID</th>
13122 <th class="head">Name</th>
13123 <th class="head">Function</th>
13124 </tr>
13125 </thead>
13126 <tbody valign="top">
13127 <tr class="row-even"><td>0</td>
13128 <td>DEV_RTI19_RTI_CLK</td>
13129 <td>Input muxed clock</td>
13130 </tr>
13131 <tr class="row-odd"><td>1</td>
13132 <td>DEV_RTI19_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13133 <td>Parent input clock option to DEV_RTI19_RTI_CLK</td>
13134 </tr>
13135 <tr class="row-even"><td>2</td>
13136 <td>DEV_RTI19_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13137 <td>Parent input clock option to DEV_RTI19_RTI_CLK</td>
13138 </tr>
13139 <tr class="row-odd"><td>3</td>
13140 <td>DEV_RTI19_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13141 <td>Parent input clock option to DEV_RTI19_RTI_CLK</td>
13142 </tr>
13143 <tr class="row-even"><td>4</td>
13144 <td>DEV_RTI19_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13145 <td>Parent input clock option to DEV_RTI19_RTI_CLK</td>
13146 </tr>
13147 <tr class="row-odd"><td>5</td>
13148 <td>DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13149 <td>Parent input clock option to DEV_RTI19_RTI_CLK</td>
13150 </tr>
13151 <tr class="row-even"><td>6</td>
13152 <td>DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13153 <td>Parent input clock option to DEV_RTI19_RTI_CLK</td>
13154 </tr>
13155 <tr class="row-odd"><td>7</td>
13156 <td>DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13157 <td>Parent input clock option to DEV_RTI19_RTI_CLK</td>
13158 </tr>
13159 <tr class="row-even"><td>8</td>
13160 <td>DEV_RTI19_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13161 <td>Parent input clock option to DEV_RTI19_RTI_CLK</td>
13162 </tr>
13163 <tr class="row-odd"><td>9</td>
13164 <td>DEV_RTI19_VBUSP_CLK</td>
13165 <td>Input clock</td>
13166 </tr>
13167 </tbody>
13168 </table>
13169 </div>
13170 <div class="section" id="clocks-for-rti2-device">
13171 <span id="soc-doc-j784s4-public-clks-rti2"></span><h3>Clocks for RTI2 Device<a class="headerlink" href="#clocks-for-rti2-device" title="Permalink to this headline">¶</a></h3>
13172 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI2</span></a> (ID = 350)</p>
13173 <p>Following is a mapping of Clocks IDs to function:</p>
13174 <table border="1" class="docutils">
13175 <colgroup>
13176 <col width="9%" />
13177 <col width="54%" />
13178 <col width="36%" />
13179 </colgroup>
13180 <thead valign="bottom">
13181 <tr class="row-odd"><th class="head">Clock ID</th>
13182 <th class="head">Name</th>
13183 <th class="head">Function</th>
13184 </tr>
13185 </thead>
13186 <tbody valign="top">
13187 <tr class="row-even"><td>0</td>
13188 <td>DEV_RTI2_RTI_CLK</td>
13189 <td>Input muxed clock</td>
13190 </tr>
13191 <tr class="row-odd"><td>1</td>
13192 <td>DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13193 <td>Parent input clock option to DEV_RTI2_RTI_CLK</td>
13194 </tr>
13195 <tr class="row-even"><td>2</td>
13196 <td>DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13197 <td>Parent input clock option to DEV_RTI2_RTI_CLK</td>
13198 </tr>
13199 <tr class="row-odd"><td>3</td>
13200 <td>DEV_RTI2_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13201 <td>Parent input clock option to DEV_RTI2_RTI_CLK</td>
13202 </tr>
13203 <tr class="row-even"><td>4</td>
13204 <td>DEV_RTI2_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13205 <td>Parent input clock option to DEV_RTI2_RTI_CLK</td>
13206 </tr>
13207 <tr class="row-odd"><td>5</td>
13208 <td>DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13209 <td>Parent input clock option to DEV_RTI2_RTI_CLK</td>
13210 </tr>
13211 <tr class="row-even"><td>6</td>
13212 <td>DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13213 <td>Parent input clock option to DEV_RTI2_RTI_CLK</td>
13214 </tr>
13215 <tr class="row-odd"><td>7</td>
13216 <td>DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13217 <td>Parent input clock option to DEV_RTI2_RTI_CLK</td>
13218 </tr>
13219 <tr class="row-even"><td>8</td>
13220 <td>DEV_RTI2_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13221 <td>Parent input clock option to DEV_RTI2_RTI_CLK</td>
13222 </tr>
13223 <tr class="row-odd"><td>9</td>
13224 <td>DEV_RTI2_VBUSP_CLK</td>
13225 <td>Input clock</td>
13226 </tr>
13227 </tbody>
13228 </table>
13229 </div>
13230 <div class="section" id="clocks-for-rti28-device">
13231 <span id="soc-doc-j784s4-public-clks-rti28"></span><h3>Clocks for RTI28 Device<a class="headerlink" href="#clocks-for-rti28-device" title="Permalink to this headline">¶</a></h3>
13232 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI28</span></a> (ID = 361)</p>
13233 <p>Following is a mapping of Clocks IDs to function:</p>
13234 <table border="1" class="docutils">
13235 <colgroup>
13236 <col width="9%" />
13237 <col width="54%" />
13238 <col width="37%" />
13239 </colgroup>
13240 <thead valign="bottom">
13241 <tr class="row-odd"><th class="head">Clock ID</th>
13242 <th class="head">Name</th>
13243 <th class="head">Function</th>
13244 </tr>
13245 </thead>
13246 <tbody valign="top">
13247 <tr class="row-even"><td>0</td>
13248 <td>DEV_RTI28_RTI_CLK</td>
13249 <td>Input muxed clock</td>
13250 </tr>
13251 <tr class="row-odd"><td>1</td>
13252 <td>DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13253 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
13254 </tr>
13255 <tr class="row-even"><td>2</td>
13256 <td>DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13257 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
13258 </tr>
13259 <tr class="row-odd"><td>3</td>
13260 <td>DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13261 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
13262 </tr>
13263 <tr class="row-even"><td>4</td>
13264 <td>DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13265 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
13266 </tr>
13267 <tr class="row-odd"><td>5</td>
13268 <td>DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13269 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
13270 </tr>
13271 <tr class="row-even"><td>6</td>
13272 <td>DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13273 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
13274 </tr>
13275 <tr class="row-odd"><td>7</td>
13276 <td>DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13277 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
13278 </tr>
13279 <tr class="row-even"><td>8</td>
13280 <td>DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13281 <td>Parent input clock option to DEV_RTI28_RTI_CLK</td>
13282 </tr>
13283 <tr class="row-odd"><td>9</td>
13284 <td>DEV_RTI28_VBUSP_CLK</td>
13285 <td>Input clock</td>
13286 </tr>
13287 </tbody>
13288 </table>
13289 </div>
13290 <div class="section" id="clocks-for-rti29-device">
13291 <span id="soc-doc-j784s4-public-clks-rti29"></span><h3>Clocks for RTI29 Device<a class="headerlink" href="#clocks-for-rti29-device" title="Permalink to this headline">¶</a></h3>
13292 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI29</span></a> (ID = 362)</p>
13293 <p>Following is a mapping of Clocks IDs to function:</p>
13294 <table border="1" class="docutils">
13295 <colgroup>
13296 <col width="9%" />
13297 <col width="54%" />
13298 <col width="37%" />
13299 </colgroup>
13300 <thead valign="bottom">
13301 <tr class="row-odd"><th class="head">Clock ID</th>
13302 <th class="head">Name</th>
13303 <th class="head">Function</th>
13304 </tr>
13305 </thead>
13306 <tbody valign="top">
13307 <tr class="row-even"><td>0</td>
13308 <td>DEV_RTI29_RTI_CLK</td>
13309 <td>Input muxed clock</td>
13310 </tr>
13311 <tr class="row-odd"><td>1</td>
13312 <td>DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13313 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
13314 </tr>
13315 <tr class="row-even"><td>2</td>
13316 <td>DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13317 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
13318 </tr>
13319 <tr class="row-odd"><td>3</td>
13320 <td>DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13321 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
13322 </tr>
13323 <tr class="row-even"><td>4</td>
13324 <td>DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13325 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
13326 </tr>
13327 <tr class="row-odd"><td>5</td>
13328 <td>DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13329 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
13330 </tr>
13331 <tr class="row-even"><td>6</td>
13332 <td>DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13333 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
13334 </tr>
13335 <tr class="row-odd"><td>7</td>
13336 <td>DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13337 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
13338 </tr>
13339 <tr class="row-even"><td>8</td>
13340 <td>DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13341 <td>Parent input clock option to DEV_RTI29_RTI_CLK</td>
13342 </tr>
13343 <tr class="row-odd"><td>9</td>
13344 <td>DEV_RTI29_VBUSP_CLK</td>
13345 <td>Input clock</td>
13346 </tr>
13347 </tbody>
13348 </table>
13349 </div>
13350 <div class="section" id="clocks-for-rti3-device">
13351 <span id="soc-doc-j784s4-public-clks-rti3"></span><h3>Clocks for RTI3 Device<a class="headerlink" href="#clocks-for-rti3-device" title="Permalink to this headline">¶</a></h3>
13352 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI3</span></a> (ID = 351)</p>
13353 <p>Following is a mapping of Clocks IDs to function:</p>
13354 <table border="1" class="docutils">
13355 <colgroup>
13356 <col width="9%" />
13357 <col width="54%" />
13358 <col width="36%" />
13359 </colgroup>
13360 <thead valign="bottom">
13361 <tr class="row-odd"><th class="head">Clock ID</th>
13362 <th class="head">Name</th>
13363 <th class="head">Function</th>
13364 </tr>
13365 </thead>
13366 <tbody valign="top">
13367 <tr class="row-even"><td>0</td>
13368 <td>DEV_RTI3_RTI_CLK</td>
13369 <td>Input muxed clock</td>
13370 </tr>
13371 <tr class="row-odd"><td>1</td>
13372 <td>DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13373 <td>Parent input clock option to DEV_RTI3_RTI_CLK</td>
13374 </tr>
13375 <tr class="row-even"><td>2</td>
13376 <td>DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13377 <td>Parent input clock option to DEV_RTI3_RTI_CLK</td>
13378 </tr>
13379 <tr class="row-odd"><td>3</td>
13380 <td>DEV_RTI3_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13381 <td>Parent input clock option to DEV_RTI3_RTI_CLK</td>
13382 </tr>
13383 <tr class="row-even"><td>4</td>
13384 <td>DEV_RTI3_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13385 <td>Parent input clock option to DEV_RTI3_RTI_CLK</td>
13386 </tr>
13387 <tr class="row-odd"><td>5</td>
13388 <td>DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13389 <td>Parent input clock option to DEV_RTI3_RTI_CLK</td>
13390 </tr>
13391 <tr class="row-even"><td>6</td>
13392 <td>DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13393 <td>Parent input clock option to DEV_RTI3_RTI_CLK</td>
13394 </tr>
13395 <tr class="row-odd"><td>7</td>
13396 <td>DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13397 <td>Parent input clock option to DEV_RTI3_RTI_CLK</td>
13398 </tr>
13399 <tr class="row-even"><td>8</td>
13400 <td>DEV_RTI3_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13401 <td>Parent input clock option to DEV_RTI3_RTI_CLK</td>
13402 </tr>
13403 <tr class="row-odd"><td>9</td>
13404 <td>DEV_RTI3_VBUSP_CLK</td>
13405 <td>Input clock</td>
13406 </tr>
13407 </tbody>
13408 </table>
13409 </div>
13410 <div class="section" id="clocks-for-rti30-device">
13411 <span id="soc-doc-j784s4-public-clks-rti30"></span><h3>Clocks for RTI30 Device<a class="headerlink" href="#clocks-for-rti30-device" title="Permalink to this headline">¶</a></h3>
13412 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI30</span></a> (ID = 363)</p>
13413 <p>Following is a mapping of Clocks IDs to function:</p>
13414 <table border="1" class="docutils">
13415 <colgroup>
13416 <col width="9%" />
13417 <col width="54%" />
13418 <col width="37%" />
13419 </colgroup>
13420 <thead valign="bottom">
13421 <tr class="row-odd"><th class="head">Clock ID</th>
13422 <th class="head">Name</th>
13423 <th class="head">Function</th>
13424 </tr>
13425 </thead>
13426 <tbody valign="top">
13427 <tr class="row-even"><td>0</td>
13428 <td>DEV_RTI30_RTI_CLK</td>
13429 <td>Input muxed clock</td>
13430 </tr>
13431 <tr class="row-odd"><td>1</td>
13432 <td>DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13433 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
13434 </tr>
13435 <tr class="row-even"><td>2</td>
13436 <td>DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13437 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
13438 </tr>
13439 <tr class="row-odd"><td>3</td>
13440 <td>DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13441 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
13442 </tr>
13443 <tr class="row-even"><td>4</td>
13444 <td>DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13445 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
13446 </tr>
13447 <tr class="row-odd"><td>5</td>
13448 <td>DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13449 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
13450 </tr>
13451 <tr class="row-even"><td>6</td>
13452 <td>DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13453 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
13454 </tr>
13455 <tr class="row-odd"><td>7</td>
13456 <td>DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13457 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
13458 </tr>
13459 <tr class="row-even"><td>8</td>
13460 <td>DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13461 <td>Parent input clock option to DEV_RTI30_RTI_CLK</td>
13462 </tr>
13463 <tr class="row-odd"><td>9</td>
13464 <td>DEV_RTI30_VBUSP_CLK</td>
13465 <td>Input clock</td>
13466 </tr>
13467 </tbody>
13468 </table>
13469 </div>
13470 <div class="section" id="clocks-for-rti31-device">
13471 <span id="soc-doc-j784s4-public-clks-rti31"></span><h3>Clocks for RTI31 Device<a class="headerlink" href="#clocks-for-rti31-device" title="Permalink to this headline">¶</a></h3>
13472 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI31</span></a> (ID = 364)</p>
13473 <p>Following is a mapping of Clocks IDs to function:</p>
13474 <table border="1" class="docutils">
13475 <colgroup>
13476 <col width="9%" />
13477 <col width="54%" />
13478 <col width="37%" />
13479 </colgroup>
13480 <thead valign="bottom">
13481 <tr class="row-odd"><th class="head">Clock ID</th>
13482 <th class="head">Name</th>
13483 <th class="head">Function</th>
13484 </tr>
13485 </thead>
13486 <tbody valign="top">
13487 <tr class="row-even"><td>0</td>
13488 <td>DEV_RTI31_RTI_CLK</td>
13489 <td>Input muxed clock</td>
13490 </tr>
13491 <tr class="row-odd"><td>1</td>
13492 <td>DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13493 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
13494 </tr>
13495 <tr class="row-even"><td>2</td>
13496 <td>DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13497 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
13498 </tr>
13499 <tr class="row-odd"><td>3</td>
13500 <td>DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13501 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
13502 </tr>
13503 <tr class="row-even"><td>4</td>
13504 <td>DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13505 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
13506 </tr>
13507 <tr class="row-odd"><td>5</td>
13508 <td>DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13509 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
13510 </tr>
13511 <tr class="row-even"><td>6</td>
13512 <td>DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13513 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
13514 </tr>
13515 <tr class="row-odd"><td>7</td>
13516 <td>DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13517 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
13518 </tr>
13519 <tr class="row-even"><td>8</td>
13520 <td>DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13521 <td>Parent input clock option to DEV_RTI31_RTI_CLK</td>
13522 </tr>
13523 <tr class="row-odd"><td>9</td>
13524 <td>DEV_RTI31_VBUSP_CLK</td>
13525 <td>Input clock</td>
13526 </tr>
13527 </tbody>
13528 </table>
13529 </div>
13530 <div class="section" id="clocks-for-rti32-device">
13531 <span id="soc-doc-j784s4-public-clks-rti32"></span><h3>Clocks for RTI32 Device<a class="headerlink" href="#clocks-for-rti32-device" title="Permalink to this headline">¶</a></h3>
13532 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI32</span></a> (ID = 365)</p>
13533 <p>Following is a mapping of Clocks IDs to function:</p>
13534 <table border="1" class="docutils">
13535 <colgroup>
13536 <col width="9%" />
13537 <col width="54%" />
13538 <col width="37%" />
13539 </colgroup>
13540 <thead valign="bottom">
13541 <tr class="row-odd"><th class="head">Clock ID</th>
13542 <th class="head">Name</th>
13543 <th class="head">Function</th>
13544 </tr>
13545 </thead>
13546 <tbody valign="top">
13547 <tr class="row-even"><td>0</td>
13548 <td>DEV_RTI32_RTI_CLK</td>
13549 <td>Input muxed clock</td>
13550 </tr>
13551 <tr class="row-odd"><td>1</td>
13552 <td>DEV_RTI32_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13553 <td>Parent input clock option to DEV_RTI32_RTI_CLK</td>
13554 </tr>
13555 <tr class="row-even"><td>2</td>
13556 <td>DEV_RTI32_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13557 <td>Parent input clock option to DEV_RTI32_RTI_CLK</td>
13558 </tr>
13559 <tr class="row-odd"><td>3</td>
13560 <td>DEV_RTI32_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13561 <td>Parent input clock option to DEV_RTI32_RTI_CLK</td>
13562 </tr>
13563 <tr class="row-even"><td>4</td>
13564 <td>DEV_RTI32_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13565 <td>Parent input clock option to DEV_RTI32_RTI_CLK</td>
13566 </tr>
13567 <tr class="row-odd"><td>5</td>
13568 <td>DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13569 <td>Parent input clock option to DEV_RTI32_RTI_CLK</td>
13570 </tr>
13571 <tr class="row-even"><td>6</td>
13572 <td>DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13573 <td>Parent input clock option to DEV_RTI32_RTI_CLK</td>
13574 </tr>
13575 <tr class="row-odd"><td>7</td>
13576 <td>DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13577 <td>Parent input clock option to DEV_RTI32_RTI_CLK</td>
13578 </tr>
13579 <tr class="row-even"><td>8</td>
13580 <td>DEV_RTI32_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13581 <td>Parent input clock option to DEV_RTI32_RTI_CLK</td>
13582 </tr>
13583 <tr class="row-odd"><td>9</td>
13584 <td>DEV_RTI32_VBUSP_CLK</td>
13585 <td>Input clock</td>
13586 </tr>
13587 </tbody>
13588 </table>
13589 </div>
13590 <div class="section" id="clocks-for-rti33-device">
13591 <span id="soc-doc-j784s4-public-clks-rti33"></span><h3>Clocks for RTI33 Device<a class="headerlink" href="#clocks-for-rti33-device" title="Permalink to this headline">¶</a></h3>
13592 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI33</span></a> (ID = 366)</p>
13593 <p>Following is a mapping of Clocks IDs to function:</p>
13594 <table border="1" class="docutils">
13595 <colgroup>
13596 <col width="9%" />
13597 <col width="54%" />
13598 <col width="37%" />
13599 </colgroup>
13600 <thead valign="bottom">
13601 <tr class="row-odd"><th class="head">Clock ID</th>
13602 <th class="head">Name</th>
13603 <th class="head">Function</th>
13604 </tr>
13605 </thead>
13606 <tbody valign="top">
13607 <tr class="row-even"><td>0</td>
13608 <td>DEV_RTI33_RTI_CLK</td>
13609 <td>Input muxed clock</td>
13610 </tr>
13611 <tr class="row-odd"><td>1</td>
13612 <td>DEV_RTI33_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13613 <td>Parent input clock option to DEV_RTI33_RTI_CLK</td>
13614 </tr>
13615 <tr class="row-even"><td>2</td>
13616 <td>DEV_RTI33_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13617 <td>Parent input clock option to DEV_RTI33_RTI_CLK</td>
13618 </tr>
13619 <tr class="row-odd"><td>3</td>
13620 <td>DEV_RTI33_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13621 <td>Parent input clock option to DEV_RTI33_RTI_CLK</td>
13622 </tr>
13623 <tr class="row-even"><td>4</td>
13624 <td>DEV_RTI33_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13625 <td>Parent input clock option to DEV_RTI33_RTI_CLK</td>
13626 </tr>
13627 <tr class="row-odd"><td>5</td>
13628 <td>DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13629 <td>Parent input clock option to DEV_RTI33_RTI_CLK</td>
13630 </tr>
13631 <tr class="row-even"><td>6</td>
13632 <td>DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13633 <td>Parent input clock option to DEV_RTI33_RTI_CLK</td>
13634 </tr>
13635 <tr class="row-odd"><td>7</td>
13636 <td>DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13637 <td>Parent input clock option to DEV_RTI33_RTI_CLK</td>
13638 </tr>
13639 <tr class="row-even"><td>8</td>
13640 <td>DEV_RTI33_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13641 <td>Parent input clock option to DEV_RTI33_RTI_CLK</td>
13642 </tr>
13643 <tr class="row-odd"><td>9</td>
13644 <td>DEV_RTI33_VBUSP_CLK</td>
13645 <td>Input clock</td>
13646 </tr>
13647 </tbody>
13648 </table>
13649 </div>
13650 <div class="section" id="clocks-for-rti4-device">
13651 <span id="soc-doc-j784s4-public-clks-rti4"></span><h3>Clocks for RTI4 Device<a class="headerlink" href="#clocks-for-rti4-device" title="Permalink to this headline">¶</a></h3>
13652 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI4</span></a> (ID = 352)</p>
13653 <p>Following is a mapping of Clocks IDs to function:</p>
13654 <table border="1" class="docutils">
13655 <colgroup>
13656 <col width="9%" />
13657 <col width="54%" />
13658 <col width="36%" />
13659 </colgroup>
13660 <thead valign="bottom">
13661 <tr class="row-odd"><th class="head">Clock ID</th>
13662 <th class="head">Name</th>
13663 <th class="head">Function</th>
13664 </tr>
13665 </thead>
13666 <tbody valign="top">
13667 <tr class="row-even"><td>0</td>
13668 <td>DEV_RTI4_RTI_CLK</td>
13669 <td>Input muxed clock</td>
13670 </tr>
13671 <tr class="row-odd"><td>1</td>
13672 <td>DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13673 <td>Parent input clock option to DEV_RTI4_RTI_CLK</td>
13674 </tr>
13675 <tr class="row-even"><td>2</td>
13676 <td>DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13677 <td>Parent input clock option to DEV_RTI4_RTI_CLK</td>
13678 </tr>
13679 <tr class="row-odd"><td>3</td>
13680 <td>DEV_RTI4_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13681 <td>Parent input clock option to DEV_RTI4_RTI_CLK</td>
13682 </tr>
13683 <tr class="row-even"><td>4</td>
13684 <td>DEV_RTI4_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13685 <td>Parent input clock option to DEV_RTI4_RTI_CLK</td>
13686 </tr>
13687 <tr class="row-odd"><td>5</td>
13688 <td>DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13689 <td>Parent input clock option to DEV_RTI4_RTI_CLK</td>
13690 </tr>
13691 <tr class="row-even"><td>6</td>
13692 <td>DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13693 <td>Parent input clock option to DEV_RTI4_RTI_CLK</td>
13694 </tr>
13695 <tr class="row-odd"><td>7</td>
13696 <td>DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13697 <td>Parent input clock option to DEV_RTI4_RTI_CLK</td>
13698 </tr>
13699 <tr class="row-even"><td>8</td>
13700 <td>DEV_RTI4_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13701 <td>Parent input clock option to DEV_RTI4_RTI_CLK</td>
13702 </tr>
13703 <tr class="row-odd"><td>9</td>
13704 <td>DEV_RTI4_VBUSP_CLK</td>
13705 <td>Input clock</td>
13706 </tr>
13707 </tbody>
13708 </table>
13709 </div>
13710 <div class="section" id="clocks-for-rti5-device">
13711 <span id="soc-doc-j784s4-public-clks-rti5"></span><h3>Clocks for RTI5 Device<a class="headerlink" href="#clocks-for-rti5-device" title="Permalink to this headline">¶</a></h3>
13712 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI5</span></a> (ID = 353)</p>
13713 <p>Following is a mapping of Clocks IDs to function:</p>
13714 <table border="1" class="docutils">
13715 <colgroup>
13716 <col width="9%" />
13717 <col width="54%" />
13718 <col width="36%" />
13719 </colgroup>
13720 <thead valign="bottom">
13721 <tr class="row-odd"><th class="head">Clock ID</th>
13722 <th class="head">Name</th>
13723 <th class="head">Function</th>
13724 </tr>
13725 </thead>
13726 <tbody valign="top">
13727 <tr class="row-even"><td>0</td>
13728 <td>DEV_RTI5_RTI_CLK</td>
13729 <td>Input muxed clock</td>
13730 </tr>
13731 <tr class="row-odd"><td>1</td>
13732 <td>DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13733 <td>Parent input clock option to DEV_RTI5_RTI_CLK</td>
13734 </tr>
13735 <tr class="row-even"><td>2</td>
13736 <td>DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13737 <td>Parent input clock option to DEV_RTI5_RTI_CLK</td>
13738 </tr>
13739 <tr class="row-odd"><td>3</td>
13740 <td>DEV_RTI5_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13741 <td>Parent input clock option to DEV_RTI5_RTI_CLK</td>
13742 </tr>
13743 <tr class="row-even"><td>4</td>
13744 <td>DEV_RTI5_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13745 <td>Parent input clock option to DEV_RTI5_RTI_CLK</td>
13746 </tr>
13747 <tr class="row-odd"><td>5</td>
13748 <td>DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13749 <td>Parent input clock option to DEV_RTI5_RTI_CLK</td>
13750 </tr>
13751 <tr class="row-even"><td>6</td>
13752 <td>DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13753 <td>Parent input clock option to DEV_RTI5_RTI_CLK</td>
13754 </tr>
13755 <tr class="row-odd"><td>7</td>
13756 <td>DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13757 <td>Parent input clock option to DEV_RTI5_RTI_CLK</td>
13758 </tr>
13759 <tr class="row-even"><td>8</td>
13760 <td>DEV_RTI5_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13761 <td>Parent input clock option to DEV_RTI5_RTI_CLK</td>
13762 </tr>
13763 <tr class="row-odd"><td>9</td>
13764 <td>DEV_RTI5_VBUSP_CLK</td>
13765 <td>Input clock</td>
13766 </tr>
13767 </tbody>
13768 </table>
13769 </div>
13770 <div class="section" id="clocks-for-rti6-device">
13771 <span id="soc-doc-j784s4-public-clks-rti6"></span><h3>Clocks for RTI6 Device<a class="headerlink" href="#clocks-for-rti6-device" title="Permalink to this headline">¶</a></h3>
13772 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI6</span></a> (ID = 354)</p>
13773 <p>Following is a mapping of Clocks IDs to function:</p>
13774 <table border="1" class="docutils">
13775 <colgroup>
13776 <col width="9%" />
13777 <col width="54%" />
13778 <col width="36%" />
13779 </colgroup>
13780 <thead valign="bottom">
13781 <tr class="row-odd"><th class="head">Clock ID</th>
13782 <th class="head">Name</th>
13783 <th class="head">Function</th>
13784 </tr>
13785 </thead>
13786 <tbody valign="top">
13787 <tr class="row-even"><td>0</td>
13788 <td>DEV_RTI6_RTI_CLK</td>
13789 <td>Input muxed clock</td>
13790 </tr>
13791 <tr class="row-odd"><td>1</td>
13792 <td>DEV_RTI6_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13793 <td>Parent input clock option to DEV_RTI6_RTI_CLK</td>
13794 </tr>
13795 <tr class="row-even"><td>2</td>
13796 <td>DEV_RTI6_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13797 <td>Parent input clock option to DEV_RTI6_RTI_CLK</td>
13798 </tr>
13799 <tr class="row-odd"><td>3</td>
13800 <td>DEV_RTI6_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13801 <td>Parent input clock option to DEV_RTI6_RTI_CLK</td>
13802 </tr>
13803 <tr class="row-even"><td>4</td>
13804 <td>DEV_RTI6_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13805 <td>Parent input clock option to DEV_RTI6_RTI_CLK</td>
13806 </tr>
13807 <tr class="row-odd"><td>5</td>
13808 <td>DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13809 <td>Parent input clock option to DEV_RTI6_RTI_CLK</td>
13810 </tr>
13811 <tr class="row-even"><td>6</td>
13812 <td>DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13813 <td>Parent input clock option to DEV_RTI6_RTI_CLK</td>
13814 </tr>
13815 <tr class="row-odd"><td>7</td>
13816 <td>DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13817 <td>Parent input clock option to DEV_RTI6_RTI_CLK</td>
13818 </tr>
13819 <tr class="row-even"><td>8</td>
13820 <td>DEV_RTI6_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13821 <td>Parent input clock option to DEV_RTI6_RTI_CLK</td>
13822 </tr>
13823 <tr class="row-odd"><td>9</td>
13824 <td>DEV_RTI6_VBUSP_CLK</td>
13825 <td>Input clock</td>
13826 </tr>
13827 </tbody>
13828 </table>
13829 </div>
13830 <div class="section" id="clocks-for-rti7-device">
13831 <span id="soc-doc-j784s4-public-clks-rti7"></span><h3>Clocks for RTI7 Device<a class="headerlink" href="#clocks-for-rti7-device" title="Permalink to this headline">¶</a></h3>
13832 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_RTI7</span></a> (ID = 355)</p>
13833 <p>Following is a mapping of Clocks IDs to function:</p>
13834 <table border="1" class="docutils">
13835 <colgroup>
13836 <col width="9%" />
13837 <col width="54%" />
13838 <col width="36%" />
13839 </colgroup>
13840 <thead valign="bottom">
13841 <tr class="row-odd"><th class="head">Clock ID</th>
13842 <th class="head">Name</th>
13843 <th class="head">Function</th>
13844 </tr>
13845 </thead>
13846 <tbody valign="top">
13847 <tr class="row-even"><td>0</td>
13848 <td>DEV_RTI7_RTI_CLK</td>
13849 <td>Input muxed clock</td>
13850 </tr>
13851 <tr class="row-odd"><td>1</td>
13852 <td>DEV_RTI7_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13853 <td>Parent input clock option to DEV_RTI7_RTI_CLK</td>
13854 </tr>
13855 <tr class="row-even"><td>2</td>
13856 <td>DEV_RTI7_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
13857 <td>Parent input clock option to DEV_RTI7_RTI_CLK</td>
13858 </tr>
13859 <tr class="row-odd"><td>3</td>
13860 <td>DEV_RTI7_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
13861 <td>Parent input clock option to DEV_RTI7_RTI_CLK</td>
13862 </tr>
13863 <tr class="row-even"><td>4</td>
13864 <td>DEV_RTI7_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK</td>
13865 <td>Parent input clock option to DEV_RTI7_RTI_CLK</td>
13866 </tr>
13867 <tr class="row-odd"><td>5</td>
13868 <td>DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
13869 <td>Parent input clock option to DEV_RTI7_RTI_CLK</td>
13870 </tr>
13871 <tr class="row-even"><td>6</td>
13872 <td>DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0</td>
13873 <td>Parent input clock option to DEV_RTI7_RTI_CLK</td>
13874 </tr>
13875 <tr class="row-odd"><td>7</td>
13876 <td>DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1</td>
13877 <td>Parent input clock option to DEV_RTI7_RTI_CLK</td>
13878 </tr>
13879 <tr class="row-even"><td>8</td>
13880 <td>DEV_RTI7_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2</td>
13881 <td>Parent input clock option to DEV_RTI7_RTI_CLK</td>
13882 </tr>
13883 <tr class="row-odd"><td>9</td>
13884 <td>DEV_RTI7_VBUSP_CLK</td>
13885 <td>Input clock</td>
13886 </tr>
13887 </tbody>
13888 </table>
13889 </div>
13890 <div class="section" id="clocks-for-sa2-cpsw-psilss0-device">
13891 <span id="soc-doc-j784s4-public-clks-sa2-cpsw-psilss0"></span><h3>Clocks for SA2_CPSW_PSILSS0 Device<a class="headerlink" href="#clocks-for-sa2-cpsw-psilss0-device" title="Permalink to this headline">¶</a></h3>
13892 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_SA2_CPSW_PSILSS0</span></a> (ID = 207)</p>
13893 <p>Following is a mapping of Clocks IDs to function:</p>
13894 <table border="1" class="docutils">
13895 <colgroup>
13896 <col width="21%" />
13897 <col width="57%" />
13898 <col width="22%" />
13899 </colgroup>
13900 <thead valign="bottom">
13901 <tr class="row-odd"><th class="head">Clock ID</th>
13902 <th class="head">Name</th>
13903 <th class="head">Function</th>
13904 </tr>
13905 </thead>
13906 <tbody valign="top">
13907 <tr class="row-even"><td>0</td>
13908 <td>DEV_SA2_CPSW_PSILSS0_MAIN_2_CLK</td>
13909 <td>Input clock</td>
13910 </tr>
13911 <tr class="row-odd"><td>1</td>
13912 <td>DEV_SA2_CPSW_PSILSS0_MAIN_CLK</td>
13913 <td>Input clock</td>
13914 </tr>
13915 </tbody>
13916 </table>
13917 </div>
13918 <div class="section" id="clocks-for-sa2-ul0-device">
13919 <span id="soc-doc-j784s4-public-clks-sa2-ul0"></span><h3>Clocks for SA2_UL0 Device<a class="headerlink" href="#clocks-for-sa2-ul0-device" title="Permalink to this headline">¶</a></h3>
13920 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_SA2_UL0</span></a> (ID = 369)</p>
13921 <p>Following is a mapping of Clocks IDs to function:</p>
13922 <table border="1" class="docutils">
13923 <colgroup>
13924 <col width="24%" />
13925 <col width="49%" />
13926 <col width="27%" />
13927 </colgroup>
13928 <thead valign="bottom">
13929 <tr class="row-odd"><th class="head">Clock ID</th>
13930 <th class="head">Name</th>
13931 <th class="head">Function</th>
13932 </tr>
13933 </thead>
13934 <tbody valign="top">
13935 <tr class="row-even"><td>0</td>
13936 <td>DEV_SA2_UL0_PKA_IN_CLK</td>
13937 <td>Input clock</td>
13938 </tr>
13939 <tr class="row-odd"><td>1</td>
13940 <td>DEV_SA2_UL0_X1_CLK</td>
13941 <td>Input clock</td>
13942 </tr>
13943 <tr class="row-even"><td>2</td>
13944 <td>DEV_SA2_UL0_X2_CLK</td>
13945 <td>Input clock</td>
13946 </tr>
13947 </tbody>
13948 </table>
13949 </div>
13950 <div class="section" id="clocks-for-serdes-10g0-device">
13951 <span id="soc-doc-j784s4-public-clks-serdes-10g0"></span><h3>Clocks for SERDES_10G0 Device<a class="headerlink" href="#clocks-for-serdes-10g0-device" title="Permalink to this headline">¶</a></h3>
13952 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_SERDES_10G0</span></a> (ID = 404)</p>
13953 <p>Following is a mapping of Clocks IDs to function:</p>
13954 <table border="1" class="docutils">
13955 <colgroup>
13956 <col width="8%" />
13957 <col width="50%" />
13958 <col width="42%" />
13959 </colgroup>
13960 <thead valign="bottom">
13961 <tr class="row-odd"><th class="head">Clock ID</th>
13962 <th class="head">Name</th>
13963 <th class="head">Function</th>
13964 </tr>
13965 </thead>
13966 <tbody valign="top">
13967 <tr class="row-even"><td>2</td>
13968 <td>DEV_SERDES_10G0_CLK</td>
13969 <td>Input clock</td>
13970 </tr>
13971 <tr class="row-odd"><td>3</td>
13972 <td>DEV_SERDES_10G0_CMN_REFCLK_M</td>
13973 <td>Input clock</td>
13974 </tr>
13975 <tr class="row-even"><td>3</td>
13976 <td>DEV_SERDES_10G0_CMN_REFCLK_M</td>
13977 <td>Output clock</td>
13978 </tr>
13979 <tr class="row-odd"><td>4</td>
13980 <td>DEV_SERDES_10G0_CMN_REFCLK_P</td>
13981 <td>Input clock</td>
13982 </tr>
13983 <tr class="row-even"><td>4</td>
13984 <td>DEV_SERDES_10G0_CMN_REFCLK_P</td>
13985 <td>Output clock</td>
13986 </tr>
13987 <tr class="row-odd"><td>5</td>
13988 <td>DEV_SERDES_10G0_CORE_REF1_CLK</td>
13989 <td>Input clock</td>
13990 </tr>
13991 <tr class="row-even"><td>6</td>
13992 <td>DEV_SERDES_10G0_CORE_REF_CLK</td>
13993 <td>Input muxed clock</td>
13994 </tr>
13995 <tr class="row-odd"><td>7</td>
13996 <td>DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
13997 <td>Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK</td>
13998 </tr>
13999 <tr class="row-even"><td>8</td>
14000 <td>DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14001 <td>Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK</td>
14002 </tr>
14003 <tr class="row-odd"><td>9</td>
14004 <td>DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
14005 <td>Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK</td>
14006 </tr>
14007 <tr class="row-even"><td>10</td>
14008 <td>DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
14009 <td>Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK</td>
14010 </tr>
14011 <tr class="row-odd"><td>15</td>
14012 <td>DEV_SERDES_10G0_IP1_LN0_TXCLK</td>
14013 <td>Input clock</td>
14014 </tr>
14015 <tr class="row-even"><td>21</td>
14016 <td>DEV_SERDES_10G0_IP1_LN1_TXCLK</td>
14017 <td>Input clock</td>
14018 </tr>
14019 <tr class="row-odd"><td>24</td>
14020 <td>DEV_SERDES_10G0_IP1_LN2_REFCLK</td>
14021 <td>Output clock</td>
14022 </tr>
14023 <tr class="row-even"><td>25</td>
14024 <td>DEV_SERDES_10G0_IP1_LN2_RXCLK</td>
14025 <td>Output clock</td>
14026 </tr>
14027 <tr class="row-odd"><td>26</td>
14028 <td>DEV_SERDES_10G0_IP1_LN2_RXFCLK</td>
14029 <td>Output clock</td>
14030 </tr>
14031 <tr class="row-even"><td>27</td>
14032 <td>DEV_SERDES_10G0_IP1_LN2_TXCLK</td>
14033 <td>Input clock</td>
14034 </tr>
14035 <tr class="row-odd"><td>28</td>
14036 <td>DEV_SERDES_10G0_IP1_LN2_TXFCLK</td>
14037 <td>Output clock</td>
14038 </tr>
14039 <tr class="row-even"><td>29</td>
14040 <td>DEV_SERDES_10G0_IP1_LN2_TXMCLK</td>
14041 <td>Output clock</td>
14042 </tr>
14043 <tr class="row-odd"><td>30</td>
14044 <td>DEV_SERDES_10G0_IP1_LN3_REFCLK</td>
14045 <td>Output clock</td>
14046 </tr>
14047 <tr class="row-even"><td>31</td>
14048 <td>DEV_SERDES_10G0_IP1_LN3_RXCLK</td>
14049 <td>Output clock</td>
14050 </tr>
14051 <tr class="row-odd"><td>32</td>
14052 <td>DEV_SERDES_10G0_IP1_LN3_RXFCLK</td>
14053 <td>Output clock</td>
14054 </tr>
14055 <tr class="row-even"><td>33</td>
14056 <td>DEV_SERDES_10G0_IP1_LN3_TXCLK</td>
14057 <td>Input clock</td>
14058 </tr>
14059 <tr class="row-odd"><td>34</td>
14060 <td>DEV_SERDES_10G0_IP1_LN3_TXFCLK</td>
14061 <td>Output clock</td>
14062 </tr>
14063 <tr class="row-even"><td>35</td>
14064 <td>DEV_SERDES_10G0_IP1_LN3_TXMCLK</td>
14065 <td>Output clock</td>
14066 </tr>
14067 <tr class="row-odd"><td>36</td>
14068 <td>DEV_SERDES_10G0_IP2_LN0_REFCLK</td>
14069 <td>Output clock</td>
14070 </tr>
14071 <tr class="row-even"><td>37</td>
14072 <td>DEV_SERDES_10G0_IP2_LN0_RXCLK</td>
14073 <td>Output clock</td>
14074 </tr>
14075 <tr class="row-odd"><td>38</td>
14076 <td>DEV_SERDES_10G0_IP2_LN0_RXFCLK</td>
14077 <td>Output clock</td>
14078 </tr>
14079 <tr class="row-even"><td>39</td>
14080 <td>DEV_SERDES_10G0_IP2_LN0_TXCLK</td>
14081 <td>Input clock</td>
14082 </tr>
14083 <tr class="row-odd"><td>40</td>
14084 <td>DEV_SERDES_10G0_IP2_LN0_TXFCLK</td>
14085 <td>Output clock</td>
14086 </tr>
14087 <tr class="row-even"><td>41</td>
14088 <td>DEV_SERDES_10G0_IP2_LN0_TXMCLK</td>
14089 <td>Output clock</td>
14090 </tr>
14091 <tr class="row-odd"><td>42</td>
14092 <td>DEV_SERDES_10G0_IP2_LN1_REFCLK</td>
14093 <td>Output clock</td>
14094 </tr>
14095 <tr class="row-even"><td>43</td>
14096 <td>DEV_SERDES_10G0_IP2_LN1_RXCLK</td>
14097 <td>Output clock</td>
14098 </tr>
14099 <tr class="row-odd"><td>44</td>
14100 <td>DEV_SERDES_10G0_IP2_LN1_RXFCLK</td>
14101 <td>Output clock</td>
14102 </tr>
14103 <tr class="row-even"><td>45</td>
14104 <td>DEV_SERDES_10G0_IP2_LN1_TXCLK</td>
14105 <td>Input clock</td>
14106 </tr>
14107 <tr class="row-odd"><td>46</td>
14108 <td>DEV_SERDES_10G0_IP2_LN1_TXFCLK</td>
14109 <td>Output clock</td>
14110 </tr>
14111 <tr class="row-even"><td>47</td>
14112 <td>DEV_SERDES_10G0_IP2_LN1_TXMCLK</td>
14113 <td>Output clock</td>
14114 </tr>
14115 <tr class="row-odd"><td>48</td>
14116 <td>DEV_SERDES_10G0_IP2_LN2_REFCLK</td>
14117 <td>Output clock</td>
14118 </tr>
14119 <tr class="row-even"><td>49</td>
14120 <td>DEV_SERDES_10G0_IP2_LN2_RXCLK</td>
14121 <td>Output clock</td>
14122 </tr>
14123 <tr class="row-odd"><td>50</td>
14124 <td>DEV_SERDES_10G0_IP2_LN2_RXFCLK</td>
14125 <td>Output clock</td>
14126 </tr>
14127 <tr class="row-even"><td>51</td>
14128 <td>DEV_SERDES_10G0_IP2_LN2_TXCLK</td>
14129 <td>Input clock</td>
14130 </tr>
14131 <tr class="row-odd"><td>52</td>
14132 <td>DEV_SERDES_10G0_IP2_LN2_TXFCLK</td>
14133 <td>Output clock</td>
14134 </tr>
14135 <tr class="row-even"><td>53</td>
14136 <td>DEV_SERDES_10G0_IP2_LN2_TXMCLK</td>
14137 <td>Output clock</td>
14138 </tr>
14139 <tr class="row-odd"><td>54</td>
14140 <td>DEV_SERDES_10G0_IP2_LN3_REFCLK</td>
14141 <td>Output clock</td>
14142 </tr>
14143 <tr class="row-even"><td>55</td>
14144 <td>DEV_SERDES_10G0_IP2_LN3_RXCLK</td>
14145 <td>Output clock</td>
14146 </tr>
14147 <tr class="row-odd"><td>56</td>
14148 <td>DEV_SERDES_10G0_IP2_LN3_RXFCLK</td>
14149 <td>Output clock</td>
14150 </tr>
14151 <tr class="row-even"><td>57</td>
14152 <td>DEV_SERDES_10G0_IP2_LN3_TXCLK</td>
14153 <td>Input clock</td>
14154 </tr>
14155 <tr class="row-odd"><td>58</td>
14156 <td>DEV_SERDES_10G0_IP2_LN3_TXFCLK</td>
14157 <td>Output clock</td>
14158 </tr>
14159 <tr class="row-even"><td>59</td>
14160 <td>DEV_SERDES_10G0_IP2_LN3_TXMCLK</td>
14161 <td>Output clock</td>
14162 </tr>
14163 <tr class="row-odd"><td>78</td>
14164 <td>DEV_SERDES_10G0_IP3_LN3_REFCLK</td>
14165 <td>Output clock</td>
14166 </tr>
14167 <tr class="row-even"><td>79</td>
14168 <td>DEV_SERDES_10G0_IP3_LN3_RXCLK</td>
14169 <td>Output clock</td>
14170 </tr>
14171 <tr class="row-odd"><td>80</td>
14172 <td>DEV_SERDES_10G0_IP3_LN3_RXFCLK</td>
14173 <td>Output clock</td>
14174 </tr>
14175 <tr class="row-even"><td>81</td>
14176 <td>DEV_SERDES_10G0_IP3_LN3_TXCLK</td>
14177 <td>Input clock</td>
14178 </tr>
14179 <tr class="row-odd"><td>82</td>
14180 <td>DEV_SERDES_10G0_IP3_LN3_TXFCLK</td>
14181 <td>Output clock</td>
14182 </tr>
14183 <tr class="row-even"><td>83</td>
14184 <td>DEV_SERDES_10G0_IP3_LN3_TXMCLK</td>
14185 <td>Output clock</td>
14186 </tr>
14187 <tr class="row-odd"><td>84</td>
14188 <td>DEV_SERDES_10G0_IP4_LN0_REFCLK</td>
14189 <td>Output clock</td>
14190 </tr>
14191 <tr class="row-even"><td>85</td>
14192 <td>DEV_SERDES_10G0_IP4_LN0_RXCLK</td>
14193 <td>Output clock</td>
14194 </tr>
14195 <tr class="row-odd"><td>86</td>
14196 <td>DEV_SERDES_10G0_IP4_LN0_RXFCLK</td>
14197 <td>Output clock</td>
14198 </tr>
14199 <tr class="row-even"><td>87</td>
14200 <td>DEV_SERDES_10G0_IP4_LN0_TXCLK</td>
14201 <td>Input clock</td>
14202 </tr>
14203 <tr class="row-odd"><td>88</td>
14204 <td>DEV_SERDES_10G0_IP4_LN0_TXFCLK</td>
14205 <td>Output clock</td>
14206 </tr>
14207 <tr class="row-even"><td>89</td>
14208 <td>DEV_SERDES_10G0_IP4_LN0_TXMCLK</td>
14209 <td>Output clock</td>
14210 </tr>
14211 <tr class="row-odd"><td>90</td>
14212 <td>DEV_SERDES_10G0_IP4_LN1_REFCLK</td>
14213 <td>Output clock</td>
14214 </tr>
14215 <tr class="row-even"><td>91</td>
14216 <td>DEV_SERDES_10G0_IP4_LN1_RXCLK</td>
14217 <td>Output clock</td>
14218 </tr>
14219 <tr class="row-odd"><td>92</td>
14220 <td>DEV_SERDES_10G0_IP4_LN1_RXFCLK</td>
14221 <td>Output clock</td>
14222 </tr>
14223 <tr class="row-even"><td>93</td>
14224 <td>DEV_SERDES_10G0_IP4_LN1_TXCLK</td>
14225 <td>Input clock</td>
14226 </tr>
14227 <tr class="row-odd"><td>94</td>
14228 <td>DEV_SERDES_10G0_IP4_LN1_TXFCLK</td>
14229 <td>Output clock</td>
14230 </tr>
14231 <tr class="row-even"><td>95</td>
14232 <td>DEV_SERDES_10G0_IP4_LN1_TXMCLK</td>
14233 <td>Output clock</td>
14234 </tr>
14235 <tr class="row-odd"><td>96</td>
14236 <td>DEV_SERDES_10G0_IP4_LN2_REFCLK</td>
14237 <td>Output clock</td>
14238 </tr>
14239 <tr class="row-even"><td>97</td>
14240 <td>DEV_SERDES_10G0_IP4_LN2_RXCLK</td>
14241 <td>Output clock</td>
14242 </tr>
14243 <tr class="row-odd"><td>98</td>
14244 <td>DEV_SERDES_10G0_IP4_LN2_RXFCLK</td>
14245 <td>Output clock</td>
14246 </tr>
14247 <tr class="row-even"><td>99</td>
14248 <td>DEV_SERDES_10G0_IP4_LN2_TXCLK</td>
14249 <td>Input clock</td>
14250 </tr>
14251 <tr class="row-odd"><td>100</td>
14252 <td>DEV_SERDES_10G0_IP4_LN2_TXFCLK</td>
14253 <td>Output clock</td>
14254 </tr>
14255 <tr class="row-even"><td>101</td>
14256 <td>DEV_SERDES_10G0_IP4_LN2_TXMCLK</td>
14257 <td>Output clock</td>
14258 </tr>
14259 <tr class="row-odd"><td>102</td>
14260 <td>DEV_SERDES_10G0_IP4_LN3_REFCLK</td>
14261 <td>Output clock</td>
14262 </tr>
14263 <tr class="row-even"><td>103</td>
14264 <td>DEV_SERDES_10G0_IP4_LN3_RXCLK</td>
14265 <td>Output clock</td>
14266 </tr>
14267 <tr class="row-odd"><td>104</td>
14268 <td>DEV_SERDES_10G0_IP4_LN3_RXFCLK</td>
14269 <td>Output clock</td>
14270 </tr>
14271 <tr class="row-even"><td>105</td>
14272 <td>DEV_SERDES_10G0_IP4_LN3_TXCLK</td>
14273 <td>Input clock</td>
14274 </tr>
14275 <tr class="row-odd"><td>106</td>
14276 <td>DEV_SERDES_10G0_IP4_LN3_TXFCLK</td>
14277 <td>Output clock</td>
14278 </tr>
14279 <tr class="row-even"><td>107</td>
14280 <td>DEV_SERDES_10G0_IP4_LN3_TXMCLK</td>
14281 <td>Output clock</td>
14282 </tr>
14283 <tr class="row-odd"><td>129</td>
14284 <td>DEV_SERDES_10G0_TAP_TCK</td>
14285 <td>Input clock</td>
14286 </tr>
14287 </tbody>
14288 </table>
14289 </div>
14290 <div class="section" id="clocks-for-serdes-10g1-device">
14291 <span id="soc-doc-j784s4-public-clks-serdes-10g1"></span><h3>Clocks for SERDES_10G1 Device<a class="headerlink" href="#clocks-for-serdes-10g1-device" title="Permalink to this headline">¶</a></h3>
14292 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_SERDES_10G1</span></a> (ID = 405)</p>
14293 <p>Following is a mapping of Clocks IDs to function:</p>
14294 <table border="1" class="docutils">
14295 <colgroup>
14296 <col width="8%" />
14297 <col width="50%" />
14298 <col width="42%" />
14299 </colgroup>
14300 <thead valign="bottom">
14301 <tr class="row-odd"><th class="head">Clock ID</th>
14302 <th class="head">Name</th>
14303 <th class="head">Function</th>
14304 </tr>
14305 </thead>
14306 <tbody valign="top">
14307 <tr class="row-even"><td>2</td>
14308 <td>DEV_SERDES_10G1_CLK</td>
14309 <td>Input clock</td>
14310 </tr>
14311 <tr class="row-odd"><td>3</td>
14312 <td>DEV_SERDES_10G1_CMN_REFCLK_M</td>
14313 <td>Input clock</td>
14314 </tr>
14315 <tr class="row-even"><td>3</td>
14316 <td>DEV_SERDES_10G1_CMN_REFCLK_M</td>
14317 <td>Output clock</td>
14318 </tr>
14319 <tr class="row-odd"><td>4</td>
14320 <td>DEV_SERDES_10G1_CMN_REFCLK_P</td>
14321 <td>Input clock</td>
14322 </tr>
14323 <tr class="row-even"><td>4</td>
14324 <td>DEV_SERDES_10G1_CMN_REFCLK_P</td>
14325 <td>Output clock</td>
14326 </tr>
14327 <tr class="row-odd"><td>5</td>
14328 <td>DEV_SERDES_10G1_CORE_REF1_CLK</td>
14329 <td>Input clock</td>
14330 </tr>
14331 <tr class="row-even"><td>6</td>
14332 <td>DEV_SERDES_10G1_CORE_REF_CLK</td>
14333 <td>Input muxed clock</td>
14334 </tr>
14335 <tr class="row-odd"><td>7</td>
14336 <td>DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14337 <td>Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK</td>
14338 </tr>
14339 <tr class="row-even"><td>8</td>
14340 <td>DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14341 <td>Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK</td>
14342 </tr>
14343 <tr class="row-odd"><td>9</td>
14344 <td>DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
14345 <td>Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK</td>
14346 </tr>
14347 <tr class="row-even"><td>10</td>
14348 <td>DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
14349 <td>Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK</td>
14350 </tr>
14351 <tr class="row-odd"><td>12</td>
14352 <td>DEV_SERDES_10G1_IP1_LN0_REFCLK</td>
14353 <td>Output clock</td>
14354 </tr>
14355 <tr class="row-even"><td>13</td>
14356 <td>DEV_SERDES_10G1_IP1_LN0_RXCLK</td>
14357 <td>Output clock</td>
14358 </tr>
14359 <tr class="row-odd"><td>14</td>
14360 <td>DEV_SERDES_10G1_IP1_LN0_RXFCLK</td>
14361 <td>Output clock</td>
14362 </tr>
14363 <tr class="row-even"><td>15</td>
14364 <td>DEV_SERDES_10G1_IP1_LN0_TXCLK</td>
14365 <td>Input clock</td>
14366 </tr>
14367 <tr class="row-odd"><td>16</td>
14368 <td>DEV_SERDES_10G1_IP1_LN0_TXFCLK</td>
14369 <td>Output clock</td>
14370 </tr>
14371 <tr class="row-even"><td>17</td>
14372 <td>DEV_SERDES_10G1_IP1_LN0_TXMCLK</td>
14373 <td>Output clock</td>
14374 </tr>
14375 <tr class="row-odd"><td>18</td>
14376 <td>DEV_SERDES_10G1_IP1_LN1_REFCLK</td>
14377 <td>Output clock</td>
14378 </tr>
14379 <tr class="row-even"><td>19</td>
14380 <td>DEV_SERDES_10G1_IP1_LN1_RXCLK</td>
14381 <td>Output clock</td>
14382 </tr>
14383 <tr class="row-odd"><td>20</td>
14384 <td>DEV_SERDES_10G1_IP1_LN1_RXFCLK</td>
14385 <td>Output clock</td>
14386 </tr>
14387 <tr class="row-even"><td>21</td>
14388 <td>DEV_SERDES_10G1_IP1_LN1_TXCLK</td>
14389 <td>Input clock</td>
14390 </tr>
14391 <tr class="row-odd"><td>22</td>
14392 <td>DEV_SERDES_10G1_IP1_LN1_TXFCLK</td>
14393 <td>Output clock</td>
14394 </tr>
14395 <tr class="row-even"><td>23</td>
14396 <td>DEV_SERDES_10G1_IP1_LN1_TXMCLK</td>
14397 <td>Output clock</td>
14398 </tr>
14399 <tr class="row-odd"><td>24</td>
14400 <td>DEV_SERDES_10G1_IP1_LN2_REFCLK</td>
14401 <td>Output clock</td>
14402 </tr>
14403 <tr class="row-even"><td>25</td>
14404 <td>DEV_SERDES_10G1_IP1_LN2_RXCLK</td>
14405 <td>Output clock</td>
14406 </tr>
14407 <tr class="row-odd"><td>26</td>
14408 <td>DEV_SERDES_10G1_IP1_LN2_RXFCLK</td>
14409 <td>Output clock</td>
14410 </tr>
14411 <tr class="row-even"><td>27</td>
14412 <td>DEV_SERDES_10G1_IP1_LN2_TXCLK</td>
14413 <td>Input clock</td>
14414 </tr>
14415 <tr class="row-odd"><td>28</td>
14416 <td>DEV_SERDES_10G1_IP1_LN2_TXFCLK</td>
14417 <td>Output clock</td>
14418 </tr>
14419 <tr class="row-even"><td>29</td>
14420 <td>DEV_SERDES_10G1_IP1_LN2_TXMCLK</td>
14421 <td>Output clock</td>
14422 </tr>
14423 <tr class="row-odd"><td>30</td>
14424 <td>DEV_SERDES_10G1_IP1_LN3_REFCLK</td>
14425 <td>Output clock</td>
14426 </tr>
14427 <tr class="row-even"><td>31</td>
14428 <td>DEV_SERDES_10G1_IP1_LN3_RXCLK</td>
14429 <td>Output clock</td>
14430 </tr>
14431 <tr class="row-odd"><td>32</td>
14432 <td>DEV_SERDES_10G1_IP1_LN3_RXFCLK</td>
14433 <td>Output clock</td>
14434 </tr>
14435 <tr class="row-even"><td>33</td>
14436 <td>DEV_SERDES_10G1_IP1_LN3_TXCLK</td>
14437 <td>Input clock</td>
14438 </tr>
14439 <tr class="row-odd"><td>34</td>
14440 <td>DEV_SERDES_10G1_IP1_LN3_TXFCLK</td>
14441 <td>Output clock</td>
14442 </tr>
14443 <tr class="row-even"><td>35</td>
14444 <td>DEV_SERDES_10G1_IP1_LN3_TXMCLK</td>
14445 <td>Output clock</td>
14446 </tr>
14447 <tr class="row-odd"><td>36</td>
14448 <td>DEV_SERDES_10G1_IP2_LN0_REFCLK</td>
14449 <td>Output clock</td>
14450 </tr>
14451 <tr class="row-even"><td>37</td>
14452 <td>DEV_SERDES_10G1_IP2_LN0_RXCLK</td>
14453 <td>Output clock</td>
14454 </tr>
14455 <tr class="row-odd"><td>38</td>
14456 <td>DEV_SERDES_10G1_IP2_LN0_RXFCLK</td>
14457 <td>Output clock</td>
14458 </tr>
14459 <tr class="row-even"><td>39</td>
14460 <td>DEV_SERDES_10G1_IP2_LN0_TXCLK</td>
14461 <td>Input clock</td>
14462 </tr>
14463 <tr class="row-odd"><td>40</td>
14464 <td>DEV_SERDES_10G1_IP2_LN0_TXFCLK</td>
14465 <td>Output clock</td>
14466 </tr>
14467 <tr class="row-even"><td>41</td>
14468 <td>DEV_SERDES_10G1_IP2_LN0_TXMCLK</td>
14469 <td>Output clock</td>
14470 </tr>
14471 <tr class="row-odd"><td>42</td>
14472 <td>DEV_SERDES_10G1_IP2_LN1_REFCLK</td>
14473 <td>Output clock</td>
14474 </tr>
14475 <tr class="row-even"><td>43</td>
14476 <td>DEV_SERDES_10G1_IP2_LN1_RXCLK</td>
14477 <td>Output clock</td>
14478 </tr>
14479 <tr class="row-odd"><td>44</td>
14480 <td>DEV_SERDES_10G1_IP2_LN1_RXFCLK</td>
14481 <td>Output clock</td>
14482 </tr>
14483 <tr class="row-even"><td>45</td>
14484 <td>DEV_SERDES_10G1_IP2_LN1_TXCLK</td>
14485 <td>Input clock</td>
14486 </tr>
14487 <tr class="row-odd"><td>46</td>
14488 <td>DEV_SERDES_10G1_IP2_LN1_TXFCLK</td>
14489 <td>Output clock</td>
14490 </tr>
14491 <tr class="row-even"><td>47</td>
14492 <td>DEV_SERDES_10G1_IP2_LN1_TXMCLK</td>
14493 <td>Output clock</td>
14494 </tr>
14495 <tr class="row-odd"><td>48</td>
14496 <td>DEV_SERDES_10G1_IP2_LN2_REFCLK</td>
14497 <td>Output clock</td>
14498 </tr>
14499 <tr class="row-even"><td>49</td>
14500 <td>DEV_SERDES_10G1_IP2_LN2_RXCLK</td>
14501 <td>Output clock</td>
14502 </tr>
14503 <tr class="row-odd"><td>50</td>
14504 <td>DEV_SERDES_10G1_IP2_LN2_RXFCLK</td>
14505 <td>Output clock</td>
14506 </tr>
14507 <tr class="row-even"><td>51</td>
14508 <td>DEV_SERDES_10G1_IP2_LN2_TXCLK</td>
14509 <td>Input clock</td>
14510 </tr>
14511 <tr class="row-odd"><td>52</td>
14512 <td>DEV_SERDES_10G1_IP2_LN2_TXFCLK</td>
14513 <td>Output clock</td>
14514 </tr>
14515 <tr class="row-even"><td>53</td>
14516 <td>DEV_SERDES_10G1_IP2_LN2_TXMCLK</td>
14517 <td>Output clock</td>
14518 </tr>
14519 <tr class="row-odd"><td>54</td>
14520 <td>DEV_SERDES_10G1_IP2_LN3_REFCLK</td>
14521 <td>Output clock</td>
14522 </tr>
14523 <tr class="row-even"><td>55</td>
14524 <td>DEV_SERDES_10G1_IP2_LN3_RXCLK</td>
14525 <td>Output clock</td>
14526 </tr>
14527 <tr class="row-odd"><td>56</td>
14528 <td>DEV_SERDES_10G1_IP2_LN3_RXFCLK</td>
14529 <td>Output clock</td>
14530 </tr>
14531 <tr class="row-even"><td>57</td>
14532 <td>DEV_SERDES_10G1_IP2_LN3_TXCLK</td>
14533 <td>Input clock</td>
14534 </tr>
14535 <tr class="row-odd"><td>58</td>
14536 <td>DEV_SERDES_10G1_IP2_LN3_TXFCLK</td>
14537 <td>Output clock</td>
14538 </tr>
14539 <tr class="row-even"><td>59</td>
14540 <td>DEV_SERDES_10G1_IP2_LN3_TXMCLK</td>
14541 <td>Output clock</td>
14542 </tr>
14543 <tr class="row-odd"><td>72</td>
14544 <td>DEV_SERDES_10G1_IP3_LN2_REFCLK</td>
14545 <td>Output clock</td>
14546 </tr>
14547 <tr class="row-even"><td>73</td>
14548 <td>DEV_SERDES_10G1_IP3_LN2_RXCLK</td>
14549 <td>Output clock</td>
14550 </tr>
14551 <tr class="row-odd"><td>74</td>
14552 <td>DEV_SERDES_10G1_IP3_LN2_RXFCLK</td>
14553 <td>Output clock</td>
14554 </tr>
14555 <tr class="row-even"><td>75</td>
14556 <td>DEV_SERDES_10G1_IP3_LN2_TXCLK</td>
14557 <td>Input clock</td>
14558 </tr>
14559 <tr class="row-odd"><td>76</td>
14560 <td>DEV_SERDES_10G1_IP3_LN2_TXFCLK</td>
14561 <td>Output clock</td>
14562 </tr>
14563 <tr class="row-even"><td>77</td>
14564 <td>DEV_SERDES_10G1_IP3_LN2_TXMCLK</td>
14565 <td>Output clock</td>
14566 </tr>
14567 <tr class="row-odd"><td>78</td>
14568 <td>DEV_SERDES_10G1_IP3_LN3_REFCLK</td>
14569 <td>Output clock</td>
14570 </tr>
14571 <tr class="row-even"><td>79</td>
14572 <td>DEV_SERDES_10G1_IP3_LN3_RXCLK</td>
14573 <td>Output clock</td>
14574 </tr>
14575 <tr class="row-odd"><td>80</td>
14576 <td>DEV_SERDES_10G1_IP3_LN3_RXFCLK</td>
14577 <td>Output clock</td>
14578 </tr>
14579 <tr class="row-even"><td>81</td>
14580 <td>DEV_SERDES_10G1_IP3_LN3_TXCLK</td>
14581 <td>Input clock</td>
14582 </tr>
14583 <tr class="row-odd"><td>82</td>
14584 <td>DEV_SERDES_10G1_IP3_LN3_TXFCLK</td>
14585 <td>Output clock</td>
14586 </tr>
14587 <tr class="row-even"><td>83</td>
14588 <td>DEV_SERDES_10G1_IP3_LN3_TXMCLK</td>
14589 <td>Output clock</td>
14590 </tr>
14591 <tr class="row-odd"><td>129</td>
14592 <td>DEV_SERDES_10G1_TAP_TCK</td>
14593 <td>Input clock</td>
14594 </tr>
14595 </tbody>
14596 </table>
14597 </div>
14598 <div class="section" id="clocks-for-serdes-10g2-device">
14599 <span id="soc-doc-j784s4-public-clks-serdes-10g2"></span><h3>Clocks for SERDES_10G2 Device<a class="headerlink" href="#clocks-for-serdes-10g2-device" title="Permalink to this headline">¶</a></h3>
14600 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_SERDES_10G2</span></a> (ID = 406)</p>
14601 <p>Following is a mapping of Clocks IDs to function:</p>
14602 <table border="1" class="docutils">
14603 <colgroup>
14604 <col width="8%" />
14605 <col width="50%" />
14606 <col width="42%" />
14607 </colgroup>
14608 <thead valign="bottom">
14609 <tr class="row-odd"><th class="head">Clock ID</th>
14610 <th class="head">Name</th>
14611 <th class="head">Function</th>
14612 </tr>
14613 </thead>
14614 <tbody valign="top">
14615 <tr class="row-even"><td>2</td>
14616 <td>DEV_SERDES_10G2_CLK</td>
14617 <td>Input clock</td>
14618 </tr>
14619 <tr class="row-odd"><td>3</td>
14620 <td>DEV_SERDES_10G2_CMN_REFCLK_M</td>
14621 <td>Input clock</td>
14622 </tr>
14623 <tr class="row-even"><td>3</td>
14624 <td>DEV_SERDES_10G2_CMN_REFCLK_M</td>
14625 <td>Output clock</td>
14626 </tr>
14627 <tr class="row-odd"><td>4</td>
14628 <td>DEV_SERDES_10G2_CMN_REFCLK_P</td>
14629 <td>Input clock</td>
14630 </tr>
14631 <tr class="row-even"><td>5</td>
14632 <td>DEV_SERDES_10G2_CORE_REF1_CLK</td>
14633 <td>Input clock</td>
14634 </tr>
14635 <tr class="row-odd"><td>6</td>
14636 <td>DEV_SERDES_10G2_CORE_REF_CLK</td>
14637 <td>Input muxed clock</td>
14638 </tr>
14639 <tr class="row-even"><td>7</td>
14640 <td>DEV_SERDES_10G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14641 <td>Parent input clock option to DEV_SERDES_10G2_CORE_REF_CLK</td>
14642 </tr>
14643 <tr class="row-odd"><td>8</td>
14644 <td>DEV_SERDES_10G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14645 <td>Parent input clock option to DEV_SERDES_10G2_CORE_REF_CLK</td>
14646 </tr>
14647 <tr class="row-even"><td>9</td>
14648 <td>DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
14649 <td>Parent input clock option to DEV_SERDES_10G2_CORE_REF_CLK</td>
14650 </tr>
14651 <tr class="row-odd"><td>10</td>
14652 <td>DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
14653 <td>Parent input clock option to DEV_SERDES_10G2_CORE_REF_CLK</td>
14654 </tr>
14655 <tr class="row-even"><td>12</td>
14656 <td>DEV_SERDES_10G2_IP1_LN0_REFCLK</td>
14657 <td>Output clock</td>
14658 </tr>
14659 <tr class="row-odd"><td>13</td>
14660 <td>DEV_SERDES_10G2_IP1_LN0_RXCLK</td>
14661 <td>Output clock</td>
14662 </tr>
14663 <tr class="row-even"><td>14</td>
14664 <td>DEV_SERDES_10G2_IP1_LN0_RXFCLK</td>
14665 <td>Output clock</td>
14666 </tr>
14667 <tr class="row-odd"><td>15</td>
14668 <td>DEV_SERDES_10G2_IP1_LN0_TXCLK</td>
14669 <td>Input clock</td>
14670 </tr>
14671 <tr class="row-even"><td>16</td>
14672 <td>DEV_SERDES_10G2_IP1_LN0_TXFCLK</td>
14673 <td>Output clock</td>
14674 </tr>
14675 <tr class="row-odd"><td>17</td>
14676 <td>DEV_SERDES_10G2_IP1_LN0_TXMCLK</td>
14677 <td>Output clock</td>
14678 </tr>
14679 <tr class="row-even"><td>18</td>
14680 <td>DEV_SERDES_10G2_IP1_LN1_REFCLK</td>
14681 <td>Output clock</td>
14682 </tr>
14683 <tr class="row-odd"><td>19</td>
14684 <td>DEV_SERDES_10G2_IP1_LN1_RXCLK</td>
14685 <td>Output clock</td>
14686 </tr>
14687 <tr class="row-even"><td>20</td>
14688 <td>DEV_SERDES_10G2_IP1_LN1_RXFCLK</td>
14689 <td>Output clock</td>
14690 </tr>
14691 <tr class="row-odd"><td>21</td>
14692 <td>DEV_SERDES_10G2_IP1_LN1_TXCLK</td>
14693 <td>Input clock</td>
14694 </tr>
14695 <tr class="row-even"><td>22</td>
14696 <td>DEV_SERDES_10G2_IP1_LN1_TXFCLK</td>
14697 <td>Output clock</td>
14698 </tr>
14699 <tr class="row-odd"><td>23</td>
14700 <td>DEV_SERDES_10G2_IP1_LN1_TXMCLK</td>
14701 <td>Output clock</td>
14702 </tr>
14703 <tr class="row-even"><td>24</td>
14704 <td>DEV_SERDES_10G2_IP1_LN2_REFCLK</td>
14705 <td>Output clock</td>
14706 </tr>
14707 <tr class="row-odd"><td>25</td>
14708 <td>DEV_SERDES_10G2_IP1_LN2_RXCLK</td>
14709 <td>Output clock</td>
14710 </tr>
14711 <tr class="row-even"><td>26</td>
14712 <td>DEV_SERDES_10G2_IP1_LN2_RXFCLK</td>
14713 <td>Output clock</td>
14714 </tr>
14715 <tr class="row-odd"><td>27</td>
14716 <td>DEV_SERDES_10G2_IP1_LN2_TXCLK</td>
14717 <td>Input clock</td>
14718 </tr>
14719 <tr class="row-even"><td>28</td>
14720 <td>DEV_SERDES_10G2_IP1_LN2_TXFCLK</td>
14721 <td>Output clock</td>
14722 </tr>
14723 <tr class="row-odd"><td>29</td>
14724 <td>DEV_SERDES_10G2_IP1_LN2_TXMCLK</td>
14725 <td>Output clock</td>
14726 </tr>
14727 <tr class="row-even"><td>30</td>
14728 <td>DEV_SERDES_10G2_IP1_LN3_REFCLK</td>
14729 <td>Output clock</td>
14730 </tr>
14731 <tr class="row-odd"><td>31</td>
14732 <td>DEV_SERDES_10G2_IP1_LN3_RXCLK</td>
14733 <td>Output clock</td>
14734 </tr>
14735 <tr class="row-even"><td>32</td>
14736 <td>DEV_SERDES_10G2_IP1_LN3_RXFCLK</td>
14737 <td>Output clock</td>
14738 </tr>
14739 <tr class="row-odd"><td>33</td>
14740 <td>DEV_SERDES_10G2_IP1_LN3_TXCLK</td>
14741 <td>Input clock</td>
14742 </tr>
14743 <tr class="row-even"><td>34</td>
14744 <td>DEV_SERDES_10G2_IP1_LN3_TXFCLK</td>
14745 <td>Output clock</td>
14746 </tr>
14747 <tr class="row-odd"><td>35</td>
14748 <td>DEV_SERDES_10G2_IP1_LN3_TXMCLK</td>
14749 <td>Output clock</td>
14750 </tr>
14751 <tr class="row-even"><td>48</td>
14752 <td>DEV_SERDES_10G2_IP2_LN2_REFCLK</td>
14753 <td>Output clock</td>
14754 </tr>
14755 <tr class="row-odd"><td>49</td>
14756 <td>DEV_SERDES_10G2_IP2_LN2_RXCLK</td>
14757 <td>Output clock</td>
14758 </tr>
14759 <tr class="row-even"><td>50</td>
14760 <td>DEV_SERDES_10G2_IP2_LN2_RXFCLK</td>
14761 <td>Output clock</td>
14762 </tr>
14763 <tr class="row-odd"><td>51</td>
14764 <td>DEV_SERDES_10G2_IP2_LN2_TXCLK</td>
14765 <td>Input clock</td>
14766 </tr>
14767 <tr class="row-even"><td>52</td>
14768 <td>DEV_SERDES_10G2_IP2_LN2_TXFCLK</td>
14769 <td>Output clock</td>
14770 </tr>
14771 <tr class="row-odd"><td>53</td>
14772 <td>DEV_SERDES_10G2_IP2_LN2_TXMCLK</td>
14773 <td>Output clock</td>
14774 </tr>
14775 <tr class="row-even"><td>54</td>
14776 <td>DEV_SERDES_10G2_IP2_LN3_REFCLK</td>
14777 <td>Output clock</td>
14778 </tr>
14779 <tr class="row-odd"><td>55</td>
14780 <td>DEV_SERDES_10G2_IP2_LN3_RXCLK</td>
14781 <td>Output clock</td>
14782 </tr>
14783 <tr class="row-even"><td>56</td>
14784 <td>DEV_SERDES_10G2_IP2_LN3_RXFCLK</td>
14785 <td>Output clock</td>
14786 </tr>
14787 <tr class="row-odd"><td>57</td>
14788 <td>DEV_SERDES_10G2_IP2_LN3_TXCLK</td>
14789 <td>Input clock</td>
14790 </tr>
14791 <tr class="row-even"><td>58</td>
14792 <td>DEV_SERDES_10G2_IP2_LN3_TXFCLK</td>
14793 <td>Output clock</td>
14794 </tr>
14795 <tr class="row-odd"><td>59</td>
14796 <td>DEV_SERDES_10G2_IP2_LN3_TXMCLK</td>
14797 <td>Output clock</td>
14798 </tr>
14799 <tr class="row-even"><td>129</td>
14800 <td>DEV_SERDES_10G2_TAP_TCK</td>
14801 <td>Input clock</td>
14802 </tr>
14803 </tbody>
14804 </table>
14805 </div>
14806 <div class="section" id="clocks-for-serdes-10g4-device">
14807 <span id="soc-doc-j784s4-public-clks-serdes-10g4"></span><h3>Clocks for SERDES_10G4 Device<a class="headerlink" href="#clocks-for-serdes-10g4-device" title="Permalink to this headline">¶</a></h3>
14808 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_SERDES_10G4</span></a> (ID = 407)</p>
14809 <p>Following is a mapping of Clocks IDs to function:</p>
14810 <table border="1" class="docutils">
14811 <colgroup>
14812 <col width="8%" />
14813 <col width="50%" />
14814 <col width="42%" />
14815 </colgroup>
14816 <thead valign="bottom">
14817 <tr class="row-odd"><th class="head">Clock ID</th>
14818 <th class="head">Name</th>
14819 <th class="head">Function</th>
14820 </tr>
14821 </thead>
14822 <tbody valign="top">
14823 <tr class="row-even"><td>2</td>
14824 <td>DEV_SERDES_10G4_CLK</td>
14825 <td>Input clock</td>
14826 </tr>
14827 <tr class="row-odd"><td>3</td>
14828 <td>DEV_SERDES_10G4_CMN_REFCLK_M</td>
14829 <td>Input clock</td>
14830 </tr>
14831 <tr class="row-even"><td>3</td>
14832 <td>DEV_SERDES_10G4_CMN_REFCLK_M</td>
14833 <td>Output clock</td>
14834 </tr>
14835 <tr class="row-odd"><td>4</td>
14836 <td>DEV_SERDES_10G4_CMN_REFCLK_P</td>
14837 <td>Input clock</td>
14838 </tr>
14839 <tr class="row-even"><td>4</td>
14840 <td>DEV_SERDES_10G4_CMN_REFCLK_P</td>
14841 <td>Output clock</td>
14842 </tr>
14843 <tr class="row-odd"><td>5</td>
14844 <td>DEV_SERDES_10G4_CORE_REF1_CLK</td>
14845 <td>Input clock</td>
14846 </tr>
14847 <tr class="row-even"><td>6</td>
14848 <td>DEV_SERDES_10G4_CORE_REF_CLK</td>
14849 <td>Input muxed clock</td>
14850 </tr>
14851 <tr class="row-odd"><td>7</td>
14852 <td>DEV_SERDES_10G4_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
14853 <td>Parent input clock option to DEV_SERDES_10G4_CORE_REF_CLK</td>
14854 </tr>
14855 <tr class="row-even"><td>8</td>
14856 <td>DEV_SERDES_10G4_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
14857 <td>Parent input clock option to DEV_SERDES_10G4_CORE_REF_CLK</td>
14858 </tr>
14859 <tr class="row-odd"><td>9</td>
14860 <td>DEV_SERDES_10G4_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK</td>
14861 <td>Parent input clock option to DEV_SERDES_10G4_CORE_REF_CLK</td>
14862 </tr>
14863 <tr class="row-even"><td>10</td>
14864 <td>DEV_SERDES_10G4_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK</td>
14865 <td>Parent input clock option to DEV_SERDES_10G4_CORE_REF_CLK</td>
14866 </tr>
14867 <tr class="row-odd"><td>12</td>
14868 <td>DEV_SERDES_10G4_IP1_LN0_REFCLK</td>
14869 <td>Output clock</td>
14870 </tr>
14871 <tr class="row-even"><td>13</td>
14872 <td>DEV_SERDES_10G4_IP1_LN0_RXCLK</td>
14873 <td>Output clock</td>
14874 </tr>
14875 <tr class="row-odd"><td>14</td>
14876 <td>DEV_SERDES_10G4_IP1_LN0_RXFCLK</td>
14877 <td>Output clock</td>
14878 </tr>
14879 <tr class="row-even"><td>15</td>
14880 <td>DEV_SERDES_10G4_IP1_LN0_TXCLK</td>
14881 <td>Input clock</td>
14882 </tr>
14883 <tr class="row-odd"><td>16</td>
14884 <td>DEV_SERDES_10G4_IP1_LN0_TXFCLK</td>
14885 <td>Output clock</td>
14886 </tr>
14887 <tr class="row-even"><td>17</td>
14888 <td>DEV_SERDES_10G4_IP1_LN0_TXMCLK</td>
14889 <td>Output clock</td>
14890 </tr>
14891 <tr class="row-odd"><td>18</td>
14892 <td>DEV_SERDES_10G4_IP1_LN1_REFCLK</td>
14893 <td>Output clock</td>
14894 </tr>
14895 <tr class="row-even"><td>19</td>
14896 <td>DEV_SERDES_10G4_IP1_LN1_RXCLK</td>
14897 <td>Output clock</td>
14898 </tr>
14899 <tr class="row-odd"><td>20</td>
14900 <td>DEV_SERDES_10G4_IP1_LN1_RXFCLK</td>
14901 <td>Output clock</td>
14902 </tr>
14903 <tr class="row-even"><td>21</td>
14904 <td>DEV_SERDES_10G4_IP1_LN1_TXCLK</td>
14905 <td>Input clock</td>
14906 </tr>
14907 <tr class="row-odd"><td>22</td>
14908 <td>DEV_SERDES_10G4_IP1_LN1_TXFCLK</td>
14909 <td>Output clock</td>
14910 </tr>
14911 <tr class="row-even"><td>23</td>
14912 <td>DEV_SERDES_10G4_IP1_LN1_TXMCLK</td>
14913 <td>Output clock</td>
14914 </tr>
14915 <tr class="row-odd"><td>24</td>
14916 <td>DEV_SERDES_10G4_IP1_LN2_REFCLK</td>
14917 <td>Output clock</td>
14918 </tr>
14919 <tr class="row-even"><td>25</td>
14920 <td>DEV_SERDES_10G4_IP1_LN2_RXCLK</td>
14921 <td>Output clock</td>
14922 </tr>
14923 <tr class="row-odd"><td>26</td>
14924 <td>DEV_SERDES_10G4_IP1_LN2_RXFCLK</td>
14925 <td>Output clock</td>
14926 </tr>
14927 <tr class="row-even"><td>27</td>
14928 <td>DEV_SERDES_10G4_IP1_LN2_TXCLK</td>
14929 <td>Input clock</td>
14930 </tr>
14931 <tr class="row-odd"><td>28</td>
14932 <td>DEV_SERDES_10G4_IP1_LN2_TXFCLK</td>
14933 <td>Output clock</td>
14934 </tr>
14935 <tr class="row-even"><td>29</td>
14936 <td>DEV_SERDES_10G4_IP1_LN2_TXMCLK</td>
14937 <td>Output clock</td>
14938 </tr>
14939 <tr class="row-odd"><td>30</td>
14940 <td>DEV_SERDES_10G4_IP1_LN3_REFCLK</td>
14941 <td>Output clock</td>
14942 </tr>
14943 <tr class="row-even"><td>31</td>
14944 <td>DEV_SERDES_10G4_IP1_LN3_RXCLK</td>
14945 <td>Output clock</td>
14946 </tr>
14947 <tr class="row-odd"><td>32</td>
14948 <td>DEV_SERDES_10G4_IP1_LN3_RXFCLK</td>
14949 <td>Output clock</td>
14950 </tr>
14951 <tr class="row-even"><td>33</td>
14952 <td>DEV_SERDES_10G4_IP1_LN3_TXCLK</td>
14953 <td>Input clock</td>
14954 </tr>
14955 <tr class="row-odd"><td>34</td>
14956 <td>DEV_SERDES_10G4_IP1_LN3_TXFCLK</td>
14957 <td>Output clock</td>
14958 </tr>
14959 <tr class="row-even"><td>35</td>
14960 <td>DEV_SERDES_10G4_IP1_LN3_TXMCLK</td>
14961 <td>Output clock</td>
14962 </tr>
14963 <tr class="row-odd"><td>36</td>
14964 <td>DEV_SERDES_10G4_IP2_LN0_REFCLK</td>
14965 <td>Output clock</td>
14966 </tr>
14967 <tr class="row-even"><td>37</td>
14968 <td>DEV_SERDES_10G4_IP2_LN0_RXCLK</td>
14969 <td>Output clock</td>
14970 </tr>
14971 <tr class="row-odd"><td>38</td>
14972 <td>DEV_SERDES_10G4_IP2_LN0_RXFCLK</td>
14973 <td>Output clock</td>
14974 </tr>
14975 <tr class="row-even"><td>39</td>
14976 <td>DEV_SERDES_10G4_IP2_LN0_TXCLK</td>
14977 <td>Input clock</td>
14978 </tr>
14979 <tr class="row-odd"><td>40</td>
14980 <td>DEV_SERDES_10G4_IP2_LN0_TXFCLK</td>
14981 <td>Output clock</td>
14982 </tr>
14983 <tr class="row-even"><td>41</td>
14984 <td>DEV_SERDES_10G4_IP2_LN0_TXMCLK</td>
14985 <td>Output clock</td>
14986 </tr>
14987 <tr class="row-odd"><td>42</td>
14988 <td>DEV_SERDES_10G4_IP2_LN1_REFCLK</td>
14989 <td>Output clock</td>
14990 </tr>
14991 <tr class="row-even"><td>43</td>
14992 <td>DEV_SERDES_10G4_IP2_LN1_RXCLK</td>
14993 <td>Output clock</td>
14994 </tr>
14995 <tr class="row-odd"><td>44</td>
14996 <td>DEV_SERDES_10G4_IP2_LN1_RXFCLK</td>
14997 <td>Output clock</td>
14998 </tr>
14999 <tr class="row-even"><td>45</td>
15000 <td>DEV_SERDES_10G4_IP2_LN1_TXCLK</td>
15001 <td>Input clock</td>
15002 </tr>
15003 <tr class="row-odd"><td>46</td>
15004 <td>DEV_SERDES_10G4_IP2_LN1_TXFCLK</td>
15005 <td>Output clock</td>
15006 </tr>
15007 <tr class="row-even"><td>47</td>
15008 <td>DEV_SERDES_10G4_IP2_LN1_TXMCLK</td>
15009 <td>Output clock</td>
15010 </tr>
15011 <tr class="row-odd"><td>48</td>
15012 <td>DEV_SERDES_10G4_IP2_LN2_REFCLK</td>
15013 <td>Output clock</td>
15014 </tr>
15015 <tr class="row-even"><td>49</td>
15016 <td>DEV_SERDES_10G4_IP2_LN2_RXCLK</td>
15017 <td>Output clock</td>
15018 </tr>
15019 <tr class="row-odd"><td>50</td>
15020 <td>DEV_SERDES_10G4_IP2_LN2_RXFCLK</td>
15021 <td>Output clock</td>
15022 </tr>
15023 <tr class="row-even"><td>51</td>
15024 <td>DEV_SERDES_10G4_IP2_LN2_TXCLK</td>
15025 <td>Input clock</td>
15026 </tr>
15027 <tr class="row-odd"><td>52</td>
15028 <td>DEV_SERDES_10G4_IP2_LN2_TXFCLK</td>
15029 <td>Output clock</td>
15030 </tr>
15031 <tr class="row-even"><td>53</td>
15032 <td>DEV_SERDES_10G4_IP2_LN2_TXMCLK</td>
15033 <td>Output clock</td>
15034 </tr>
15035 <tr class="row-odd"><td>54</td>
15036 <td>DEV_SERDES_10G4_IP2_LN3_REFCLK</td>
15037 <td>Output clock</td>
15038 </tr>
15039 <tr class="row-even"><td>55</td>
15040 <td>DEV_SERDES_10G4_IP2_LN3_RXCLK</td>
15041 <td>Output clock</td>
15042 </tr>
15043 <tr class="row-odd"><td>56</td>
15044 <td>DEV_SERDES_10G4_IP2_LN3_RXFCLK</td>
15045 <td>Output clock</td>
15046 </tr>
15047 <tr class="row-even"><td>57</td>
15048 <td>DEV_SERDES_10G4_IP2_LN3_TXCLK</td>
15049 <td>Input clock</td>
15050 </tr>
15051 <tr class="row-odd"><td>58</td>
15052 <td>DEV_SERDES_10G4_IP2_LN3_TXFCLK</td>
15053 <td>Output clock</td>
15054 </tr>
15055 <tr class="row-even"><td>59</td>
15056 <td>DEV_SERDES_10G4_IP2_LN3_TXMCLK</td>
15057 <td>Output clock</td>
15058 </tr>
15059 <tr class="row-odd"><td>78</td>
15060 <td>DEV_SERDES_10G4_IP3_LN3_REFCLK</td>
15061 <td>Output clock</td>
15062 </tr>
15063 <tr class="row-even"><td>79</td>
15064 <td>DEV_SERDES_10G4_IP3_LN3_RXCLK</td>
15065 <td>Output clock</td>
15066 </tr>
15067 <tr class="row-odd"><td>80</td>
15068 <td>DEV_SERDES_10G4_IP3_LN3_RXFCLK</td>
15069 <td>Output clock</td>
15070 </tr>
15071 <tr class="row-even"><td>81</td>
15072 <td>DEV_SERDES_10G4_IP3_LN3_TXCLK</td>
15073 <td>Input clock</td>
15074 </tr>
15075 <tr class="row-odd"><td>82</td>
15076 <td>DEV_SERDES_10G4_IP3_LN3_TXFCLK</td>
15077 <td>Output clock</td>
15078 </tr>
15079 <tr class="row-even"><td>83</td>
15080 <td>DEV_SERDES_10G4_IP3_LN3_TXMCLK</td>
15081 <td>Output clock</td>
15082 </tr>
15083 <tr class="row-odd"><td>84</td>
15084 <td>DEV_SERDES_10G4_IP4_LN0_REFCLK</td>
15085 <td>Output clock</td>
15086 </tr>
15087 <tr class="row-even"><td>85</td>
15088 <td>DEV_SERDES_10G4_IP4_LN0_RXCLK</td>
15089 <td>Output clock</td>
15090 </tr>
15091 <tr class="row-odd"><td>86</td>
15092 <td>DEV_SERDES_10G4_IP4_LN0_RXFCLK</td>
15093 <td>Output clock</td>
15094 </tr>
15095 <tr class="row-even"><td>87</td>
15096 <td>DEV_SERDES_10G4_IP4_LN0_TXCLK</td>
15097 <td>Input clock</td>
15098 </tr>
15099 <tr class="row-odd"><td>88</td>
15100 <td>DEV_SERDES_10G4_IP4_LN0_TXFCLK</td>
15101 <td>Output clock</td>
15102 </tr>
15103 <tr class="row-even"><td>89</td>
15104 <td>DEV_SERDES_10G4_IP4_LN0_TXMCLK</td>
15105 <td>Output clock</td>
15106 </tr>
15107 <tr class="row-odd"><td>90</td>
15108 <td>DEV_SERDES_10G4_IP4_LN1_REFCLK</td>
15109 <td>Output clock</td>
15110 </tr>
15111 <tr class="row-even"><td>91</td>
15112 <td>DEV_SERDES_10G4_IP4_LN1_RXCLK</td>
15113 <td>Output clock</td>
15114 </tr>
15115 <tr class="row-odd"><td>92</td>
15116 <td>DEV_SERDES_10G4_IP4_LN1_RXFCLK</td>
15117 <td>Output clock</td>
15118 </tr>
15119 <tr class="row-even"><td>93</td>
15120 <td>DEV_SERDES_10G4_IP4_LN1_TXCLK</td>
15121 <td>Input clock</td>
15122 </tr>
15123 <tr class="row-odd"><td>94</td>
15124 <td>DEV_SERDES_10G4_IP4_LN1_TXFCLK</td>
15125 <td>Output clock</td>
15126 </tr>
15127 <tr class="row-even"><td>95</td>
15128 <td>DEV_SERDES_10G4_IP4_LN1_TXMCLK</td>
15129 <td>Output clock</td>
15130 </tr>
15131 <tr class="row-odd"><td>96</td>
15132 <td>DEV_SERDES_10G4_IP4_LN2_REFCLK</td>
15133 <td>Output clock</td>
15134 </tr>
15135 <tr class="row-even"><td>97</td>
15136 <td>DEV_SERDES_10G4_IP4_LN2_RXCLK</td>
15137 <td>Output clock</td>
15138 </tr>
15139 <tr class="row-odd"><td>98</td>
15140 <td>DEV_SERDES_10G4_IP4_LN2_RXFCLK</td>
15141 <td>Output clock</td>
15142 </tr>
15143 <tr class="row-even"><td>99</td>
15144 <td>DEV_SERDES_10G4_IP4_LN2_TXCLK</td>
15145 <td>Input clock</td>
15146 </tr>
15147 <tr class="row-odd"><td>100</td>
15148 <td>DEV_SERDES_10G4_IP4_LN2_TXFCLK</td>
15149 <td>Output clock</td>
15150 </tr>
15151 <tr class="row-even"><td>101</td>
15152 <td>DEV_SERDES_10G4_IP4_LN2_TXMCLK</td>
15153 <td>Output clock</td>
15154 </tr>
15155 <tr class="row-odd"><td>102</td>
15156 <td>DEV_SERDES_10G4_IP4_LN3_REFCLK</td>
15157 <td>Output clock</td>
15158 </tr>
15159 <tr class="row-even"><td>103</td>
15160 <td>DEV_SERDES_10G4_IP4_LN3_RXCLK</td>
15161 <td>Output clock</td>
15162 </tr>
15163 <tr class="row-odd"><td>104</td>
15164 <td>DEV_SERDES_10G4_IP4_LN3_RXFCLK</td>
15165 <td>Output clock</td>
15166 </tr>
15167 <tr class="row-even"><td>105</td>
15168 <td>DEV_SERDES_10G4_IP4_LN3_TXCLK</td>
15169 <td>Input clock</td>
15170 </tr>
15171 <tr class="row-odd"><td>106</td>
15172 <td>DEV_SERDES_10G4_IP4_LN3_TXFCLK</td>
15173 <td>Output clock</td>
15174 </tr>
15175 <tr class="row-even"><td>107</td>
15176 <td>DEV_SERDES_10G4_IP4_LN3_TXMCLK</td>
15177 <td>Output clock</td>
15178 </tr>
15179 </tbody>
15180 </table>
15181 </div>
15182 <div class="section" id="clocks-for-stm0-device">
15183 <span id="soc-doc-j784s4-public-clks-stm0"></span><h3>Clocks for STM0 Device<a class="headerlink" href="#clocks-for-stm0-device" title="Permalink to this headline">¶</a></h3>
15184 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_STM0</span></a> (ID = 77)</p>
15185 <p>Following is a mapping of Clocks IDs to function:</p>
15186 <table border="1" class="docutils">
15187 <colgroup>
15188 <col width="27%" />
15189 <col width="44%" />
15190 <col width="29%" />
15191 </colgroup>
15192 <thead valign="bottom">
15193 <tr class="row-odd"><th class="head">Clock ID</th>
15194 <th class="head">Name</th>
15195 <th class="head">Function</th>
15196 </tr>
15197 </thead>
15198 <tbody valign="top">
15199 <tr class="row-even"><td>0</td>
15200 <td>DEV_STM0_ATB_CLK</td>
15201 <td>Input clock</td>
15202 </tr>
15203 <tr class="row-odd"><td>1</td>
15204 <td>DEV_STM0_CORE_CLK</td>
15205 <td>Input clock</td>
15206 </tr>
15207 <tr class="row-even"><td>2</td>
15208 <td>DEV_STM0_VBUSP_CLK</td>
15209 <td>Input clock</td>
15210 </tr>
15211 </tbody>
15212 </table>
15213 </div>
15214 <div class="section" id="clocks-for-timer0-device">
15215 <span id="soc-doc-j784s4-public-clks-timer0"></span><h3>Clocks for TIMER0 Device<a class="headerlink" href="#clocks-for-timer0-device" title="Permalink to this headline">¶</a></h3>
15216 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER0</span></a> (ID = 97)</p>
15217 <p>Following is a mapping of Clocks IDs to function:</p>
15218 <table border="1" class="docutils">
15219 <colgroup>
15220 <col width="8%" />
15221 <col width="54%" />
15222 <col width="38%" />
15223 </colgroup>
15224 <thead valign="bottom">
15225 <tr class="row-odd"><th class="head">Clock ID</th>
15226 <th class="head">Name</th>
15227 <th class="head">Function</th>
15228 </tr>
15229 </thead>
15230 <tbody valign="top">
15231 <tr class="row-even"><td>0</td>
15232 <td>DEV_TIMER0_TIMER_HCLK_CLK</td>
15233 <td>Input clock</td>
15234 </tr>
15235 <tr class="row-odd"><td>1</td>
15236 <td>DEV_TIMER0_TIMER_PWM</td>
15237 <td>Output clock</td>
15238 </tr>
15239 <tr class="row-even"><td>2</td>
15240 <td>DEV_TIMER0_TIMER_TCLK_CLK</td>
15241 <td>Input muxed clock</td>
15242 </tr>
15243 <tr class="row-odd"><td>3</td>
15244 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15245 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15246 </tr>
15247 <tr class="row-even"><td>4</td>
15248 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15249 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15250 </tr>
15251 <tr class="row-odd"><td>5</td>
15252 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK</td>
15253 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15254 </tr>
15255 <tr class="row-even"><td>6</td>
15256 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
15257 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15258 </tr>
15259 <tr class="row-odd"><td>7</td>
15260 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
15261 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15262 </tr>
15263 <tr class="row-even"><td>8</td>
15264 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
15265 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15266 </tr>
15267 <tr class="row-odd"><td>9</td>
15268 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
15269 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15270 </tr>
15271 <tr class="row-even"><td>10</td>
15272 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
15273 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15274 </tr>
15275 <tr class="row-odd"><td>11</td>
15276 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
15277 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15278 </tr>
15279 <tr class="row-even"><td>12</td>
15280 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
15281 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15282 </tr>
15283 <tr class="row-odd"><td>13</td>
15284 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
15285 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15286 </tr>
15287 <tr class="row-even"><td>14</td>
15288 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
15289 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15290 </tr>
15291 <tr class="row-odd"><td>15</td>
15292 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2</td>
15293 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15294 </tr>
15295 <tr class="row-even"><td>16</td>
15296 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3</td>
15297 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15298 </tr>
15299 <tr class="row-odd"><td>17</td>
15300 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0</td>
15301 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15302 </tr>
15303 <tr class="row-even"><td>18</td>
15304 <td>DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0</td>
15305 <td>Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK</td>
15306 </tr>
15307 </tbody>
15308 </table>
15309 </div>
15310 <div class="section" id="clocks-for-timer1-device">
15311 <span id="soc-doc-j784s4-public-clks-timer1"></span><h3>Clocks for TIMER1 Device<a class="headerlink" href="#clocks-for-timer1-device" title="Permalink to this headline">¶</a></h3>
15312 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER1</span></a> (ID = 98)</p>
15313 <p>Following is a mapping of Clocks IDs to function:</p>
15314 <table border="1" class="docutils">
15315 <colgroup>
15316 <col width="9%" />
15317 <col width="49%" />
15318 <col width="42%" />
15319 </colgroup>
15320 <thead valign="bottom">
15321 <tr class="row-odd"><th class="head">Clock ID</th>
15322 <th class="head">Name</th>
15323 <th class="head">Function</th>
15324 </tr>
15325 </thead>
15326 <tbody valign="top">
15327 <tr class="row-even"><td>0</td>
15328 <td>DEV_TIMER1_TIMER_HCLK_CLK</td>
15329 <td>Input clock</td>
15330 </tr>
15331 <tr class="row-odd"><td>2</td>
15332 <td>DEV_TIMER1_TIMER_TCLK_CLK</td>
15333 <td>Input muxed clock</td>
15334 </tr>
15335 <tr class="row-even"><td>3</td>
15336 <td>DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1</td>
15337 <td>Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK</td>
15338 </tr>
15339 <tr class="row-odd"><td>4</td>
15340 <td>DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM</td>
15341 <td>Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK</td>
15342 </tr>
15343 </tbody>
15344 </table>
15345 </div>
15346 <div class="section" id="clocks-for-timer10-device">
15347 <span id="soc-doc-j784s4-public-clks-timer10"></span><h3>Clocks for TIMER10 Device<a class="headerlink" href="#clocks-for-timer10-device" title="Permalink to this headline">¶</a></h3>
15348 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER10</span></a> (ID = 107)</p>
15349 <p>Following is a mapping of Clocks IDs to function:</p>
15350 <table border="1" class="docutils">
15351 <colgroup>
15352 <col width="8%" />
15353 <col width="54%" />
15354 <col width="38%" />
15355 </colgroup>
15356 <thead valign="bottom">
15357 <tr class="row-odd"><th class="head">Clock ID</th>
15358 <th class="head">Name</th>
15359 <th class="head">Function</th>
15360 </tr>
15361 </thead>
15362 <tbody valign="top">
15363 <tr class="row-even"><td>0</td>
15364 <td>DEV_TIMER10_TIMER_HCLK_CLK</td>
15365 <td>Input clock</td>
15366 </tr>
15367 <tr class="row-odd"><td>1</td>
15368 <td>DEV_TIMER10_TIMER_PWM</td>
15369 <td>Output clock</td>
15370 </tr>
15371 <tr class="row-even"><td>2</td>
15372 <td>DEV_TIMER10_TIMER_TCLK_CLK</td>
15373 <td>Input muxed clock</td>
15374 </tr>
15375 <tr class="row-odd"><td>3</td>
15376 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15377 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15378 </tr>
15379 <tr class="row-even"><td>4</td>
15380 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15381 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15382 </tr>
15383 <tr class="row-odd"><td>5</td>
15384 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK</td>
15385 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15386 </tr>
15387 <tr class="row-even"><td>6</td>
15388 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
15389 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15390 </tr>
15391 <tr class="row-odd"><td>7</td>
15392 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
15393 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15394 </tr>
15395 <tr class="row-even"><td>8</td>
15396 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
15397 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15398 </tr>
15399 <tr class="row-odd"><td>9</td>
15400 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
15401 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15402 </tr>
15403 <tr class="row-even"><td>10</td>
15404 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
15405 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15406 </tr>
15407 <tr class="row-odd"><td>11</td>
15408 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
15409 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15410 </tr>
15411 <tr class="row-even"><td>12</td>
15412 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
15413 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15414 </tr>
15415 <tr class="row-odd"><td>13</td>
15416 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
15417 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15418 </tr>
15419 <tr class="row-even"><td>14</td>
15420 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
15421 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15422 </tr>
15423 <tr class="row-odd"><td>15</td>
15424 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2</td>
15425 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15426 </tr>
15427 <tr class="row-even"><td>16</td>
15428 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3</td>
15429 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15430 </tr>
15431 <tr class="row-odd"><td>17</td>
15432 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0</td>
15433 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15434 </tr>
15435 <tr class="row-even"><td>18</td>
15436 <td>DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0</td>
15437 <td>Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK</td>
15438 </tr>
15439 </tbody>
15440 </table>
15441 </div>
15442 <div class="section" id="clocks-for-timer11-device">
15443 <span id="soc-doc-j784s4-public-clks-timer11"></span><h3>Clocks for TIMER11 Device<a class="headerlink" href="#clocks-for-timer11-device" title="Permalink to this headline">¶</a></h3>
15444 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER11</span></a> (ID = 108)</p>
15445 <p>Following is a mapping of Clocks IDs to function:</p>
15446 <table border="1" class="docutils">
15447 <colgroup>
15448 <col width="9%" />
15449 <col width="50%" />
15450 <col width="42%" />
15451 </colgroup>
15452 <thead valign="bottom">
15453 <tr class="row-odd"><th class="head">Clock ID</th>
15454 <th class="head">Name</th>
15455 <th class="head">Function</th>
15456 </tr>
15457 </thead>
15458 <tbody valign="top">
15459 <tr class="row-even"><td>0</td>
15460 <td>DEV_TIMER11_TIMER_HCLK_CLK</td>
15461 <td>Input clock</td>
15462 </tr>
15463 <tr class="row-odd"><td>2</td>
15464 <td>DEV_TIMER11_TIMER_TCLK_CLK</td>
15465 <td>Input muxed clock</td>
15466 </tr>
15467 <tr class="row-even"><td>3</td>
15468 <td>DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11</td>
15469 <td>Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK</td>
15470 </tr>
15471 <tr class="row-odd"><td>4</td>
15472 <td>DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM</td>
15473 <td>Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK</td>
15474 </tr>
15475 </tbody>
15476 </table>
15477 </div>
15478 <div class="section" id="clocks-for-timer12-device">
15479 <span id="soc-doc-j784s4-public-clks-timer12"></span><h3>Clocks for TIMER12 Device<a class="headerlink" href="#clocks-for-timer12-device" title="Permalink to this headline">¶</a></h3>
15480 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER12</span></a> (ID = 109)</p>
15481 <p>Following is a mapping of Clocks IDs to function:</p>
15482 <table border="1" class="docutils">
15483 <colgroup>
15484 <col width="8%" />
15485 <col width="54%" />
15486 <col width="38%" />
15487 </colgroup>
15488 <thead valign="bottom">
15489 <tr class="row-odd"><th class="head">Clock ID</th>
15490 <th class="head">Name</th>
15491 <th class="head">Function</th>
15492 </tr>
15493 </thead>
15494 <tbody valign="top">
15495 <tr class="row-even"><td>0</td>
15496 <td>DEV_TIMER12_TIMER_HCLK_CLK</td>
15497 <td>Input clock</td>
15498 </tr>
15499 <tr class="row-odd"><td>1</td>
15500 <td>DEV_TIMER12_TIMER_PWM</td>
15501 <td>Output clock</td>
15502 </tr>
15503 <tr class="row-even"><td>2</td>
15504 <td>DEV_TIMER12_TIMER_TCLK_CLK</td>
15505 <td>Input muxed clock</td>
15506 </tr>
15507 <tr class="row-odd"><td>3</td>
15508 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15509 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15510 </tr>
15511 <tr class="row-even"><td>4</td>
15512 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15513 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15514 </tr>
15515 <tr class="row-odd"><td>5</td>
15516 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK</td>
15517 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15518 </tr>
15519 <tr class="row-even"><td>6</td>
15520 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
15521 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15522 </tr>
15523 <tr class="row-odd"><td>7</td>
15524 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
15525 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15526 </tr>
15527 <tr class="row-even"><td>8</td>
15528 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
15529 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15530 </tr>
15531 <tr class="row-odd"><td>9</td>
15532 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
15533 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15534 </tr>
15535 <tr class="row-even"><td>10</td>
15536 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
15537 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15538 </tr>
15539 <tr class="row-odd"><td>11</td>
15540 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
15541 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15542 </tr>
15543 <tr class="row-even"><td>12</td>
15544 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
15545 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15546 </tr>
15547 <tr class="row-odd"><td>13</td>
15548 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
15549 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15550 </tr>
15551 <tr class="row-even"><td>14</td>
15552 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
15553 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15554 </tr>
15555 <tr class="row-odd"><td>15</td>
15556 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2</td>
15557 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15558 </tr>
15559 <tr class="row-even"><td>16</td>
15560 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3</td>
15561 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15562 </tr>
15563 <tr class="row-odd"><td>17</td>
15564 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0</td>
15565 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15566 </tr>
15567 <tr class="row-even"><td>18</td>
15568 <td>DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0</td>
15569 <td>Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK</td>
15570 </tr>
15571 </tbody>
15572 </table>
15573 </div>
15574 <div class="section" id="clocks-for-timer13-device">
15575 <span id="soc-doc-j784s4-public-clks-timer13"></span><h3>Clocks for TIMER13 Device<a class="headerlink" href="#clocks-for-timer13-device" title="Permalink to this headline">¶</a></h3>
15576 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER13</span></a> (ID = 110)</p>
15577 <p>Following is a mapping of Clocks IDs to function:</p>
15578 <table border="1" class="docutils">
15579 <colgroup>
15580 <col width="9%" />
15581 <col width="50%" />
15582 <col width="42%" />
15583 </colgroup>
15584 <thead valign="bottom">
15585 <tr class="row-odd"><th class="head">Clock ID</th>
15586 <th class="head">Name</th>
15587 <th class="head">Function</th>
15588 </tr>
15589 </thead>
15590 <tbody valign="top">
15591 <tr class="row-even"><td>0</td>
15592 <td>DEV_TIMER13_TIMER_HCLK_CLK</td>
15593 <td>Input clock</td>
15594 </tr>
15595 <tr class="row-odd"><td>2</td>
15596 <td>DEV_TIMER13_TIMER_TCLK_CLK</td>
15597 <td>Input muxed clock</td>
15598 </tr>
15599 <tr class="row-even"><td>3</td>
15600 <td>DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13</td>
15601 <td>Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK</td>
15602 </tr>
15603 <tr class="row-odd"><td>4</td>
15604 <td>DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM</td>
15605 <td>Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK</td>
15606 </tr>
15607 </tbody>
15608 </table>
15609 </div>
15610 <div class="section" id="clocks-for-timer14-device">
15611 <span id="soc-doc-j784s4-public-clks-timer14"></span><h3>Clocks for TIMER14 Device<a class="headerlink" href="#clocks-for-timer14-device" title="Permalink to this headline">¶</a></h3>
15612 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER14</span></a> (ID = 111)</p>
15613 <p>Following is a mapping of Clocks IDs to function:</p>
15614 <table border="1" class="docutils">
15615 <colgroup>
15616 <col width="8%" />
15617 <col width="54%" />
15618 <col width="38%" />
15619 </colgroup>
15620 <thead valign="bottom">
15621 <tr class="row-odd"><th class="head">Clock ID</th>
15622 <th class="head">Name</th>
15623 <th class="head">Function</th>
15624 </tr>
15625 </thead>
15626 <tbody valign="top">
15627 <tr class="row-even"><td>0</td>
15628 <td>DEV_TIMER14_TIMER_HCLK_CLK</td>
15629 <td>Input clock</td>
15630 </tr>
15631 <tr class="row-odd"><td>1</td>
15632 <td>DEV_TIMER14_TIMER_PWM</td>
15633 <td>Output clock</td>
15634 </tr>
15635 <tr class="row-even"><td>2</td>
15636 <td>DEV_TIMER14_TIMER_TCLK_CLK</td>
15637 <td>Input muxed clock</td>
15638 </tr>
15639 <tr class="row-odd"><td>3</td>
15640 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15641 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15642 </tr>
15643 <tr class="row-even"><td>4</td>
15644 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15645 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15646 </tr>
15647 <tr class="row-odd"><td>5</td>
15648 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK</td>
15649 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15650 </tr>
15651 <tr class="row-even"><td>6</td>
15652 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
15653 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15654 </tr>
15655 <tr class="row-odd"><td>7</td>
15656 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
15657 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15658 </tr>
15659 <tr class="row-even"><td>8</td>
15660 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
15661 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15662 </tr>
15663 <tr class="row-odd"><td>9</td>
15664 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
15665 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15666 </tr>
15667 <tr class="row-even"><td>10</td>
15668 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
15669 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15670 </tr>
15671 <tr class="row-odd"><td>11</td>
15672 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
15673 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15674 </tr>
15675 <tr class="row-even"><td>12</td>
15676 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
15677 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15678 </tr>
15679 <tr class="row-odd"><td>13</td>
15680 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
15681 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15682 </tr>
15683 <tr class="row-even"><td>14</td>
15684 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
15685 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15686 </tr>
15687 <tr class="row-odd"><td>15</td>
15688 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2</td>
15689 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15690 </tr>
15691 <tr class="row-even"><td>16</td>
15692 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3</td>
15693 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15694 </tr>
15695 <tr class="row-odd"><td>17</td>
15696 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0</td>
15697 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15698 </tr>
15699 <tr class="row-even"><td>18</td>
15700 <td>DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0</td>
15701 <td>Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK</td>
15702 </tr>
15703 </tbody>
15704 </table>
15705 </div>
15706 <div class="section" id="clocks-for-timer15-device">
15707 <span id="soc-doc-j784s4-public-clks-timer15"></span><h3>Clocks for TIMER15 Device<a class="headerlink" href="#clocks-for-timer15-device" title="Permalink to this headline">¶</a></h3>
15708 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER15</span></a> (ID = 112)</p>
15709 <p>Following is a mapping of Clocks IDs to function:</p>
15710 <table border="1" class="docutils">
15711 <colgroup>
15712 <col width="9%" />
15713 <col width="50%" />
15714 <col width="42%" />
15715 </colgroup>
15716 <thead valign="bottom">
15717 <tr class="row-odd"><th class="head">Clock ID</th>
15718 <th class="head">Name</th>
15719 <th class="head">Function</th>
15720 </tr>
15721 </thead>
15722 <tbody valign="top">
15723 <tr class="row-even"><td>0</td>
15724 <td>DEV_TIMER15_TIMER_HCLK_CLK</td>
15725 <td>Input clock</td>
15726 </tr>
15727 <tr class="row-odd"><td>2</td>
15728 <td>DEV_TIMER15_TIMER_TCLK_CLK</td>
15729 <td>Input muxed clock</td>
15730 </tr>
15731 <tr class="row-even"><td>3</td>
15732 <td>DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15</td>
15733 <td>Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK</td>
15734 </tr>
15735 <tr class="row-odd"><td>4</td>
15736 <td>DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM</td>
15737 <td>Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK</td>
15738 </tr>
15739 </tbody>
15740 </table>
15741 </div>
15742 <div class="section" id="clocks-for-timer16-device">
15743 <span id="soc-doc-j784s4-public-clks-timer16"></span><h3>Clocks for TIMER16 Device<a class="headerlink" href="#clocks-for-timer16-device" title="Permalink to this headline">¶</a></h3>
15744 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER16</span></a> (ID = 113)</p>
15745 <p>Following is a mapping of Clocks IDs to function:</p>
15746 <table border="1" class="docutils">
15747 <colgroup>
15748 <col width="9%" />
15749 <col width="47%" />
15750 <col width="44%" />
15751 </colgroup>
15752 <thead valign="bottom">
15753 <tr class="row-odd"><th class="head">Clock ID</th>
15754 <th class="head">Name</th>
15755 <th class="head">Function</th>
15756 </tr>
15757 </thead>
15758 <tbody valign="top">
15759 <tr class="row-even"><td>0</td>
15760 <td>DEV_TIMER16_TIMER_HCLK_CLK</td>
15761 <td>Input clock</td>
15762 </tr>
15763 <tr class="row-odd"><td>1</td>
15764 <td>DEV_TIMER16_TIMER_PWM</td>
15765 <td>Output clock</td>
15766 </tr>
15767 <tr class="row-even"><td>2</td>
15768 <td>DEV_TIMER16_TIMER_TCLK_CLK</td>
15769 <td>Input muxed clock</td>
15770 </tr>
15771 <tr class="row-odd"><td>3</td>
15772 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT16</td>
15773 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
15774 </tr>
15775 <tr class="row-even"><td>4</td>
15776 <td>DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER16_AFS_SEL_OUT0</td>
15777 <td>Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK</td>
15778 </tr>
15779 </tbody>
15780 </table>
15781 </div>
15782 <div class="section" id="clocks-for-timer17-device">
15783 <span id="soc-doc-j784s4-public-clks-timer17"></span><h3>Clocks for TIMER17 Device<a class="headerlink" href="#clocks-for-timer17-device" title="Permalink to this headline">¶</a></h3>
15784 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER17</span></a> (ID = 114)</p>
15785 <p>Following is a mapping of Clocks IDs to function:</p>
15786 <table border="1" class="docutils">
15787 <colgroup>
15788 <col width="9%" />
15789 <col width="50%" />
15790 <col width="42%" />
15791 </colgroup>
15792 <thead valign="bottom">
15793 <tr class="row-odd"><th class="head">Clock ID</th>
15794 <th class="head">Name</th>
15795 <th class="head">Function</th>
15796 </tr>
15797 </thead>
15798 <tbody valign="top">
15799 <tr class="row-even"><td>0</td>
15800 <td>DEV_TIMER17_TIMER_HCLK_CLK</td>
15801 <td>Input clock</td>
15802 </tr>
15803 <tr class="row-odd"><td>2</td>
15804 <td>DEV_TIMER17_TIMER_TCLK_CLK</td>
15805 <td>Input muxed clock</td>
15806 </tr>
15807 <tr class="row-even"><td>3</td>
15808 <td>DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER17_AFS_EN_OUT0</td>
15809 <td>Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK</td>
15810 </tr>
15811 <tr class="row-odd"><td>4</td>
15812 <td>DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM</td>
15813 <td>Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK</td>
15814 </tr>
15815 </tbody>
15816 </table>
15817 </div>
15818 <div class="section" id="clocks-for-timer18-device">
15819 <span id="soc-doc-j784s4-public-clks-timer18"></span><h3>Clocks for TIMER18 Device<a class="headerlink" href="#clocks-for-timer18-device" title="Permalink to this headline">¶</a></h3>
15820 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER18</span></a> (ID = 115)</p>
15821 <p>Following is a mapping of Clocks IDs to function:</p>
15822 <table border="1" class="docutils">
15823 <colgroup>
15824 <col width="9%" />
15825 <col width="47%" />
15826 <col width="44%" />
15827 </colgroup>
15828 <thead valign="bottom">
15829 <tr class="row-odd"><th class="head">Clock ID</th>
15830 <th class="head">Name</th>
15831 <th class="head">Function</th>
15832 </tr>
15833 </thead>
15834 <tbody valign="top">
15835 <tr class="row-even"><td>0</td>
15836 <td>DEV_TIMER18_TIMER_HCLK_CLK</td>
15837 <td>Input clock</td>
15838 </tr>
15839 <tr class="row-odd"><td>1</td>
15840 <td>DEV_TIMER18_TIMER_PWM</td>
15841 <td>Output clock</td>
15842 </tr>
15843 <tr class="row-even"><td>2</td>
15844 <td>DEV_TIMER18_TIMER_TCLK_CLK</td>
15845 <td>Input muxed clock</td>
15846 </tr>
15847 <tr class="row-odd"><td>3</td>
15848 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT18</td>
15849 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
15850 </tr>
15851 <tr class="row-even"><td>4</td>
15852 <td>DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER18_AFS_SEL_OUT0</td>
15853 <td>Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK</td>
15854 </tr>
15855 </tbody>
15856 </table>
15857 </div>
15858 <div class="section" id="clocks-for-timer19-device">
15859 <span id="soc-doc-j784s4-public-clks-timer19"></span><h3>Clocks for TIMER19 Device<a class="headerlink" href="#clocks-for-timer19-device" title="Permalink to this headline">¶</a></h3>
15860 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER19</span></a> (ID = 116)</p>
15861 <p>Following is a mapping of Clocks IDs to function:</p>
15862 <table border="1" class="docutils">
15863 <colgroup>
15864 <col width="9%" />
15865 <col width="50%" />
15866 <col width="42%" />
15867 </colgroup>
15868 <thead valign="bottom">
15869 <tr class="row-odd"><th class="head">Clock ID</th>
15870 <th class="head">Name</th>
15871 <th class="head">Function</th>
15872 </tr>
15873 </thead>
15874 <tbody valign="top">
15875 <tr class="row-even"><td>0</td>
15876 <td>DEV_TIMER19_TIMER_HCLK_CLK</td>
15877 <td>Input clock</td>
15878 </tr>
15879 <tr class="row-odd"><td>2</td>
15880 <td>DEV_TIMER19_TIMER_TCLK_CLK</td>
15881 <td>Input muxed clock</td>
15882 </tr>
15883 <tr class="row-even"><td>3</td>
15884 <td>DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER19_AFS_EN_OUT0</td>
15885 <td>Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK</td>
15886 </tr>
15887 <tr class="row-odd"><td>4</td>
15888 <td>DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM</td>
15889 <td>Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK</td>
15890 </tr>
15891 </tbody>
15892 </table>
15893 </div>
15894 <div class="section" id="clocks-for-timer2-device">
15895 <span id="soc-doc-j784s4-public-clks-timer2"></span><h3>Clocks for TIMER2 Device<a class="headerlink" href="#clocks-for-timer2-device" title="Permalink to this headline">¶</a></h3>
15896 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER2</span></a> (ID = 99)</p>
15897 <p>Following is a mapping of Clocks IDs to function:</p>
15898 <table border="1" class="docutils">
15899 <colgroup>
15900 <col width="8%" />
15901 <col width="54%" />
15902 <col width="38%" />
15903 </colgroup>
15904 <thead valign="bottom">
15905 <tr class="row-odd"><th class="head">Clock ID</th>
15906 <th class="head">Name</th>
15907 <th class="head">Function</th>
15908 </tr>
15909 </thead>
15910 <tbody valign="top">
15911 <tr class="row-even"><td>0</td>
15912 <td>DEV_TIMER2_TIMER_HCLK_CLK</td>
15913 <td>Input clock</td>
15914 </tr>
15915 <tr class="row-odd"><td>1</td>
15916 <td>DEV_TIMER2_TIMER_PWM</td>
15917 <td>Output clock</td>
15918 </tr>
15919 <tr class="row-even"><td>2</td>
15920 <td>DEV_TIMER2_TIMER_TCLK_CLK</td>
15921 <td>Input muxed clock</td>
15922 </tr>
15923 <tr class="row-odd"><td>3</td>
15924 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
15925 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15926 </tr>
15927 <tr class="row-even"><td>4</td>
15928 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
15929 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15930 </tr>
15931 <tr class="row-odd"><td>5</td>
15932 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK</td>
15933 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15934 </tr>
15935 <tr class="row-even"><td>6</td>
15936 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
15937 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15938 </tr>
15939 <tr class="row-odd"><td>7</td>
15940 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
15941 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15942 </tr>
15943 <tr class="row-even"><td>8</td>
15944 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
15945 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15946 </tr>
15947 <tr class="row-odd"><td>9</td>
15948 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
15949 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15950 </tr>
15951 <tr class="row-even"><td>10</td>
15952 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
15953 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15954 </tr>
15955 <tr class="row-odd"><td>11</td>
15956 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
15957 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15958 </tr>
15959 <tr class="row-even"><td>12</td>
15960 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
15961 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15962 </tr>
15963 <tr class="row-odd"><td>13</td>
15964 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
15965 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15966 </tr>
15967 <tr class="row-even"><td>14</td>
15968 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
15969 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15970 </tr>
15971 <tr class="row-odd"><td>15</td>
15972 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2</td>
15973 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15974 </tr>
15975 <tr class="row-even"><td>16</td>
15976 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3</td>
15977 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15978 </tr>
15979 <tr class="row-odd"><td>17</td>
15980 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0</td>
15981 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15982 </tr>
15983 <tr class="row-even"><td>18</td>
15984 <td>DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0</td>
15985 <td>Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK</td>
15986 </tr>
15987 </tbody>
15988 </table>
15989 </div>
15990 <div class="section" id="clocks-for-timer3-device">
15991 <span id="soc-doc-j784s4-public-clks-timer3"></span><h3>Clocks for TIMER3 Device<a class="headerlink" href="#clocks-for-timer3-device" title="Permalink to this headline">¶</a></h3>
15992 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER3</span></a> (ID = 100)</p>
15993 <p>Following is a mapping of Clocks IDs to function:</p>
15994 <table border="1" class="docutils">
15995 <colgroup>
15996 <col width="9%" />
15997 <col width="49%" />
15998 <col width="42%" />
15999 </colgroup>
16000 <thead valign="bottom">
16001 <tr class="row-odd"><th class="head">Clock ID</th>
16002 <th class="head">Name</th>
16003 <th class="head">Function</th>
16004 </tr>
16005 </thead>
16006 <tbody valign="top">
16007 <tr class="row-even"><td>0</td>
16008 <td>DEV_TIMER3_TIMER_HCLK_CLK</td>
16009 <td>Input clock</td>
16010 </tr>
16011 <tr class="row-odd"><td>2</td>
16012 <td>DEV_TIMER3_TIMER_TCLK_CLK</td>
16013 <td>Input muxed clock</td>
16014 </tr>
16015 <tr class="row-even"><td>3</td>
16016 <td>DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3</td>
16017 <td>Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK</td>
16018 </tr>
16019 <tr class="row-odd"><td>4</td>
16020 <td>DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM</td>
16021 <td>Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK</td>
16022 </tr>
16023 </tbody>
16024 </table>
16025 </div>
16026 <div class="section" id="clocks-for-timer4-device">
16027 <span id="soc-doc-j784s4-public-clks-timer4"></span><h3>Clocks for TIMER4 Device<a class="headerlink" href="#clocks-for-timer4-device" title="Permalink to this headline">¶</a></h3>
16028 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER4</span></a> (ID = 101)</p>
16029 <p>Following is a mapping of Clocks IDs to function:</p>
16030 <table border="1" class="docutils">
16031 <colgroup>
16032 <col width="8%" />
16033 <col width="54%" />
16034 <col width="38%" />
16035 </colgroup>
16036 <thead valign="bottom">
16037 <tr class="row-odd"><th class="head">Clock ID</th>
16038 <th class="head">Name</th>
16039 <th class="head">Function</th>
16040 </tr>
16041 </thead>
16042 <tbody valign="top">
16043 <tr class="row-even"><td>0</td>
16044 <td>DEV_TIMER4_TIMER_HCLK_CLK</td>
16045 <td>Input clock</td>
16046 </tr>
16047 <tr class="row-odd"><td>1</td>
16048 <td>DEV_TIMER4_TIMER_PWM</td>
16049 <td>Output clock</td>
16050 </tr>
16051 <tr class="row-even"><td>2</td>
16052 <td>DEV_TIMER4_TIMER_TCLK_CLK</td>
16053 <td>Input muxed clock</td>
16054 </tr>
16055 <tr class="row-odd"><td>3</td>
16056 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16057 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16058 </tr>
16059 <tr class="row-even"><td>4</td>
16060 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16061 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16062 </tr>
16063 <tr class="row-odd"><td>5</td>
16064 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK</td>
16065 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16066 </tr>
16067 <tr class="row-even"><td>6</td>
16068 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
16069 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16070 </tr>
16071 <tr class="row-odd"><td>7</td>
16072 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
16073 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16074 </tr>
16075 <tr class="row-even"><td>8</td>
16076 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
16077 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16078 </tr>
16079 <tr class="row-odd"><td>9</td>
16080 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
16081 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16082 </tr>
16083 <tr class="row-even"><td>10</td>
16084 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
16085 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16086 </tr>
16087 <tr class="row-odd"><td>11</td>
16088 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
16089 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16090 </tr>
16091 <tr class="row-even"><td>12</td>
16092 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
16093 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16094 </tr>
16095 <tr class="row-odd"><td>13</td>
16096 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
16097 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16098 </tr>
16099 <tr class="row-even"><td>14</td>
16100 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
16101 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16102 </tr>
16103 <tr class="row-odd"><td>15</td>
16104 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2</td>
16105 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16106 </tr>
16107 <tr class="row-even"><td>16</td>
16108 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3</td>
16109 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16110 </tr>
16111 <tr class="row-odd"><td>17</td>
16112 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0</td>
16113 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16114 </tr>
16115 <tr class="row-even"><td>18</td>
16116 <td>DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0</td>
16117 <td>Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK</td>
16118 </tr>
16119 </tbody>
16120 </table>
16121 </div>
16122 <div class="section" id="clocks-for-timer5-device">
16123 <span id="soc-doc-j784s4-public-clks-timer5"></span><h3>Clocks for TIMER5 Device<a class="headerlink" href="#clocks-for-timer5-device" title="Permalink to this headline">¶</a></h3>
16124 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER5</span></a> (ID = 102)</p>
16125 <p>Following is a mapping of Clocks IDs to function:</p>
16126 <table border="1" class="docutils">
16127 <colgroup>
16128 <col width="9%" />
16129 <col width="49%" />
16130 <col width="42%" />
16131 </colgroup>
16132 <thead valign="bottom">
16133 <tr class="row-odd"><th class="head">Clock ID</th>
16134 <th class="head">Name</th>
16135 <th class="head">Function</th>
16136 </tr>
16137 </thead>
16138 <tbody valign="top">
16139 <tr class="row-even"><td>0</td>
16140 <td>DEV_TIMER5_TIMER_HCLK_CLK</td>
16141 <td>Input clock</td>
16142 </tr>
16143 <tr class="row-odd"><td>2</td>
16144 <td>DEV_TIMER5_TIMER_TCLK_CLK</td>
16145 <td>Input muxed clock</td>
16146 </tr>
16147 <tr class="row-even"><td>3</td>
16148 <td>DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5</td>
16149 <td>Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK</td>
16150 </tr>
16151 <tr class="row-odd"><td>4</td>
16152 <td>DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM</td>
16153 <td>Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK</td>
16154 </tr>
16155 </tbody>
16156 </table>
16157 </div>
16158 <div class="section" id="clocks-for-timer6-device">
16159 <span id="soc-doc-j784s4-public-clks-timer6"></span><h3>Clocks for TIMER6 Device<a class="headerlink" href="#clocks-for-timer6-device" title="Permalink to this headline">¶</a></h3>
16160 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER6</span></a> (ID = 103)</p>
16161 <p>Following is a mapping of Clocks IDs to function:</p>
16162 <table border="1" class="docutils">
16163 <colgroup>
16164 <col width="8%" />
16165 <col width="54%" />
16166 <col width="38%" />
16167 </colgroup>
16168 <thead valign="bottom">
16169 <tr class="row-odd"><th class="head">Clock ID</th>
16170 <th class="head">Name</th>
16171 <th class="head">Function</th>
16172 </tr>
16173 </thead>
16174 <tbody valign="top">
16175 <tr class="row-even"><td>0</td>
16176 <td>DEV_TIMER6_TIMER_HCLK_CLK</td>
16177 <td>Input clock</td>
16178 </tr>
16179 <tr class="row-odd"><td>1</td>
16180 <td>DEV_TIMER6_TIMER_PWM</td>
16181 <td>Output clock</td>
16182 </tr>
16183 <tr class="row-even"><td>2</td>
16184 <td>DEV_TIMER6_TIMER_TCLK_CLK</td>
16185 <td>Input muxed clock</td>
16186 </tr>
16187 <tr class="row-odd"><td>3</td>
16188 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16189 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16190 </tr>
16191 <tr class="row-even"><td>4</td>
16192 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16193 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16194 </tr>
16195 <tr class="row-odd"><td>5</td>
16196 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK</td>
16197 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16198 </tr>
16199 <tr class="row-even"><td>6</td>
16200 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
16201 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16202 </tr>
16203 <tr class="row-odd"><td>7</td>
16204 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
16205 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16206 </tr>
16207 <tr class="row-even"><td>8</td>
16208 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
16209 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16210 </tr>
16211 <tr class="row-odd"><td>9</td>
16212 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
16213 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16214 </tr>
16215 <tr class="row-even"><td>10</td>
16216 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
16217 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16218 </tr>
16219 <tr class="row-odd"><td>11</td>
16220 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
16221 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16222 </tr>
16223 <tr class="row-even"><td>12</td>
16224 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
16225 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16226 </tr>
16227 <tr class="row-odd"><td>13</td>
16228 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
16229 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16230 </tr>
16231 <tr class="row-even"><td>14</td>
16232 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
16233 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16234 </tr>
16235 <tr class="row-odd"><td>15</td>
16236 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2</td>
16237 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16238 </tr>
16239 <tr class="row-even"><td>16</td>
16240 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3</td>
16241 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16242 </tr>
16243 <tr class="row-odd"><td>17</td>
16244 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0</td>
16245 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16246 </tr>
16247 <tr class="row-even"><td>18</td>
16248 <td>DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0</td>
16249 <td>Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK</td>
16250 </tr>
16251 </tbody>
16252 </table>
16253 </div>
16254 <div class="section" id="clocks-for-timer7-device">
16255 <span id="soc-doc-j784s4-public-clks-timer7"></span><h3>Clocks for TIMER7 Device<a class="headerlink" href="#clocks-for-timer7-device" title="Permalink to this headline">¶</a></h3>
16256 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER7</span></a> (ID = 104)</p>
16257 <p>Following is a mapping of Clocks IDs to function:</p>
16258 <table border="1" class="docutils">
16259 <colgroup>
16260 <col width="9%" />
16261 <col width="49%" />
16262 <col width="42%" />
16263 </colgroup>
16264 <thead valign="bottom">
16265 <tr class="row-odd"><th class="head">Clock ID</th>
16266 <th class="head">Name</th>
16267 <th class="head">Function</th>
16268 </tr>
16269 </thead>
16270 <tbody valign="top">
16271 <tr class="row-even"><td>0</td>
16272 <td>DEV_TIMER7_TIMER_HCLK_CLK</td>
16273 <td>Input clock</td>
16274 </tr>
16275 <tr class="row-odd"><td>2</td>
16276 <td>DEV_TIMER7_TIMER_TCLK_CLK</td>
16277 <td>Input muxed clock</td>
16278 </tr>
16279 <tr class="row-even"><td>3</td>
16280 <td>DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7</td>
16281 <td>Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK</td>
16282 </tr>
16283 <tr class="row-odd"><td>4</td>
16284 <td>DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM</td>
16285 <td>Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK</td>
16286 </tr>
16287 </tbody>
16288 </table>
16289 </div>
16290 <div class="section" id="clocks-for-timer8-device">
16291 <span id="soc-doc-j784s4-public-clks-timer8"></span><h3>Clocks for TIMER8 Device<a class="headerlink" href="#clocks-for-timer8-device" title="Permalink to this headline">¶</a></h3>
16292 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER8</span></a> (ID = 105)</p>
16293 <p>Following is a mapping of Clocks IDs to function:</p>
16294 <table border="1" class="docutils">
16295 <colgroup>
16296 <col width="8%" />
16297 <col width="54%" />
16298 <col width="38%" />
16299 </colgroup>
16300 <thead valign="bottom">
16301 <tr class="row-odd"><th class="head">Clock ID</th>
16302 <th class="head">Name</th>
16303 <th class="head">Function</th>
16304 </tr>
16305 </thead>
16306 <tbody valign="top">
16307 <tr class="row-even"><td>0</td>
16308 <td>DEV_TIMER8_TIMER_HCLK_CLK</td>
16309 <td>Input clock</td>
16310 </tr>
16311 <tr class="row-odd"><td>1</td>
16312 <td>DEV_TIMER8_TIMER_PWM</td>
16313 <td>Output clock</td>
16314 </tr>
16315 <tr class="row-even"><td>2</td>
16316 <td>DEV_TIMER8_TIMER_TCLK_CLK</td>
16317 <td>Input muxed clock</td>
16318 </tr>
16319 <tr class="row-odd"><td>3</td>
16320 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16321 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16322 </tr>
16323 <tr class="row-even"><td>4</td>
16324 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16325 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16326 </tr>
16327 <tr class="row-odd"><td>5</td>
16328 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK</td>
16329 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16330 </tr>
16331 <tr class="row-even"><td>6</td>
16332 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK</td>
16333 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16334 </tr>
16335 <tr class="row-odd"><td>7</td>
16336 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK</td>
16337 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16338 </tr>
16339 <tr class="row-even"><td>8</td>
16340 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT</td>
16341 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16342 </tr>
16343 <tr class="row-odd"><td>9</td>
16344 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
16345 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16346 </tr>
16347 <tr class="row-even"><td>10</td>
16348 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT</td>
16349 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16350 </tr>
16351 <tr class="row-odd"><td>11</td>
16352 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT</td>
16353 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16354 </tr>
16355 <tr class="row-even"><td>12</td>
16356 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK</td>
16357 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16358 </tr>
16359 <tr class="row-odd"><td>13</td>
16360 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK</td>
16361 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16362 </tr>
16363 <tr class="row-even"><td>14</td>
16364 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK</td>
16365 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16366 </tr>
16367 <tr class="row-odd"><td>15</td>
16368 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2</td>
16369 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16370 </tr>
16371 <tr class="row-even"><td>16</td>
16372 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3</td>
16373 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16374 </tr>
16375 <tr class="row-odd"><td>17</td>
16376 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0</td>
16377 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16378 </tr>
16379 <tr class="row-even"><td>18</td>
16380 <td>DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_J7AM_MAIN_0_CPTS_GENF0</td>
16381 <td>Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK</td>
16382 </tr>
16383 </tbody>
16384 </table>
16385 </div>
16386 <div class="section" id="clocks-for-timer9-device">
16387 <span id="soc-doc-j784s4-public-clks-timer9"></span><h3>Clocks for TIMER9 Device<a class="headerlink" href="#clocks-for-timer9-device" title="Permalink to this headline">¶</a></h3>
16388 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMER9</span></a> (ID = 106)</p>
16389 <p>Following is a mapping of Clocks IDs to function:</p>
16390 <table border="1" class="docutils">
16391 <colgroup>
16392 <col width="9%" />
16393 <col width="49%" />
16394 <col width="42%" />
16395 </colgroup>
16396 <thead valign="bottom">
16397 <tr class="row-odd"><th class="head">Clock ID</th>
16398 <th class="head">Name</th>
16399 <th class="head">Function</th>
16400 </tr>
16401 </thead>
16402 <tbody valign="top">
16403 <tr class="row-even"><td>0</td>
16404 <td>DEV_TIMER9_TIMER_HCLK_CLK</td>
16405 <td>Input clock</td>
16406 </tr>
16407 <tr class="row-odd"><td>2</td>
16408 <td>DEV_TIMER9_TIMER_TCLK_CLK</td>
16409 <td>Input muxed clock</td>
16410 </tr>
16411 <tr class="row-even"><td>3</td>
16412 <td>DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9</td>
16413 <td>Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK</td>
16414 </tr>
16415 <tr class="row-odd"><td>4</td>
16416 <td>DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM</td>
16417 <td>Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK</td>
16418 </tr>
16419 </tbody>
16420 </table>
16421 </div>
16422 <div class="section" id="clocks-for-timesync-intrtr0-device">
16423 <span id="soc-doc-j784s4-public-clks-timesync-intrtr0"></span><h3>Clocks for TIMESYNC_INTRTR0 Device<a class="headerlink" href="#clocks-for-timesync-intrtr0-device" title="Permalink to this headline">¶</a></h3>
16424 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_TIMESYNC_INTRTR0</span></a> (ID = 176)</p>
16425 <p>Following is a mapping of Clocks IDs to function:</p>
16426 <table border="1" class="docutils">
16427 <colgroup>
16428 <col width="21%" />
16429 <col width="55%" />
16430 <col width="23%" />
16431 </colgroup>
16432 <thead valign="bottom">
16433 <tr class="row-odd"><th class="head">Clock ID</th>
16434 <th class="head">Name</th>
16435 <th class="head">Function</th>
16436 </tr>
16437 </thead>
16438 <tbody valign="top">
16439 <tr class="row-even"><td>0</td>
16440 <td>DEV_TIMESYNC_INTRTR0_INTR_CLK</td>
16441 <td>Input clock</td>
16442 </tr>
16443 </tbody>
16444 </table>
16445 </div>
16446 <div class="section" id="clocks-for-uart0-device">
16447 <span id="soc-doc-j784s4-public-clks-uart0"></span><h3>Clocks for UART0 Device<a class="headerlink" href="#clocks-for-uart0-device" title="Permalink to this headline">¶</a></h3>
16448 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_UART0</span></a> (ID = 146)</p>
16449 <p>Following is a mapping of Clocks IDs to function:</p>
16450 <table border="1" class="docutils">
16451 <colgroup>
16452 <col width="26%" />
16453 <col width="46%" />
16454 <col width="28%" />
16455 </colgroup>
16456 <thead valign="bottom">
16457 <tr class="row-odd"><th class="head">Clock ID</th>
16458 <th class="head">Name</th>
16459 <th class="head">Function</th>
16460 </tr>
16461 </thead>
16462 <tbody valign="top">
16463 <tr class="row-even"><td>0</td>
16464 <td>DEV_UART0_FCLK_CLK</td>
16465 <td>Input clock</td>
16466 </tr>
16467 <tr class="row-odd"><td>3</td>
16468 <td>DEV_UART0_VBUSP_CLK</td>
16469 <td>Input clock</td>
16470 </tr>
16471 </tbody>
16472 </table>
16473 </div>
16474 <div class="section" id="clocks-for-uart1-device">
16475 <span id="soc-doc-j784s4-public-clks-uart1"></span><h3>Clocks for UART1 Device<a class="headerlink" href="#clocks-for-uart1-device" title="Permalink to this headline">¶</a></h3>
16476 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_UART1</span></a> (ID = 388)</p>
16477 <p>Following is a mapping of Clocks IDs to function:</p>
16478 <table border="1" class="docutils">
16479 <colgroup>
16480 <col width="26%" />
16481 <col width="46%" />
16482 <col width="28%" />
16483 </colgroup>
16484 <thead valign="bottom">
16485 <tr class="row-odd"><th class="head">Clock ID</th>
16486 <th class="head">Name</th>
16487 <th class="head">Function</th>
16488 </tr>
16489 </thead>
16490 <tbody valign="top">
16491 <tr class="row-even"><td>0</td>
16492 <td>DEV_UART1_FCLK_CLK</td>
16493 <td>Input clock</td>
16494 </tr>
16495 <tr class="row-odd"><td>3</td>
16496 <td>DEV_UART1_VBUSP_CLK</td>
16497 <td>Input clock</td>
16498 </tr>
16499 </tbody>
16500 </table>
16501 </div>
16502 <div class="section" id="clocks-for-uart2-device">
16503 <span id="soc-doc-j784s4-public-clks-uart2"></span><h3>Clocks for UART2 Device<a class="headerlink" href="#clocks-for-uart2-device" title="Permalink to this headline">¶</a></h3>
16504 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_UART2</span></a> (ID = 389)</p>
16505 <p>Following is a mapping of Clocks IDs to function:</p>
16506 <table border="1" class="docutils">
16507 <colgroup>
16508 <col width="26%" />
16509 <col width="46%" />
16510 <col width="28%" />
16511 </colgroup>
16512 <thead valign="bottom">
16513 <tr class="row-odd"><th class="head">Clock ID</th>
16514 <th class="head">Name</th>
16515 <th class="head">Function</th>
16516 </tr>
16517 </thead>
16518 <tbody valign="top">
16519 <tr class="row-even"><td>0</td>
16520 <td>DEV_UART2_FCLK_CLK</td>
16521 <td>Input clock</td>
16522 </tr>
16523 <tr class="row-odd"><td>3</td>
16524 <td>DEV_UART2_VBUSP_CLK</td>
16525 <td>Input clock</td>
16526 </tr>
16527 </tbody>
16528 </table>
16529 </div>
16530 <div class="section" id="clocks-for-uart3-device">
16531 <span id="soc-doc-j784s4-public-clks-uart3"></span><h3>Clocks for UART3 Device<a class="headerlink" href="#clocks-for-uart3-device" title="Permalink to this headline">¶</a></h3>
16532 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_UART3</span></a> (ID = 390)</p>
16533 <p>Following is a mapping of Clocks IDs to function:</p>
16534 <table border="1" class="docutils">
16535 <colgroup>
16536 <col width="26%" />
16537 <col width="46%" />
16538 <col width="28%" />
16539 </colgroup>
16540 <thead valign="bottom">
16541 <tr class="row-odd"><th class="head">Clock ID</th>
16542 <th class="head">Name</th>
16543 <th class="head">Function</th>
16544 </tr>
16545 </thead>
16546 <tbody valign="top">
16547 <tr class="row-even"><td>0</td>
16548 <td>DEV_UART3_FCLK_CLK</td>
16549 <td>Input clock</td>
16550 </tr>
16551 <tr class="row-odd"><td>3</td>
16552 <td>DEV_UART3_VBUSP_CLK</td>
16553 <td>Input clock</td>
16554 </tr>
16555 </tbody>
16556 </table>
16557 </div>
16558 <div class="section" id="clocks-for-uart4-device">
16559 <span id="soc-doc-j784s4-public-clks-uart4"></span><h3>Clocks for UART4 Device<a class="headerlink" href="#clocks-for-uart4-device" title="Permalink to this headline">¶</a></h3>
16560 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_UART4</span></a> (ID = 391)</p>
16561 <p>Following is a mapping of Clocks IDs to function:</p>
16562 <table border="1" class="docutils">
16563 <colgroup>
16564 <col width="26%" />
16565 <col width="46%" />
16566 <col width="28%" />
16567 </colgroup>
16568 <thead valign="bottom">
16569 <tr class="row-odd"><th class="head">Clock ID</th>
16570 <th class="head">Name</th>
16571 <th class="head">Function</th>
16572 </tr>
16573 </thead>
16574 <tbody valign="top">
16575 <tr class="row-even"><td>0</td>
16576 <td>DEV_UART4_FCLK_CLK</td>
16577 <td>Input clock</td>
16578 </tr>
16579 <tr class="row-odd"><td>3</td>
16580 <td>DEV_UART4_VBUSP_CLK</td>
16581 <td>Input clock</td>
16582 </tr>
16583 </tbody>
16584 </table>
16585 </div>
16586 <div class="section" id="clocks-for-uart5-device">
16587 <span id="soc-doc-j784s4-public-clks-uart5"></span><h3>Clocks for UART5 Device<a class="headerlink" href="#clocks-for-uart5-device" title="Permalink to this headline">¶</a></h3>
16588 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_UART5</span></a> (ID = 392)</p>
16589 <p>Following is a mapping of Clocks IDs to function:</p>
16590 <table border="1" class="docutils">
16591 <colgroup>
16592 <col width="26%" />
16593 <col width="46%" />
16594 <col width="28%" />
16595 </colgroup>
16596 <thead valign="bottom">
16597 <tr class="row-odd"><th class="head">Clock ID</th>
16598 <th class="head">Name</th>
16599 <th class="head">Function</th>
16600 </tr>
16601 </thead>
16602 <tbody valign="top">
16603 <tr class="row-even"><td>0</td>
16604 <td>DEV_UART5_FCLK_CLK</td>
16605 <td>Input clock</td>
16606 </tr>
16607 <tr class="row-odd"><td>3</td>
16608 <td>DEV_UART5_VBUSP_CLK</td>
16609 <td>Input clock</td>
16610 </tr>
16611 </tbody>
16612 </table>
16613 </div>
16614 <div class="section" id="clocks-for-uart6-device">
16615 <span id="soc-doc-j784s4-public-clks-uart6"></span><h3>Clocks for UART6 Device<a class="headerlink" href="#clocks-for-uart6-device" title="Permalink to this headline">¶</a></h3>
16616 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_UART6</span></a> (ID = 393)</p>
16617 <p>Following is a mapping of Clocks IDs to function:</p>
16618 <table border="1" class="docutils">
16619 <colgroup>
16620 <col width="26%" />
16621 <col width="46%" />
16622 <col width="28%" />
16623 </colgroup>
16624 <thead valign="bottom">
16625 <tr class="row-odd"><th class="head">Clock ID</th>
16626 <th class="head">Name</th>
16627 <th class="head">Function</th>
16628 </tr>
16629 </thead>
16630 <tbody valign="top">
16631 <tr class="row-even"><td>0</td>
16632 <td>DEV_UART6_FCLK_CLK</td>
16633 <td>Input clock</td>
16634 </tr>
16635 <tr class="row-odd"><td>3</td>
16636 <td>DEV_UART6_VBUSP_CLK</td>
16637 <td>Input clock</td>
16638 </tr>
16639 </tbody>
16640 </table>
16641 </div>
16642 <div class="section" id="clocks-for-uart7-device">
16643 <span id="soc-doc-j784s4-public-clks-uart7"></span><h3>Clocks for UART7 Device<a class="headerlink" href="#clocks-for-uart7-device" title="Permalink to this headline">¶</a></h3>
16644 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_UART7</span></a> (ID = 394)</p>
16645 <p>Following is a mapping of Clocks IDs to function:</p>
16646 <table border="1" class="docutils">
16647 <colgroup>
16648 <col width="26%" />
16649 <col width="46%" />
16650 <col width="28%" />
16651 </colgroup>
16652 <thead valign="bottom">
16653 <tr class="row-odd"><th class="head">Clock ID</th>
16654 <th class="head">Name</th>
16655 <th class="head">Function</th>
16656 </tr>
16657 </thead>
16658 <tbody valign="top">
16659 <tr class="row-even"><td>0</td>
16660 <td>DEV_UART7_FCLK_CLK</td>
16661 <td>Input clock</td>
16662 </tr>
16663 <tr class="row-odd"><td>3</td>
16664 <td>DEV_UART7_VBUSP_CLK</td>
16665 <td>Input clock</td>
16666 </tr>
16667 </tbody>
16668 </table>
16669 </div>
16670 <div class="section" id="clocks-for-uart8-device">
16671 <span id="soc-doc-j784s4-public-clks-uart8"></span><h3>Clocks for UART8 Device<a class="headerlink" href="#clocks-for-uart8-device" title="Permalink to this headline">¶</a></h3>
16672 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_UART8</span></a> (ID = 395)</p>
16673 <p>Following is a mapping of Clocks IDs to function:</p>
16674 <table border="1" class="docutils">
16675 <colgroup>
16676 <col width="26%" />
16677 <col width="46%" />
16678 <col width="28%" />
16679 </colgroup>
16680 <thead valign="bottom">
16681 <tr class="row-odd"><th class="head">Clock ID</th>
16682 <th class="head">Name</th>
16683 <th class="head">Function</th>
16684 </tr>
16685 </thead>
16686 <tbody valign="top">
16687 <tr class="row-even"><td>0</td>
16688 <td>DEV_UART8_FCLK_CLK</td>
16689 <td>Input clock</td>
16690 </tr>
16691 <tr class="row-odd"><td>3</td>
16692 <td>DEV_UART8_VBUSP_CLK</td>
16693 <td>Input clock</td>
16694 </tr>
16695 </tbody>
16696 </table>
16697 </div>
16698 <div class="section" id="clocks-for-uart9-device">
16699 <span id="soc-doc-j784s4-public-clks-uart9"></span><h3>Clocks for UART9 Device<a class="headerlink" href="#clocks-for-uart9-device" title="Permalink to this headline">¶</a></h3>
16700 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_UART9</span></a> (ID = 396)</p>
16701 <p>Following is a mapping of Clocks IDs to function:</p>
16702 <table border="1" class="docutils">
16703 <colgroup>
16704 <col width="26%" />
16705 <col width="46%" />
16706 <col width="28%" />
16707 </colgroup>
16708 <thead valign="bottom">
16709 <tr class="row-odd"><th class="head">Clock ID</th>
16710 <th class="head">Name</th>
16711 <th class="head">Function</th>
16712 </tr>
16713 </thead>
16714 <tbody valign="top">
16715 <tr class="row-even"><td>0</td>
16716 <td>DEV_UART9_FCLK_CLK</td>
16717 <td>Input clock</td>
16718 </tr>
16719 <tr class="row-odd"><td>3</td>
16720 <td>DEV_UART9_VBUSP_CLK</td>
16721 <td>Input clock</td>
16722 </tr>
16723 </tbody>
16724 </table>
16725 </div>
16726 <div class="section" id="clocks-for-ufs0-device">
16727 <span id="soc-doc-j784s4-public-clks-ufs0"></span><h3>Clocks for UFS0 Device<a class="headerlink" href="#clocks-for-ufs0-device" title="Permalink to this headline">¶</a></h3>
16728 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_UFS0</span></a> (ID = 387)</p>
16729 <p>Following is a mapping of Clocks IDs to function:</p>
16730 <table border="1" class="docutils">
16731 <colgroup>
16732 <col width="9%" />
16733 <col width="51%" />
16734 <col width="40%" />
16735 </colgroup>
16736 <thead valign="bottom">
16737 <tr class="row-odd"><th class="head">Clock ID</th>
16738 <th class="head">Name</th>
16739 <th class="head">Function</th>
16740 </tr>
16741 </thead>
16742 <tbody valign="top">
16743 <tr class="row-even"><td>1</td>
16744 <td>DEV_UFS0_UFSHCI_HCLK_CLK</td>
16745 <td>Input clock</td>
16746 </tr>
16747 <tr class="row-odd"><td>3</td>
16748 <td>DEV_UFS0_UFSHCI_MCLK_CLK</td>
16749 <td>Input muxed clock</td>
16750 </tr>
16751 <tr class="row-even"><td>4</td>
16752 <td>DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16753 <td>Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK</td>
16754 </tr>
16755 <tr class="row-odd"><td>5</td>
16756 <td>DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16757 <td>Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK</td>
16758 </tr>
16759 <tr class="row-even"><td>6</td>
16760 <td>DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK</td>
16761 <td>Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK</td>
16762 </tr>
16763 <tr class="row-odd"><td>7</td>
16764 <td>DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT</td>
16765 <td>Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK</td>
16766 </tr>
16767 <tr class="row-even"><td>8</td>
16768 <td>DEV_UFS0_UFSHCI_MPHY_REFCLK</td>
16769 <td>Output clock</td>
16770 </tr>
16771 <tr class="row-odd"><td>23</td>
16772 <td>DEV_UFS0_UFSHCI_MPHY_TX_REF_SYMBOLCLK</td>
16773 <td>Output clock</td>
16774 </tr>
16775 <tr class="row-even"><td>24</td>
16776 <td>DEV_UFS0_UFSHCI_MPHY_M31_VCO_19P2M_CLK</td>
16777 <td>Output clock</td>
16778 </tr>
16779 <tr class="row-odd"><td>25</td>
16780 <td>DEV_UFS0_UFSHCI_MPHY_M31_VCO_26M_CLK</td>
16781 <td>Output clock</td>
16782 </tr>
16783 </tbody>
16784 </table>
16785 </div>
16786 <div class="section" id="clocks-for-usb0-device">
16787 <span id="soc-doc-j784s4-public-clks-usb0"></span><h3>Clocks for USB0 Device<a class="headerlink" href="#clocks-for-usb0-device" title="Permalink to this headline">¶</a></h3>
16788 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_USB0</span></a> (ID = 398)</p>
16789 <p>Following is a mapping of Clocks IDs to function:</p>
16790 <table border="1" class="docutils">
16791 <colgroup>
16792 <col width="9%" />
16793 <col width="48%" />
16794 <col width="43%" />
16795 </colgroup>
16796 <thead valign="bottom">
16797 <tr class="row-odd"><th class="head">Clock ID</th>
16798 <th class="head">Name</th>
16799 <th class="head">Function</th>
16800 </tr>
16801 </thead>
16802 <tbody valign="top">
16803 <tr class="row-even"><td>0</td>
16804 <td>DEV_USB0_ACLK_CLK</td>
16805 <td>Input clock</td>
16806 </tr>
16807 <tr class="row-odd"><td>1</td>
16808 <td>DEV_USB0_BUF_CLK</td>
16809 <td>Input clock</td>
16810 </tr>
16811 <tr class="row-even"><td>2</td>
16812 <td>DEV_USB0_CLK_LPM_CLK</td>
16813 <td>Input clock</td>
16814 </tr>
16815 <tr class="row-odd"><td>3</td>
16816 <td>DEV_USB0_PCLK_CLK</td>
16817 <td>Input clock</td>
16818 </tr>
16819 <tr class="row-even"><td>4</td>
16820 <td>DEV_USB0_PIPE_REFCLK</td>
16821 <td>Input muxed clock</td>
16822 </tr>
16823 <tr class="row-odd"><td>5</td>
16824 <td>DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_REFCLK</td>
16825 <td>Parent input clock option to DEV_USB0_PIPE_REFCLK</td>
16826 </tr>
16827 <tr class="row-even"><td>6</td>
16828 <td>DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_REFCLK</td>
16829 <td>Parent input clock option to DEV_USB0_PIPE_REFCLK</td>
16830 </tr>
16831 <tr class="row-odd"><td>7</td>
16832 <td>DEV_USB0_PIPE_RXCLK</td>
16833 <td>Input muxed clock</td>
16834 </tr>
16835 <tr class="row-even"><td>8</td>
16836 <td>DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_RXCLK</td>
16837 <td>Parent input clock option to DEV_USB0_PIPE_RXCLK</td>
16838 </tr>
16839 <tr class="row-odd"><td>9</td>
16840 <td>DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_RXCLK</td>
16841 <td>Parent input clock option to DEV_USB0_PIPE_RXCLK</td>
16842 </tr>
16843 <tr class="row-even"><td>10</td>
16844 <td>DEV_USB0_PIPE_RXFCLK</td>
16845 <td>Input muxed clock</td>
16846 </tr>
16847 <tr class="row-odd"><td>11</td>
16848 <td>DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_RXFCLK</td>
16849 <td>Parent input clock option to DEV_USB0_PIPE_RXFCLK</td>
16850 </tr>
16851 <tr class="row-even"><td>12</td>
16852 <td>DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_RXFCLK</td>
16853 <td>Parent input clock option to DEV_USB0_PIPE_RXFCLK</td>
16854 </tr>
16855 <tr class="row-odd"><td>13</td>
16856 <td>DEV_USB0_PIPE_TXCLK</td>
16857 <td>Output clock</td>
16858 </tr>
16859 <tr class="row-even"><td>14</td>
16860 <td>DEV_USB0_PIPE_TXFCLK</td>
16861 <td>Input muxed clock</td>
16862 </tr>
16863 <tr class="row-odd"><td>15</td>
16864 <td>DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_TXFCLK</td>
16865 <td>Parent input clock option to DEV_USB0_PIPE_TXFCLK</td>
16866 </tr>
16867 <tr class="row-even"><td>16</td>
16868 <td>DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_TXFCLK</td>
16869 <td>Parent input clock option to DEV_USB0_PIPE_TXFCLK</td>
16870 </tr>
16871 <tr class="row-odd"><td>17</td>
16872 <td>DEV_USB0_PIPE_TXMCLK</td>
16873 <td>Input muxed clock</td>
16874 </tr>
16875 <tr class="row-even"><td>18</td>
16876 <td>DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT3_MAIN_0_IP3_LN3_TXMCLK</td>
16877 <td>Parent input clock option to DEV_USB0_PIPE_TXMCLK</td>
16878 </tr>
16879 <tr class="row-odd"><td>19</td>
16880 <td>DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT3_MAIN_4_IP3_LN3_TXMCLK</td>
16881 <td>Parent input clock option to DEV_USB0_PIPE_TXMCLK</td>
16882 </tr>
16883 <tr class="row-even"><td>20</td>
16884 <td>DEV_USB0_USB2_APB_PCLK_CLK</td>
16885 <td>Input clock</td>
16886 </tr>
16887 <tr class="row-odd"><td>21</td>
16888 <td>DEV_USB0_USB2_REFCLOCK_CLK</td>
16889 <td>Input muxed clock</td>
16890 </tr>
16891 <tr class="row-even"><td>22</td>
16892 <td>DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
16893 <td>Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK</td>
16894 </tr>
16895 <tr class="row-odd"><td>23</td>
16896 <td>DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT</td>
16897 <td>Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK</td>
16898 </tr>
16899 <tr class="row-even"><td>28</td>
16900 <td>DEV_USB0_USB2_TAP_TCK</td>
16901 <td>Input clock</td>
16902 </tr>
16903 </tbody>
16904 </table>
16905 </div>
16906 <div class="section" id="clocks-for-vpac0-device">
16907 <span id="soc-doc-j784s4-public-clks-vpac0"></span><h3>Clocks for VPAC0 Device<a class="headerlink" href="#clocks-for-vpac0-device" title="Permalink to this headline">¶</a></h3>
16908 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_VPAC0</span></a> (ID = 399)</p>
16909 <p>Following is a mapping of Clocks IDs to function:</p>
16910 <table border="1" class="docutils">
16911 <colgroup>
16912 <col width="10%" />
16913 <col width="50%" />
16914 <col width="40%" />
16915 </colgroup>
16916 <thead valign="bottom">
16917 <tr class="row-odd"><th class="head">Clock ID</th>
16918 <th class="head">Name</th>
16919 <th class="head">Function</th>
16920 </tr>
16921 </thead>
16922 <tbody valign="top">
16923 <tr class="row-even"><td>0</td>
16924 <td>DEV_VPAC0_LDC0_CLK_CLK</td>
16925 <td>Input clock</td>
16926 </tr>
16927 <tr class="row-odd"><td>1</td>
16928 <td>DEV_VPAC0_MAIN_CLK</td>
16929 <td>Input muxed clock</td>
16930 </tr>
16931 <tr class="row-even"><td>2</td>
16932 <td>DEV_VPAC0_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK</td>
16933 <td>Parent input clock option to DEV_VPAC0_MAIN_CLK</td>
16934 </tr>
16935 <tr class="row-odd"><td>3</td>
16936 <td>DEV_VPAC0_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK</td>
16937 <td>Parent input clock option to DEV_VPAC0_MAIN_CLK</td>
16938 </tr>
16939 <tr class="row-even"><td>4</td>
16940 <td>DEV_VPAC0_MSC_CLK</td>
16941 <td>Input clock</td>
16942 </tr>
16943 <tr class="row-odd"><td>5</td>
16944 <td>DEV_VPAC0_NF_CLK_CLK</td>
16945 <td>Input clock</td>
16946 </tr>
16947 <tr class="row-even"><td>6</td>
16948 <td>DEV_VPAC0_PSIL_LEAF_CLK</td>
16949 <td>Input clock</td>
16950 </tr>
16951 <tr class="row-odd"><td>7</td>
16952 <td>DEV_VPAC0_VISS0_CLK_CLK</td>
16953 <td>Input clock</td>
16954 </tr>
16955 </tbody>
16956 </table>
16957 </div>
16958 <div class="section" id="clocks-for-vpac1-device">
16959 <span id="soc-doc-j784s4-public-clks-vpac1"></span><h3>Clocks for VPAC1 Device<a class="headerlink" href="#clocks-for-vpac1-device" title="Permalink to this headline">¶</a></h3>
16960 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_VPAC1</span></a> (ID = 400)</p>
16961 <p>Following is a mapping of Clocks IDs to function:</p>
16962 <table border="1" class="docutils">
16963 <colgroup>
16964 <col width="10%" />
16965 <col width="50%" />
16966 <col width="40%" />
16967 </colgroup>
16968 <thead valign="bottom">
16969 <tr class="row-odd"><th class="head">Clock ID</th>
16970 <th class="head">Name</th>
16971 <th class="head">Function</th>
16972 </tr>
16973 </thead>
16974 <tbody valign="top">
16975 <tr class="row-even"><td>0</td>
16976 <td>DEV_VPAC1_LDC0_CLK_CLK</td>
16977 <td>Input clock</td>
16978 </tr>
16979 <tr class="row-odd"><td>1</td>
16980 <td>DEV_VPAC1_MAIN_CLK</td>
16981 <td>Input muxed clock</td>
16982 </tr>
16983 <tr class="row-even"><td>2</td>
16984 <td>DEV_VPAC1_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK</td>
16985 <td>Parent input clock option to DEV_VPAC1_MAIN_CLK</td>
16986 </tr>
16987 <tr class="row-odd"><td>3</td>
16988 <td>DEV_VPAC1_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK</td>
16989 <td>Parent input clock option to DEV_VPAC1_MAIN_CLK</td>
16990 </tr>
16991 <tr class="row-even"><td>4</td>
16992 <td>DEV_VPAC1_MSC_CLK</td>
16993 <td>Input clock</td>
16994 </tr>
16995 <tr class="row-odd"><td>5</td>
16996 <td>DEV_VPAC1_NF_CLK_CLK</td>
16997 <td>Input clock</td>
16998 </tr>
16999 <tr class="row-even"><td>6</td>
17000 <td>DEV_VPAC1_PSIL_LEAF_CLK</td>
17001 <td>Input clock</td>
17002 </tr>
17003 <tr class="row-odd"><td>7</td>
17004 <td>DEV_VPAC1_VISS0_CLK_CLK</td>
17005 <td>Input clock</td>
17006 </tr>
17007 </tbody>
17008 </table>
17009 </div>
17010 <div class="section" id="clocks-for-vusr-dual0-device">
17011 <span id="soc-doc-j784s4-public-clks-vusr-dual0"></span><h3>Clocks for VUSR_DUAL0 Device<a class="headerlink" href="#clocks-for-vusr-dual0-device" title="Permalink to this headline">¶</a></h3>
17012 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_VUSR_DUAL0</span></a> (ID = 401)</p>
17013 <p>Following is a mapping of Clocks IDs to function:</p>
17014 <table border="1" class="docutils">
17015 <colgroup>
17016 <col width="20%" />
17017 <col width="56%" />
17018 <col width="24%" />
17019 </colgroup>
17020 <thead valign="bottom">
17021 <tr class="row-odd"><th class="head">Clock ID</th>
17022 <th class="head">Name</th>
17023 <th class="head">Function</th>
17024 </tr>
17025 </thead>
17026 <tbody valign="top">
17027 <tr class="row-even"><td>0</td>
17028 <td>DEV_VUSR_DUAL0_V0_CLK</td>
17029 <td>Input clock</td>
17030 </tr>
17031 <tr class="row-odd"><td>1</td>
17032 <td>DEV_VUSR_DUAL0_V0_RXFL_CLK</td>
17033 <td>Output clock</td>
17034 </tr>
17035 <tr class="row-even"><td>2</td>
17036 <td>DEV_VUSR_DUAL0_V0_RXPM_CLK</td>
17037 <td>Input clock</td>
17038 </tr>
17039 <tr class="row-odd"><td>3</td>
17040 <td>DEV_VUSR_DUAL0_V0_TXFL_CLK</td>
17041 <td>Input clock</td>
17042 </tr>
17043 <tr class="row-even"><td>4</td>
17044 <td>DEV_VUSR_DUAL0_V0_TXPM_CLK</td>
17045 <td>Output clock</td>
17046 </tr>
17047 <tr class="row-odd"><td>5</td>
17048 <td>DEV_VUSR_DUAL0_V1_CLK</td>
17049 <td>Input clock</td>
17050 </tr>
17051 <tr class="row-even"><td>6</td>
17052 <td>DEV_VUSR_DUAL0_V1_RXFL_CLK</td>
17053 <td>Output clock</td>
17054 </tr>
17055 <tr class="row-odd"><td>7</td>
17056 <td>DEV_VUSR_DUAL0_V1_RXPM_CLK</td>
17057 <td>Input clock</td>
17058 </tr>
17059 <tr class="row-even"><td>8</td>
17060 <td>DEV_VUSR_DUAL0_V1_TXFL_CLK</td>
17061 <td>Input clock</td>
17062 </tr>
17063 <tr class="row-odd"><td>9</td>
17064 <td>DEV_VUSR_DUAL0_V1_TXPM_CLK</td>
17065 <td>Output clock</td>
17066 </tr>
17067 <tr class="row-even"><td>10</td>
17068 <td>DEV_VUSR_DUAL0_VUSRX_LN0_REFCLK</td>
17069 <td>Input clock</td>
17070 </tr>
17071 <tr class="row-odd"><td>11</td>
17072 <td>DEV_VUSR_DUAL0_VUSRX_LN0_RXCLK</td>
17073 <td>Input clock</td>
17074 </tr>
17075 <tr class="row-even"><td>12</td>
17076 <td>DEV_VUSR_DUAL0_VUSRX_LN0_RXFCLK</td>
17077 <td>Input clock</td>
17078 </tr>
17079 <tr class="row-odd"><td>13</td>
17080 <td>DEV_VUSR_DUAL0_VUSRX_LN0_TXCLK</td>
17081 <td>Output clock</td>
17082 </tr>
17083 <tr class="row-even"><td>14</td>
17084 <td>DEV_VUSR_DUAL0_VUSRX_LN0_TXFCLK</td>
17085 <td>Input clock</td>
17086 </tr>
17087 <tr class="row-odd"><td>15</td>
17088 <td>DEV_VUSR_DUAL0_VUSRX_LN0_TXMCLK</td>
17089 <td>Input clock</td>
17090 </tr>
17091 <tr class="row-even"><td>16</td>
17092 <td>DEV_VUSR_DUAL0_VUSRX_LN1_REFCLK</td>
17093 <td>Input clock</td>
17094 </tr>
17095 <tr class="row-odd"><td>17</td>
17096 <td>DEV_VUSR_DUAL0_VUSRX_LN1_RXCLK</td>
17097 <td>Input clock</td>
17098 </tr>
17099 <tr class="row-even"><td>18</td>
17100 <td>DEV_VUSR_DUAL0_VUSRX_LN1_RXFCLK</td>
17101 <td>Input clock</td>
17102 </tr>
17103 <tr class="row-odd"><td>19</td>
17104 <td>DEV_VUSR_DUAL0_VUSRX_LN1_TXCLK</td>
17105 <td>Output clock</td>
17106 </tr>
17107 <tr class="row-even"><td>20</td>
17108 <td>DEV_VUSR_DUAL0_VUSRX_LN1_TXFCLK</td>
17109 <td>Input clock</td>
17110 </tr>
17111 <tr class="row-odd"><td>21</td>
17112 <td>DEV_VUSR_DUAL0_VUSRX_LN1_TXMCLK</td>
17113 <td>Input clock</td>
17114 </tr>
17115 <tr class="row-even"><td>22</td>
17116 <td>DEV_VUSR_DUAL0_VUSRX_LN2_REFCLK</td>
17117 <td>Input clock</td>
17118 </tr>
17119 <tr class="row-odd"><td>23</td>
17120 <td>DEV_VUSR_DUAL0_VUSRX_LN2_RXCLK</td>
17121 <td>Input clock</td>
17122 </tr>
17123 <tr class="row-even"><td>24</td>
17124 <td>DEV_VUSR_DUAL0_VUSRX_LN2_RXFCLK</td>
17125 <td>Input clock</td>
17126 </tr>
17127 <tr class="row-odd"><td>25</td>
17128 <td>DEV_VUSR_DUAL0_VUSRX_LN2_TXCLK</td>
17129 <td>Output clock</td>
17130 </tr>
17131 <tr class="row-even"><td>26</td>
17132 <td>DEV_VUSR_DUAL0_VUSRX_LN2_TXFCLK</td>
17133 <td>Input clock</td>
17134 </tr>
17135 <tr class="row-odd"><td>27</td>
17136 <td>DEV_VUSR_DUAL0_VUSRX_LN2_TXMCLK</td>
17137 <td>Input clock</td>
17138 </tr>
17139 <tr class="row-even"><td>28</td>
17140 <td>DEV_VUSR_DUAL0_VUSRX_LN3_REFCLK</td>
17141 <td>Input clock</td>
17142 </tr>
17143 <tr class="row-odd"><td>29</td>
17144 <td>DEV_VUSR_DUAL0_VUSRX_LN3_RXCLK</td>
17145 <td>Input clock</td>
17146 </tr>
17147 <tr class="row-even"><td>30</td>
17148 <td>DEV_VUSR_DUAL0_VUSRX_LN3_RXFCLK</td>
17149 <td>Input clock</td>
17150 </tr>
17151 <tr class="row-odd"><td>31</td>
17152 <td>DEV_VUSR_DUAL0_VUSRX_LN3_TXCLK</td>
17153 <td>Output clock</td>
17154 </tr>
17155 <tr class="row-even"><td>32</td>
17156 <td>DEV_VUSR_DUAL0_VUSRX_LN3_TXFCLK</td>
17157 <td>Input clock</td>
17158 </tr>
17159 <tr class="row-odd"><td>33</td>
17160 <td>DEV_VUSR_DUAL0_VUSRX_LN3_TXMCLK</td>
17161 <td>Input clock</td>
17162 </tr>
17163 </tbody>
17164 </table>
17165 </div>
17166 <div class="section" id="clocks-for-wkupmcu2main-vd-device">
17167 <span id="soc-doc-j784s4-public-clks-wkupmcu2main-vd"></span><h3>Clocks for WKUPMCU2MAIN_VD Device<a class="headerlink" href="#clocks-for-wkupmcu2main-vd-device" title="Permalink to this headline">¶</a></h3>
17168 <p><strong>This device has no defined clocks.</strong></p>
17169 </div>
17170 <div class="section" id="clocks-for-wkup-ddpa0-device">
17171 <span id="soc-doc-j784s4-public-clks-wkup-ddpa0"></span><h3>Clocks for WKUP_DDPA0 Device<a class="headerlink" href="#clocks-for-wkup-ddpa0-device" title="Permalink to this headline">¶</a></h3>
17172 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_WKUP_DDPA0</span></a> (ID = 211)</p>
17173 <p>Following is a mapping of Clocks IDs to function:</p>
17174 <table border="1" class="docutils">
17175 <colgroup>
17176 <col width="24%" />
17177 <col width="50%" />
17178 <col width="26%" />
17179 </colgroup>
17180 <thead valign="bottom">
17181 <tr class="row-odd"><th class="head">Clock ID</th>
17182 <th class="head">Name</th>
17183 <th class="head">Function</th>
17184 </tr>
17185 </thead>
17186 <tbody valign="top">
17187 <tr class="row-even"><td>0</td>
17188 <td>DEV_WKUP_DDPA0_DDPA_CLK</td>
17189 <td>Input clock</td>
17190 </tr>
17191 </tbody>
17192 </table>
17193 </div>
17194 <div class="section" id="clocks-for-wkup-esm0-device">
17195 <span id="soc-doc-j784s4-public-clks-wkup-esm0"></span><h3>Clocks for WKUP_ESM0 Device<a class="headerlink" href="#clocks-for-wkup-esm0-device" title="Permalink to this headline">¶</a></h3>
17196 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_WKUP_ESM0</span></a> (ID = 147)</p>
17197 <p>Following is a mapping of Clocks IDs to function:</p>
17198 <table border="1" class="docutils">
17199 <colgroup>
17200 <col width="27%" />
17201 <col width="43%" />
17202 <col width="30%" />
17203 </colgroup>
17204 <thead valign="bottom">
17205 <tr class="row-odd"><th class="head">Clock ID</th>
17206 <th class="head">Name</th>
17207 <th class="head">Function</th>
17208 </tr>
17209 </thead>
17210 <tbody valign="top">
17211 <tr class="row-even"><td>0</td>
17212 <td>DEV_WKUP_ESM0_CLK</td>
17213 <td>Input clock</td>
17214 </tr>
17215 </tbody>
17216 </table>
17217 </div>
17218 <div class="section" id="clocks-for-wkup-gpio0-device">
17219 <span id="soc-doc-j784s4-public-clks-wkup-gpio0"></span><h3>Clocks for WKUP_GPIO0 Device<a class="headerlink" href="#clocks-for-wkup-gpio0-device" title="Permalink to this headline">¶</a></h3>
17220 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_WKUP_GPIO0</span></a> (ID = 167)</p>
17221 <p>Following is a mapping of Clocks IDs to function:</p>
17222 <table border="1" class="docutils">
17223 <colgroup>
17224 <col width="24%" />
17225 <col width="49%" />
17226 <col width="27%" />
17227 </colgroup>
17228 <thead valign="bottom">
17229 <tr class="row-odd"><th class="head">Clock ID</th>
17230 <th class="head">Name</th>
17231 <th class="head">Function</th>
17232 </tr>
17233 </thead>
17234 <tbody valign="top">
17235 <tr class="row-even"><td>0</td>
17236 <td>DEV_WKUP_GPIO0_MMR_CLK</td>
17237 <td>Input clock</td>
17238 </tr>
17239 </tbody>
17240 </table>
17241 </div>
17242 <div class="section" id="clocks-for-wkup-gpio1-device">
17243 <span id="soc-doc-j784s4-public-clks-wkup-gpio1"></span><h3>Clocks for WKUP_GPIO1 Device<a class="headerlink" href="#clocks-for-wkup-gpio1-device" title="Permalink to this headline">¶</a></h3>
17244 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_WKUP_GPIO1</span></a> (ID = 168)</p>
17245 <p>Following is a mapping of Clocks IDs to function:</p>
17246 <table border="1" class="docutils">
17247 <colgroup>
17248 <col width="24%" />
17249 <col width="49%" />
17250 <col width="27%" />
17251 </colgroup>
17252 <thead valign="bottom">
17253 <tr class="row-odd"><th class="head">Clock ID</th>
17254 <th class="head">Name</th>
17255 <th class="head">Function</th>
17256 </tr>
17257 </thead>
17258 <tbody valign="top">
17259 <tr class="row-even"><td>0</td>
17260 <td>DEV_WKUP_GPIO1_MMR_CLK</td>
17261 <td>Input clock</td>
17262 </tr>
17263 </tbody>
17264 </table>
17265 </div>
17266 <div class="section" id="clocks-for-wkup-gpiomux-intrtr0-device">
17267 <span id="soc-doc-j784s4-public-clks-wkup-gpiomux-intrtr0"></span><h3>Clocks for WKUP_GPIOMUX_INTRTR0 Device<a class="headerlink" href="#clocks-for-wkup-gpiomux-intrtr0-device" title="Permalink to this headline">¶</a></h3>
17268 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_WKUP_GPIOMUX_INTRTR0</span></a> (ID = 177)</p>
17269 <p>Following is a mapping of Clocks IDs to function:</p>
17270 <table border="1" class="docutils">
17271 <colgroup>
17272 <col width="20%" />
17273 <col width="58%" />
17274 <col width="22%" />
17275 </colgroup>
17276 <thead valign="bottom">
17277 <tr class="row-odd"><th class="head">Clock ID</th>
17278 <th class="head">Name</th>
17279 <th class="head">Function</th>
17280 </tr>
17281 </thead>
17282 <tbody valign="top">
17283 <tr class="row-even"><td>0</td>
17284 <td>DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK</td>
17285 <td>Input clock</td>
17286 </tr>
17287 </tbody>
17288 </table>
17289 </div>
17290 <div class="section" id="clocks-for-wkup-i2c0-device">
17291 <span id="soc-doc-j784s4-public-clks-wkup-i2c0"></span><h3>Clocks for WKUP_I2C0 Device<a class="headerlink" href="#clocks-for-wkup-i2c0-device" title="Permalink to this headline">¶</a></h3>
17292 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_WKUP_I2C0</span></a> (ID = 279)</p>
17293 <p>Following is a mapping of Clocks IDs to function:</p>
17294 <table border="1" class="docutils">
17295 <colgroup>
17296 <col width="9%" />
17297 <col width="50%" />
17298 <col width="41%" />
17299 </colgroup>
17300 <thead valign="bottom">
17301 <tr class="row-odd"><th class="head">Clock ID</th>
17302 <th class="head">Name</th>
17303 <th class="head">Function</th>
17304 </tr>
17305 </thead>
17306 <tbody valign="top">
17307 <tr class="row-even"><td>0</td>
17308 <td>DEV_WKUP_I2C0_CLK</td>
17309 <td>Input clock</td>
17310 </tr>
17311 <tr class="row-odd"><td>1</td>
17312 <td>DEV_WKUP_I2C0_PISCL</td>
17313 <td>Input clock</td>
17314 </tr>
17315 <tr class="row-even"><td>2</td>
17316 <td>DEV_WKUP_I2C0_PISYS_CLK</td>
17317 <td>Input muxed clock</td>
17318 </tr>
17319 <tr class="row-odd"><td>3</td>
17320 <td>DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK</td>
17321 <td>Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK</td>
17322 </tr>
17323 <tr class="row-even"><td>4</td>
17324 <td>DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
17325 <td>Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK</td>
17326 </tr>
17327 <tr class="row-odd"><td>5</td>
17328 <td>DEV_WKUP_I2C0_PORSCL</td>
17329 <td>Output clock</td>
17330 </tr>
17331 </tbody>
17332 </table>
17333 </div>
17334 <div class="section" id="clocks-for-wkup-j7am-wakeup-16ff0-device">
17335 <span id="soc-doc-j784s4-public-clks-wkup-j7am-wakeup-16ff0"></span><h3>Clocks for WKUP_J7AM_WAKEUP_16FF0 Device<a class="headerlink" href="#clocks-for-wkup-j7am-wakeup-16ff0-device" title="Permalink to this headline">¶</a></h3>
17336 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_WKUP_J7AM_WAKEUP_16FF0</span></a> (ID = 208)</p>
17337 <p>Following is a mapping of Clocks IDs to function:</p>
17338 <table border="1" class="docutils">
17339 <colgroup>
17340 <col width="15%" />
17341 <col width="67%" />
17342 <col width="18%" />
17343 </colgroup>
17344 <thead valign="bottom">
17345 <tr class="row-odd"><th class="head">Clock ID</th>
17346 <th class="head">Name</th>
17347 <th class="head">Function</th>
17348 </tr>
17349 </thead>
17350 <tbody valign="top">
17351 <tr class="row-even"><td>0</td>
17352 <td>DEV_WKUP_J7AM_WAKEUP_16FF0_PLL_CTRL_WKUP_CLK24_CLK</td>
17353 <td>Input clock</td>
17354 </tr>
17355 <tr class="row-odd"><td>1</td>
17356 <td>DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_12P5M_CLK</td>
17357 <td>Output clock</td>
17358 </tr>
17359 <tr class="row-even"><td>2</td>
17360 <td>DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_32K_CLK</td>
17361 <td>Output clock</td>
17362 </tr>
17363 </tbody>
17364 </table>
17365 </div>
17366 <div class="section" id="clocks-for-wkup-porz-sync0-device">
17367 <span id="soc-doc-j784s4-public-clks-wkup-porz-sync0"></span><h3>Clocks for WKUP_PORZ_SYNC0 Device<a class="headerlink" href="#clocks-for-wkup-porz-sync0-device" title="Permalink to this headline">¶</a></h3>
17368 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_WKUP_PORZ_SYNC0</span></a> (ID = 175)</p>
17369 <p>Following is a mapping of Clocks IDs to function:</p>
17370 <table border="1" class="docutils">
17371 <colgroup>
17372 <col width="20%" />
17373 <col width="59%" />
17374 <col width="21%" />
17375 </colgroup>
17376 <thead valign="bottom">
17377 <tr class="row-odd"><th class="head">Clock ID</th>
17378 <th class="head">Name</th>
17379 <th class="head">Function</th>
17380 </tr>
17381 </thead>
17382 <tbody valign="top">
17383 <tr class="row-even"><td>0</td>
17384 <td>DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK</td>
17385 <td>Input clock</td>
17386 </tr>
17387 </tbody>
17388 </table>
17389 </div>
17390 <div class="section" id="clocks-for-wkup-psc0-device">
17391 <span id="soc-doc-j784s4-public-clks-wkup-psc0"></span><h3>Clocks for WKUP_PSC0 Device<a class="headerlink" href="#clocks-for-wkup-psc0-device" title="Permalink to this headline">¶</a></h3>
17392 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_WKUP_PSC0</span></a> (ID = 178)</p>
17393 <p>Following is a mapping of Clocks IDs to function:</p>
17394 <table border="1" class="docutils">
17395 <colgroup>
17396 <col width="24%" />
17397 <col width="49%" />
17398 <col width="27%" />
17399 </colgroup>
17400 <thead valign="bottom">
17401 <tr class="row-odd"><th class="head">Clock ID</th>
17402 <th class="head">Name</th>
17403 <th class="head">Function</th>
17404 </tr>
17405 </thead>
17406 <tbody valign="top">
17407 <tr class="row-even"><td>0</td>
17408 <td>DEV_WKUP_PSC0_CLK</td>
17409 <td>Input clock</td>
17410 </tr>
17411 <tr class="row-odd"><td>1</td>
17412 <td>DEV_WKUP_PSC0_SLOW_CLK</td>
17413 <td>Input clock</td>
17414 </tr>
17415 </tbody>
17416 </table>
17417 </div>
17418 <div class="section" id="clocks-for-wkup-sms0-device">
17419 <span id="soc-doc-j784s4-public-clks-wkup-sms0"></span><h3>Clocks for WKUP_SMS0 Device<a class="headerlink" href="#clocks-for-wkup-sms0-device" title="Permalink to this headline">¶</a></h3>
17420 <p><strong>This device has no defined clocks.</strong></p>
17421 </div>
17422 <div class="section" id="clocks-for-wkup-uart0-device">
17423 <span id="soc-doc-j784s4-public-clks-wkup-uart0"></span><h3>Clocks for WKUP_UART0 Device<a class="headerlink" href="#clocks-for-wkup-uart0-device" title="Permalink to this headline">¶</a></h3>
17424 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_WKUP_UART0</span></a> (ID = 397)</p>
17425 <p>Following is a mapping of Clocks IDs to function:</p>
17426 <table border="1" class="docutils">
17427 <colgroup>
17428 <col width="10%" />
17429 <col width="46%" />
17430 <col width="44%" />
17431 </colgroup>
17432 <thead valign="bottom">
17433 <tr class="row-odd"><th class="head">Clock ID</th>
17434 <th class="head">Name</th>
17435 <th class="head">Function</th>
17436 </tr>
17437 </thead>
17438 <tbody valign="top">
17439 <tr class="row-even"><td>0</td>
17440 <td>DEV_WKUP_UART0_FCLK_CLK</td>
17441 <td>Input muxed clock</td>
17442 </tr>
17443 <tr class="row-odd"><td>1</td>
17444 <td>DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUP_USART_CLKSEL_OUT0</td>
17445 <td>Parent input clock option to DEV_WKUP_UART0_FCLK_CLK</td>
17446 </tr>
17447 <tr class="row-even"><td>2</td>
17448 <td>DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT</td>
17449 <td>Parent input clock option to DEV_WKUP_UART0_FCLK_CLK</td>
17450 </tr>
17451 <tr class="row-odd"><td>7</td>
17452 <td>DEV_WKUP_UART0_VBUSP_CLK</td>
17453 <td>Input clock</td>
17454 </tr>
17455 </tbody>
17456 </table>
17457 </div>
17458 <div class="section" id="clocks-for-wkup-vtm0-device">
17459 <span id="soc-doc-j784s4-public-clks-wkup-vtm0"></span><h3>Clocks for WKUP_VTM0 Device<a class="headerlink" href="#clocks-for-wkup-vtm0-device" title="Permalink to this headline">¶</a></h3>
17460 <p>Device: <a class="reference internal" href="devices.html#soc-doc-j784s4-public-devices-desc-device-list"><span class="std std-ref">J784S4_DEV_WKUP_VTM0</span></a> (ID = 243)</p>
17461 <p>Following is a mapping of Clocks IDs to function:</p>
17462 <table border="1" class="docutils">
17463 <colgroup>
17464 <col width="23%" />
17465 <col width="53%" />
17466 <col width="25%" />
17467 </colgroup>
17468 <thead valign="bottom">
17469 <tr class="row-odd"><th class="head">Clock ID</th>
17470 <th class="head">Name</th>
17471 <th class="head">Function</th>
17472 </tr>
17473 </thead>
17474 <tbody valign="top">
17475 <tr class="row-even"><td>0</td>
17476 <td>DEV_WKUP_VTM0_FIX_REF2_CLK</td>
17477 <td>Input clock</td>
17478 </tr>
17479 <tr class="row-odd"><td>1</td>
17480 <td>DEV_WKUP_VTM0_FIX_REF_CLK</td>
17481 <td>Input clock</td>
17482 </tr>
17483 <tr class="row-even"><td>2</td>
17484 <td>DEV_WKUP_VTM0_VBUSP_CLK</td>
17485 <td>Input clock</td>
17486 </tr>
17487 </tbody>
17488 </table>
17489 </div>
17490 </div>
17491 </div>
17492
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