[processor-sdk/pdk.git] / packages / ti / drv / sciclient / soc / sysfw / binaries / system-firmware-public-documentation / _sources / 5_soc_doc / am62x / hosts.rst.txt
1 =======================
2 AM62X Host Descriptions
3 =======================
5 .. _soc_doc_am62x_public_host_desc_intro:
7 Introduction
8 ============
10 This chapter provides information of Host IDs that are permitted in
11 the AM62X SoC. These host IDs represent processing entities (or PEs)
12 which is mandatory identification of a Host in a processor.
14 Typically a host is a 'compute entity' which may be an actual
15 processor or even a virtual machine. We just use host or processing
16 entity to indicate the same thing.
18 .. _soc_doc_am62x_public_host_desc_host_list:
20 Enumeration of Host IDs
21 =======================
23 +-----------+-------------+-------------------+--------------------------------------------+
24 | Host ID | Host Name | Security Status | Description |
25 +===========+=============+===================+============================================+
26 | 0 | TIFS | Secure | Device Management and Security Control |
27 +-----------+-------------+-------------------+--------------------------------------------+
28 | 254 | DM | Non Secure | Device Management |
29 +-----------+-------------+-------------------+--------------------------------------------+
30 | 35 | MAIN_0_R5_0 | Secure | Cortex R5_0 context 0 on Main island(BOOT) |
31 +-----------+-------------+-------------------+--------------------------------------------+
32 | 36 | MAIN_0_R5_1 | Non Secure | Cortex R5_0 context 1 on Main island |
33 +-----------+-------------+-------------------+--------------------------------------------+
34 | 37 | MAIN_0_R5_2 | Secure | Cortex R5_0 context 2 on Main island |
35 +-----------+-------------+-------------------+--------------------------------------------+
36 | 38 | MAIN_0_R5_3 | Non Secure | Cortex R5_0 context 3 on Main island |
37 +-----------+-------------+-------------------+--------------------------------------------+
38 | 10 | A53_0 | Secure | Cortex a53 context 0 on Main island |
39 +-----------+-------------+-------------------+--------------------------------------------+
40 | 11 | A53_1 | Secure | Cortex A53 context 1 on Main island |
41 +-----------+-------------+-------------------+--------------------------------------------+
42 | 12 | A53_2 | Non Secure | Cortex A53 context 2 on Main island |
43 +-----------+-------------+-------------------+--------------------------------------------+
44 | 13 | A53_3 | Non Secure | Cortex A53 context 3 on Main island |
45 +-----------+-------------+-------------------+--------------------------------------------+
46 | 30 | M4_0 | Non Secure | M4 |
47 +-----------+-------------+-------------------+--------------------------------------------+
48 | 31 | GPU | Non Secure | GPU context 0 on Main island |
49 +-----------+-------------+-------------------+--------------------------------------------+
50 | 14 | A53_4 | Non Secure | Cortex A53 context 1 on Main island |
51 +-----------+-------------+-------------------+--------------------------------------------+
52 | 250 | DM2TIFS | Secure | DM to TIFS communication |
53 +-----------+-------------+-------------------+--------------------------------------------+
54 | 251 | TIFS2DM | Non Secure | TIFS to DM communication |
55 +-----------+-------------+-------------------+--------------------------------------------+
57 .. note::
59 * Description provides an intended purpose
60 of the host ID, though on some systems,
61 this might be used differently, backing memory and
62 link allocations are made with the specified purpose
63 in mind
64 * Security Status provides an intended purpose for the
65 Host context