packages/ti/drv/sciclient/soc/sysfw/binaries/system-firmware-public-documentation/_sources/5_soc_doc/am64x/pll_data.rst.txt

   1 ==================
   2 AM64X PLL Defaults
   3 ==================
   4
   5 .. _soc_doc_am64x_public_plls_desc_intro:
   6
   7
   8 PLL Defaults for AM64X Device
   9 =============================
  10
  11 This chapter provides information on the PLL defaults which the System firmware programs
  12 for AM64X SoC.
  13
  14
  15 This is what the system firmware programs after the PM board configuration is provided.
  16 The exact M and N values programmed are based on the crystal connected on the board.
  17 The crystal frequency is understood by the ROM from the BOOTPINS. This value is read
  18 by the System Firmware from the DEVSTAT register to determine which HFOSC is connected to the device
  19
  20
  21 The System Firmware maintains a table of device clock frequency defaults at which the PLLs
  22 are programmed. This document is a reference that the users of System Firmware
  23 can look at to determine the default PLL configuration done during boot when PM board configuration
  24 message is sent.
  25
  26
  27 Once the PM Init during board configuration is complete the bootloader or application can
  28 program individual clocks of individual modules to tweak the clocks based on the usecase
  29 which differ from the default. The APIs to refer to setting individual module clocks are
  30 :ref:`pm_clocks_msg_set_freq`, :ref:`pm_clocks_msg_query_freq`.
  31
  32
  33 The following table gives the PLL configurations for the input crystal Frequency of 19.2 MHz.
  34
  35 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  36 | PLL Name                           |   CLKOUT Freq (Hz) |   N+1 |   M |   Fractional M |   M2 |   HSDIV0 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   | HSDIV5   | HSDIV6   | HSDIV7   | HSDIV8   |
  37 +====================================+====================+=======+=====+================+======+==========+==========+==========+==========+==========+==========+==========+==========+==========+
  38 | MCU (PLLFRACF_SSMOD_16FFT_MCU_0)   |         2400000000 |     1 | 125 |              0 |    1 |        6 | 25       | 25       | 12       | 12       | NA       | NA       | NA       | NA       |
  39 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  40 | MAIN (PLLFRACF_SSMOD_16FFT_MAIN_0) |         1000000000 |     3 | 312 |        8388608 |    2 |        4 | 10       | 25       | 15       | 8        | 5        | 5        | 5        | 8        |
  41 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  42 | PER0 (PLLFRACF_SSMOD_16FFT_MAIN_1) |          960000000 |     1 | 100 |              0 |    2 |       10 | 12       | 5        | 10       | 80       | 6        | 16       | NA       | NA       |
  43 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  44 | PER1 (PLLFRACF_SSMOD_16FFT_MAIN_2) |         1800000000 |     1 |  93 |       12582912 |    1 |        8 | NA       | 9        | 6        | 18       | 8        | 8        | 18       | 30       |
  45 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  46 | ARM0 (PLLFRACF_SSMOD_16FFT_MAIN_8) |         2000000000 |     3 | 312 |        8388608 |    1 |        2 | NA       | NA       | NA       | NA       | NA       | NA       | NA       | NA       |
  47 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  48 | DDR (PLLFRACF_SSMOD_16FFT_MAIN_12) |         1600000000 |     3 | 250 |              0 |    1 |        4 | NA       | NA       | NA       | NA       | NA       | NA       | NA       | NA       |
  49 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  50 | R5F (PLLFRACF_SSMOD_16FFT_MAIN_14) |         2400000000 |     1 | 125 |              0 |    1 |        3 | 3        | NA       | NA       | NA       | NA       | NA       | NA       | NA       |
  51 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  52
  53 The following table gives the PLL configurations for the input crystal Frequency of 20.0 MHz.
  54
  55 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  56 | PLL Name                           |   CLKOUT Freq (Hz) |   N+1 |   M |   Fractional M |   M2 |   HSDIV0 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   | HSDIV5   | HSDIV6   | HSDIV7   | HSDIV8   |
  57 +====================================+====================+=======+=====+================+======+==========+==========+==========+==========+==========+==========+==========+==========+==========+
  58 | MCU (PLLFRACF_SSMOD_16FFT_MCU_0)   |         2400000000 |     1 | 120 |              0 |    1 |        6 | 25       | 25       | 12       | 12       | NA       | NA       | NA       | NA       |
  59 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  60 | MAIN (PLLFRACF_SSMOD_16FFT_MAIN_0) |         1000000000 |     1 | 100 |              0 |    2 |        4 | 10       | 25       | 15       | 8        | 5        | 5        | 5        | 8        |
  61 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  62 | PER0 (PLLFRACF_SSMOD_16FFT_MAIN_1) |          960000000 |     1 |  96 |              0 |    2 |       10 | 12       | 5        | 10       | 80       | 6        | 16       | NA       | NA       |
  63 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  64 | PER1 (PLLFRACF_SSMOD_16FFT_MAIN_2) |         1800000000 |     1 |  90 |              0 |    1 |        8 | NA       | 9        | 6        | 18       | 8        | 8        | 18       | 30       |
  65 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  66 | ARM0 (PLLFRACF_SSMOD_16FFT_MAIN_8) |         2000000000 |     1 | 100 |              0 |    1 |        2 | NA       | NA       | NA       | NA       | NA       | NA       | NA       | NA       |
  67 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  68 | DDR (PLLFRACF_SSMOD_16FFT_MAIN_12) |         1600000000 |     1 |  80 |              0 |    1 |        4 | NA       | NA       | NA       | NA       | NA       | NA       | NA       | NA       |
  69 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  70 | R5F (PLLFRACF_SSMOD_16FFT_MAIN_14) |         2400000000 |     1 | 120 |              0 |    1 |        3 | 3        | NA       | NA       | NA       | NA       | NA       | NA       | NA       |
  71 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  72
  73 The following table gives the PLL configurations for the input crystal Frequency of 24.0 MHz.
  74
  75 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  76 | PLL Name                           |   CLKOUT Freq (Hz) |   N+1 |   M |   Fractional M |   M2 |   HSDIV0 |   HSDIV1 |   HSDIV2 |   HSDIV3 |   HSDIV4 |   HSDIV5 |   HSDIV6 | HSDIV7   | HSDIV8   |
  77 +====================================+====================+=======+=====+================+======+==========+==========+==========+==========+==========+==========+==========+==========+==========+
  78 | PER0 (PLLFRACF_SSMOD_16FFT_MAIN_1) |          960000000 |     1 |  80 |              0 |    2 |       10 |       12 |        5 |       10 |       80 |        6 |       16 | NA       | NA       |
  79 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  80
  81 The following table gives the PLL configurations for the input crystal Frequency of 25.0 MHz.
  82
  83 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  84 | PLL Name                           |   CLKOUT Freq (Hz) |   N+1 |   M |   Fractional M |   M2 |   HSDIV0 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   | HSDIV5   | HSDIV6   | HSDIV7   | HSDIV8   |
  85 +====================================+====================+=======+=====+================+======+==========+==========+==========+==========+==========+==========+==========+==========+==========+
  86 | MCU (PLLFRACF_SSMOD_16FFT_MCU_0)   |         2400000000 |     1 |  96 |              0 |    1 |        6 | 25       | 25       | 12       | 12       | NA       | NA       | NA       | NA       |
  87 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  88 | MAIN (PLLFRACF_SSMOD_16FFT_MAIN_0) |         1000000000 |     1 |  80 |              0 |    2 |        4 | 10       | 25       | 15       | 8        | 5        | 5        | 5        | 8        |
  89 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  90 | PER0 (PLLFRACF_SSMOD_16FFT_MAIN_1) |          960000000 |     5 | 384 |              0 |    2 |       10 | 12       | 5        | 10       | 80       | 6        | 16       | NA       | NA       |
  91 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  92 | PER1 (PLLFRACF_SSMOD_16FFT_MAIN_2) |         1800000000 |     1 |  72 |              0 |    1 |        8 | NA       | 9        | 6        | 18       | 8        | 8        | 18       | 30       |
  93 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  94 | ARM0 (PLLFRACF_SSMOD_16FFT_MAIN_8) |         2000000000 |     1 |  80 |              0 |    1 |        2 | NA       | NA       | NA       | NA       | NA       | NA       | NA       | NA       |
  95 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  96 | DDR (PLLFRACF_SSMOD_16FFT_MAIN_12) |         1600000000 |     1 |  64 |              0 |    1 |        4 | NA       | NA       | NA       | NA       | NA       | NA       | NA       | NA       |
  97 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
  98 | R5F (PLLFRACF_SSMOD_16FFT_MAIN_14) |         2400000000 |     1 |  96 |              0 |    1 |        3 | 3        | NA       | NA       | NA       | NA       | NA       | NA       | NA       |
  99 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
 100
 101 The following table gives the PLL configurations for the input crystal Frequency of 26.0 MHz.
 102
 103 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
 104 | PLL Name                           |   CLKOUT Freq (Hz) |   N+1 |   M |   Fractional M |   M2 |   HSDIV0 |   HSDIV1 |   HSDIV2 |   HSDIV3 |   HSDIV4 |   HSDIV5 |   HSDIV6 | HSDIV7   | HSDIV8   |
 105 +====================================+====================+=======+=====+================+======+==========+==========+==========+==========+==========+==========+==========+==========+==========+
 106 | PER0 (PLLFRACF_SSMOD_16FFT_MAIN_1) |          960000000 |     1 |  73 |       14196106 |    2 |       10 |       12 |        5 |       10 |       80 |        6 |       16 | NA       | NA       |
 107 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
 108
 109 The following table gives the PLL configurations for the input crystal Frequency of 27.0 MHz.
 110
 111 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
 112 | PLL Name                           |   CLKOUT Freq (Hz) |   N+1 |   M |   Fractional M |   M2 |   HSDIV0 |   HSDIV1 |   HSDIV2 |   HSDIV3 |   HSDIV4 |   HSDIV5 |   HSDIV6 | HSDIV7   | HSDIV8   |
 113 +====================================+====================+=======+=====+================+======+==========+==========+==========+==========+==========+==========+==========+==========+==========+
 114 | PER0 (PLLFRACF_SSMOD_16FFT_MAIN_1) |          960000000 |     5 | 384 |              0 |    2 |       10 |       12 |        5 |       10 |       80 |        6 |       16 | NA       | NA       |
 115 +------------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
 116