packages/ti/drv/sciclient/soc/sysfw/binaries/system-firmware-public-documentation/_sources/5_soc_doc/am65x_sr2/pll_data.rst.txt

   1 ================
   2 AM6 PLL Defaults
   3 ================
   4
   5 .. _soc_doc_am65x_sr2_public_plls_desc_intro:
   6
   7
   8 PLL Defaults for AM6 Device
   9 ===========================
  10
  11 This chapter provides information on the PLL defaults which the System firmware programs
  12 for AM6 SoC.
  13
  14
  15 This is what the system firmware programs after the PM board configuration is provided.
  16 The exact M and N values programmed are based on the crystal connected on the board.
  17 The crystal frequency is understood by the ROM from the BOOTPINS. This value is read
  18 by the System Firmware from the DEVSTAT register to determine which HFOSC is connected to the device
  19
  20
  21 The System Firmware maintains a table of device clock frequency defaults at which the PLLs
  22 are programmed. This document is a reference that the users of System Firmware
  23 can look at to determine the default PLL configuration done during boot when PM board configuration
  24 message is sent.
  25
  26
  27 Once the PM Init during board configuration is complete the bootloader or application can
  28 program individual clocks of individual modules to tweak the clocks based on the usecase
  29 which differ from the default. The APIs to refer to setting individual module clocks are
  30 :ref:`pm_clocks_msg_set_freq`, :ref:`pm_clocks_msg_query_freq`.
  31
  32
  33 The following table gives the PLL configurations for the input crystal Frequency of 19.2 MHz.
  34
  35 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  36 | PLL Name                          | CLKOUT Freq (Hz)   |   N+1 |    M |   Fractional M |   M2 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   |
  37 +===================================+====================+=======+======+================+======+==========+==========+==========+==========+
  38 | MCU0 (ADPLLM_HSDIV_WRAP_MCU_0)    | 400000000U         |     2 |  250 |              0 |    6 | 40       | 30       | 25       | 15       |
  39 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  40 | CPSW (ADPLLM_HSDIV_WRAP_MCU_1)    | 250000000U         |    12 | 1250 |              0 |    8 | 10       | 10       | 15       | 6        |
  41 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  42 | MAIN (ADPLLLJM_HSDIV_WRAP_MAIN_0) | 100000000U         |    12 | 1250 |              0 |   20 | 4        | 40       | 8        | 20       |
  43 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  44 | PER0 (ADPLLLJM_WRAP_MAIN_1)       | 960000000U         |     8 |  800 |              0 |    2 | NA       | NA       | NA       | NA       |
  45 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  46 | PER1 (ADPLLLJM_HSDIV_WRAP_MAIN_2) | 300000000U         |     8 |  750 |              0 |    6 | 8        | 18       | 9        | 4        |
  47 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  48 | DDR (ADPLLLJM_WRAP_MAIN_3)        | 333333333U         |    12 |  625 |              0 |    3 | NA       | NA       | NA       | NA       |
  49 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  50 | DSS (ADPLLLJM_WRAP_MAIN_4)        | 1155000000U        |    32 | 1925 |              0 |    1 | NA       | NA       | NA       | NA       |
  51 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  52 | ARM (ADPLLM_WRAP_MAIN_6)          | 800000000U         |     3 |  250 |              0 |    2 | NA       | NA       | NA       | NA       |
  53 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  54 | ARM (ADPLLM_WRAP_MAIN_7)          | 800000000U         |     3 |  250 |              0 |    2 | NA       | NA       | NA       | NA       |
  55 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  56
  57 The following table gives the PLL configurations for the input crystal Frequency of 20.0 MHz.
  58
  59 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
  60 | PLL Name                          | CLKOUT Freq (Hz)   |   N+1 |   M |   Fractional M |   M2 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   |
  61 +===================================+====================+=======+=====+================+======+==========+==========+==========+==========+
  62 | MCU0 (ADPLLM_HSDIV_WRAP_MCU_0)    | 400000000U         |     1 | 120 |              0 |    6 | 40       | 30       | 25       | 15       |
  63 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
  64 | CPSW (ADPLLM_HSDIV_WRAP_MCU_1)    | 250000000U         |     1 | 100 |              0 |    8 | 10       | 10       | 15       | 6        |
  65 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
  66 | MAIN (ADPLLLJM_HSDIV_WRAP_MAIN_0) | 100000000U         |     1 | 100 |              0 |   20 | 4        | 40       | 8        | 20       |
  67 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
  68 | PER0 (ADPLLLJM_WRAP_MAIN_1)       | 960000000U         |     8 | 768 |              0 |    2 | NA       | NA       | NA       | NA       |
  69 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
  70 | PER1 (ADPLLLJM_HSDIV_WRAP_MAIN_2) | 300000000U         |     8 | 720 |              0 |    6 | 8        | 18       | 9        | 4        |
  71 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
  72 | DDR (ADPLLLJM_WRAP_MAIN_3)        | 333333333U         |     8 | 400 |              0 |    3 | NA       | NA       | NA       | NA       |
  73 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
  74 | DSS (ADPLLLJM_WRAP_MAIN_4)        | 1155000000U        |     8 | 462 |              0 |    1 | NA       | NA       | NA       | NA       |
  75 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
  76 | ARM (ADPLLM_WRAP_MAIN_6)          | 800000000U         |     1 |  80 |              0 |    2 | NA       | NA       | NA       | NA       |
  77 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
  78 | ARM (ADPLLM_WRAP_MAIN_7)          | 800000000U         |     1 |  80 |              0 |    2 | NA       | NA       | NA       | NA       |
  79 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
  80
  81 The following table gives the PLL configurations for the input crystal Frequency of 24.0 MHz.
  82
  83 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  84 | PLL Name                          | CLKOUT Freq (Hz)   |   N+1 |    M |   Fractional M |   M2 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   |
  85 +===================================+====================+=======+======+================+======+==========+==========+==========+==========+
  86 | MCU0 (ADPLLM_HSDIV_WRAP_MCU_0)    | 400000000U         |     1 |  100 |              0 |    6 | 40       | 30       | 25       | 15       |
  87 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  88 | CPSW (ADPLLM_HSDIV_WRAP_MCU_1)    | 250000000U         |     3 |  250 |              0 |    8 | 10       | 10       | 15       | 6        |
  89 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  90 | MAIN (ADPLLLJM_HSDIV_WRAP_MAIN_0) | 100000000U         |    12 | 1000 |              0 |   20 | 4        | 40       | 8        | 20       |
  91 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  92 | PER0 (ADPLLLJM_WRAP_MAIN_1)       | 960000000U         |    10 |  800 |              0 |    2 | NA       | NA       | NA       | NA       |
  93 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  94 | PER1 (ADPLLLJM_HSDIV_WRAP_MAIN_2) | 300000000U         |    10 |  750 |              0 |    6 | 8        | 18       | 9        | 4        |
  95 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  96 | DDR (ADPLLLJM_WRAP_MAIN_3)        | 333333333U         |    12 |  500 |              0 |    3 | NA       | NA       | NA       | NA       |
  97 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
  98 | DSS (ADPLLLJM_WRAP_MAIN_4)        | 1155000000U        |    24 | 1155 |              0 |    1 | NA       | NA       | NA       | NA       |
  99 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 100 | ARM (ADPLLM_WRAP_MAIN_6)          | 800000000U         |     3 |  200 |              0 |    2 | NA       | NA       | NA       | NA       |
 101 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 102 | ARM (ADPLLM_WRAP_MAIN_7)          | 800000000U         |     3 |  200 |              0 |    2 | NA       | NA       | NA       | NA       |
 103 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 104
 105 The following table gives the PLL configurations for the input crystal Frequency of 25.0 MHz.
 106
 107 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
 108 | PLL Name                          | CLKOUT Freq (Hz)   |   N+1 |   M |   Fractional M |   M2 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   |
 109 +===================================+====================+=======+=====+================+======+==========+==========+==========+==========+
 110 | MCU0 (ADPLLM_HSDIV_WRAP_MCU_0)    | 400000000U         |     1 |  96 |              0 |    6 | 40       | 30       | 25       | 15       |
 111 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
 112 | CPSW (ADPLLM_HSDIV_WRAP_MCU_1)    | 250000000U         |     1 |  80 |              0 |    8 | 10       | 10       | 15       | 6        |
 113 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
 114 | MAIN (ADPLLLJM_HSDIV_WRAP_MAIN_0) | 100000000U         |    10 | 800 |              0 |   20 | 4        | 40       | 8        | 20       |
 115 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
 116 | PER0 (ADPLLLJM_WRAP_MAIN_1)       | 960000000U         |    10 | 768 |              0 |    2 | NA       | NA       | NA       | NA       |
 117 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
 118 | PER1 (ADPLLLJM_HSDIV_WRAP_MAIN_2) | 300000000U         |    10 | 720 |              0 |    6 | 8        | 18       | 9        | 4        |
 119 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
 120 | DDR (ADPLLLJM_WRAP_MAIN_3)        | 333333333U         |    10 | 400 |              0 |    3 | NA       | NA       | NA       | NA       |
 121 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
 122 | DSS (ADPLLLJM_WRAP_MAIN_4)        | 1155000000U        |    10 | 462 |              0 |    1 | NA       | NA       | NA       | NA       |
 123 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
 124 | ARM (ADPLLM_WRAP_MAIN_6)          | 800000000U         |     1 |  64 |              0 |    2 | NA       | NA       | NA       | NA       |
 125 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
 126 | ARM (ADPLLM_WRAP_MAIN_7)          | 800000000U         |     1 |  64 |              0 |    2 | NA       | NA       | NA       | NA       |
 127 +-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
 128
 129 The following table gives the PLL configurations for the input crystal Frequency of 26.0 MHz.
 130
 131 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 132 | PLL Name                          | CLKOUT Freq (Hz)   |   N+1 |    M |   Fractional M |   M2 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   |
 133 +===================================+====================+=======+======+================+======+==========+==========+==========+==========+
 134 | MCU0 (ADPLLM_HSDIV_WRAP_MCU_0)    | 400000000U         |    13 | 1200 |              0 |    6 | 40       | 30       | 25       | 15       |
 135 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 136 | CPSW (ADPLLM_HSDIV_WRAP_MCU_1)    | 250000000U         |    13 | 1000 |              0 |    8 | 10       | 10       | 15       | 6        |
 137 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 138 | MAIN (ADPLLLJM_HSDIV_WRAP_MAIN_0) | 100000000U         |    13 | 1000 |              0 |   20 | 4        | 40       | 8        | 20       |
 139 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 140 | PER0 (ADPLLLJM_WRAP_MAIN_1)       | 960000000U         |    13 |  960 |              0 |    2 | NA       | NA       | NA       | NA       |
 141 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 142 | PER1 (ADPLLLJM_HSDIV_WRAP_MAIN_2) | 300000000U         |    13 |  900 |              0 |    6 | 8        | 18       | 9        | 4        |
 143 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 144 | DDR (ADPLLLJM_WRAP_MAIN_3)        | 333333333U         |    13 |  500 |              0 |    3 | NA       | NA       | NA       | NA       |
 145 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 146 | DSS (ADPLLLJM_WRAP_MAIN_4)        | 1155000000U        |    26 | 1155 |              0 |    1 | NA       | NA       | NA       | NA       |
 147 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 148 | ARM (ADPLLM_WRAP_MAIN_6)          | 800000000U         |    13 |  800 |              0 |    2 | NA       | NA       | NA       | NA       |
 149 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 150 | ARM (ADPLLM_WRAP_MAIN_7)          | 800000000U         |    13 |  800 |              0 |    2 | NA       | NA       | NA       | NA       |
 151 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 152
 153 The following table gives the PLL configurations for the input crystal Frequency of 27.0 MHz.
 154
 155 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 156 | PLL Name                          | CLKOUT Freq (Hz)   |   N+1 |    M |   Fractional M |   M2 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   |
 157 +===================================+====================+=======+======+================+======+==========+==========+==========+==========+
 158 | MCU0 (ADPLLM_HSDIV_WRAP_MCU_0)    | 400000000U         |     9 |  800 |              0 |    6 | 40       | 30       | 25       | 15       |
 159 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 160 | CPSW (ADPLLM_HSDIV_WRAP_MCU_1)    | 250000000U         |    27 | 2000 |              0 |    8 | 10       | 10       | 15       | 6        |
 161 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 162 | MAIN (ADPLLLJM_HSDIV_WRAP_MAIN_0) | 100000000U         |    27 | 2000 |              0 |   20 | 4        | 40       | 8        | 20       |
 163 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 164 | PER0 (ADPLLLJM_WRAP_MAIN_1)       | 960000000U         |    18 | 1280 |              0 |    2 | NA       | NA       | NA       | NA       |
 165 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 166 | PER1 (ADPLLLJM_HSDIV_WRAP_MAIN_2) | 300000000U         |    12 |  800 |              0 |    6 | 8        | 18       | 9        | 4        |
 167 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 168 | DDR (ADPLLLJM_WRAP_MAIN_3)        | 333333333U         |    27 | 1000 |              0 |    3 | NA       | NA       | NA       | NA       |
 169 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 170 | DSS (ADPLLLJM_WRAP_MAIN_4)        | 1155000000U        |    18 | 1540 |              0 |    2 | NA       | NA       | NA       | NA       |
 171 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 172 | ARM (ADPLLM_WRAP_MAIN_6)          | 800000000U         |    27 | 1600 |              0 |    2 | NA       | NA       | NA       | NA       |
 173 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 174 | ARM (ADPLLM_WRAP_MAIN_7)          | 800000000U         |    27 | 1600 |              0 |    2 | NA       | NA       | NA       | NA       |
 175 +-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
 176