[processor-sdk/pdk.git] / packages / ti / drv / sciclient / soc / sysfw / include / am64x / tisci_hosts.h
1 /*
2 * Copyright (C) 2017-2020 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33 /**
34 * \ingroup TISCI
35 * \defgroup tisci_hosts tisci_hosts
36 *
37 * DMSC controls the power management, security and resource management
38 * of the device.
39 *
40 *
41 * @{
42 */
43 /**
44 *
45 * \brief This file contains:
46 *
47 * WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!
48 * System Firmware Source File
49 *
50 * Host IDs for AM64X device
51 *
52 * Data version: 200505_104840
53 *
54 */
55 #ifndef TISCI_HOSTS_H
56 #define TISCI_HOSTS_H
58 /** DMSC(Secure): Device Management and Security Control */
59 #define TISCI_HOST_ID_DMSC (0U)
60 /** MAIN_0_R5_0(Secure): Cortex R5_0 context 0 on Main island(BOOT) */
61 #define TISCI_HOST_ID_MAIN_0_R5_0 (35U)
62 /** MAIN_0_R5_1(Non Secure): Cortex R5_0 context 1 on Main island */
63 #define TISCI_HOST_ID_MAIN_0_R5_1 (36U)
64 /** MAIN_0_R5_2(Secure): Cortex R5_0 context 2 on Main island */
65 #define TISCI_HOST_ID_MAIN_0_R5_2 (37U)
66 /** MAIN_0_R5_3(Non Secure): Cortex R5_0 context 3 on Main island */
67 #define TISCI_HOST_ID_MAIN_0_R5_3 (38U)
68 /** A53_0(Secure): Cortex a53 context 0 on Main islana - ATF */
69 #define TISCI_HOST_ID_A53_0 (10U)
70 /** A53_1(Non Secure): Cortex A53 context 1 on Main island - EL2/Hyp */
71 #define TISCI_HOST_ID_A53_1 (11U)
72 /** A53_2(Non Secure): Cortex A53 context 2 on Main island - VM/OS1 */
73 #define TISCI_HOST_ID_A53_2 (12U)
74 /** A53_3(Non Secure): Cortex A53 context 3 on Main island - VM2/OS2 */
75 #define TISCI_HOST_ID_A53_3 (13U)
76 /** M4_0(Non Secure): M4 */
77 #define TISCI_HOST_ID_M4_0 (30U)
78 /** MAIN_1_R5_0(Secure): Cortex R5_1 context 0 on Main island */
79 #define TISCI_HOST_ID_MAIN_1_R5_0 (40U)
80 /** MAIN_1_R5_1(Non Secure): Cortex R5_1 context 1 on Main island */
81 #define TISCI_HOST_ID_MAIN_1_R5_1 (41U)
82 /** MAIN_1_R5_2(Secure): Cortex R5_1 context 2 on Main island */
83 #define TISCI_HOST_ID_MAIN_1_R5_2 (42U)
84 /** MAIN_1_R5_3(Non Secure): Cortex R5_1 context 3 on Main island */
85 #define TISCI_HOST_ID_MAIN_1_R5_3 (43U)
86 /** ICSSG_0(Non Secure): ICSSG context 0 on Main island */
87 #define TISCI_HOST_ID_ICSSG_0 (50U)
89 /**
90 * Host catch all. Used in board configuration resource assignments to define
91 * resource ranges useable by all hosts. Cannot be used
92 */
93 #define TISCI_HOST_ID_ALL (128U)
95 /** Number of unique hosts on the SoC */
96 #define TISCI_HOST_ID_CNT (15U)
98 #endif /* TISCI_HOSTS_H */
100 /* @} */