1 /*
2 * Copyright (c) 2018, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /**
33 * \file sciclient_rm_csl.c
34 *
35 * \brief File containing the SCICLIENT API interfaces to the resource
36 * management services through CSL API.
37 *
38 */
40 /* ========================================================================== */
41 /* Include Files */
42 /* ========================================================================== */
44 #include <stdint.h>
45 #include <ti/csl/csl_types.h>
46 #include <ti/drv/sciclient/sciclient.h>
48 #include <ti/csl/soc.h>
49 #include <ti/csl/csl_psilcfg.h>
50 #include <ti/csl/csl_ringacc.h>
51 #include <ti/csl/csl_udmap.h>
52 #include <ti/csl/csl_intaggr.h>
53 #include <ti/csl/csl_intr_router.h>
55 /* ========================================================================== */
56 /* Macros & Typedefs */
57 /* ========================================================================== */
59 #if defined (SOC_AM65XX)
60 /** \brief Number of input virtual interrupts to IR in main NAVSS */
61 #define UDMA_NAVSS0_IR_NUM_IN_INTR (440U)
62 /** \brief Number of output interrupts from IR in main NAVSS */
63 #define UDMA_NAVSS0_IR_NUM_OUT_INTR (152U)
64 /** \brief Number of input virtual interrupts to IR in MCU NAVSS */
65 #define UDMA_MCU_NAVSS0_IR_NUM_IN_INTR (440U)
66 /** \brief Number of output interrupts from IR in MCU NAVSS */
67 #define UDMA_MCU_NAVSS0_IR_NUM_OUT_INTR (152U)
68 #else
69 /** \brief Number of input virtual interrupts to IR in main NAVSS */
70 #define UDMA_NAVSS0_IR_NUM_IN_INTR (512U)
71 /** \brief Number of output interrupts from IR in main NAVSS */
72 #define UDMA_NAVSS0_IR_NUM_OUT_INTR (408U)
73 /** \brief Number of input virtual interrupts to IR in MCU NAVSS */
74 #define UDMA_MCU_NAVSS0_IR_NUM_IN_INTR (512U)
75 /** \brief Number of output interrupts from IR in MCU NAVSS */
76 #define UDMA_MCU_NAVSS0_IR_NUM_OUT_INTR (64U)
77 #endif
79 /** \brief UTC start thread ID for a SOC */
80 #define UDMA_UTC_START_THREAD_ID (CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILD_THREAD_OFFSET)
82 /* ========================================================================== */
83 /* Structure Declarations */
84 /* ========================================================================== */
85 #if defined (LOKI_BUILD)
86 #define HOST_EMULATION (1U)
87 #endif
90 #if defined (HOST_EMULATION)
91 /* These variables are defined for supporting host emulation ( PC emulation ) and
92 will not be used for target*/
93 extern CSL_udmap_gcfgRegs gHost_udmap_gcfgRegs;
94 extern CSL_udmap_rxfcfgRegs gHost_udmap_rxfcfgRegs;
95 extern CSL_udmap_txccfgRegs gHost_udmap_txccfgRegs;
96 extern CSL_udmap_rxccfgRegs gHost_udmap_rxccfgRegs;
97 extern CSL_udmap_txcrtRegs gHost_udmap_txcrtRegs;
98 extern CSL_udmap_rxcrtRegs gHost_udmap_rxcrtRegs;
99 extern CSL_ringacc_gcfgRegs gHost_ringacc_gcfgRegs;
100 extern CSL_ringacc_cfgRegs gHost_ringacc_cfgRegs;
101 extern CSL_ringacc_rtRegs gHost_ringacc_rtRegs;
102 extern CSL_ringacc_monitorRegs gHost_ringacc_monitorRegs;
103 extern CSL_ringacc_fifosRegs gHost_ringacc_fifosRegs;
104 extern CSL_ringacc_iscRegs gHost_ringacc_iscRegs;
105 extern CSL_psilcfgRegs gHost_psilcfgRegs;
106 extern CSL_intaggr_cfgRegs gHost_intaggr_cfgRegs;
107 extern CSL_intaggr_imapRegs gHost_intaggr_imapRegs;
108 extern CSL_intaggr_intrRegs gHost_intaggr_intrRegs;
109 extern CSL_intaggr_l2gRegs gHost_intaggr_l2gRegs;
110 extern CSL_intaggr_mcastRegs gHost_intaggr_mcastRegs;
111 extern CSL_intaggr_gcntcfgRegs gHost_intaggr_gcntcfgRegs;
112 extern CSL_intaggr_gcntrtiRegs gHost_intaggr_gcntrtiRegs;
113 extern CSL_intr_router_cfgRegs gHost_intr_router_cfgRegs;
114 #endif
116 typedef struct
117 {
118 CSL_UdmapCfg udmapRegs;
119 /**< UDMAP register configuration */
120 CSL_RingAccCfg raRegs;
121 /**< RA register configuration */
122 CSL_psilcfgRegs *psilCfgRegs;
123 /**< PSILCFG register configuration */
124 CSL_IntaggrCfg iaRegs;
125 /**< Interrupt Aggregator configuration */
126 CSL_IntrRouterCfg irRegs;
127 /**< Interrupt Router configuration */
128 uint32_t txUdmaThreadIdStart;
129 uint32_t txUdmaThreadIdEnd;
130 uint32_t rxUdmaThreadIdStart;
131 uint32_t rxUdmaThreadIdEnd;
132 } SciUdmaRmObj;
134 /* ========================================================================== */
135 /* Function Declarations */
136 /* ========================================================================== */
138 /* None */
140 /* ========================================================================== */
141 /* Global Variables */
142 /* ========================================================================== */
143 #if defined (HOST_EMULATION) || defined (LOKI_BUILD)
144 /* These variables are defined for supporting host emulation ( PC emulation ) and
145 will not be used for target*/
146 static SciUdmaRmObj gSciUdmaRmObjMain =
147 {
148 {
149 &gHost_udmap_gcfgRegs,
150 &gHost_udmap_rxfcfgRegs,
151 &gHost_udmap_txccfgRegs,
152 &gHost_udmap_rxccfgRegs,
153 &gHost_udmap_txcrtRegs,
154 &gHost_udmap_rxcrtRegs
155 },
156 {
157 &gHost_ringacc_gcfgRegs,
158 &gHost_ringacc_cfgRegs,
159 &gHost_ringacc_rtRegs,
160 &gHost_ringacc_monitorRegs,
161 &gHost_ringacc_fifosRegs,
162 &gHost_ringacc_iscRegs,
163 CSL_NAVSS_MAIN_RINGACC_RING_CNT
164 },
165 &gHost_psilcfgRegs,
166 {
167 &gHost_intaggr_cfgRegs,
168 &gHost_intaggr_imapRegs,
169 &gHost_intaggr_intrRegs,
170 &gHost_intaggr_l2gRegs,
171 &gHost_intaggr_mcastRegs,
172 &gHost_intaggr_gcntcfgRegs,
173 &gHost_intaggr_gcntrtiRegs,
174 4608U,
175 256U,
176 4U,
177 512U,
178 512U
179 },
181 {
182 &gHost_intr_router_cfgRegs,
183 NULL,
184 UDMA_NAVSS0_IR_NUM_IN_INTR,
185 UDMA_NAVSS0_IR_NUM_OUT_INTR
186 },
187 CSL_PSILCFG_NAVSS_MAIN_UDMAP0_TSTRM_THREAD_OFFSET,
188 CSL_PSILCFG_NAVSS_MAIN_UDMAP0_TSTRM_THREAD_OFFSET + CSL_PSILCFG_NAVSS_MAIN_UDMAP0_TSTRM_THREAD_CNT - 1,
189 CSL_PSILCFG_NAVSS_MAIN_UDMAP0_RSTRM_THREAD_OFFSET,
190 CSL_PSILCFG_NAVSS_MAIN_UDMAP0_RSTRM_THREAD_OFFSET + CSL_PSILCFG_NAVSS_MAIN_UDMAP0_RSTRM_THREAD_CNT - 1,
191 };
193 static SciUdmaRmObj gSciUdmaRmObjMcu =
194 {
195 {
196 &gHost_udmap_gcfgRegs,
197 &gHost_udmap_rxfcfgRegs,
198 &gHost_udmap_txccfgRegs,
199 &gHost_udmap_rxccfgRegs,
200 &gHost_udmap_txcrtRegs,
201 &gHost_udmap_rxcrtRegs
202 },
204 {
205 &gHost_ringacc_gcfgRegs,
206 &gHost_ringacc_cfgRegs,
207 &gHost_ringacc_rtRegs,
208 &gHost_ringacc_monitorRegs,
209 &gHost_ringacc_fifosRegs,
210 &gHost_ringacc_iscRegs,
211 CSL_NAVSS_MCU_RINGACC_RING_CNT
212 },
213 &gHost_psilcfgRegs,
215 {
216 &gHost_intaggr_cfgRegs,
217 &gHost_intaggr_imapRegs,
218 &gHost_intaggr_intrRegs,
219 &gHost_intaggr_l2gRegs,
220 &gHost_intaggr_mcastRegs,
221 &gHost_intaggr_gcntcfgRegs,
222 &gHost_intaggr_gcntrtiRegs,
223 1536,
224 256U,
225 4U,
226 256U,
227 128U
228 },
230 {
231 &gHost_intr_router_cfgRegs,
232 NULL,
233 UDMA_MCU_NAVSS0_IR_NUM_IN_INTR,
234 UDMA_MCU_NAVSS0_IR_NUM_OUT_INTR
235 },
236 CSL_PSILCFG_NAVSS_MCU_UDMAP0_TSTRM_THREAD_OFFSET,
237 CSL_PSILCFG_NAVSS_MCU_UDMAP0_TSTRM_THREAD_OFFSET + CSL_PSILCFG_NAVSS_MCU_UDMAP0_TSTRM_THREAD_CNT - 1,
238 CSL_PSILCFG_NAVSS_MCU_UDMAP0_RSTRM_THREAD_OFFSET,
239 CSL_PSILCFG_NAVSS_MCU_UDMAP0_RSTRM_THREAD_OFFSET + CSL_PSILCFG_NAVSS_MCU_UDMAP0_RSTRM_THREAD_CNT - 1,
240 };
241 #else
242 static SciUdmaRmObj gSciUdmaRmObjMain =
243 {
244 .udmapRegs =
245 {
246 .pGenCfgRegs = ((CSL_udmap_gcfgRegs *) CSL_NAVSS0_UDMASS_UDMAP0_CFG_BASE),
247 .pRxFlowCfgRegs = ((CSL_udmap_rxfcfgRegs *) CSL_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE),
248 .pTxChanCfgRegs = ((CSL_udmap_txccfgRegs *) CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE),
249 .pRxChanCfgRegs = ((CSL_udmap_rxccfgRegs *) CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE),
250 .pTxChanRtRegs = ((CSL_udmap_txcrtRegs *) CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE),
251 .pRxChanRtRegs = ((CSL_udmap_rxcrtRegs *) CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE)
252 },
253 .raRegs =
254 {
255 .pGlbRegs = (CSL_ringacc_gcfgRegs *) CSL_NAVSS0_UDMASS_RINGACC0_GCFG_BASE,
256 .pCfgRegs = (CSL_ringacc_cfgRegs *) CSL_NAVSS0_UDMASS_RINGACC0_CFG_BASE,
257 .pRtRegs = (CSL_ringacc_rtRegs *) CSL_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE,
258 .pMonRegs = (CSL_ringacc_monitorRegs *) CSL_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE,
259 .pFifoRegs = (CSL_ringacc_fifosRegs *) CSL_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE,
260 #if defined (SOC_AM65XX)
261 .pIscRegs = (CSL_ringacc_iscRegs *) CSL_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE,
262 #else
263 .pIscRegs = (CSL_ringacc_iscRegs *) CSL_NAVSS0_UDMASS_RINGACC0_ISC_BASE,
264 #endif
265 .maxRings = CSL_NAVSS_MAIN_RINGACC_RING_CNT
266 },
267 .psilCfgRegs = (CSL_psilcfgRegs *) CSL_NAVSS0_UDMASS_PSILCFG0_CFG_PROXY_BASE,
268 .iaRegs =
269 {
270 .pCfgRegs = (CSL_intaggr_cfgRegs *) CSL_NAVSS0_UDMASS_INTA0_CFG_BASE,
271 .pImapRegs = (CSL_intaggr_imapRegs *) CSL_NAVSS0_UDMASS_INTA0_IMAP_BASE,
272 .pIntrRegs = (CSL_intaggr_intrRegs *) CSL_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE,
273 #if defined (SOC_AM65XX)
274 .pL2gRegs = (CSL_intaggr_l2gRegs *) CSL_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_BASE,
275 #else
276 .pL2gRegs = (CSL_intaggr_l2gRegs *) CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE,
277 #endif
278 .pMcastRegs = (CSL_intaggr_mcastRegs *) CSL_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE,
279 .pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE,
280 .pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE,
281 .srcEventCnt = 4608U,
282 .virtIntrCnt = 256U,
283 .localEventCnt = 4U,
284 .globalEventCnt = 512U,
285 .mcastEventCnt = 512U
286 },
287 .irRegs =
288 {
289 .pIntrRouterRegs = (CSL_intr_router_cfgRegs *) CSL_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE,
290 .pIntdRegs = (CSL_intr_router_intd_cfgRegs *) NULL,
291 .numInputIntrs = UDMA_NAVSS0_IR_NUM_IN_INTR,
292 .numOutputIntrs = UDMA_NAVSS0_IR_NUM_OUT_INTR
293 },
294 .txUdmaThreadIdStart = CSL_PSILCFG_NAVSS_MAIN_UDMAP0_TSTRM_THREAD_OFFSET,
295 .txUdmaThreadIdEnd = CSL_PSILCFG_NAVSS_MAIN_UDMAP0_TSTRM_THREAD_OFFSET + CSL_PSILCFG_NAVSS_MAIN_UDMAP0_TSTRM_THREAD_CNT - 1,
296 .rxUdmaThreadIdStart = CSL_PSILCFG_NAVSS_MAIN_UDMAP0_RSTRM_THREAD_OFFSET,
297 .rxUdmaThreadIdEnd = CSL_PSILCFG_NAVSS_MAIN_UDMAP0_RSTRM_THREAD_OFFSET + CSL_PSILCFG_NAVSS_MAIN_UDMAP0_RSTRM_THREAD_CNT - 1,
298 };
300 static SciUdmaRmObj gSciUdmaRmObjMcu =
301 {
302 .udmapRegs =
303 {
304 .pGenCfgRegs = ((CSL_udmap_gcfgRegs *) CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE),
305 .pRxFlowCfgRegs = ((CSL_udmap_rxfcfgRegs *) CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE),
306 .pTxChanCfgRegs = ((CSL_udmap_txccfgRegs *) CSL_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE),
307 .pRxChanCfgRegs = ((CSL_udmap_rxccfgRegs *) CSL_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE),
308 .pTxChanRtRegs = ((CSL_udmap_txcrtRegs *) CSL_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE),
309 .pRxChanRtRegs = ((CSL_udmap_rxcrtRegs *) CSL_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE)
310 },
311 .raRegs =
312 {
313 .pGlbRegs = (CSL_ringacc_gcfgRegs *) CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE,
314 .pCfgRegs = (CSL_ringacc_cfgRegs *) CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE,
315 .pRtRegs = (CSL_ringacc_rtRegs *) CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE,
316 .pMonRegs = (CSL_ringacc_monitorRegs *) CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE,
317 .pFifoRegs = (CSL_ringacc_fifosRegs *) CSL_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE,
318 #if defined (SOC_AM65XX)
319 .pIscRegs = (CSL_ringacc_iscRegs *) CSL_MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE,
320 #else
321 .pIscRegs = (CSL_ringacc_iscRegs *) CSL_MCU_NAVSS0_UDMASS_RINGACC0_ISC_BASE,
322 #endif
323 .maxRings = CSL_NAVSS_MCU_RINGACC_RING_CNT
324 },
325 .psilCfgRegs = (CSL_psilcfgRegs *) CSL_MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY_BASE,
326 .iaRegs =
327 {
328 .pCfgRegs = (CSL_intaggr_cfgRegs *) CSL_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE,
329 .pImapRegs = (CSL_intaggr_imapRegs *) CSL_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE,
330 .pIntrRegs = (CSL_intaggr_intrRegs *) CSL_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE,
331 #if defined (SOC_AM65XX)
332 .pL2gRegs = (CSL_intaggr_l2gRegs *) CSL_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_BASE,
333 #else
334 .pL2gRegs = (CSL_intaggr_l2gRegs *) CSL_MCU_NAVSS0_UDMASS_INTA0_I2G_BASE,
335 #endif
336 .pMcastRegs = (CSL_intaggr_mcastRegs *) CSL_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE,
337 .pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) CSL_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE,
338 .pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) CSL_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE,
339 .srcEventCnt = 1536,
340 .virtIntrCnt = 256U,
341 .localEventCnt = 4U,
342 .globalEventCnt = 256U,
343 .mcastEventCnt = 128U
344 },
345 .irRegs =
346 {
347 .pIntrRouterRegs = (CSL_intr_router_cfgRegs *) CSL_MCU_NAVSS0_INTR0_CFG_BASE,
348 .pIntdRegs = (CSL_intr_router_intd_cfgRegs *) NULL,
349 .numInputIntrs = UDMA_MCU_NAVSS0_IR_NUM_IN_INTR,
350 .numOutputIntrs = UDMA_MCU_NAVSS0_IR_NUM_OUT_INTR
351 },
352 .txUdmaThreadIdStart = CSL_PSILCFG_NAVSS_MCU_UDMAP0_TSTRM_THREAD_OFFSET,
353 .txUdmaThreadIdEnd = CSL_PSILCFG_NAVSS_MCU_UDMAP0_TSTRM_THREAD_OFFSET + CSL_PSILCFG_NAVSS_MCU_UDMAP0_TSTRM_THREAD_CNT - 1,
354 .rxUdmaThreadIdStart = CSL_PSILCFG_NAVSS_MCU_UDMAP0_RSTRM_THREAD_OFFSET,
355 .rxUdmaThreadIdEnd = CSL_PSILCFG_NAVSS_MCU_UDMAP0_RSTRM_THREAD_OFFSET + CSL_PSILCFG_NAVSS_MCU_UDMAP0_RSTRM_THREAD_CNT - 1,
356 };
357 #endif
358 /* ========================================================================== */
359 /* Function Definitions */
360 /* ========================================================================== */
362 void Sciclient_rmInit(void)
363 {
364 /* UDMA not present in CC QT build. Only DRU is present */
365 #ifndef CC_QT_BUILD
366 /*
367 * UTC config init
368 */
369 /* One time setup of UTC thread base */
370 CSL_udmapSetUtcCtrl(&gSciUdmaRmObjMain.udmapRegs, UDMA_UTC_START_THREAD_ID);
371 CSL_udmapSetUtcCtrl(&gSciUdmaRmObjMcu.udmapRegs, UDMA_UTC_START_THREAD_ID);
372 #endif
373 }
375 int32_t Sciclient_rmIrqSet(const struct tisci_msg_rm_irq_set_req *req,
376 const struct tisci_msg_rm_irq_set_resp *resp,
377 uint32_t timeout)
378 {
379 int32_t retVal = CSL_PASS;
380 uint16_t eventOffset; /* Within a IA - convert from global to local offset within IA */
381 uint32_t chOffset; /* Within a UDMA - convert from global source index to local offset within UDMAP */
382 uint32_t irOffset; /* Within a IR - convert from cpu dest interrupt index to local IR offset within UDMAP */
383 uint64_t vintrBitNum;
384 SciUdmaRmObj *rmObj;
386 /* Program ring OES */
387 if((TISCI_DEV_NAVSS0_RINGACC0 == req->src_id) ||
388 (TISCI_DEV_MCU_NAVSS0_RINGACC0 == req->src_id))
389 {
390 rmObj = &gSciUdmaRmObjMain;
391 if(TISCI_DEV_MCU_NAVSS0_RINGACC0 == req->src_id)
392 {
393 rmObj = &gSciUdmaRmObjMcu;
394 }
396 if(TISCI_MSG_VALUE_RM_GLOBAL_EVENT_VALID & req->valid_params)
397 {
398 retVal += CSL_ringaccSetEvent(
399 &rmObj->raRegs, req->src_index, req->global_event);
400 }
401 }
403 /* Program channel OES */
404 if((TISCI_DEV_NAVSS0_UDMAP0 == req->src_id) ||
405 (TISCI_DEV_MCU_NAVSS0_UDMAP0 == req->src_id))
406 {
407 rmObj = &gSciUdmaRmObjMain;
408 if(TISCI_DEV_MCU_NAVSS0_UDMAP0 == req->src_id)
409 {
410 rmObj = &gSciUdmaRmObjMcu;
411 }
413 if(TISCI_MSG_VALUE_RM_GLOBAL_EVENT_VALID & req->valid_params)
414 {
415 if(req->src_index < TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START)
416 {
417 /* TX OES programming */
418 chOffset = req->src_index;
419 CSL_REG32_WR(&rmObj->udmapRegs.pTxChanCfgRegs->CHAN[chOffset].TOES[0], CSL_FMK(UDMAP_TXCCFG_CHAN_TOES_EVT_NUM, req->global_event));
420 }
421 else if(req->src_index < TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START)
422 {
423 /* TX EOES programming */
424 chOffset = req->src_index - TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START;
425 CSL_REG32_WR(&rmObj->udmapRegs.pTxChanCfgRegs->CHAN[chOffset].TEOES[0], CSL_FMK(UDMAP_TXCCFG_CHAN_TEOES_EVT_NUM, req->global_event));
426 }
427 else if(req->src_index < TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START)
428 {
429 /* RX OES programming */
430 chOffset = req->src_index - TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START;
431 CSL_REG32_WR(&rmObj->udmapRegs.pRxChanCfgRegs->CHAN[chOffset].ROES[0], CSL_FMK(UDMAP_RXCCFG_CHAN_ROES_EVT_NUM, req->global_event));
432 }
433 else
434 {
435 /* RX EOES programming */
436 chOffset = req->src_index - TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START;
437 CSL_REG32_WR(&rmObj->udmapRegs.pRxChanCfgRegs->CHAN[chOffset].REOES[0], CSL_FMK(UDMAP_RXCCFG_CHAN_REOES_EVT_NUM, req->global_event));
438 }
439 }
440 }
442 /* Program IA/VINT */
443 if((TISCI_DEV_NAVSS0_UDMASS_INTAGGR_0 == req->ia_id) ||
444 (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0 == req->ia_id))
445 {
446 if((TISCI_MSG_VALUE_RM_IA_ID_VALID & req->valid_params) &&
447 (TISCI_MSG_VALUE_RM_VINT_VALID & req->valid_params) &&
448 (TISCI_MSG_VALUE_RM_VINT_STATUS_BIT_INDEX_VALID & req->valid_params))
449 {
450 rmObj = &gSciUdmaRmObjMain;
451 eventOffset = req->global_event & 0x1FFFU; /* Max 8K events */
452 if(TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0 == req->ia_id)
453 {
454 rmObj = &gSciUdmaRmObjMcu;
455 eventOffset = req->global_event & 0x7FFU; /* Max 2K events */
456 }
458 vintrBitNum = req->vint * 64U;
459 vintrBitNum += req->vint_status_bit_index;
460 retVal += CSL_intaggrMapEventIntr(
461 &rmObj->iaRegs, eventOffset, vintrBitNum);
462 retVal += CSL_intaggrClrIntr(&rmObj->iaRegs, vintrBitNum);
463 retVal += CSL_intaggrSetIntrEnable(&rmObj->iaRegs, vintrBitNum, TRUE);
464 }
465 }
467 /* Program IR */
468 if((TISCI_MSG_VALUE_RM_DST_ID_VALID & req->valid_params) &&
469 (TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID & req->valid_params) &&
470 (TISCI_MSG_VALUE_RM_VINT_VALID & req->valid_params) &&
471 (TISCI_MSG_VALUE_RM_IA_ID_VALID & req->valid_params))
472 {
473 rmObj = &gSciUdmaRmObjMain;
474 if(TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0 == req->ia_id)
475 {
476 rmObj = &gSciUdmaRmObjMcu;
477 }
479 #if defined (SOC_J721E) || defined (SOC_J7200)
480 /* Program GIC IR */
481 if(TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS == req->dst_id)
482 {
483 if(req->dst_host_irq <= CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_63)
484 {
485 irOffset = req->dst_host_irq - CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_0;
486 }
487 else
488 {
489 irOffset = req->dst_host_irq - CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_64;
490 irOffset += 64U;
491 }
493 CSL_intrRouterCfgMux(&rmObj->irRegs, req->vint, irOffset);
494 }
496 /* Program C66x IR */
497 if((TISCI_DEV_C66SS0 == req->dst_id) ||
498 (TISCI_DEV_C66SS1 == req->dst_id))
499 {
500 //TODO: Hack till proper core support in TISCI
501 #if defined (BUILD_C66X_1) || defined (BUILD_C66X_2)
502 CSL_IntrRouterCfg c66xIrRegs;
503 uint32_t c66xIrOffset;
505 /* Program NAVSS IR */
506 #if defined (BUILD_C66X_1)
507 irOffset = (req->dst_host_irq - CSLR_C66_COREPAC0_C66_EVENT_IN_C66_0_INTROUTER0_OUTL_54) + 320;
508 #endif
509 #if defined (BUILD_C66X_2)
510 irOffset = (req->dst_host_irq - CSLR_C66_COREPAC1_C66_EVENT_IN_C66_1_INTROUTER0_OUTL_54) + 352;
511 #endif
512 CSL_intrRouterCfgMux(&rmObj->irRegs, req->vint, irOffset);
514 /* Program C66x IR */
515 c66xIrRegs.pIntdRegs = (CSL_intr_router_intd_cfgRegs *) NULL;
516 c66xIrRegs.numInputIntrs = 400;
517 c66xIrRegs.numOutputIntrs = 97;
518 #if defined (BUILD_C66X_1)
519 c66xIrRegs.pIntrRouterRegs = (CSL_intr_router_cfgRegs *) 0x10000000;
520 c66xIrOffset = (req->dst_host_irq - CSLR_C66_COREPAC0_C66_EVENT_IN_C66_0_INTROUTER0_OUTL_54) + 54;
521 #endif
522 #if defined (BUILD_C66X_2)
523 c66xIrRegs.pIntrRouterRegs = (CSL_intr_router_cfgRegs *) 0x10000000;
524 c66xIrOffset = (req->dst_host_irq - CSLR_C66_COREPAC1_C66_EVENT_IN_C66_1_INTROUTER0_OUTL_54) + 54;
525 #endif
526 CSL_intrRouterCfgMux(&c66xIrRegs, 0, c66xIrOffset);
527 #endif /* (BUILD_C66X_1) || (BUILD_C66X_2) */
528 }
530 /* Program MCU1 IR */
531 if((TISCI_DEV_MCU_R5FSS0_CORE0 == req->dst_id) ||
532 (TISCI_DEV_MCU_R5FSS0_CORE1 == req->dst_id))
533 {
534 if(req->dst_host_irq >= CSLR_MCU_R5FSS0_CORE0_INTR_MCU_NAVSS0_INTR_ROUTER_0_OUTL_INTR_0)
535 {
536 irOffset = req->dst_host_irq - CSLR_MCU_R5FSS0_CORE0_INTR_MCU_NAVSS0_INTR_ROUTER_0_OUTL_INTR_0;
537 CSL_intrRouterCfgMux(&rmObj->irRegs, req->vint, irOffset);
538 }
539 }
541 /* Program MCU2_0 IR */
542 if(TISCI_DEV_R5FSS0_CORE0 == req->dst_id)
543 {
544 if(req->dst_host_irq >= (CSLR_R5FSS0_CORE0_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_192 - 192))
545 {
546 irOffset = req->dst_host_irq - (CSLR_R5FSS0_CORE0_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_192 - 192);
547 CSL_intrRouterCfgMux(&rmObj->irRegs, req->vint, irOffset);
548 }
549 }
551 /* Program MCU2_1 IR */
552 if(TISCI_DEV_R5FSS0_CORE1 == req->dst_id)
553 {
554 if(req->dst_host_irq > (CSLR_R5FSS0_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_224 - 224))
555 {
556 irOffset = req->dst_host_irq - (CSLR_R5FSS0_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_224 - 224);
557 CSL_intrRouterCfgMux(&rmObj->irRegs, req->vint, irOffset);
558 }
559 }
561 /* Program MCU3_0 IR */
562 if(TISCI_DEV_R5FSS1_CORE0 == req->dst_id)
563 {
564 if(req->dst_host_irq >= (CSLR_R5FSS1_CORE0_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_256 - 256))
565 {
566 irOffset = req->dst_host_irq - (CSLR_R5FSS0_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_224 - 256);
567 CSL_intrRouterCfgMux(&rmObj->irRegs, req->vint, irOffset);
568 }
569 }
571 /* Program MCU3_1 IR */
572 if(TISCI_DEV_R5FSS1_CORE1 == req->dst_id)
573 {
574 if(req->dst_host_irq >= (CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_288 - 288))
575 {
576 irOffset = req->dst_host_irq - (CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_288 - 288);
577 CSL_intrRouterCfgMux(&rmObj->irRegs, req->vint, irOffset);
578 }
579 }
581 /* Program NAVSS IR, used for IPC/Mailbox */
582 if( TISCI_DEV_NAVSS0_INTR_ROUTER_0 == req->dst_id)
583 {
584 irOffset = req->dst_host_irq;
585 CSL_intrRouterCfgMux(&rmObj->irRegs, req->vint, irOffset);
586 }
588 #else /* J721E */
589 /* Program GIC IR */
590 if(TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS == req->dst_id)
591 {
592 if(req->dst_host_irq <= CSL_GIC0_INTR_NAVSS0_BUS_A53_PEND_63)
593 {
594 irOffset = req->dst_host_irq - CSL_GIC0_INTR_NAVSS0_BUS_A53_PEND_0;
595 }
596 else
597 {
598 irOffset = req->dst_host_irq - CSL_GIC0_INTR_NAVSS0_BUS_A53_PEND_64;
599 irOffset += 64U;
600 }
602 CSL_intrRouterCfgMux(&rmObj->irRegs, req->vint, irOffset);
603 }
605 /* Program MCU IR */
606 if((TISCI_DEV_MCU_R5FSS0_CORE0 == req->dst_id) ||
607 (TISCI_DEV_MCU_R5FSS0_CORE1 == req->dst_id))
608 {
609 irOffset = req->dst_host_irq - CSL_MCU0_INTR_NAVSS0_R5_0_PEND_0;
610 CSL_intrRouterCfgMux(&rmObj->irRegs, req->vint, irOffset);
611 }
612 #endif
613 }
615 return (retVal);
616 }
618 int32_t Sciclient_rmIrqRelease(const struct tisci_msg_rm_irq_release_req *req,
619 uint32_t timeout)
620 {
621 int32_t retVal = CSL_PASS;
622 uint16_t eventOffset; /* Within a IA - convert from global to local offset within IA */
623 uint32_t chOffset; /* Within a UDMA - convert from global source index to local offset within UDMAP */
624 uint32_t irOffset; /* Within a IR - convert from cpu dest interrupt index to local IR offset within UDMAP */
625 uint64_t vintrBitNum;
626 SciUdmaRmObj *rmObj;
628 /* Reset ring OES */
629 if((TISCI_DEV_NAVSS0_RINGACC0 == req->src_id) ||
630 (TISCI_DEV_MCU_NAVSS0_RINGACC0 == req->src_id))
631 {
632 rmObj = &gSciUdmaRmObjMain;
633 if(TISCI_DEV_MCU_NAVSS0_RINGACC0 == req->src_id)
634 {
635 rmObj = &gSciUdmaRmObjMcu;
636 }
638 if(TISCI_MSG_VALUE_RM_GLOBAL_EVENT_VALID & req->valid_params)
639 {
640 retVal += CSL_ringaccSetEvent(
641 &rmObj->raRegs, req->src_index, CSL_UDMAP_NO_EVENT);
642 }
643 }
645 /* Reset channel OES */
646 if((TISCI_DEV_NAVSS0_UDMAP0 == req->src_id) ||
647 (TISCI_DEV_MCU_NAVSS0_UDMAP0 == req->src_id))
648 {
649 rmObj = &gSciUdmaRmObjMain;
650 if(TISCI_DEV_MCU_NAVSS0_UDMAP0 == req->src_id)
651 {
652 rmObj = &gSciUdmaRmObjMcu;
653 }
655 if(TISCI_MSG_VALUE_RM_GLOBAL_EVENT_VALID & req->valid_params)
656 {
657 if(req->src_index < TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START)
658 {
659 /* TX OES programming */
660 chOffset = req->src_index;
661 CSL_REG32_WR(&rmObj->udmapRegs.pTxChanCfgRegs->CHAN[chOffset].TOES[0], CSL_FMK(UDMAP_TXCCFG_CHAN_TOES_EVT_NUM, CSL_UDMAP_NO_EVENT));
662 }
663 else if(req->src_index < TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START)
664 {
665 /* TX EOES programming */
666 chOffset = req->src_index - TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START;
667 CSL_REG32_WR(&rmObj->udmapRegs.pTxChanCfgRegs->CHAN[chOffset].TEOES[0], CSL_FMK(UDMAP_TXCCFG_CHAN_TEOES_EVT_NUM, CSL_UDMAP_NO_EVENT));
668 }
669 else if(req->src_index < TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START)
670 {
671 /* RX OES programming */
672 chOffset = req->src_index - TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START;
673 CSL_REG32_WR(&rmObj->udmapRegs.pRxChanCfgRegs->CHAN[chOffset].ROES[0], CSL_FMK(UDMAP_RXCCFG_CHAN_ROES_EVT_NUM, CSL_UDMAP_NO_EVENT));
674 }
675 else
676 {
677 /* RX EOES programming */
678 chOffset = req->src_index - TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START;
679 CSL_REG32_WR(&rmObj->udmapRegs.pRxChanCfgRegs->CHAN[chOffset].REOES[0], CSL_FMK(UDMAP_RXCCFG_CHAN_REOES_EVT_NUM, CSL_UDMAP_NO_EVENT));
680 }
681 }
682 }
684 /* Disable IA/VINT */
685 if((TISCI_DEV_NAVSS0_UDMASS_INTAGGR_0 == req->ia_id) ||
686 (TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0 == req->ia_id))
687 {
688 if((TISCI_MSG_VALUE_RM_IA_ID_VALID & req->valid_params) &&
689 (TISCI_MSG_VALUE_RM_VINT_VALID & req->valid_params) &&
690 (TISCI_MSG_VALUE_RM_VINT_STATUS_BIT_INDEX_VALID & req->valid_params))
691 {
692 rmObj = &gSciUdmaRmObjMain;
693 eventOffset = req->global_event & 0x1FFFU; /* Max 8K events */
694 if(TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0 == req->ia_id)
695 {
696 rmObj = &gSciUdmaRmObjMcu;
697 eventOffset = req->global_event & 0x7FFU; /* Max 2K events */
698 }
700 vintrBitNum = req->vint * 64U;
701 vintrBitNum += req->vint_status_bit_index;
702 retVal += CSL_intaggrMapEventIntr(&rmObj->iaRegs, eventOffset, 0U);
703 retVal += CSL_intaggrSetIntrEnable(&rmObj->iaRegs, vintrBitNum, FALSE);
704 retVal += CSL_intaggrClrIntr(&rmObj->iaRegs, vintrBitNum);
705 }
706 }
708 /* Reset IR */
709 if((TISCI_MSG_VALUE_RM_DST_ID_VALID & req->valid_params) &&
710 (TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID & req->valid_params) &&
711 (TISCI_MSG_VALUE_RM_VINT_VALID & req->valid_params) &&
712 (TISCI_MSG_VALUE_RM_IA_ID_VALID & req->valid_params))
713 {
714 rmObj = &gSciUdmaRmObjMain;
715 if(TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0 == req->ia_id)
716 {
717 rmObj = &gSciUdmaRmObjMcu;
718 }
720 #if defined (SOC_J721E)
721 /* Reset GIC IR */
722 if(TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS == req->dst_id)
723 {
724 if(req->dst_host_irq <= CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_63)
725 {
726 irOffset = req->dst_host_irq - CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_0;
727 }
728 else
729 {
730 irOffset = req->dst_host_irq - CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_64;
731 irOffset += 64U;
732 }
734 CSL_intrRouterCfgMux(&rmObj->irRegs, 0U, irOffset);
735 }
737 /* Reset MCU IR */
738 if((TISCI_DEV_C66SS0 == req->dst_id) ||
739 (TISCI_DEV_C66SS1 == req->dst_id))
740 {
741 #if defined (BUILD_C66X_1) || defined (BUILD_C66X_2)
742 CSL_IntrRouterCfg c66xIrRegs;
743 uint32_t c66xIrOffset;
745 /* Program NAVSS IR */
746 #if defined (BUILD_C66X_1)
747 irOffset = (req->dst_host_irq - CSLR_C66_COREPAC0_C66_EVENT_IN_C66_0_INTROUTER0_OUTL_54) + 320;
748 #endif
749 #if defined (BUILD_C66X_2)
750 irOffset = (req->dst_host_irq - CSLR_C66_COREPAC1_C66_EVENT_IN_C66_1_INTROUTER0_OUTL_54) + 352;
751 #endif
752 CSL_intrRouterCfgMux(&rmObj->irRegs, 0U, irOffset);
754 /* Program C66x IR */
755 c66xIrRegs.pIntdRegs = (CSL_intr_router_intd_cfgRegs *) NULL;
756 c66xIrRegs.numInputIntrs = 400;
757 c66xIrRegs.numOutputIntrs = 97;
758 #if defined (BUILD_C66X_1)
759 c66xIrRegs.pIntrRouterRegs = (CSL_intr_router_cfgRegs *) 0x10000000;
760 c66xIrOffset = (req->dst_host_irq - CSLR_C66_COREPAC0_C66_EVENT_IN_C66_0_INTROUTER0_OUTL_54) + 54;
761 #endif
762 #if defined (BUILD_C66X_2)
763 c66xIrRegs.pIntrRouterRegs = (CSL_intr_router_cfgRegs *) 0x10000000;
764 c66xIrOffset = (req->dst_host_irq - CSLR_C66_COREPAC1_C66_EVENT_IN_C66_1_INTROUTER0_OUTL_54) + 54;
765 #endif
766 CSL_intrRouterCfgMux(&c66xIrRegs, 0U, c66xIrOffset);
767 #else
768 //TODO: Hack till proper core support in TISCI
769 if(req->dst_host_irq >= CSLR_R5FSS0_CORE0_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_192)
770 {
771 #if defined (BUILD_MCU2_0) || defined (BUILD_MCU2_1)
772 irOffset = req->dst_host_irq - 32U;
773 if(TISCI_DEV_MCU_R5FSS0_CORE1 == req->dst_id)
774 {
775 irOffset = req->dst_host_irq;
776 }
777 #else
778 irOffset = req->dst_host_irq + 32U;
779 if(TISCI_DEV_MCU_R5FSS0_CORE1 == req->dst_id)
780 {
781 irOffset = req->dst_host_irq + 64U;
782 }
783 #endif
784 }
785 else
786 {
787 irOffset = req->dst_host_irq - CSLR_MCU_R5FSS0_CORE0_INTR_MCU_NAVSS0_INTR_ROUTER_0_OUTL_INTR_0;
788 }
789 CSL_intrRouterCfgMux(&rmObj->irRegs, 0U, irOffset);
790 #endif
791 }
792 #else
793 /* Reset GIC IR */
794 if(TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS == req->dst_id)
795 {
796 if(req->dst_host_irq <= CSL_GIC0_INTR_NAVSS0_BUS_A53_PEND_63)
797 {
798 irOffset = req->dst_host_irq - CSL_GIC0_INTR_NAVSS0_BUS_A53_PEND_0;
799 }
800 else
801 {
802 irOffset = req->dst_host_irq - CSL_GIC0_INTR_NAVSS0_BUS_A53_PEND_64;
803 irOffset += 64U;
804 }
806 CSL_intrRouterCfgMux(&rmObj->irRegs, 0U, irOffset);
807 }
809 /* Reset MCU IR */
810 if((TISCI_DEV_MCU_R5FSS0_CORE0 == req->dst_id) ||
811 (TISCI_DEV_MCU_R5FSS0_CORE1 == req->dst_id))
812 {
813 irOffset = req->dst_host_irq - CSL_MCU0_INTR_NAVSS0_R5_0_PEND_0;
814 CSL_intrRouterCfgMux(&rmObj->irRegs, 0U, irOffset);
815 }
816 #endif
817 }
819 return (retVal);
820 }
822 int32_t Sciclient_rmRingCfg(const struct tisci_msg_rm_ring_cfg_req *req,
823 const struct tisci_msg_rm_ring_cfg_resp *resp,
824 uint32_t timeout)
825 {
826 int32_t retVal = CSL_PASS;
827 uint32_t orderId;
828 CSL_RingAccRingCfg ringCfg;
829 SciUdmaRmObj *rmObj;
831 rmObj = &gSciUdmaRmObjMain;
832 if(TISCI_DEV_MCU_NAVSS0_RINGACC0 == req->nav_id)
833 {
834 rmObj = &gSciUdmaRmObjMcu;
835 }
837 /* Copy params */
838 ringCfg.physBase = ((uint64_t) req->addr_lo |
839 (((uint64_t) req->addr_hi) << 32U));
840 ringCfg.virtBase = (void *) ((uintptr_t) ringCfg.physBase);/* Assume same as physical address */
841 ringCfg.mode = req->mode;
842 ringCfg.elCnt = req->count;
843 ringCfg.elSz = ((uint32_t) 1U << (req->size + 2U));
844 ringCfg.evtNum = CSL_UDMAP_NO_EVENT;
845 ringCfg.credSecure = 0U;
846 ringCfg.credPriv = 0U;
847 ringCfg.credPrivId = CSL_RINGACC_CRED_PASSTHRU;
848 ringCfg.credVirtId = CSL_RINGACC_CRED_PASSTHRU;
849 retVal = CSL_ringaccInitRing(&rmObj->raRegs, req->index, &ringCfg);
851 /* Set order ID */
852 orderId = req->order_id;
853 if(TISCI_MSG_VALUE_RM_NULL_ORDER_ID == orderId)
854 {
855 orderId = CSL_RINGACC_ORDERID_BYPASS;
856 }
857 CSL_ringaccSetRingOrderId(&rmObj->raRegs, &ringCfg, orderId);
859 /* Ring reset */
860 CSL_ringaccResetRing(&rmObj->raRegs, &ringCfg);
862 return (retVal);
863 }
865 int32_t Sciclient_rmRingMonCfg(const struct tisci_msg_rm_ring_mon_cfg_req *req,
866 const struct tisci_msg_rm_ring_mon_cfg_resp *resp,
867 uint32_t timeout)
868 {
869 int32_t retVal = CSL_PASS;
871 /* No plan to support CSL implementation */
873 return (retVal);
874 }
876 int32_t Sciclient_rmUdmapTxChCfg(
877 const struct tisci_msg_rm_udmap_tx_ch_cfg_req *req,
878 const struct tisci_msg_rm_udmap_tx_ch_cfg_resp *resp,
879 uint32_t timeout)
880 {
881 int32_t retVal = CSL_PASS;
882 CSL_UdmapTxChanCfg txChCfg;
883 SciUdmaRmObj *rmObj;
885 rmObj = &gSciUdmaRmObjMain;
886 if(TISCI_DEV_MCU_NAVSS0_UDMAP0 == req->nav_id)
887 {
888 rmObj = &gSciUdmaRmObjMcu;
889 }
891 CSL_udmapInitTxChanCfg(&txChCfg);
893 /* Copy params */
894 txChCfg.pauseOnError = req->tx_pause_on_err;
895 txChCfg.filterEinfo = req->tx_filt_einfo;
896 txChCfg.filterPsWords = req->tx_filt_pswords;
897 txChCfg.addrType = req->tx_atype;
898 txChCfg.chanType = req->tx_chan_type;
899 txChCfg.fetchWordSize = req->tx_fetch_size;
900 txChCfg.trEventNum = CSL_UDMAP_NO_EVENT;
901 txChCfg.errEventNum = CSL_UDMAP_NO_EVENT;
902 txChCfg.busPriority = req->tx_priority;
903 txChCfg.busQos = req->tx_qos;
904 txChCfg.busOrderId = req->tx_orderid;
905 txChCfg.dmaPriority = req->tx_sched_priority;
906 txChCfg.txCredit = req->tx_credit_count;
907 txChCfg.txThread = CSL_REG32_RD(&rmObj->udmapRegs.pTxChanCfgRegs->CHAN[req->index].THREAD);/* Already set in pair - don't overwrite */
908 txChCfg.txTrCQ = req->txcq_qnum;
909 txChCfg.bNoTeardownCompletePkt = req->tx_supr_tdpkt;
911 /* Config UDMAP TX channel */
912 CSL_udmapTxChanCfg(&rmObj->udmapRegs, req->index, &txChCfg);
914 return (retVal);
915 }
917 int32_t Sciclient_rmUdmapRxChCfg(
918 const struct tisci_msg_rm_udmap_rx_ch_cfg_req *req,
919 const struct tisci_msg_rm_udmap_rx_ch_cfg_resp *resp,
920 uint32_t timeout)
921 {
922 int32_t retVal = CSL_PASS;
923 CSL_UdmapRxChanCfg rxChCfg;
924 SciUdmaRmObj *rmObj;
926 rmObj = &gSciUdmaRmObjMain;
927 if(TISCI_DEV_MCU_NAVSS0_UDMAP0 == req->nav_id)
928 {
929 rmObj = &gSciUdmaRmObjMcu;
930 }
932 CSL_udmapInitRxChanCfg(&rxChCfg);
934 /* Copy params */
935 rxChCfg.pauseOnError = req->rx_pause_on_err;
936 rxChCfg.addrType = req->rx_atype;
937 rxChCfg.chanType = req->rx_chan_type;
938 rxChCfg.fetchWordSize = req->rx_fetch_size;
939 rxChCfg.trEventNum = CSL_UDMAP_NO_EVENT;
940 rxChCfg.errEventNum = CSL_UDMAP_NO_EVENT;
941 rxChCfg.busPriority = req->rx_priority;
942 rxChCfg.busQos = req->rx_qos;
943 rxChCfg.busOrderId = req->rx_orderid;
944 rxChCfg.dmaPriority = req->rx_sched_priority;
945 rxChCfg.flowIdFwRangeStart = req->flowid_start;
946 rxChCfg.flowIdFwRangeCnt = req->flowid_cnt;
947 rxChCfg.bIgnoreShortPkts = req->rx_ignore_short;
948 rxChCfg.bIgnoreLongPkts = req->rx_ignore_long;
949 rxChCfg.rxThread = CSL_REG32_RD(&rmObj->udmapRegs.pRxChanCfgRegs->CHAN[req->index].THREAD);/* Already set in pair - don't overwrite */
950 rxChCfg.rxTrCQ = req->rxcq_qnum;
952 /* Config UDMAP RX channel */
953 CSL_udmapRxChanCfg(&rmObj->udmapRegs, req->index, &rxChCfg);
955 return (retVal);
956 }
958 int32_t Sciclient_rmUdmapFlowCfg(
959 const struct tisci_msg_rm_udmap_flow_cfg_req *req,
960 const struct tisci_msg_rm_udmap_flow_cfg_resp *resp,
961 uint32_t timeout)
962 {
963 int32_t retVal = CSL_PASS;
964 CSL_UdmapRxFlowCfg flowCfg;
965 SciUdmaRmObj *rmObj;
967 rmObj = &gSciUdmaRmObjMain;
968 if(TISCI_DEV_MCU_NAVSS0_UDMAP0 == req->nav_id)
969 {
970 rmObj = &gSciUdmaRmObjMcu;
971 }
973 flowCfg.einfoPresent = req->rx_einfo_present;
974 flowCfg.psInfoPresent = req->rx_psinfo_present;
975 flowCfg.errorHandling = req->rx_error_handling;
976 flowCfg.descType = req->rx_desc_type;
977 flowCfg.psLocation = req->rx_ps_location;
978 flowCfg.sopOffset = req->rx_sop_offset;
979 flowCfg.defaultRxCQ = req->rx_dest_qnum;
980 flowCfg.srcTag.loSel = req->rx_src_tag_lo_sel;
981 flowCfg.srcTag.loVal = req->rx_src_tag_lo;
982 flowCfg.srcTag.hiSel = req->rx_src_tag_hi_sel;
983 flowCfg.srcTag.hiVal = req->rx_src_tag_hi;
984 flowCfg.dstTag.loSel = req->rx_dest_tag_lo_sel;
985 flowCfg.dstTag.loVal = req->rx_dest_tag_lo;
986 flowCfg.dstTag.hiSel = req->rx_dest_tag_hi_sel;
987 flowCfg.dstTag.hiVal = req->rx_dest_tag_hi;
988 flowCfg.fdqThresh[0].fEnable = 0U; /* Set through optional config */
989 flowCfg.fdqThresh[0].pktSize = 0U; /* Set through optional config */
990 flowCfg.fdqThresh[0].queue = req->rx_fdq0_sz0_qnum;
991 flowCfg.fdq[0] = req->rx_fdq0_sz0_qnum;
992 flowCfg.fdqThresh[1].fEnable = 0U;
993 flowCfg.fdqThresh[1].pktSize = 0U; /* Set through optional config */
994 flowCfg.fdqThresh[1].queue = req->rx_fdq1_qnum;
995 flowCfg.fdq[1] = req->rx_fdq1_qnum;
996 flowCfg.fdqThresh[2].fEnable = 0U; /* Set through optional config */
997 flowCfg.fdqThresh[2].pktSize = 0U; /* Set through optional config */
998 flowCfg.fdqThresh[2].queue = req->rx_fdq2_qnum;
999 flowCfg.fdq[2] = req->rx_fdq2_qnum;
1000 flowCfg.fdqThresh[3].fEnable = 0U; /* Not Used */
1001 flowCfg.fdqThresh[3].pktSize = 0U; /* Not Used */
1002 flowCfg.fdqThresh[3].queue = req->rx_fdq3_qnum;
1003 flowCfg.fdq[3] = req->rx_fdq3_qnum;
1004 CSL_udmapRxFlowCfg(&rmObj->udmapRegs, req->flow_index, &flowCfg);
1006 return (retVal);
1007 }
1009 int32_t Sciclient_rmUdmapFlowSizeThreshCfg(
1010 const struct tisci_msg_rm_udmap_flow_size_thresh_cfg_req *req,
1011 const struct tisci_msg_rm_udmap_flow_size_thresh_cfg_resp *resp,
1012 uint32_t timeout)
1013 {
1014 int32_t retVal = CSL_PASS;
1015 uint32_t regVal;
1016 SciUdmaRmObj *rmObj;
1018 rmObj = &gSciUdmaRmObjMain;
1019 if(TISCI_DEV_MCU_NAVSS0_UDMAP0 == req->nav_id)
1020 {
1021 rmObj = &gSciUdmaRmObjMcu;
1022 }
1024 regVal = CSL_REG32_RD(&rmObj->udmapRegs.pRxFlowCfgRegs->FLOW[req->flow_index].RFC);
1025 CSL_FINS(regVal, UDMAP_RXFCFG_FLOW_RFC_SIZE_THRESH_EN, req->rx_size_thresh_en);
1026 CSL_REG32_WR(&rmObj->udmapRegs.pRxFlowCfgRegs->FLOW[req->flow_index].RFC, regVal);
1028 regVal = CSL_REG32_RD(&rmObj->udmapRegs.pRxFlowCfgRegs->FLOW[req->flow_index].RFF);
1029 CSL_FINS(regVal, UDMAP_RXFCFG_FLOW_RFF_SIZE_THRESH0, req->rx_size_thresh0);
1030 CSL_FINS(regVal, UDMAP_RXFCFG_FLOW_RFF_SIZE_THRESH1, req->rx_size_thresh1);
1031 CSL_REG32_WR(&rmObj->udmapRegs.pRxFlowCfgRegs->FLOW[req->flow_index].RFF, regVal);
1033 regVal = CSL_REG32_RD(&rmObj->udmapRegs.pRxFlowCfgRegs->FLOW[req->flow_index].RFG);
1034 CSL_FINS(regVal, UDMAP_RXFCFG_FLOW_RFG_SIZE_THRESH2, req->rx_size_thresh2);
1035 CSL_FINS(regVal, UDMAP_RXFCFG_FLOW_RFG_FDQ0_SZ1_QNUM, req->rx_fdq0_sz1_qnum);
1036 CSL_REG32_WR(&rmObj->udmapRegs.pRxFlowCfgRegs->FLOW[req->flow_index].RFG, regVal);
1038 regVal = CSL_REG32_RD(&rmObj->udmapRegs.pRxFlowCfgRegs->FLOW[req->flow_index].RFH);
1039 CSL_FINS(regVal, UDMAP_RXFCFG_FLOW_RFH_FDQ0_SZ2_QNUM, req->rx_fdq0_sz2_qnum);
1040 CSL_FINS(regVal, UDMAP_RXFCFG_FLOW_RFH_FDQ0_SZ2_QNUM, req->rx_fdq0_sz3_qnum);
1041 CSL_REG32_WR(&rmObj->udmapRegs.pRxFlowCfgRegs->FLOW[req->flow_index].RFH, regVal);
1043 return (retVal);
1044 }
1046 int32_t Sciclient_rmPsilPair(const struct tisci_msg_rm_psil_pair_req *req,
1047 uint32_t timeout)
1048 {
1049 int32_t retVal = CSL_PASS;
1050 uint32_t chIdx;
1051 bool cslRetVal;
1052 SciUdmaRmObj *rmObj;
1054 rmObj = &gSciUdmaRmObjMain;
1055 if(TISCI_DEV_MCU_NAVSS0 == req->nav_id)
1056 {
1057 rmObj = &gSciUdmaRmObjMcu;
1058 }
1060 /* Pair source thread with destination thread */
1061 cslRetVal = CSL_psilcfgCreateRoute(
1062 rmObj->psilCfgRegs, req->src_thread, req->dst_thread);
1063 if(TRUE != cslRetVal)
1064 {
1065 retVal = CSL_EFAIL;
1066 }
1068 if((req->src_thread >= rmObj->txUdmaThreadIdStart) &&
1069 (req->src_thread <= rmObj->txUdmaThreadIdEnd))
1070 {
1071 /* Program peer thread ID to TX channel */
1072 chIdx = req->src_thread - rmObj->txUdmaThreadIdStart;
1073 CSL_REG32_WR(&rmObj->udmapRegs.pTxChanCfgRegs->CHAN[chIdx].THREAD, req->dst_thread);
1074 }
1075 if((req->dst_thread >= rmObj->rxUdmaThreadIdStart) &&
1076 (req->dst_thread <= rmObj->rxUdmaThreadIdEnd))
1077 {
1078 /* Program peer thread ID to RX channel */
1079 chIdx = req->dst_thread - rmObj->rxUdmaThreadIdStart;
1080 CSL_REG32_WR(&rmObj->udmapRegs.pRxChanCfgRegs->CHAN[chIdx].THREAD, req->src_thread);
1081 }
1083 return (retVal);
1084 }
1086 int32_t Sciclient_rmPsilUnpair(const struct tisci_msg_rm_psil_unpair_req *req,
1087 uint32_t timeout)
1088 {
1089 int32_t retVal = CSL_PASS;
1090 bool cslRetVal;
1091 SciUdmaRmObj *rmObj;
1093 rmObj = &gSciUdmaRmObjMain;
1094 if(TISCI_DEV_MCU_NAVSS0 == req->nav_id)
1095 {
1096 rmObj = &gSciUdmaRmObjMcu;
1097 }
1099 cslRetVal = CSL_psilcfgSetThreadRealtimeEnable(
1100 rmObj->psilCfgRegs, req->src_thread, FALSE);
1101 if(TRUE != cslRetVal)
1102 {
1103 retVal = CSL_EFAIL;
1104 }
1106 cslRetVal = CSL_psilcfgSetThreadRealtimeEnable(
1107 rmObj->psilCfgRegs, req->dst_thread, FALSE);
1108 if(TRUE != cslRetVal)
1109 {
1110 retVal = CSL_EFAIL;
1111 }
1113 return (retVal);
1114 }
1116 int32_t Sciclient_rmUdmapGcfgCfg(
1117 const struct tisci_msg_rm_udmap_gcfg_cfg_req *req,
1118 const struct tisci_msg_rm_udmap_gcfg_cfg_resp *resp,
1119 uint32_t timeout)
1120 {
1121 int32_t retVal = CSL_PASS;
1123 /* Not required to be supported in CSL method. Just return pass */
1125 return (retVal);
1126 }
1128 int32_t Sciclient_rmPsilRead(const struct tisci_msg_rm_psil_read_req *req,
1129 struct tisci_msg_rm_psil_read_resp *resp,
1130 uint32_t timeout)
1131 {
1132 int32_t retVal = CSL_PASS;
1133 bool cslRetVal;
1134 SciUdmaRmObj *rmObj;
1136 rmObj = &gSciUdmaRmObjMain;
1137 if(TISCI_DEV_MCU_NAVSS0 == req->nav_id)
1138 {
1139 rmObj = &gSciUdmaRmObjMcu;
1140 }
1142 cslRetVal = CSL_psilcfgRead(
1143 rmObj->psilCfgRegs,
1144 req->thread,
1145 req->taddr,
1146 &resp->data);
1147 if(TRUE != cslRetVal)
1148 {
1149 retVal = CSL_EFAIL;
1150 }
1152 return (retVal);
1153 }
1155 int32_t Sciclient_rmPsilWrite(const struct tisci_msg_rm_psil_write_req *req,
1156 uint32_t timeout)
1157 {
1158 int32_t retVal = CSL_PASS;
1159 bool cslRetVal;
1160 SciUdmaRmObj *rmObj;
1162 rmObj = &gSciUdmaRmObjMain;
1163 if(TISCI_DEV_MCU_NAVSS0 == req->nav_id)
1164 {
1165 rmObj = &gSciUdmaRmObjMcu;
1166 }
1168 cslRetVal = CSL_psilcfgWrite(
1169 rmObj->psilCfgRegs,
1170 req->thread,
1171 req->taddr,
1172 req->data);
1173 if(TRUE != cslRetVal)
1174 {
1175 retVal = CSL_EFAIL;
1176 }
1178 return (retVal);
1179 }
1182 /* -------------------------------------------------------------------------- */
1183 /* Internal Function Definitions */
1184 /* -------------------------------------------------------------------------- */
1186 /* None */