1 /**
2 * \file SPI_soc.c
3 *
4 * \brief AM64X device specific hardware attributes.
5 *
6 */
8 /*
9 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/csl/soc/am64x/src/cslr_soc.h>
42 #include <ti/csl/soc/am64x/src/csl_psilcfg_thread_map.h>
43 #include <ti/drv/spi/soc/SPI_soc.h>
45 #define MCSPI_PER_CNT (7U)
46 #define OSPI_PER_CNT (1U)
47 #define SPI_PER_CNT (MCSPI_PER_CNT + OSPI_PER_CNT)
49 /* SPI configuration structure */
50 SPI_v1_HWAttrs spiInitCfg[MCSPI_PER_CNT] =
51 {
52 {
53 /* McSPI0 on the Main domain */
54 CSL_MCSPI0_CFG_BASE, /* baseAddr */
55 #if defined (BUILD_MPU)
56 /* A53 cores on the Main domain */
57 CSLR_GICSS0_SPI_MCSPI0_INTR_SPI_0, /* intNum */
58 #elif defined (BUILD_MCU)
59 /* R5 cores on the Main domain */
60 CSLR_R5FSS0_CORE0_INTR_MCSPI0_INTR_SPI_0,
61 #else
62 /* M4 core on the MCU Channel */
63 0U, /* TBD, no MCSPI0 interrupt routed to M4 core */
64 #endif
65 0, /* eventId */
66 SPI_PINMODE_4_PIN, /* pinMode */
67 MCSPI_CHANNEL_0, /* chNum */
68 MCSPI_SINGLE_CH, /* chMode */
69 true, /* enableIntr */
70 48000000, /* inputClkFreq */
71 MCSPI_INITDLY_0, /* initDelay */
72 MCSPI_RX_TX_FIFO_SIZE, /* rxTrigLvl */
73 MCSPI_RX_TX_FIFO_SIZE, /* txTrigLvl */
74 {
75 {
76 MCSPI_CS_POL_LOW, /* csPolarity */
77 MCSPI_DATA_LINE_COMM_MODE_7, /* dataLineCommMode */
78 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY, /* tcs */
79 MCSPI_TX_RX_MODE, /* trMode */
80 },
81 {
82 MCSPI_CS_POL_LOW,
83 MCSPI_DATA_LINE_COMM_MODE_7,
84 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
85 MCSPI_TX_RX_MODE,
86 },
87 {
88 MCSPI_CS_POL_LOW,
89 MCSPI_DATA_LINE_COMM_MODE_7,
90 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
91 MCSPI_TX_RX_MODE,
92 },
93 {
94 MCSPI_CS_POL_LOW,
95 MCSPI_DATA_LINE_COMM_MODE_7,
96 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
97 MCSPI_TX_RX_MODE,
98 },
99 },
100 CSL_PDMA_CH_MAIN0_MCSPI0_CH0_RX, /* rxDmaEventNumber */
101 CSL_PDMA_CH_MAIN0_MCSPI0_CH0_TX, /* txDmaEventNumber */
102 0, /* edmaTxTCC */
103 0, /* edmaRxTCC */
104 0, /* edmaTxTC */
105 0, /* edmaRxTC */
106 NULL, /* edmaHandle */
107 false, /* dmaMode */
108 NULL /* dmaInfo */
109 },
110 {
111 /* McSPI1 on the Main domain */
112 CSL_MCSPI1_CFG_BASE,
113 #if defined (BUILD_MPU)
114 CSLR_GICSS0_SPI_MCSPI1_INTR_SPI_0,
115 #elif defined (BUILD_MCU)
116 CSLR_R5FSS0_CORE0_INTR_MCSPI1_INTR_SPI_0,
117 #else
118 0U,
119 #endif
120 0,
121 SPI_PINMODE_4_PIN,
122 MCSPI_CHANNEL_0,
123 MCSPI_SINGLE_CH,
124 true,
125 48000000,
126 MCSPI_INITDLY_0,
127 MCSPI_RX_TX_FIFO_SIZE,
128 MCSPI_RX_TX_FIFO_SIZE,
129 {
130 {
131 MCSPI_CS_POL_LOW,
132 MCSPI_DATA_LINE_COMM_MODE_7,
133 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
134 MCSPI_TX_RX_MODE,
135 },
136 {
137 MCSPI_CS_POL_LOW,
138 MCSPI_DATA_LINE_COMM_MODE_7,
139 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
140 MCSPI_TX_RX_MODE,
141 },
142 {
143 MCSPI_CS_POL_LOW,
144 MCSPI_DATA_LINE_COMM_MODE_7,
145 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
146 MCSPI_TX_RX_MODE,
147 },
148 {
149 MCSPI_CS_POL_LOW,
150 MCSPI_DATA_LINE_COMM_MODE_7,
151 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
152 MCSPI_TX_RX_MODE,
153 },
154 },
155 CSL_PDMA_CH_MAIN0_MCSPI1_CH0_RX,
156 CSL_PDMA_CH_MAIN0_MCSPI1_CH0_TX,
157 0,
158 0,
159 0,
160 0,
161 NULL,
162 false,
163 NULL
164 },
165 {
166 /* McSPI2 on the Main domain */
167 CSL_MCSPI2_CFG_BASE,
168 #if defined (BUILD_MPU)
169 CSLR_GICSS0_SPI_MCSPI2_INTR_SPI_0,
170 #elif defined (BUILD_MCU)
171 CSLR_R5FSS0_CORE0_INTR_MCSPI2_INTR_SPI_0,
172 #else
173 0U,
174 #endif
175 0,
176 SPI_PINMODE_4_PIN,
177 MCSPI_CHANNEL_0,
178 MCSPI_SINGLE_CH,
179 true,
180 48000000,
181 MCSPI_INITDLY_0,
182 MCSPI_RX_TX_FIFO_SIZE,
183 MCSPI_RX_TX_FIFO_SIZE,
184 {
185 {
186 MCSPI_CS_POL_LOW,
187 MCSPI_DATA_LINE_COMM_MODE_7,
188 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
189 MCSPI_TX_RX_MODE,
190 },
191 {
192 MCSPI_CS_POL_LOW,
193 MCSPI_DATA_LINE_COMM_MODE_7,
194 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
195 MCSPI_TX_RX_MODE,
196 },
197 {
198 MCSPI_CS_POL_LOW,
199 MCSPI_DATA_LINE_COMM_MODE_7,
200 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
201 MCSPI_TX_RX_MODE,
202 },
203 {
204 MCSPI_CS_POL_LOW,
205 MCSPI_DATA_LINE_COMM_MODE_7,
206 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
207 MCSPI_TX_RX_MODE,
208 },
209 },
210 CSL_PDMA_CH_MAIN0_MCSPI2_CH0_RX,
211 CSL_PDMA_CH_MAIN0_MCSPI2_CH0_TX,
212 0,
213 0,
214 0,
215 0,
216 NULL,
217 false,
218 NULL
219 },
220 {
221 /* McSPI3 on the Main domain */
222 CSL_MCSPI3_CFG_BASE,
223 #if defined (BUILD_MPU)
224 CSLR_GICSS0_SPI_MCSPI3_INTR_SPI_0,
225 #elif defined (BUILD_MCU)
226 CSLR_R5FSS0_CORE0_INTR_MCSPI3_INTR_SPI_0,
227 #else
228 0U,
229 #endif
230 0,
231 SPI_PINMODE_4_PIN,
232 MCSPI_CHANNEL_0,
233 MCSPI_SINGLE_CH,
234 true,
235 48000000,
236 MCSPI_INITDLY_0,
237 MCSPI_RX_TX_FIFO_SIZE,
238 MCSPI_RX_TX_FIFO_SIZE,
239 {
240 {
241 MCSPI_CS_POL_LOW,
242 MCSPI_DATA_LINE_COMM_MODE_7,
243 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
244 MCSPI_TX_RX_MODE,
245 },
246 {
247 MCSPI_CS_POL_LOW,
248 MCSPI_DATA_LINE_COMM_MODE_7,
249 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
250 MCSPI_TX_RX_MODE,
251 },
252 {
253 MCSPI_CS_POL_LOW,
254 MCSPI_DATA_LINE_COMM_MODE_7,
255 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
256 MCSPI_TX_RX_MODE,
257 },
258 {
259 MCSPI_CS_POL_LOW,
260 MCSPI_DATA_LINE_COMM_MODE_7,
261 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
262 MCSPI_TX_RX_MODE,
263 },
264 },
265 CSL_PDMA_CH_MAIN0_MCSPI3_CH0_RX,
266 CSL_PDMA_CH_MAIN0_MCSPI3_CH0_TX,
267 0,
268 0,
269 0,
270 0,
271 NULL,
272 false,
273 NULL
274 },
275 {
276 /* McSPI4 on the Main domain */
277 CSL_MCSPI4_CFG_BASE,
278 #if defined (BUILD_MPU)
279 CSLR_GICSS0_SPI_MCSPI4_INTR_SPI_0,
280 #elif defined (BUILD_MCU)
281 CSLR_R5FSS0_CORE0_INTR_MCSPI4_INTR_SPI_0,
282 #else
283 0U,
284 #endif
285 0,
286 SPI_PINMODE_4_PIN,
287 MCSPI_CHANNEL_0,
288 MCSPI_SINGLE_CH,
289 true,
290 48000000,
291 MCSPI_INITDLY_0,
292 MCSPI_RX_TX_FIFO_SIZE,
293 MCSPI_RX_TX_FIFO_SIZE,
294 {
295 {
296 MCSPI_CS_POL_LOW,
297 MCSPI_DATA_LINE_COMM_MODE_7,
298 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
299 MCSPI_TX_RX_MODE,
300 },
301 {
302 MCSPI_CS_POL_LOW,
303 MCSPI_DATA_LINE_COMM_MODE_7,
304 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
305 MCSPI_TX_RX_MODE,
306 },
307 {
308 MCSPI_CS_POL_LOW,
309 MCSPI_DATA_LINE_COMM_MODE_7,
310 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
311 MCSPI_TX_RX_MODE,
312 },
313 {
314 MCSPI_CS_POL_LOW,
315 MCSPI_DATA_LINE_COMM_MODE_7,
316 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
317 MCSPI_TX_RX_MODE,
318 },
319 },
320 CSL_PDMA_CH_MAIN1_MCSPI4_CH0_RX,
321 CSL_PDMA_CH_MAIN1_MCSPI4_CH0_TX,
322 0,
323 0,
324 0,
325 0,
326 NULL,
327 false,
328 NULL
329 },
330 {
331 /* McSPI0 on the MCU Channel */
332 CSL_MCU_MCSPI0_CFG_BASE,
333 #if defined (BUILD_MPU)
334 CSLR_GICSS0_SPI_MCU_MCSPI0_INTR_SPI_0,
335 #elif defined (BUILD_MCU)
336 CSLR_R5FSS0_CORE0_INTR_MCU_MCSPI0_INTR_SPI_0,
337 #else
338 CSLR_MCU_M4FSS0_CORE0_NVIC_MCU_MCSPI0_INTR_SPI_0,
339 #endif
340 0,
341 SPI_PINMODE_4_PIN,
342 MCSPI_CHANNEL_0,
343 MCSPI_SINGLE_CH,
344 true,
345 48000000,
346 MCSPI_INITDLY_0,
347 MCSPI_RX_TX_FIFO_SIZE,
348 MCSPI_RX_TX_FIFO_SIZE,
349 {
350 {
351 MCSPI_CS_POL_LOW,
352 MCSPI_DATA_LINE_COMM_MODE_7,
353 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
354 MCSPI_TX_RX_MODE,
355 },
356 {
357 MCSPI_CS_POL_LOW,
358 MCSPI_DATA_LINE_COMM_MODE_7,
359 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
360 MCSPI_TX_RX_MODE,
361 },
362 {
363 MCSPI_CS_POL_LOW,
364 MCSPI_DATA_LINE_COMM_MODE_7,
365 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
366 MCSPI_TX_RX_MODE,
367 },
368 {
369 MCSPI_CS_POL_LOW,
370 MCSPI_DATA_LINE_COMM_MODE_7,
371 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
372 MCSPI_TX_RX_MODE,
373 },
374 },
375 0, /* PDMA not supported for peripherals on MCU channel */
376 0,
377 0,
378 0,
379 0,
380 0,
381 NULL,
382 false,
383 NULL
384 },
385 {
386 /* McSPI1 on the MCU Channel */
387 CSL_MCU_MCSPI1_CFG_BASE,
388 #if defined (BUILD_MPU)
389 CSLR_GICSS0_SPI_MCU_MCSPI1_INTR_SPI_0,
390 #elif defined (BUILD_MCU)
391 CSLR_R5FSS0_CORE0_INTR_MCU_MCSPI1_INTR_SPI_0,
392 #else
393 CSLR_MCU_M4FSS0_CORE0_NVIC_MCU_MCSPI1_INTR_SPI_0,
394 #endif
395 0,
396 SPI_PINMODE_4_PIN,
397 MCSPI_CHANNEL_0,
398 MCSPI_SINGLE_CH,
399 true,
400 48000000,
401 MCSPI_INITDLY_0,
402 MCSPI_RX_TX_FIFO_SIZE,
403 MCSPI_RX_TX_FIFO_SIZE,
404 {
405 {
406 MCSPI_CS_POL_LOW,
407 MCSPI_DATA_LINE_COMM_MODE_7,
408 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
409 MCSPI_TX_RX_MODE,
410 },
411 {
412 MCSPI_CS_POL_LOW,
413 MCSPI_DATA_LINE_COMM_MODE_7,
414 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
415 MCSPI_TX_RX_MODE,
416 },
417 {
418 MCSPI_CS_POL_LOW,
419 MCSPI_DATA_LINE_COMM_MODE_7,
420 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
421 MCSPI_TX_RX_MODE,
422 },
423 {
424 MCSPI_CS_POL_LOW,
425 MCSPI_DATA_LINE_COMM_MODE_7,
426 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
427 MCSPI_TX_RX_MODE,
428 },
429 },
430 0,
431 0,
432 0,
433 0,
434 0,
435 0,
436 NULL,
437 false,
438 NULL
439 }
440 };
443 /* SPI objects */
444 SPI_v1_Object SpiObjects[MCSPI_PER_CNT];
446 /* OSPI configuration structure */
447 OSPI_v0_HwAttrs ospiInitCfg =
448 {
449 /* OSPI0 on the Main domain */
450 CSL_FSS0_OSPI0_CTRL_BASE, /* baseAddr, flash config register baseAddr */
451 #if defined (BUILD_MPU)
452 /* A53 cores on the Main domain */
453 CSL_FSS0_DAT_REG0_BASE, /* dataAddr, OSPI data base address */
454 #elif defined (BUILD_MCU)
455 /* R5 cores on the Main domain */
456 CSL_FSS0_DAT_REG1_BASE,
457 #else
458 /* M4 core on the MCU channel */
459 CSL_FSS0_DAT_REG1_BASE,
460 #endif
461 OSPI_MODULE_CLOCK, /* funcClk, input frequency */
462 #if defined (BUILD_MPU)
463 CSLR_GICSS0_SPI_FSS0_OSPI_0_OSPI_LVL_INTR_0, /* intrNum, interrupt number */
464 #elif defined (BUILD_MCU)
465 CSLR_R5FSS0_CORE0_INTR_FSS0_OSPI_0_OSPI_LVL_INTR_0,
466 #else
467 0U, /* TBD, no OSPI0 interrupt routed to M4 core */
468 #endif
469 0, /* Event ID not used for ARM INTC */
470 OSPI_OPER_MODE_CFG, /* operMode */
471 CSL_OSPI_CS0, /* chipSelect */
472 CSL_OSPI_CLK_MODE_0, /* frmFmt */
473 {
474 0, /* default Chip Select Start of Transfer Delay */
475 0, /* default Chip Select End of Transfer Delay */
476 0, /* default Chip Select De-Assert Different Slaves Delay */
477 0 /* default Chip Select De-Assert Delay */
478 },
479 256, /* device page size is 256 bytes */
480 17, /* device block size is 2 ^ 17 = 128K bytes */
481 OSPI_XFER_LINES_OCTAL, /* xferLines */
482 (bool)false, /* Interrupt mode */
483 (bool)true, /* Direct Access Controller mode */
484 (bool)false, /* DMA mode */
485 NULL, /* dmaInfo */
486 (bool)true, /* enable PHY */
487 0, /* rdDataCapDelay */
488 (bool)true, /* enable DDR */
489 (bool)false, /* enable XIP */
490 10U /* Chip Select Start Of Transfer delay */
491 };
493 /* OSPI objects */
494 OSPI_v0_Object OspiObjects;
496 /* SPI configuration structure */
497 CSL_PUBLIC_CONST SPI_config_list SPI_config = {
498 {
499 &SPI_FxnTable_v1,
500 &SpiObjects[0],
501 &spiInitCfg[0]
502 },
503 {
504 &SPI_FxnTable_v1,
505 &SpiObjects[1],
506 &spiInitCfg[1]
507 },
508 {
509 &SPI_FxnTable_v1,
510 &SpiObjects[2],
511 &spiInitCfg[2]
512 },
513 {
514 &SPI_FxnTable_v1,
515 &SpiObjects[3],
516 &spiInitCfg[3]
517 },
518 {
519 &SPI_FxnTable_v1,
520 &SpiObjects[4],
521 &spiInitCfg[4]
522 },
523 {
524 &SPI_FxnTable_v1,
525 &SpiObjects[5],
526 &spiInitCfg[5]
527 },
528 {
529 &SPI_FxnTable_v1,
530 &SpiObjects[6],
531 &spiInitCfg[6]
532 },
533 {
534 &OSPI_FxnTable_v0,
535 &OspiObjects,
536 &ospiInitCfg
537 }
538 };
540 /* MCSPI configuration structure */
541 MCSPI_config_list MCSPI_config = {
542 {
543 {
544 &MCSPI_FxnTable_v1,
545 (SPI_Handle)(&(SPI_config[0])),
546 0
547 },
548 {
549 &MCSPI_FxnTable_v1,
550 (SPI_Handle)(&(SPI_config[0])),
551 1
552 },
553 {
554 &MCSPI_FxnTable_v1,
555 (SPI_Handle)(&(SPI_config[0])),
556 2
557 },
558 {
559 &MCSPI_FxnTable_v1,
560 (SPI_Handle)(&(SPI_config[0])),
561 3
562 },
563 },
564 {
565 {
566 &MCSPI_FxnTable_v1,
567 (SPI_Handle)(&(SPI_config[1])),
568 0
569 },
570 {
571 &MCSPI_FxnTable_v1,
572 (SPI_Handle)(&(SPI_config[1])),
573 1
574 },
575 {
576 &MCSPI_FxnTable_v1,
577 (SPI_Handle)(&(SPI_config[1])),
578 2
579 },
580 {
581 &MCSPI_FxnTable_v1,
582 (SPI_Handle)(&(SPI_config[1])),
583 3
584 },
585 },
586 {
587 {
588 &MCSPI_FxnTable_v1,
589 (SPI_Handle)(&(SPI_config[2])),
590 0
591 },
592 {
593 &MCSPI_FxnTable_v1,
594 (SPI_Handle)(&(SPI_config[2])),
595 1
596 },
597 {
598 &MCSPI_FxnTable_v1,
599 (SPI_Handle)(&(SPI_config[2])),
600 2
601 },
602 {
603 &MCSPI_FxnTable_v1,
604 (SPI_Handle)(&(SPI_config[2])),
605 3
606 },
607 },
608 {
609 {
610 &MCSPI_FxnTable_v1,
611 (SPI_Handle)(&(SPI_config[3])),
612 0
613 },
614 {
615 &MCSPI_FxnTable_v1,
616 (SPI_Handle)(&(SPI_config[3])),
617 1
618 },
619 {
620 &MCSPI_FxnTable_v1,
621 (SPI_Handle)(&(SPI_config[3])),
622 2
623 },
624 {
625 &MCSPI_FxnTable_v1,
626 (SPI_Handle)(&(SPI_config[3])),
627 3
628 },
629 },
630 {
631 {
632 &MCSPI_FxnTable_v1,
633 (SPI_Handle)(&(SPI_config[4])),
634 0
635 },
636 {
637 &MCSPI_FxnTable_v1,
638 (SPI_Handle)(&(SPI_config[4])),
639 1
640 },
641 {
642 &MCSPI_FxnTable_v1,
643 (SPI_Handle)(&(SPI_config[4])),
644 2
645 },
646 {
647 &MCSPI_FxnTable_v1,
648 (SPI_Handle)(&(SPI_config[4])),
649 3
650 },
651 },
652 {
653 {
654 &MCSPI_FxnTable_v1,
655 (SPI_Handle)(&(SPI_config[5])),
656 0
657 },
658 {
659 &MCSPI_FxnTable_v1,
660 (SPI_Handle)(&(SPI_config[5])),
661 1
662 },
663 {
664 &MCSPI_FxnTable_v1,
665 (SPI_Handle)(&(SPI_config[5])),
666 2
667 },
668 {
669 &MCSPI_FxnTable_v1,
670 (SPI_Handle)(&(SPI_config[5])),
671 3
672 },
673 },
674 {
675 {
676 &MCSPI_FxnTable_v1,
677 (SPI_Handle)(&(SPI_config[6])),
678 0
679 },
680 {
681 &MCSPI_FxnTable_v1,
682 (SPI_Handle)(&(SPI_config[6])),
683 1
684 },
685 {
686 &MCSPI_FxnTable_v1,
687 (SPI_Handle)(&(SPI_config[6])),
688 2
689 },
690 {
691 &MCSPI_FxnTable_v1,
692 (SPI_Handle)(&(SPI_config[6])),
693 3
694 },
695 }
696 };
698 /**
699 * \brief This API gets the SoC level of SPI intial configuration
700 *
701 * \param idx SPI instance index.
702 * \param cfg Pointer to SPI SOC initial config.
703 *
704 * \return 0 success: -1: error
705 *
706 */
707 int32_t SPI_socGetInitCfg(uint32_t idx, SPI_v1_HWAttrs *cfg)
708 {
709 int32_t ret = 0;
711 if (idx < MCSPI_PER_CNT)
712 {
713 *cfg = spiInitCfg[idx];
714 }
715 else
716 {
717 ret = (int32_t)(-1);
718 }
719 return ret;
720 }
722 /**
723 * \brief This API sets the SoC level of SPI intial configuration
724 *
725 * \param idx SPI instance index.
726 * \param cfg Pointer to SPI SOC initial config.
727 *
728 * \return 0 success: -1: error
729 *
730 */
731 int32_t SPI_socSetInitCfg(uint32_t idx, const SPI_v1_HWAttrs *cfg)
732 {
733 int32_t ret = 0;
735 if (idx < MCSPI_PER_CNT)
736 {
737 spiInitCfg[idx] = *cfg;
738 }
739 else
740 {
741 ret = (int32_t)(-1);
742 }
743 return ret;
744 }
746 /**
747 * \brief This API gets the SoC level of OSPI intial configuration
748 *
749 * \param idx OSPI instance index.
750 * \param cfg Pointer to OSPI SOC initial config.
751 *
752 * \return 0 success: -1: error
753 *
754 */
755 int32_t OSPI_socGetInitCfg(uint32_t idx, OSPI_v0_HwAttrs *cfg)
756 {
757 int32_t ret = 0;
759 if (idx < OSPI_PER_CNT)
760 {
761 *cfg = ospiInitCfg;
762 }
763 else
764 {
765 ret = -1;
766 }
768 return ret;
769 }
771 /**
772 * \brief This API sets the SoC level of OSPI intial configuration
773 *
774 * \param idx OSPI instance index.
775 * \param cfg Pointer to OSPI SOC initial config.
776 *
777 * \return 0 success: -1: error
778 *
779 */
780 int32_t OSPI_socSetInitCfg(uint32_t idx, const OSPI_v0_HwAttrs *cfg)
781 {
782 int32_t ret = 0;
784 if (idx < OSPI_PER_CNT)
785 {
786 ospiInitCfg = *cfg;
787 }
788 else
789 {
790 ret = -1;
791 }
793 return ret;
794 }