1 /**
2 * \file SPI_soc.c
3 *
4 * \brief DRA78x device specific hardware attributes.
5 *
6 */
8 /*
9 * Copyright (C) 2016 - 2019 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/csl/cslr_device.h>
42 #include <ti/drv/spi/MCSPI.h>
43 #include <ti/drv/spi/soc/SPI_soc.h>
45 #define CSL_QSPI_PER_CNT 1U
46 /* SPI configuration structure */
47 SPI_v1_HWAttrs spiInitCfg[CSL_MCSPI_PER_CNT] =
48 {
49 {
50 SOC_MCSPI1_BASE,
51 #if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M'))
52 57,
53 #elif defined(_TMS320C6X)
54 OSAL_REGINT_INTVEC_EVENT_COMBINER,
55 #endif
56 91,
57 SPI_PINMODE_4_PIN,
58 MCSPI_CHANNEL_0,
59 MCSPI_SINGLE_CH,
60 true,
61 CSL_MCSPI_0_MODULE_FREQ,
62 MCSPI_INITDLY_0,
63 MCSPI_RX_TX_FIFO_SIZE,
64 MCSPI_RX_TX_FIFO_SIZE,
65 {
66 {
67 MCSPI_CS_POL_LOW,
68 MCSPI_DATA_LINE_COMM_MODE_7,
69 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
70 MCSPI_TX_RX_MODE,
71 },
72 {
73 MCSPI_CS_POL_LOW,
74 MCSPI_DATA_LINE_COMM_MODE_7,
75 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
76 MCSPI_TX_RX_MODE,
77 },
78 {
79 MCSPI_CS_POL_LOW,
80 MCSPI_DATA_LINE_COMM_MODE_7,
81 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
82 MCSPI_TX_RX_MODE,
83 },
84 {
85 MCSPI_CS_POL_LOW,
86 MCSPI_DATA_LINE_COMM_MODE_7,
87 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
88 MCSPI_TX_RX_MODE,
89 },
90 },
91 0,
92 0,
93 0,
94 0,
95 0,
96 0,
97 NULL,
98 false,
99 NULL
100 },
101 {
102 SOC_MCSPI2_BASE,
103 #if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M'))
104 58,
105 #elif defined(_TMS320C6X)
106 OSAL_REGINT_INTVEC_EVENT_COMBINER,
107 #endif
108 92,
109 SPI_PINMODE_4_PIN,
110 MCSPI_CHANNEL_0,
111 MCSPI_SINGLE_CH,
112 true,
113 CSL_MCSPI_1_MODULE_FREQ,
114 MCSPI_INITDLY_0,
115 MCSPI_RX_TX_FIFO_SIZE,
116 MCSPI_RX_TX_FIFO_SIZE,
117 {
118 {
119 MCSPI_CS_POL_LOW,
120 MCSPI_DATA_LINE_COMM_MODE_7,
121 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
122 MCSPI_TX_RX_MODE,
123 },
124 {
125 MCSPI_CS_POL_LOW,
126 MCSPI_DATA_LINE_COMM_MODE_7,
127 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
128 MCSPI_TX_RX_MODE,
129 },
130 {
131 MCSPI_CS_POL_LOW,
132 MCSPI_DATA_LINE_COMM_MODE_7,
133 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
134 MCSPI_TX_RX_MODE,
135 },
136 {
137 MCSPI_CS_POL_LOW,
138 MCSPI_DATA_LINE_COMM_MODE_7,
139 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
140 MCSPI_TX_RX_MODE,
141 },
142 },
143 0,
144 0,
145 0,
146 0,
147 0,
148 0,
149 NULL,
150 false,
151 NULL
152 },
153 {
154 SOC_MCSPI3_BASE,
155 #if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M'))
156 48,
157 #elif defined(_TMS320C6X)
158 OSAL_REGINT_INTVEC_EVENT_COMBINER,
159 #endif
160 93,
161 SPI_PINMODE_4_PIN,
162 MCSPI_CHANNEL_0,
163 MCSPI_SINGLE_CH,
164 true,
165 CSL_MCSPI_2_MODULE_FREQ,
166 MCSPI_INITDLY_0,
167 MCSPI_RX_TX_FIFO_SIZE,
168 MCSPI_RX_TX_FIFO_SIZE,
169 {
170 {
171 MCSPI_CS_POL_LOW,
172 MCSPI_DATA_LINE_COMM_MODE_7,
173 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
174 MCSPI_TX_RX_MODE,
175 },
176 {
177 MCSPI_CS_POL_LOW,
178 MCSPI_DATA_LINE_COMM_MODE_7,
179 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
180 MCSPI_TX_RX_MODE,
181 },
182 {
183 MCSPI_CS_POL_LOW,
184 MCSPI_DATA_LINE_COMM_MODE_7,
185 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
186 MCSPI_TX_RX_MODE,
187 },
188 {
189 MCSPI_CS_POL_LOW,
190 MCSPI_DATA_LINE_COMM_MODE_7,
191 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
192 MCSPI_TX_RX_MODE,
193 },
194 },
195 0,
196 0,
197 0,
198 0,
199 0,
200 0,
201 NULL,
202 false,
203 NULL
204 },
205 {
206 SOC_MCSPI4_BASE,
207 #if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M'))
208 49,
209 #elif defined(_TMS320C6X)
210 OSAL_REGINT_INTVEC_EVENT_COMBINER,
211 #endif
212 74,
213 SPI_PINMODE_4_PIN,
214 MCSPI_CHANNEL_0,
215 MCSPI_SINGLE_CH,
216 true,
217 CSL_MCSPI_3_MODULE_FREQ,
218 MCSPI_INITDLY_0,
219 MCSPI_RX_TX_FIFO_SIZE,
220 MCSPI_RX_TX_FIFO_SIZE,
221 {
222 {
223 MCSPI_CS_POL_LOW,
224 MCSPI_DATA_LINE_COMM_MODE_7,
225 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
226 MCSPI_TX_RX_MODE,
227 },
228 {
229 MCSPI_CS_POL_LOW,
230 MCSPI_DATA_LINE_COMM_MODE_7,
231 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
232 MCSPI_TX_RX_MODE,
233 },
234 {
235 MCSPI_CS_POL_LOW,
236 MCSPI_DATA_LINE_COMM_MODE_7,
237 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
238 MCSPI_TX_RX_MODE,
239 },
240 {
241 MCSPI_CS_POL_LOW,
242 MCSPI_DATA_LINE_COMM_MODE_7,
243 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
244 MCSPI_TX_RX_MODE,
245 },
246 },
247 0,
248 0,
249 0,
250 0,
251 0,
252 0,
253 NULL,
254 false,
255 NULL
256 },
257 };
260 /* SPI objects */
261 SPI_v1_Object SpiObjects[CSL_MCSPI_PER_CNT];
263 QSPI_HwAttrs qspiInitCfg[CSL_QSPI_PER_CNT] =
264 {
265 {
266 SOC_QSPI_ADDRSP0_BASE, /* register baseAddr */
267 SOC_QSPI_ADDRSP1_BASE, /* memMappedBaseAddr */
268 96000000, /* Input frequency */
269 #if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M'))
270 62U,
271 #elif defined(_TMS320C6X)
272 OSAL_REGINT_INTVEC_EVENT_COMBINER,
273 #endif
274 38U,
275 QSPI_OPER_MODE_MMAP, /* operMode */
276 0U, /* chipSelect */
277 QSPI_CS_POL_ACTIVE_LOW, /* csPol */
278 QSPI_CLK_MODE_0, /* frmFmt */
279 QSPI_DATA_DELAY_0, /* dataDelay */
280 QSPI_RX_LINES_QUAD, /* rxLines */
281 true, /* intrEnable */
282 false, /* dmaEnable */
283 NULL, /* edmaHandle */
284 0, /* edmaTcc */
285 0, /* edmaChId */
286 1U /* clkDiv */
287 }
288 };
290 /* QSPI objects */
291 QSPI_v1_Object QspiObjects[CSL_QSPI_PER_CNT];
293 /* SPI configuration structure */
294 const SPI_config_list SPI_config = {
295 {
296 &SPI_FxnTable_v1,
297 &SpiObjects[0],
298 &spiInitCfg[0]
299 },
300 {
301 &SPI_FxnTable_v1,
302 &SpiObjects[1],
303 &spiInitCfg[1]
304 },
305 {
306 &SPI_FxnTable_v1,
307 &SpiObjects[2],
308 &spiInitCfg[2]
309 },
310 {
311 &SPI_FxnTable_v1,
312 &SpiObjects[3],
313 &spiInitCfg[3]
314 },
315 {
316 &QSPI_FxnTable_v1,
317 &QspiObjects[0],
318 &qspiInitCfg[0]
319 },
320 /* "pad to full predefined length of array" */
321 {NULL, NULL, NULL},
322 {NULL, NULL, NULL}
323 };
325 /* MCSPI configuration structure */
326 MCSPI_config_list MCSPI_config = {
327 {
328 {
329 &MCSPI_FxnTable_v1,
330 (SPI_Handle)(&(SPI_config[0])),
331 0
332 },
333 {
334 &MCSPI_FxnTable_v1,
335 (SPI_Handle)(&(SPI_config[0])),
336 1
337 },
338 {
339 &MCSPI_FxnTable_v1,
340 (SPI_Handle)(&(SPI_config[0])),
341 2
342 },
343 {
344 &MCSPI_FxnTable_v1,
345 (SPI_Handle)(&(SPI_config[0])),
346 3
347 },
348 },
349 {
350 {
351 &MCSPI_FxnTable_v1,
352 (SPI_Handle)(&(SPI_config[1])),
353 0
354 },
355 {
356 &MCSPI_FxnTable_v1,
357 (SPI_Handle)(&(SPI_config[1])),
358 1
359 },
360 {
361 &MCSPI_FxnTable_v1,
362 (SPI_Handle)(&(SPI_config[1])),
363 2
364 },
365 {
366 &MCSPI_FxnTable_v1,
367 (SPI_Handle)(&(SPI_config[1])),
368 3
369 },
370 },
371 {
372 {
373 &MCSPI_FxnTable_v1,
374 (SPI_Handle)(&(SPI_config[2])),
375 0
376 },
377 {
378 &MCSPI_FxnTable_v1,
379 (SPI_Handle)(&(SPI_config[2])),
380 1
381 },
382 {
383 &MCSPI_FxnTable_v1,
384 (SPI_Handle)(&(SPI_config[2])),
385 2
386 },
387 {
388 &MCSPI_FxnTable_v1,
389 (SPI_Handle)(&(SPI_config[2])),
390 3
391 },
392 },
393 {
394 {
395 &MCSPI_FxnTable_v1,
396 (SPI_Handle)(&(SPI_config[3])),
397 0
398 },
399 {
400 &MCSPI_FxnTable_v1,
401 (SPI_Handle)(&(SPI_config[3])),
402 1
403 },
404 {
405 &MCSPI_FxnTable_v1,
406 (SPI_Handle)(&(SPI_config[3])),
407 2
408 },
409 {
410 &MCSPI_FxnTable_v1,
411 (SPI_Handle)(&(SPI_config[3])),
412 3
413 },
414 },
415 /* "pad to full predefined length of array" */
416 {
417 {NULL, NULL, 0},
418 {NULL, NULL, 0},
419 {NULL, NULL, 0},
420 {NULL, NULL, 0}
421 },
422 {
423 {NULL, NULL, 0},
424 {NULL, NULL, 0},
425 {NULL, NULL, 0},
426 {NULL, NULL, 0}
427 },
428 {
429 {NULL, NULL, 0},
430 {NULL, NULL, 0},
431 {NULL, NULL, 0},
432 {NULL, NULL, 0}
433 }
434 };
436 /**
437 * \brief This API gets the SoC level of SPI intial configuration
438 *
439 * \param index SPI instance index.
440 * \param cfg Pointer to SPI SOC initial config.
441 *
442 * \return 0 success: -1: error
443 *
444 */
445 int32_t SPI_socGetInitCfg(uint32_t index, SPI_v1_HWAttrs *cfg)
446 {
447 int32_t ret = 0;
449 if (index < CSL_MCSPI_PER_CNT)
450 {
451 *cfg = spiInitCfg[index];
452 }
453 else
454 {
455 ret = -1;
456 }
457 return ret;
458 }
460 /**
461 * \brief This API sets the SoC level of SPI intial configuration
462 *
463 * \param index SPI instance index.
464 * \param cfg Pointer to SPI SOC initial config.
465 *
466 * \return 0 success: -1: error
467 *
468 */
469 int32_t SPI_socSetInitCfg(uint32_t index, const SPI_v1_HWAttrs *cfg)
470 {
471 int32_t ret = 0;
473 if (index < CSL_MCSPI_PER_CNT)
474 {
475 spiInitCfg[index] = *cfg;
476 }
477 else
478 {
479 ret = -1;
480 }
481 return ret;
482 }