1 /**
2 * \file SPI_soc.c
3 *
4 * \brief TDA3XX device specific hardware attributes.
5 *
6 */
8 /*
9 * Copyright (C) 2014-2015 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/csl/cslr_device.h>
42 #include <ti/drv/spi/MCSPI.h>
43 #include <ti/drv/spi/soc/SPI_v1.h>
44 #include <ti/csl/src/ip/mcspi/V0/mcspi.h>
46 /* SPI configuration structure */
47 SPI_v1_HWAttrs spiInitCfg[CSL_MCSPI_PER_CNT] =
48 {
49 {
50 #if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M'))
51 SOC_MCSPI1_BASE,
52 57,
53 #endif
54 60,
55 SPI_PINMODE_4_PIN,
56 MCSPI_CHANNEL_0,
57 MCSPI_SINGLE_CH,
58 true,
59 CSL_MCSPI_0_MODULE_FREQ,
60 MCSPI_INITDLY_0,
61 MCSPI_RX_TX_FIFO_SIZE,
62 MCSPI_RX_TX_FIFO_SIZE,
63 {
64 {
65 MCSPI_CS_POL_LOW,
66 MCSPI_DATA_LINE_COMM_MODE_7,
67 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
68 MCSPI_TX_RX_MODE,
69 },
70 {
71 MCSPI_CS_POL_LOW,
72 MCSPI_DATA_LINE_COMM_MODE_7,
73 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
74 MCSPI_TX_RX_MODE,
75 },
76 {
77 MCSPI_CS_POL_LOW,
78 MCSPI_DATA_LINE_COMM_MODE_7,
79 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
80 MCSPI_TX_RX_MODE,
81 },
82 {
83 MCSPI_CS_POL_LOW,
84 MCSPI_DATA_LINE_COMM_MODE_7,
85 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
86 MCSPI_TX_RX_MODE,
87 },
88 },
89 0,
90 0,
91 0,
92 0,
93 0,
94 0,
95 NULL,
96 false
97 },
98 {
99 #if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M'))
100 SOC_MCSPI2_BASE,
101 58,
102 #endif
103 61,
104 SPI_PINMODE_4_PIN,
105 MCSPI_CHANNEL_0,
106 MCSPI_SINGLE_CH,
107 true,
108 CSL_MCSPI_1_MODULE_FREQ,
109 MCSPI_INITDLY_0,
110 MCSPI_RX_TX_FIFO_SIZE,
111 MCSPI_RX_TX_FIFO_SIZE,
112 {
113 {
114 MCSPI_CS_POL_LOW,
115 MCSPI_DATA_LINE_COMM_MODE_7,
116 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
117 MCSPI_TX_RX_MODE,
118 },
119 {
120 MCSPI_CS_POL_LOW,
121 MCSPI_DATA_LINE_COMM_MODE_7,
122 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
123 MCSPI_TX_RX_MODE,
124 },
125 {
126 MCSPI_CS_POL_LOW,
127 MCSPI_DATA_LINE_COMM_MODE_7,
128 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
129 MCSPI_TX_RX_MODE,
130 },
131 {
132 MCSPI_CS_POL_LOW,
133 MCSPI_DATA_LINE_COMM_MODE_7,
134 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
135 MCSPI_TX_RX_MODE,
136 },
137 },
138 0,
139 0,
140 0,
141 0,
142 0,
143 0,
144 NULL,
145 false
146 },
147 {
148 #if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M'))
149 SOC_MCSPI3_BASE,
150 48,
151 #endif
152 86,
153 SPI_PINMODE_4_PIN,
154 MCSPI_CHANNEL_0,
155 MCSPI_SINGLE_CH,
156 true,
157 CSL_MCSPI_2_MODULE_FREQ,
158 MCSPI_INITDLY_0,
159 MCSPI_RX_TX_FIFO_SIZE,
160 MCSPI_RX_TX_FIFO_SIZE,
161 {
162 {
163 MCSPI_CS_POL_LOW,
164 MCSPI_DATA_LINE_COMM_MODE_7,
165 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
166 MCSPI_TX_RX_MODE,
167 },
168 {
169 MCSPI_CS_POL_LOW,
170 MCSPI_DATA_LINE_COMM_MODE_7,
171 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
172 MCSPI_TX_RX_MODE,
173 },
174 {
175 MCSPI_CS_POL_LOW,
176 MCSPI_DATA_LINE_COMM_MODE_7,
177 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
178 MCSPI_TX_RX_MODE,
179 },
180 {
181 MCSPI_CS_POL_LOW,
182 MCSPI_DATA_LINE_COMM_MODE_7,
183 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
184 MCSPI_TX_RX_MODE,
185 },
186 },
187 0,
188 0,
189 0,
190 0,
191 0,
192 0,
193 NULL,
194 false
195 },
196 {
197 #if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M'))
198 SOC_MCSPI4_BASE,
199 49,
200 #endif
201 43,
202 SPI_PINMODE_4_PIN,
203 MCSPI_CHANNEL_0,
204 MCSPI_SINGLE_CH,
205 true,
206 CSL_MCSPI_3_MODULE_FREQ,
207 MCSPI_INITDLY_0,
208 MCSPI_RX_TX_FIFO_SIZE,
209 MCSPI_RX_TX_FIFO_SIZE,
210 {
211 {
212 MCSPI_CS_POL_LOW,
213 MCSPI_DATA_LINE_COMM_MODE_7,
214 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
215 MCSPI_TX_RX_MODE,
216 },
217 {
218 MCSPI_CS_POL_LOW,
219 MCSPI_DATA_LINE_COMM_MODE_7,
220 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
221 MCSPI_TX_RX_MODE,
222 },
223 {
224 MCSPI_CS_POL_LOW,
225 MCSPI_DATA_LINE_COMM_MODE_7,
226 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
227 MCSPI_TX_RX_MODE,
228 },
229 {
230 MCSPI_CS_POL_LOW,
231 MCSPI_DATA_LINE_COMM_MODE_7,
232 MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,
233 MCSPI_TX_RX_MODE,
234 },
235 },
236 0,
237 0,
238 0,
239 0,
240 0,
241 0,
242 NULL,
243 false
244 },
245 };
248 /* SPI objects */
249 SPI_v1_Object SpiObjects[CSL_MCSPI_PER_CNT];
251 /* SPI configuration structure */
252 const SPI_config_list SPI_config = {
253 {
254 &SPI_FxnTable_v1,
255 &SpiObjects[0],
256 &spiInitCfg[0]
257 },
258 {
259 &SPI_FxnTable_v1,
260 &SpiObjects[1],
261 &spiInitCfg[1]
262 },
263 {
264 &SPI_FxnTable_v1,
265 &SpiObjects[2],
266 &spiInitCfg[2]
267 },
268 {
269 &SPI_FxnTable_v1,
270 &SpiObjects[3],
271 &spiInitCfg[3]
272 },
273 /* "pad to full predefined length of array" */
274 {NULL, NULL, NULL},
275 {NULL, NULL, NULL}
276 };
278 /* MCSPI configuration structure */
279 MCSPI_config_list MCSPI_config = {
280 {
281 {
282 &MCSPI_FxnTable_v1,
283 (SPI_Handle)(&(SPI_config[0])),
284 0
285 },
286 {
287 &MCSPI_FxnTable_v1,
288 (SPI_Handle)(&(SPI_config[0])),
289 1
290 },
291 {
292 &MCSPI_FxnTable_v1,
293 (SPI_Handle)(&(SPI_config[0])),
294 2
295 },
296 {
297 &MCSPI_FxnTable_v1,
298 (SPI_Handle)(&(SPI_config[0])),
299 3
300 },
301 },
302 {
303 {
304 &MCSPI_FxnTable_v1,
305 (SPI_Handle)(&(SPI_config[1])),
306 0
307 },
308 {
309 &MCSPI_FxnTable_v1,
310 (SPI_Handle)(&(SPI_config[1])),
311 1
312 },
313 {
314 &MCSPI_FxnTable_v1,
315 (SPI_Handle)(&(SPI_config[1])),
316 2
317 },
318 {
319 &MCSPI_FxnTable_v1,
320 (SPI_Handle)(&(SPI_config[1])),
321 3
322 },
323 },
324 {
325 {
326 &MCSPI_FxnTable_v1,
327 (SPI_Handle)(&(SPI_config[2])),
328 0
329 },
330 {
331 &MCSPI_FxnTable_v1,
332 (SPI_Handle)(&(SPI_config[2])),
333 1
334 },
335 {
336 &MCSPI_FxnTable_v1,
337 (SPI_Handle)(&(SPI_config[2])),
338 2
339 },
340 {
341 &MCSPI_FxnTable_v1,
342 (SPI_Handle)(&(SPI_config[2])),
343 3
344 },
345 },
346 {
347 {
348 &MCSPI_FxnTable_v1,
349 (SPI_Handle)(&(SPI_config[3])),
350 0
351 },
352 {
353 &MCSPI_FxnTable_v1,
354 (SPI_Handle)(&(SPI_config[3])),
355 1
356 },
357 {
358 &MCSPI_FxnTable_v1,
359 (SPI_Handle)(&(SPI_config[3])),
360 2
361 },
362 {
363 &MCSPI_FxnTable_v1,
364 (SPI_Handle)(&(SPI_config[3])),
365 3
366 },
367 },
368 /* "pad to full predefined length of array" */
369 {
370 {NULL, NULL, 0},
371 {NULL, NULL, 0},
372 {NULL, NULL, 0},
373 {NULL, NULL, 0}
374 },
375 {
376 {NULL, NULL, 0},
377 {NULL, NULL, 0},
378 {NULL, NULL, 0},
379 {NULL, NULL, 0}
380 },
381 {
382 {NULL, NULL, 0},
383 {NULL, NULL, 0},
384 {NULL, NULL, 0},
385 {NULL, NULL, 0}
386 }
387 };
389 /**
390 * \brief This API gets the SoC level of SPI intial configuration
391 *
392 * \param index SPI instance index.
393 * \param cfg Pointer to SPI SOC initial config.
394 *
395 * \return 0 success: -1: error
396 *
397 */
398 int32_t SPI_socGetInitCfg(uint32_t index, SPI_v1_HWAttrs *cfg)
399 {
400 int32_t ret = 0;
402 if (index < CSL_MCSPI_PER_CNT)
403 {
404 *cfg = spiInitCfg[index];
405 }
406 else
407 {
408 ret = -1;
409 }
410 return ret;
411 }
413 /**
414 * \brief This API sets the SoC level of SPI intial configuration
415 *
416 * \param index SPI instance index.
417 * \param cfg Pointer to SPI SOC initial config.
418 *
419 * \return 0 success: -1: error
420 *
421 */
422 int32_t SPI_socSetInitCfg(uint32_t index, const SPI_v1_HWAttrs *cfg)
423 {
424 int32_t ret = 0;
426 if (index < CSL_MCSPI_PER_CNT)
427 {
428 spiInitCfg[index] = *cfg;
429 }
430 else
431 {
432 ret = -1;
433 }
434 return ret;
435 }