packages/ti/drv/spi/src/v0/OSPI_v0.c

   1 /**
   2  *  \file   OSPI_v0.c
   3  *
   4  *  \brief  OSPI IP Version 0 specific driver APIs implementation.
   5  *
   6  *   This file contains the driver APIs for OSPI controller.
   7  */
   8
   9 /*
  10  * Copyright (C) 2017 - 2020 Texas Instruments Incorporated - http://www.ti.com/
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  *
  16  * Redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer.
  18  *
  19  * Redistributions in binary form must reproduce the above copyright
  20  * notice, this list of conditions and the following disclaimer in the
  21  * documentation and/or other materials provided with the
  22  * distribution.
  23  *
  24  * Neither the name of Texas Instruments Incorporated nor the names of
  25  * its contributors may be used to endorse or promote products derived
  26  * from this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  */
  41
  42 #include <stdint.h>
  43 #include <stddef.h>
  44 #include <stdbool.h>
  45 #include <ti/csl/arch/csl_arch.h>
  46 #include <ti/drv/spi/SPI.h>
  47 #include <ti/drv/spi/src/v0/OSPI_v0.h>
  48 #include <ti/drv/spi/src/SPI_osal.h>
  49
  50 #define OSPI_DAC_WRITE_TIMEOUT      (500000U)
  51 #define OSPI_CHECK_IDLE_DELAY       (10U)
  52 #define OSPI_CALIBRATE_DELAY        (20U)
  53 #define OSPI_XIP_SETUP_DELAY        (250U)
  54
  55 /* OSPI AM57x functions */
  56 static void       OSPI_close_v0(SPI_Handle handle);
  57 static void       OSPI_init_v0(SPI_Handle handle);
  58 static SPI_Handle OSPI_open_v0(SPI_Handle handle, const SPI_Params *params);
  59 static bool       OSPI_transfer_v0(SPI_Handle handle,
  60                                    SPI_Transaction *transaction);
  61 static int32_t    OSPI_primeTransfer_v0(SPI_Handle handle,
  62                                         SPI_Transaction *transaction);
  63 static void       OSPI_transferCallback_v0(SPI_Handle handle,
  64                                            SPI_Transaction *msg);
  65 static int32_t    OSPI_control_v0(SPI_Handle handle, uint32_t cmd, const void *arg);
  66 static void       OSPI_transferCancel_v0(SPI_Handle handle);
  67 static void       OSPI_hwiFxn_v0(uintptr_t arg);
  68 static int32_t    OSPI_waitIdle(SPI_Handle handle, uint32_t timeOut);
  69 static int32_t    OSPI_flashExecCmd(const CSL_ospi_flash_cfgRegs *pRegs);
  70 static int32_t    OSPI_read_v0(SPI_Handle handle, SPI_Transaction *transaction);
  71 static int32_t    OSPI_cmdRead(const CSL_ospi_flash_cfgRegs *pRegs,
  72                                uint32_t                      cmd,
  73                                uint8_t                      *rxBuf,
  74                                uint32_t                      rxLen);
  75 static int32_t OSPI_cmdExtRead(const CSL_ospi_flash_cfgRegs *pRegs,
  76                                uint8_t                      *cmd,
  77                                uint32_t                      cmdLen,
  78                                uint8_t                      *rxBuf,
  79                                uint32_t                      rxLen,
  80                                uint32_t                      dummyCycles);
  81 static int32_t    OSPI_write_v0(SPI_Handle handle, SPI_Transaction *transaction);
  82 static int32_t    OSPI_cmdWrite(const CSL_ospi_flash_cfgRegs *pRegs,
  83                                 const uint8_t                *cmdBuf,
  84                                 uint32_t                      cmdLen,
  85                                 const uint8_t                *txBuf,
  86                                 uint32_t                      txLen);
  87 static int32_t    OSPI_waitReadSramLvl(const CSL_ospi_flash_cfgRegs *pReg,
  88                                        uint32_t *rdLevel);
  89 static int32_t    OSPI_ind_xfer_mode_read_v0(SPI_Handle handle,
  90                                              SPI_Transaction *transaction);
  91 static int32_t    OSPI_waitIndWriteComplete(const CSL_ospi_flash_cfgRegs *pRegs);
  92 static int32_t    OSPI_waitWriteSramLvl(const CSL_ospi_flash_cfgRegs *pReg,
  93                                         uint32_t *sramLvl);
  94 static int32_t    OSPI_ind_xfer_mode_write_v0(SPI_Handle handle,
  95                                               SPI_Transaction *transaction);
  96 static int32_t    OSPI_dac_xfer_mode_read_v0(SPI_Handle handle,
  97                                              const SPI_Transaction *transaction);
  98 static int32_t    OSPI_dac_xfer_mode_write_v0(SPI_Handle handle,
  99                                               const SPI_Transaction *transaction);
 100 static int32_t    OSPI_cmd_mode_write_v0(SPI_Handle handle,
 101                                          const SPI_Transaction *transaction);
 102 static int32_t    OSPI_cmd_mode_read_v0(SPI_Handle handle,
 103                                         SPI_Transaction *transaction);
 104
 105 typedef enum OSPI_intrPollMode_s
 106 {
 107     SPI_OPER_MODE_BLOCKING = 0U,  /*! Interrupt based blocking mode */
 108     SPI_OPER_MODE_POLLING,        /*! Non interrupt based blocking mode */
 109     SPI_OPER_MODE_CALLBACK        /*! Interrupt based call back mode */
 110 } OSPI_intrPollMode;
 111
 112
 113
 114 /* SPI function table for OSPI AM57x implementation */
 115 const SPI_FxnTable OSPI_FxnTable_v0 =
 116 {
 117     &OSPI_close_v0,
 118     &OSPI_control_v0,
 119     &OSPI_init_v0,
 120     &OSPI_open_v0,
 121     &OSPI_transfer_v0,
 122     &OSPI_transferCancel_v0,
 123     NULL
 124 };
 125
 126 /*
 127  *  ======== OSPI_close_v0 ========
 128  */
 129 static void OSPI_close_v0(SPI_Handle handle)
 130 {
 131     OSPI_v0_Object        *object = NULL;
 132     OSPI_v0_HwAttrs const *hwAttrs = NULL;
 133
 134     if (handle != NULL)
 135     {
 136         /* Get the pointer to the object and hwAttrs */
 137         object = (OSPI_v0_Object *)handle->object;
 138         hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
 139
 140         /* disable the interrupts */
 141         CSL_ospiIntrEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 142                            CSL_OSPI_INTR_MASK_ALL,
 143                            FALSE);
 144
 145         /* Destruct the Hwi */
 146         if(object->hwi != NULL)
 147         {
 148             /* Destruct the Hwi */
 149             (void)SPI_osalHardwareIntDestruct(object->hwi, (int32_t)hwAttrs->eventId);
 150             object->hwi = NULL;
 151         }
 152
 153         /* Destruct the instance lock */
 154         (void)SPI_osalDeleteBlockingLock(object->mutex);
 155
 156         /* Destruct the transfer completion lock */
 157         if((uint32_t)SPI_OPER_MODE_BLOCKING == object->intrPollMode)
 158         {
 159             (void)SPI_osalDeleteBlockingLock(object->transferComplete);
 160         }
 161
 162 #ifdef SPI_DMA_ENABLE
 163         if (hwAttrs->dmaEnable == (bool)true)
 164         {
 165             OSPI_dmaFreeChannel(handle);
 166         }
 167 #endif
 168
 169         /* Open flag is set false */
 170         object->isOpen = (bool)false;
 171     }
 172
 173     return;
 174 }
 175
 176 /*
 177  *  ======== OSPI_hwiFxn_v0 ========
 178  *  Hwi interrupt handler to service the OSPI peripheral
 179  *
 180  *  The handler is a generic handler for a OSPI object.
 181  */
 182 static void OSPI_hwiFxn_v0(uintptr_t arg)
 183 {
 184     uint32_t               intrStatus;
 185     OSPI_v0_Object        *object = NULL;
 186     OSPI_v0_HwAttrs const *hwAttrs = NULL;
 187     uint32_t               sramLevel, rdBytes, wrBytes;
 188
 189     /* Get the pointer to the object and hwAttrs */
 190     object = (OSPI_v0_Object *)(((SPI_Handle)arg)->object);
 191     hwAttrs = (OSPI_v0_HwAttrs const *)(((SPI_Handle)arg)->hwAttrs);
 192
 193     /* Read the interrupt status register */
 194     intrStatus = CSL_ospiIntrStatus((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr));
 195
 196     if (object->readBufIdx != NULL_PTR)
 197     {
 198                 /* Indirect read operation */
 199         if ((intrStatus & CSL_OSPI_INTR_MASK_IND_XFER) != 0U)
 200         {
 201             if(object->readCountIdx != 0U)
 202             {
 203                 while ((bool)true)
 204                 {
 205                     sramLevel = CSL_ospiGetSramLvl((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), 1U);
 206                     if (sramLevel == 0U)
 207                     {
 208                         break;
 209                     }
 210                     rdBytes = sramLevel * CSL_OSPI_FIFO_WIDTH;
 211                     rdBytes = (rdBytes > object->readCountIdx) ? object->readCountIdx : rdBytes;
 212
 213                     /* Read data from FIFO */
 214                     CSL_ospiReadFifoData(hwAttrs->dataAddr, object->readBufIdx, rdBytes);
 215
 216                     object->readBufIdx += rdBytes;
 217                     object->readCountIdx -= rdBytes;
 218                 }
 219
 220                 if ((object->readCountIdx > 0U) &&
 221                     (object->readCountIdx < (CSL_OSPI_SRAM_WARERMARK_RD_LVL * CSL_OSPI_FIFO_WIDTH)))
 222                 {
 223                     while((bool)true)
 224                     {
 225                         sramLevel = CSL_ospiGetSramLvl((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), 1U);
 226                         rdBytes = sramLevel * CSL_OSPI_FIFO_WIDTH;
 227                         if (rdBytes >= object->readCountIdx)
 228                         {
 229                             break;
 230                         }
 231                     }
 232                     rdBytes = object->readCountIdx;
 233                     CSL_ospiReadFifoData(hwAttrs->dataAddr, object->readBufIdx, rdBytes);
 234                     object->readBufIdx += rdBytes;
 235                     object->readCountIdx -= rdBytes;
 236                 }
 237             }
 238
 239             if((object->readCountIdx == 0U) || ((intrStatus & CSL_OSPI_INTR_MASK_IND_OP_DONE) != 0U))
 240             {
 241                 /* Clear indirect read operation complete status */
 242                 CSL_ospiClrIndReadComplete((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr));
 243
 244                 /* disable and clear the interrupts */
 245                 CSL_ospiIntrEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 246                                     CSL_OSPI_INTR_MASK_ALL,
 247                                     FALSE);
 248                 CSL_ospiIntrClear((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 249                                   CSL_OSPI_INTR_MASK_ALL);
 250
 251                 /* Call the call back function */
 252                 object->ospiParams.transferCallbackFxn((SPI_Handle)arg, NULL);
 253             }
 254             else
 255             {
 256                 /* Clear interrupt status */
 257                 CSL_ospiIntrClear((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), intrStatus);
 258             }
 259         }
 260         else
 261         {
 262             /* Clear interrupt status */
 263             CSL_ospiIntrClear((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), intrStatus);
 264         }
 265     }
 266     else
 267     {
 268                 /* Indirect write operation */
 269         if ((intrStatus & CSL_OSPI_INTR_MASK_IND_XFER) != 0U)
 270         {
 271             if (object->writeCountIdx != 0U)
 272             {
 273                 sramLevel = CSL_OSPI_SRAM_PARTITION_WR - \
 274                             CSL_ospiGetSramLvl((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), 0U);
 275
 276                 wrBytes = sramLevel * CSL_OSPI_FIFO_WIDTH;
 277                 wrBytes = (wrBytes > object->writeCountIdx) ? object->writeCountIdx : wrBytes;
 278
 279                 /* Write data to FIFO */
 280                 CSL_ospiWriteFifoData(hwAttrs->dataAddr, object->writeBufIdx, wrBytes);
 281
 282                 object->writeBufIdx += wrBytes;
 283                 object->writeCountIdx -= wrBytes;
 284
 285                 sramLevel = CSL_OSPI_SRAM_PARTITION_WR - \
 286                             CSL_ospiGetSramLvl((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), 0U);
 287
 288                 if ((object->writeCountIdx > 0U) &&
 289                     (object->writeCountIdx <= (sramLevel * CSL_OSPI_FIFO_WIDTH)))
 290                 {
 291                     wrBytes = object->writeCountIdx;
 292                     CSL_ospiWriteFifoData(hwAttrs->dataAddr, object->writeBufIdx, wrBytes);
 293                     object->writeBufIdx += wrBytes;
 294                     object->writeCountIdx -= wrBytes;
 295                 }
 296             }
 297
 298             if ((intrStatus & CSL_OSPI_INTR_MASK_IND_OP_DONE) != 0U)
 299             {
 300                 /* Clear indirect write operation complete status */
 301                 CSL_ospiClrIndWriteComplete((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr));
 302
 303                 /* disable and clear the interrupts */
 304                 CSL_ospiIntrEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 305                                     CSL_OSPI_INTR_MASK_ALL,
 306                                     FALSE);
 307                 CSL_ospiIntrClear((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 308                                   CSL_OSPI_INTR_MASK_ALL);
 309
 310                 /* Call the call back function */
 311                 object->ospiParams.transferCallbackFxn((SPI_Handle)arg, NULL);
 312             }
 313             else
 314             {
 315                 /* Clear interrupt status */
 316                 CSL_ospiIntrClear((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), intrStatus);
 317             }
 318         }
 319         else
 320         {
 321             /* Clear interrupt status */
 322             CSL_ospiIntrClear((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), intrStatus);
 323         }
 324     }
 325 }
 326
 327 /*
 328  *  ======== OSPI_init_v0 ========
 329  */
 330 static void OSPI_init_v0(SPI_Handle handle)
 331 {
 332     if (handle != NULL)
 333     {
 334         /* Mark the object as available */
 335         ((OSPI_v0_Object *)(handle->object))->isOpen = (bool)false;
 336     }
 337 }
 338
 339 static void OSPI_delay(uint32_t delay);
 340 static void OSPI_delay(uint32_t delay)
 341 {
 342     volatile uint32_t i = delay;
 343
 344     while (i > 0U)
 345     {
 346         i = i - 1U;
 347     }
 348 }
 349
 350 static int32_t OSPI_waitIdle(SPI_Handle handle, uint32_t timeOut)
 351 {
 352     OSPI_v0_HwAttrs const *hwAttrs;      /* OSPI hardware attributes */
 353     uint32_t               retry = 0U;
 354     int32_t                retVal = (int32_t)(-1);
 355     uint32_t               timeOutVal = timeOut;
 356
 357     /* Get the pointer to the object and hwAttrs */
 358     hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
 359
 360     while (timeOutVal != 0U)
 361     {
 362         if (CSL_ospiIsIdle((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr)) != 0U)
 363         {
 364             retry++;
 365             if (retry == 3U)
 366             {
 367                 retVal = 0;
 368                 break;
 369             }
 370         }
 371         else
 372         {
 373             retry = 0U;
 374         }
 375         OSPI_delay(OSPI_CHECK_IDLE_DELAY);
 376         timeOutVal--;
 377     }
 378
 379     return (retVal);
 380 }
 381
 382 /*
 383  *  ======== OSPI_open_v0 ========
 384  */
 385 static SPI_Handle OSPI_open_v0(SPI_Handle handle, const SPI_Params *params)
 386 {
 387     SemaphoreP_Params        semParams;
 388     uintptr_t                key;
 389     SPI_Handle               retHandle = handle;
 390     OSPI_v0_Object          *object = NULL;
 391     OSPI_v0_HwAttrs const   *hwAttrs = NULL;
 392         OsalRegisterIntrParams_t interruptRegParams;
 393     int32_t                  retFlag = 0;
 394     uint32_t                 numAddrBytes;
 395
 396     if (handle != NULL)
 397     {
 398         /* Get the pointer to the object and hwAttrs */
 399         object = (OSPI_v0_Object *)handle->object;
 400         hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
 401
 402         /* Determine if the device index was already opened */
 403         key = SPI_osalHardwareIntDisable();
 404     }
 405
 406     if ((handle == NULL) || (object->isOpen == (bool)true))
 407     {
 408         if (handle != NULL)
 409         {
 410             SPI_osalHardwareIntRestore(key);
 411             retHandle = NULL;
 412         }
 413     }
 414     else
 415     {
 416         /* Mark the handle as being used */
 417         object->isOpen = (bool)true;
 418         SPI_osalHardwareIntRestore(key);
 419
 420         /* Store the OSPI parameters */
 421         if (params == NULL) {
 422             /* No params passed in, so use the defaults */
 423             SPI_Params_init(&(object->ospiParams));
 424         }
 425         else {
 426             /* Copy the params contents */
 427             object->ospiParams = *params;
 428         }
 429
 430         /* Copy the controller mode from hardware attributes to object */
 431         object->ospiMode  = (uint32_t)hwAttrs->operMode;
 432         object->xferLines = (uint32_t)hwAttrs->xferLines;
 433         object->hwi       = NULL;
 434
 435         /* Extract OSPI operating mode based on hwAttrs and input parameters */
 436         if(SPI_MODE_BLOCKING == object->ospiParams.transferMode)
 437         {
 438             if (((bool)true == hwAttrs->intrEnable) && ((bool)false == hwAttrs->dacEnable))
 439             {
 440                 /* interrupt is only used in indirect access mode */
 441                 object->intrPollMode = (uint32_t)SPI_OPER_MODE_BLOCKING;
 442             }
 443 #ifdef SPI_DMA_ENABLE
 444             else if (((bool)true == hwAttrs->dmaEnable) && ((bool)true == hwAttrs->dacEnable))
 445             {
 446                 /* DMA mode is only used in direct access mode */
 447                 object->intrPollMode = (uint32_t)SPI_OPER_MODE_BLOCKING;
 448             }
 449 #endif
 450             else
 451             {
 452                 object->intrPollMode = (uint32_t)SPI_OPER_MODE_POLLING;
 453             }
 454         }
 455         else
 456         {
 457             object->intrPollMode = (uint32_t)SPI_OPER_MODE_CALLBACK;
 458         }
 459
 460         /* interrupt mode only enabled in indirect access controller mode */
 461         if (((bool)true == hwAttrs->intrEnable) && ((bool)false == hwAttrs->dacEnable))
 462         {
 463             Osal_RegisterInterrupt_initParams(&interruptRegParams);
 464
 465             interruptRegParams.corepacConfig.name=NULL;
 466 #ifdef __TI_ARM_V7R5__
 467             interruptRegParams.corepacConfig.priority=0x8U;
 468 #else
 469             interruptRegParams.corepacConfig.priority=0x20U;
 470 #endif
 471             interruptRegParams.corepacConfig.corepacEventNum = (int32_t)hwAttrs->eventId;
 472             interruptRegParams.corepacConfig.intVecNum = (int32_t)hwAttrs->intrNum; /* Host Interrupt vector */
 473             interruptRegParams.corepacConfig.isrRoutine = (void (*)(uintptr_t))(&OSPI_hwiFxn_v0);
 474             interruptRegParams.corepacConfig.arg = (uintptr_t)handle;
 475
 476             (void)SPI_osalRegisterInterrupt(&interruptRegParams,&(object->hwi));
 477             if(object->hwi == NULL) {
 478                 OSPI_close_v0(handle);
 479                 retHandle = NULL;
 480                 retFlag = 1;
 481             }
 482         }
 483
 484         if(retFlag == 0)
 485         {
 486             /*
 487              * Construct thread safe handles for this OSPI peripheral
 488              * Semaphore to provide exclusive access to the OSPI peripheral
 489              */
 490             SPI_osalSemParamsInit(&semParams);
 491             semParams.mode = SemaphoreP_Mode_BINARY;
 492             object->mutex = SPI_osalCreateBlockingLock(1U, &semParams);
 493
 494             /*
 495              * Store a callback function that posts the transfer complete
 496              * semaphore for synchronous mode
 497              */
 498             if (object->intrPollMode == (uint32_t)SPI_OPER_MODE_BLOCKING)
 499             {
 500                 /*
 501                  * Semaphore to cause the waiting task to block for the OSPI
 502                  * to finish
 503                  */
 504                 object->transferComplete = SPI_osalCreateBlockingLock(0, &semParams);
 505
 506                 /* Store internal callback function */
 507                 object->ospiParams.transferCallbackFxn = &OSPI_transferCallback_v0;
 508             }
 509             if(object->intrPollMode == (uint32_t)SPI_OPER_MODE_CALLBACK)
 510             {
 511                 /* Check to see if a callback function was defined for async mode */
 512                 if (object->ospiParams.transferCallbackFxn == NULL)
 513                 {
 514                     OSPI_close_v0(handle);
 515                     retHandle = NULL;
 516                     retFlag = 1;
 517                 }
 518             }
 519
 520             if(retFlag == 0)
 521             {
 522                 object->transaction = NULL;
 523
 524     #ifdef SPI_DMA_ENABLE
 525                 if (hwAttrs->dmaEnable == (bool)true)
 526                 {
 527                     (void)OSPI_dmaConfig(handle);
 528                 }
 529     #endif
 530                 /* Disable DAC */
 531                 CSL_ospiDacEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
 532
 533                 /* Disable DTR protocol */
 534                 CSL_ospiDtrEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
 535
 536                 if (hwAttrs->xipEnable == (bool)false)
 537                 {
 538                     /* Disable XIP */
 539                     CSL_ospiXipEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
 540                 }
 541
 542                 /* Disable OSPI controller */
 543                 CSL_ospiEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
 544
 545                 /* Wait until Serial Interface and OSPI pipeline is IDLE. */
 546                 if (OSPI_waitIdle(handle, OSPI_DAC_WRITE_TIMEOUT) != (int32_t)0U)
 547                 {
 548                     OSPI_close_v0(handle);
 549                     retHandle = NULL;
 550                     retFlag = 1;
 551                 }
 552             }
 553         }
 554
 555         if(retFlag == 0)
 556         {
 557             /* Chip select setup */
 558             CSL_ospiSetChipSelect((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 559                                   hwAttrs->chipSelect,
 560                                   CSL_OSPI_DECODER_SELECT4);
 561
 562             /* Set clock mode */
 563             CSL_ospiSetClkMode((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 564                                hwAttrs->frmFmt);
 565
 566             /* Disable the adapted loopback clock circuit */
 567             CSL_ospiLoopbackClkEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 568                                       FALSE);
 569
 570             /* Delay Setup */
 571             CSL_ospiSetDevDelay((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 572                                 hwAttrs->devDelays);
 573
 574             if (hwAttrs->baudRateDiv)
 575             {
 576                 CSL_ospiSetPreScaler((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 577                                      CSL_OSPI_BAUD_RATE_DIVISOR(hwAttrs->baudRateDiv));
 578             }
 579             else
 580             {
 581                 /* Set default baud rate divider value */
 582                 if (hwAttrs->phyEnable)
 583                 {
 584                     CSL_ospiSetPreScaler((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 585                                          CSL_OSPI_BAUD_RATE_DIVISOR(2U));
 586                 }
 587                 else
 588                 {
 589                     /* Disable high speed mode when PHY is disabled */
 590                     CSL_ospiSetPreScaler((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 591                                          CSL_OSPI_BAUD_RATE_DIVISOR_DEFAULT);
 592                 }
 593             }
 594
 595             if (hwAttrs->phyEnable)
 596             {
 597                 /* Enable PHY mode */
 598                 CSL_ospiPhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
 599             }
 600             else
 601             {
 602                 /* Disable PHY mode */
 603                 CSL_ospiPhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
 604             }
 605             /* Disable PHY pipeline mode */
 606             CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
 607
 608             if (hwAttrs->dtrEnable)
 609             {
 610                 numAddrBytes = CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_4;
 611             }
 612             else
 613             {
 614                 numAddrBytes = CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_3;
 615             }
 616
 617             /* Set device size cofigurations */
 618             CSL_ospiSetDevSize((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 619                                numAddrBytes,
 620                                hwAttrs->pageSize,
 621                                hwAttrs->blkSize);
 622
 623             /* Set indirect trigger address register */
 624             if (hwAttrs->dacEnable)
 625             {
 626                 CSL_ospiSetIndTrigAddr((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 627                                        0x4000000);
 628             }
 629             else
 630             {
 631                 CSL_ospiSetIndTrigAddr((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 632                                        0x3FE0000);
 633             }
 634
 635             /* Disable write completion auto polling */
 636             CSL_ospiSetWrCompAutoPolling((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 637                                          CSL_OSPI_WRITE_COMP_AUTO_POLLING_ENABLE);
 638
 639             /* Set SRAM partition configuration */
 640             CSL_ospiSetSramPartition((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 641                                      CSL_OSPI_SRAM_PARTITION_DEFAULT);
 642
 643             /* disable and clear the interrupts */
 644             CSL_ospiIntrEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 645                                 CSL_OSPI_INTR_MASK_ALL,
 646                                 FALSE);
 647             CSL_ospiIntrClear((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 648                               CSL_OSPI_INTR_MASK_ALL);
 649
 650             if (hwAttrs->dacEnable)
 651             {
 652                 CSL_ospiDacEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
 653             }
 654             else
 655             {
 656                 CSL_ospiDacEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
 657             }
 658
 659             CSL_ospiSetDataReadCapDelay((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 660                                         hwAttrs->rdDataCapDelay);
 661             CSL_ospiSetCsSotDelay((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 662                                   hwAttrs->csSotDelay);
 663             /* Enable OSPI controller */
 664             CSL_ospiEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
 665         }
 666     }
 667     return(retHandle);
 668 }
 669
 670 /*
 671  *  ======== OSPI_primeTransfer_v0 =======
 672  */
 673 static int32_t OSPI_primeTransfer_v0(SPI_Handle handle,
 674                                      SPI_Transaction *transaction)
 675 {
 676     OSPI_v0_Object        *object = NULL;
 677     OSPI_v0_HwAttrs const *hwAttrs = NULL;
 678     int32_t                retVal = 0;
 679
 680     /* Get the pointer to the object and hwAttrs */
 681     object = (OSPI_v0_Object *)handle->object;
 682     hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
 683
 684     /* Disable and clear the interrupts */
 685     CSL_ospiIntrEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 686                         CSL_OSPI_INTR_MASK_ALL,
 687                         FALSE);
 688     CSL_ospiIntrClear((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 689                       CSL_OSPI_INTR_MASK_ALL);
 690
 691     /* Interrupt mode */
 692     if(object->intrPollMode != (uint32_t)SPI_OPER_MODE_POLLING)
 693     {
 694         CSL_ospiIntrEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 695                            CSL_OSPI_INTR_MASK_ALL,
 696                            TRUE);
 697     }
 698
 699     /* Identify the direction of transfer (whether read/write) */
 700     if((uint32_t)SPI_TRANSACTION_TYPE_READ == object->transactionType)
 701     {
 702         retVal = (OSPI_read_v0(handle, transaction));
 703     }
 704     else if((uint32_t)SPI_TRANSACTION_TYPE_WRITE == object->transactionType)
 705     {
 706         retVal = (OSPI_write_v0(handle, transaction));
 707     }
 708     else
 709     {
 710         transaction->status = SPI_TRANSFER_CANCELED;
 711                 retVal = (int32_t)(-1);
 712     }
 713     return(retVal);
 714 }
 715
 716 static int32_t OSPI_waitReadSramLvl(const CSL_ospi_flash_cfgRegs *pReg,
 717                                     uint32_t *rdLevel)
 718 {
 719     uint32_t retry = OSPI_DAC_WRITE_TIMEOUT;
 720     uint32_t sramLevel;
 721     int32_t  retVal = 0;
 722     while(retry != 0U)
 723     {
 724         sramLevel = CSL_ospiGetSramLvl(pReg, 1U);
 725         if (sramLevel != 0U)
 726         {
 727             *rdLevel = sramLevel;
 728             break;
 729         }
 730         OSPI_delay(OSPI_CHECK_IDLE_DELAY);
 731         retry--;
 732     }
 733
 734     if (retry != 0U)
 735     {
 736         retVal = 0;
 737     }
 738     else
 739     {
 740         retVal = (int32_t)(-1);
 741     }
 742     return(retVal);
 743 }
 744
 745 static int32_t OSPI_waitIndReadComplete(const CSL_ospi_flash_cfgRegs *pRegs)
 746 {
 747     uint32_t retry = OSPI_DAC_WRITE_TIMEOUT;
 748     int32_t  retVal;
 749
 750     /* Check flash indirect read controller status */
 751     while (retry != 0U)
 752     {
 753         if (CSL_ospiIndReadComplete(pRegs) == TRUE)
 754         {
 755             break;
 756         }
 757         OSPI_delay(OSPI_CHECK_IDLE_DELAY);
 758         retry--;
 759     }
 760
 761     if (retry != 0U)
 762     {
 763         /* Clear indirect completion status */
 764         CSL_ospiClrIndReadComplete(pRegs);
 765         retVal = 0;
 766     }
 767     else
 768     {
 769         retVal = (int32_t)(-1);
 770     }
 771     return(retVal);
 772 }
 773
 774 static int32_t OSPI_ind_xfer_mode_read_v0(SPI_Handle handle,
 775                                           SPI_Transaction *transaction)
 776 {
 777     OSPI_v0_HwAttrs const *hwAttrs;      /* OSPI hardware attributes */
 778     OSPI_v0_Object        *object;       /* OSPI object */
 779     uint8_t               *pDst;         /* Destination address */
 780     uint32_t               count;        /* transaction length */
 781     uint32_t               offset;       /* OSPI flash offset address */
 782     uint32_t               remaining;
 783     uint32_t               sramLevel = 0, rdBytes = 0;
 784     uint32_t               retFlag = 0U;
 785     int32_t                retVal = 0;
 786
 787     /* Copy flash transaction parameters to local variables */
 788     offset = (uint32_t)((uintptr_t)transaction->arg); /* NOR Flash offset address to read */
 789     pDst = (uint8_t *)transaction->rxBuf;
 790     count = (uint32_t)transaction->count;
 791
 792     /* Get the pointer to the object and hwAttrs */
 793     hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
 794     object = (OSPI_v0_Object *)handle->object;
 795
 796     /* Disable DAC mode */
 797     CSL_ospiDacEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
 798
 799     if (hwAttrs->phyEnable == (bool)true)
 800     {
 801         /* Enable PHY pipeline mode for read */
 802         CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
 803     }
 804
 805     /* Set read address in indirect mode */
 806     CSL_ospiIndSetStartAddr((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 807                             offset,
 808                             TRUE);
 809     CSL_ospiIndReadExecute((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), count);
 810
 811     if ((uint32_t)SPI_OPER_MODE_POLLING == object->intrPollMode)
 812     {
 813         remaining = count;
 814         while(remaining > 0U)
 815         {
 816             /* Wait indirect read SRAM fifo has data */
 817             if (OSPI_waitReadSramLvl((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 818                                      &sramLevel) != (int32_t)0U)
 819             {
 820                 retFlag = 1U;
 821                 retVal = (int32_t)(-1);
 822                 transaction->status=SPI_TRANSFER_FAILED;
 823                 break;
 824             }
 825
 826             rdBytes = sramLevel * CSL_OSPI_FIFO_WIDTH;
 827             rdBytes = (rdBytes > remaining) ? remaining : rdBytes;
 828
 829             /* Read data from FIFO */
 830             CSL_ospiReadFifoData(hwAttrs->dataAddr+0x3FE0000, pDst, rdBytes);
 831
 832             pDst += rdBytes;
 833             remaining -= rdBytes;
 834         }
 835         if(retFlag == 0U)
 836         {
 837             if (OSPI_waitIndReadComplete((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr)) != (int32_t)0U)
 838             {
 839                 retFlag = 1U;
 840                 retVal = (int32_t)(-1);
 841                 transaction->status=SPI_TRANSFER_FAILED;
 842             }
 843         }
 844     }
 845 #if defined (__aarch64__) || defined (__TI_ARM_V7R4__)
 846     CSL_archMemoryFence();
 847 #endif
 848
 849     return (retVal);
 850 }
 851
 852 static uint8_t OSPI_getDeviceStatus(SPI_Handle handle);
 853 static uint8_t OSPI_getDeviceStatus(SPI_Handle handle)
 854 {
 855     OSPI_v0_HwAttrs const *hwAttrs; /* OSPI hardware attributes */
 856     OSPI_v0_Object        *object;  /* OSPI object */
 857     uint8_t                status = 0xff;
 858
 859     hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
 860     object = (OSPI_v0_Object *)handle->object;
 861
 862     (void)OSPI_cmdRead((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
 863                        object->rdStatusCmd,
 864                        &status,
 865                        1);
 866
 867     return (status);
 868 }
 869
 870 static bool OSPI_waitDeviceReady(SPI_Handle handle, uint32_t timeOut);
 871 static bool OSPI_waitDeviceReady(SPI_Handle handle, uint32_t timeOut)
 872 {
 873     bool         retVal = (bool)false;
 874     uint8_t      status;
 875     uint32_t     timeOutVal = timeOut;
 876
 877     while (timeOutVal != 0U)
 878     {
 879         status = OSPI_getDeviceStatus(handle);
 880         if ((status & 1U) == 0U)
 881         {
 882             retVal = (bool)true;
 883             break;
 884         }
 885         timeOutVal--;
 886         OSPI_delay(OSPI_CHECK_IDLE_DELAY);
 887     }
 888
 889     return (retVal);
 890 }
 891
 892 static int32_t OSPI_dac_xfer_mode_read_v0(SPI_Handle handle,
 893                                           const SPI_Transaction *transaction)
 894 {
 895     OSPI_v0_HwAttrs const *hwAttrs;      /* OSPI hardware attributes */
 896     uint8_t               *pSrc;         /* Source address */
 897     uint8_t               *pDst;         /* Destination address */
 898     uint32_t               offset;       /* OSPI flash offset address */
 899     uint32_t               i;
 900     uint32_t               size;
 901     uint32_t               remainSize;
 902
 903     /* Copy flash transaction parameters to local variables */
 904     offset = (uint32_t)((uintptr_t)transaction->arg); /* OSPI Flash offset address to read */
 905     pDst = (uint8_t *)transaction->rxBuf;
 906
 907     /* Get the pointer to the object and hwAttrs */
 908     hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
 909
 910 #ifdef SPI_DMA_ENABLE
 911     if (hwAttrs->dmaEnable == (bool)true)
 912     {
 913         if (hwAttrs->phyEnable == (bool)true)
 914         {
 915             /* Enable PHY pipeline mode for read */
 916             CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
 917         }
 918         OSPI_dmaTransfer(handle, transaction);
 919     }
 920     else
 921 #endif
 922     {
 923         if (hwAttrs->phyEnable == (bool)true)
 924         {
 925             /* Enable PHY pipeline mode for read */
 926             CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
 927         }
 928         pSrc = (uint8_t *)(hwAttrs->dataAddr + offset);
 929         remainSize = (uint32_t)transaction->count & 3U;
 930         size = (uint32_t)transaction->count - remainSize;
 931         /* Transfer the data in 32-bit size */
 932         for (i = 0U; i < size; i += 4U)
 933         {
 934             CSL_REG32_WR(pDst + i, CSL_REG32_RD(pSrc + i));
 935 #if defined (__aarch64__)
 936             CSL_archMemoryFence();
 937 #endif
 938         }
 939         /* Transfer the remaining data in 8-bit size */
 940         for (i = 0; i < remainSize; i++)
 941         {
 942             CSL_REG8_WR(pDst + size + i, CSL_REG8_RD(pSrc + size + i));
 943 #if defined (__aarch64__)
 944             CSL_archMemoryFence();
 945 #endif
 946         }
 947     CacheP_wbInv((void *)(hwAttrs->dataAddr + offset), transaction->count);
 948     }
 949
 950     return (0);
 951 }
 952
 953 static int32_t OSPI_flashExecCmd(const CSL_ospi_flash_cfgRegs *pRegs)
 954 {
 955     uint32_t retry = OSPI_DAC_WRITE_TIMEOUT;
 956     int32_t  retVal = 0;
 957     uint32_t idleFlag = FALSE;
 958
 959     while (idleFlag == FALSE)
 960     {
 961         idleFlag = CSL_ospiIsIdle(pRegs);
 962     }
 963
 964     /* Start to execute flash read/write command */
 965     CSL_ospiFlashExecCmd(pRegs);
 966
 967     while (retry != 0U)
 968     {
 969         /* Check the command execution status */
 970         if (CSL_ospiFlashExecCmdComplete(pRegs) == TRUE)
 971         {
 972             break;
 973         }
 974         OSPI_delay(OSPI_CHECK_IDLE_DELAY);
 975         retry--;
 976     }
 977
 978     if (retry == 0U)
 979     {
 980         retVal = (int32_t)(-1);
 981     }
 982
 983     idleFlag = FALSE;
 984     while (idleFlag == FALSE)
 985     {
 986         idleFlag = CSL_ospiIsIdle(pRegs);
 987     }
 988
 989     return (retVal);
 990 }
 991
 992 static int32_t OSPI_cmdRead(const CSL_ospi_flash_cfgRegs *pRegs,
 993                             uint32_t                      cmd,
 994                             uint8_t                      *rxBuf,
 995                             uint32_t                      rxLen)
 996 {
 997     uint32_t regVal;
 998     uint32_t rdLen;
 999     int32_t  retVal;
1000     uint8_t *pBuf = rxBuf;
1001
1002     (void)CSL_ospiCmdRead(pRegs, cmd, rxLen);
1003     retVal = OSPI_flashExecCmd(pRegs);
1004     if (retVal == 0)
1005     {
1006         regVal = CSL_REG32_RD(&pRegs->FLASH_RD_DATA_LOWER_REG);
1007
1008         /* Put the read value into rxBuf */
1009         rdLen = (rxLen > 4U) ? 4U : rxLen;
1010         (void)memcpy((void *)pBuf, (void *)(&regVal), rdLen);
1011         pBuf += rdLen;
1012
1013         if (rxLen > 4U) {
1014             regVal = CSL_REG32_RD(&pRegs->FLASH_RD_DATA_UPPER_REG);
1015             rdLen = rxLen - rdLen;
1016             (void)memcpy((void *)pBuf, (void *)(&regVal), rdLen);
1017         }
1018     }
1019     return (retVal);
1020 }
1021
1022 static int32_t OSPI_cmdExtRead(const CSL_ospi_flash_cfgRegs *pRegs,
1023                                uint8_t                      *cmd,
1024                                uint32_t                     cmdLen,
1025                                uint8_t                      *rxBuf,
1026                                uint32_t                     rxLen,
1027                                uint32_t                     dummyCycles)
1028 {
1029     uint32_t regVal;
1030     uint32_t rdLen;
1031     int32_t  retVal;
1032     uint8_t *pBuf = rxBuf;
1033
1034     (void)CSL_ospiCmdExtRead(pRegs, cmd, cmdLen, rxLen, dummyCycles);
1035     retVal = OSPI_flashExecCmd(pRegs);
1036     if (retVal == 0)
1037     {
1038         regVal = CSL_REG32_RD(&pRegs->FLASH_RD_DATA_LOWER_REG);
1039
1040         /* Put the read value into rxBuf */
1041         rdLen = (rxLen > 4U) ? 4U : rxLen;
1042         (void)memcpy((void *)pBuf, (void *)(&regVal), rdLen);
1043         pBuf += rdLen;
1044
1045         if (rxLen > 4U) {
1046             regVal = CSL_REG32_RD(&pRegs->FLASH_RD_DATA_UPPER_REG);
1047             rdLen = rxLen - rdLen;
1048             (void)memcpy((void *)pBuf, (void *)(&regVal), rdLen);
1049         }
1050     }
1051     return (retVal);
1052 }
1053
1054 static int32_t OSPI_cmd_mode_read_v0(SPI_Handle handle,
1055                                      SPI_Transaction *transaction)
1056 {
1057     OSPI_v0_HwAttrs const *hwAttrs;    /* OSPI hardware attributes */
1058     OSPI_v0_Object        *object;  /* OSPI object */
1059     uint8_t               *cmd;
1060     int32_t               retVal;
1061
1062     cmd = (uint8_t *)transaction->txBuf;
1063     /* Get the pointer to the hwAttrs */
1064     hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
1065     object  = (OSPI_v0_Object *)handle->object;
1066
1067     if(CSL_ospiGetDualByteOpcodeMode((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr)))
1068     {
1069         retVal = OSPI_cmdExtRead((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1070                                  (uint8_t *)cmd,
1071                                  (uint32_t)CSL_OSPI_CMD_LEN_EXTENDED,
1072                                  (uint8_t *)transaction->rxBuf,
1073                                  (uint32_t)transaction->count - CSL_OSPI_CMD_LEN_EXTENDED,
1074                                  (uint32_t)object->extRdDummyClks);
1075     }
1076     else
1077     {
1078         retVal = OSPI_cmdRead((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1079                               (uint32_t)cmd[0],
1080                               (uint8_t *)transaction->rxBuf,
1081                               (uint32_t)transaction->count - CSL_OSPI_CMD_LEN_DEFAULT);
1082     }
1083
1084     return (retVal);
1085 }
1086
1087
1088 static int32_t OSPI_read_v0(SPI_Handle handle, SPI_Transaction *transaction)
1089 {
1090     OSPI_v0_Object *object;
1091     int32_t         retVal = (int32_t)(-1);
1092
1093     object = (OSPI_v0_Object *)handle->object;
1094
1095     if((uint32_t)OSPI_OPER_MODE_IND_XFER == object->ospiMode)
1096     {
1097         retVal = (OSPI_ind_xfer_mode_read_v0(handle, transaction));
1098     }
1099     else if((uint32_t)OSPI_OPER_MODE_DAC_XFER == object->ospiMode)
1100     {
1101         retVal = (OSPI_dac_xfer_mode_read_v0(handle, transaction));
1102     }
1103     else if((uint32_t)OSPI_OPER_MODE_CFG == object->ospiMode)
1104     {
1105         retVal = (OSPI_cmd_mode_read_v0(handle, transaction));
1106     }
1107     else
1108     {
1109         transaction->status=SPI_TRANSFER_CANCELED;
1110     }
1111
1112     return(retVal);
1113 }
1114
1115 static int32_t OSPI_waitWriteSramLvl(const CSL_ospi_flash_cfgRegs *pReg,
1116                                      uint32_t *sramLvl)
1117 {
1118     uint32_t retry = CSL_OSPI_REG_RETRY;
1119     uint32_t sramLevel;
1120     int32_t  retVal = 0;
1121
1122     while(retry != 0U)
1123     {
1124         sramLevel = CSL_ospiGetSramLvl(pReg, 0);
1125         if (sramLevel <= CSL_OSPI_SRAM_WATERMARK_WR_LVL)
1126         {
1127                         *sramLvl = sramLevel;
1128             break;
1129         }
1130         (void)SPI_osalDelay(CSL_OSPI_POLL_IDLE_DELAY);
1131         retry--;
1132     }
1133
1134     if (retry != 0U)
1135     {
1136         retVal = 0;
1137     }
1138     else
1139     {
1140         retVal = (int32_t)(-1);
1141     }
1142     return(retVal);
1143 }
1144
1145 static int32_t OSPI_waitIndWriteComplete(const CSL_ospi_flash_cfgRegs *pRegs)
1146 {
1147     uint32_t retry = OSPI_DAC_WRITE_TIMEOUT;
1148     int32_t  retVal;
1149
1150     /* Check flash indirect write controller status */
1151     while (retry != 0U)
1152     {
1153         if (CSL_ospiIsIndWriteComplete(pRegs) == TRUE)
1154         {
1155             break;
1156         }
1157         OSPI_delay(OSPI_CHECK_IDLE_DELAY);
1158         retry--;
1159     }
1160
1161     if (retry != 0U)
1162     {
1163         /* Clear indirect completion status */
1164         CSL_ospiClrIndWriteComplete(pRegs);
1165         retVal = 0;
1166     }
1167     else
1168     {
1169         retVal = (int32_t)(-1);
1170     }
1171     return(retVal);
1172 }
1173
1174 static int32_t OSPI_ind_xfer_mode_write_v0(SPI_Handle handle,
1175                                            SPI_Transaction *transaction)
1176 {
1177     OSPI_v0_HwAttrs const *hwAttrs;      /* OSPI hardware attributes */
1178     OSPI_v0_Object        *object;       /* OSPI object */
1179     uint8_t               *pSrc;         /* Destination address */
1180     uint32_t               count;        /* transaction length */
1181     uint32_t               offset;       /* OSPI flash offset address */
1182     uint32_t               remaining;
1183     uint32_t               sramLevel, wrBytes;
1184     uint32_t               retFlag = 0;
1185     int32_t                retVal = 0;
1186
1187     object = (OSPI_v0_Object *)handle->object;
1188
1189     /* Copy flash transaction parameters to local variables */
1190     offset = (uint32_t)((uintptr_t)transaction->arg); /* NOR Flash offset address to write */
1191     pSrc = (uint8_t*)transaction->txBuf;
1192     count = (uint32_t)transaction->count;
1193
1194     /* Get the pointer to the object and hwAttrs */
1195     hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
1196     object = (OSPI_v0_Object *)handle->object;
1197
1198     /* Disable DAC mode */
1199     CSL_ospiDacEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
1200
1201     /* Set write address in indirect mode */
1202     CSL_ospiIndSetStartAddr((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1203                             offset,
1204                             FALSE);
1205     CSL_ospiIndWriteExecute((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), count);
1206
1207     if ((uint32_t)SPI_OPER_MODE_POLLING == object->intrPollMode)
1208     {
1209         /* Wait Indirect Write  SRAM fill level below the threshold */
1210         if (OSPI_waitWriteSramLvl((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1211                                   &sramLevel) != (int32_t)0U)
1212         {
1213             retFlag = 1U;
1214             retVal = (int32_t)(-1);
1215             transaction->status=SPI_TRANSFER_FAILED;
1216         }
1217         else
1218         {
1219             remaining = count;
1220             while(remaining > 0U)
1221             {
1222                 /* Wait indirect write SRAM fifo level below watermark */
1223                 if (OSPI_waitWriteSramLvl((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1224                                           &sramLevel) != (int32_t)0U)
1225                 {
1226                     retFlag = 1U;
1227                     retVal = (int32_t)(-1);
1228                     break;
1229                 }
1230
1231                 wrBytes = (CSL_OSPI_SRAM_PARTITION_WR - sramLevel) * CSL_OSPI_FIFO_WIDTH;
1232                 wrBytes = (wrBytes > remaining) ? remaining : wrBytes;
1233
1234                 /* Write data to FIFO */
1235                 CSL_ospiWriteFifoData(hwAttrs->dataAddr+0x3FE0000, pSrc, wrBytes);
1236
1237                 pSrc += wrBytes;
1238                 remaining -= wrBytes;
1239             }
1240
1241             if(retFlag == 0U)
1242             {
1243                 if (OSPI_waitIndWriteComplete((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr)) != (int32_t)0U)
1244                 {
1245                     retFlag = 1U;
1246                     retVal = (int32_t)(-1);
1247                 }
1248             }
1249         }
1250     }
1251
1252     if(retFlag == 1U)
1253     {
1254         transaction->status=SPI_TRANSFER_FAILED;
1255         CSL_ospiIndWriteCancel((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr));
1256     }
1257     return (retVal);
1258 }
1259
1260 static int32_t OSPI_dac_xfer_mode_write_v0(SPI_Handle handle,
1261                                            const SPI_Transaction *transaction)
1262 {
1263     OSPI_v0_HwAttrs const *hwAttrs;      /* OSPI hardware attributes */
1264     uint8_t               *pSrc;         /* Source address */
1265     uint32_t               offset;       /* OSPI flash offset address */
1266     uint32_t               i;
1267     uint8_t               *pDst;         /* Destination address */
1268     uint32_t               size;
1269     uint32_t               remainSize;
1270     int32_t                retVal = 0;
1271     uint32_t               wrWord;
1272     uint32_t               wrByte;
1273
1274     /* Copy flash transaction parameters to local variables */
1275     offset = (uint32_t)((uintptr_t)transaction->arg); /* OSPI Flash offset address to write */
1276     pSrc = (uint8_t *)transaction->txBuf;
1277
1278     /* Get the pointer to the object and hwAttrs */
1279     hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
1280
1281     /* Disable PHY pipeline mode */
1282     CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
1283
1284 #ifdef SPI_DMA_ENABLE
1285     if (hwAttrs->dmaEnable == (bool)true)
1286     {
1287         OSPI_dmaTransfer(handle, transaction);
1288     }
1289     else
1290 #endif
1291     {
1292         pDst = (uint8_t *)(hwAttrs->dataAddr + offset);
1293         remainSize = (uint32_t)transaction->count & 3U;
1294         size = (uint32_t)transaction->count - remainSize;
1295         /* Transfer the data in 32-bit size */
1296         for (i = 0U; i < size; i += 4U)
1297         {
1298             wrWord = CSL_REG32_RD(pSrc + i);
1299             CSL_REG32_WR(pDst + i, wrWord);
1300             if (OSPI_waitDeviceReady(handle, OSPI_DAC_WRITE_TIMEOUT))
1301             {
1302                 retVal = (int32_t)(0);
1303             }
1304             else
1305             {
1306                 retVal = (int32_t)(-1);
1307             }
1308         }
1309         if (retVal == (int32_t)(0))
1310         {
1311             /* Transfer the remaining data in 8-bit size */
1312             for (i = 0; i < remainSize; i++)
1313             {
1314                 wrByte = CSL_REG8_RD(pSrc + size + i);
1315                 CSL_REG8_WR(pDst + size + i, wrByte);
1316                 if (OSPI_waitDeviceReady(handle, OSPI_DAC_WRITE_TIMEOUT))
1317                 {
1318                     retVal = 0;
1319                 }
1320                 else
1321                 {
1322                     retVal = (int32_t)(-1);
1323                 }
1324             }
1325         }
1326     }
1327     CacheP_wbInv((void *)(hwAttrs->dataAddr + offset), transaction->count);
1328     return (retVal);
1329 }
1330
1331 static int32_t OSPI_cmdWrite(const CSL_ospi_flash_cfgRegs *pRegs,
1332                              const uint8_t                *cmdBuf,
1333                              uint32_t                      cmdLen,
1334                              const uint8_t                *txBuf,
1335                              uint32_t                      txLen)
1336 {
1337     (void)CSL_ospiCmdWrite(pRegs, cmdBuf, cmdLen, txBuf, txLen);
1338     return (OSPI_flashExecCmd(pRegs));
1339 }
1340
1341 static int32_t OSPI_cmd_mode_write_v0(SPI_Handle handle,
1342                                       const SPI_Transaction *transaction)
1343 {
1344     OSPI_v0_HwAttrs const *hwAttrs; /* OSPI hardware attributes */
1345     uint8_t               *txBuf;
1346     uint32_t               dataLen;
1347     uint32_t               cmdLen;
1348     int32_t                retVal = 0;
1349
1350     txBuf = (uint8_t *)transaction->txBuf;
1351     dataLen = (uint32_t)((uintptr_t)transaction->arg);
1352     cmdLen = (uint32_t)transaction->count - dataLen;
1353     /* Get the pointer to the object and hwAttrs */
1354     hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
1355
1356     if (dataLen != 0U)
1357     {
1358         retVal = (OSPI_cmdWrite((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1359                                  txBuf,
1360                                  cmdLen,
1361                                  &txBuf[cmdLen],
1362                                  dataLen));
1363     }
1364     else
1365     {
1366         retVal = (OSPI_cmdWrite((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1367                                  txBuf,
1368                                  cmdLen,
1369                                  NULL,
1370                                  0));
1371     }
1372     return (retVal);
1373 }
1374
1375
1376 static int32_t OSPI_write_v0(SPI_Handle handle, SPI_Transaction *transaction)
1377 {
1378     OSPI_v0_Object  *object;
1379     int32_t          retVal = (int32_t)(-1);
1380
1381     /* Get the pointer to the object and hwAttrs */
1382     object = (OSPI_v0_Object *)handle->object;
1383
1384     if((uint32_t)OSPI_OPER_MODE_IND_XFER == object->ospiMode)
1385     {
1386         retVal = (OSPI_ind_xfer_mode_write_v0(handle, transaction));
1387     }
1388     else if((uint32_t)OSPI_OPER_MODE_DAC_XFER == object->ospiMode)
1389     {
1390         retVal = (OSPI_dac_xfer_mode_write_v0(handle, transaction));
1391     }
1392     else if((uint32_t)OSPI_OPER_MODE_CFG == object->ospiMode)
1393     {
1394         retVal = (OSPI_cmd_mode_write_v0(handle, transaction));
1395     }
1396     else
1397     {
1398         transaction->status=SPI_TRANSFER_CANCELED;
1399     }
1400     return (retVal);
1401 }
1402
1403
1404 /*
1405  *  ======== OSPI_transfer_v0 ========
1406  */
1407 static bool OSPI_transfer_v0(SPI_Handle handle, SPI_Transaction *transaction)
1408 {
1409     bool                   ret = (bool)false; /* return value */
1410     OSPI_v0_HwAttrs const *hwAttrs;     /* OSPI hardware attributes */
1411     OSPI_v0_Object        *object;      /* OSPI object */
1412     uintptr_t              key;
1413     int32_t                xferRet;
1414
1415     /* Check if anything needs to be written or read */
1416     if ((handle != NULL) && (transaction != NULL) && (0U != (uint32_t)transaction->count))
1417     {
1418         /* Get the pointer to the object and hwAttrs */
1419         object = (OSPI_v0_Object *)handle->object;
1420         hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
1421
1422         /* Check if a transfer is in progress */
1423         key = SPI_osalHardwareIntDisable();
1424         if (object->transaction != NULL)
1425         {
1426             SPI_osalHardwareIntRestore(key);
1427             /* Transfer is in progress */
1428             transaction->status = SPI_TRANSFER_CANCELED;
1429         }
1430         else
1431         {
1432             /* Save the pointer to the transaction */
1433             object->transaction = transaction;
1434
1435             /* Acquire the lock for this particular I2C handle */
1436             (void)SPI_osalPendLock(object->mutex, SemaphoreP_WAIT_FOREVER);
1437
1438             /* Book keeping of transmit and receive buffers. */
1439             object->writeBufIdx = (uint8_t *)transaction->txBuf;
1440             object->writeCountIdx = (uint32_t)transaction->count;
1441             object->readBufIdx =  (uint8_t *)transaction->rxBuf;
1442             object->readCountIdx = (uint32_t)transaction->count;
1443
1444              /*
1445              * OSPI_primeTransfer_v0 is a longer process and
1446              * protection is needed from the OSPI interrupt
1447              */
1448             if ((uint32_t)SPI_OPER_MODE_POLLING != object->intrPollMode)
1449             {
1450                 SPI_osalHardwareIntrEnable((int32_t)hwAttrs->intrNum, (int32_t)hwAttrs->eventId);
1451             }
1452
1453             xferRet = OSPI_primeTransfer_v0(handle, transaction);
1454             SPI_osalHardwareIntRestore(key);
1455
1456             if (xferRet == 0)
1457             {
1458                 if (object->intrPollMode == (uint32_t)SPI_OPER_MODE_BLOCKING)
1459                 {
1460                     ret = (bool)true;
1461                     if (object->ospiMode == (uint32_t)OSPI_OPER_MODE_IND_XFER)
1462                     {
1463                         /* In indirect transfer mode, wait for the lock
1464                            posted form the word completion interrupt */
1465                         (void)SPI_osalPendLock(object->transferComplete, SemaphoreP_WAIT_FOREVER);
1466                     }
1467 #ifdef SPI_DMA_ENABLE
1468                     if ((object->ospiMode == (uint32_t)OSPI_OPER_MODE_DAC_XFER) && (hwAttrs->dmaEnable == (bool)true))
1469                     {
1470                         /* in direct transfer mode with DMA enabled, wait for the lock
1471                            posted form the word completion interrupt */
1472                         (void)SPI_osalPendLock(object->transferComplete, SemaphoreP_WAIT_FOREVER);
1473                         if((uint32_t)SPI_TRANSACTION_TYPE_WRITE == object->transactionType)
1474                         {
1475                             ret = OSPI_waitDeviceReady(handle, OSPI_DAC_WRITE_TIMEOUT);
1476                         }
1477                     }
1478 #endif
1479                     /* transfer is completed and semaphore is posted. */
1480                 }
1481                 else
1482                 {
1483                     /* Always return true if in Asynchronous mode */
1484                     ret = (bool)true;
1485                 }
1486                 transaction->status = SPI_TRANSFER_COMPLETED;
1487                 /* Release the lock for this particular SPI handle */
1488
1489                 (void)SPI_osalPostLock(object->mutex);
1490             }
1491             else
1492             {
1493                 transaction->status=SPI_TRANSFER_FAILED;
1494             }
1495
1496             if (object->intrPollMode != (uint32_t)SPI_OPER_MODE_CALLBACK)
1497             {
1498                 object->transaction = NULL;
1499             }
1500         }
1501     }
1502     else
1503     {
1504         if (transaction != NULL)
1505         {
1506             transaction->status = SPI_TRANSFER_CANCELED;
1507         }
1508     }
1509
1510     /* Return the number of bytes transferred by the I2C */
1511     return (ret);
1512 }
1513
1514 /*
1515  *  ======== OSPI_transferCallback_v0 ========
1516  */
1517 static void OSPI_transferCallback_v0(SPI_Handle handle, SPI_Transaction *msg)
1518 {
1519     OSPI_v0_Object        *object;  /* OSPI object */
1520
1521     if (handle != NULL)
1522     {
1523         /* Get the pointer to the object */
1524         object = (OSPI_v0_Object *)handle->object;
1525
1526         /* Indicate transfer complete */
1527         (void)SPI_osalPostLock(object->transferComplete);
1528         msg = msg;
1529     }
1530
1531 }
1532
1533 static int32_t OSPI_configDdr(SPI_Handle handle, uint32_t cmd, uint32_t addr, uint32_t data);
1534 static int32_t OSPI_configDdr(SPI_Handle handle, uint32_t cmd, uint32_t addr, uint32_t data)
1535 {
1536     OSPI_v0_HwAttrs const *hwAttrs; /* OSPI hardware attributes */
1537     int32_t                retVal;
1538
1539     hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
1540     CSL_ospiFlashStig((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), cmd, addr, data);
1541     retVal = OSPI_flashExecCmd((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr));
1542     if (retVal == 0)
1543     {
1544         if (hwAttrs->dacEnable)
1545         {
1546             CSL_ospiDacEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
1547         }
1548         else
1549         {
1550             CSL_ospiDacEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
1551         }
1552
1553         /* Enable DTR protocol */
1554         if (hwAttrs->dtrEnable == (bool)true)
1555         {
1556             CSL_ospiDtrEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
1557         }
1558         else
1559         {
1560             CSL_ospiDtrEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
1561         }
1562     }
1563
1564     return (retVal);
1565 }
1566
1567 static int32_t OSPI_enableXip (SPI_Handle handle, uint32_t cmd, uint32_t addr, uint32_t data)
1568 {
1569     OSPI_v0_HwAttrs const *hwAttrs; /* OSPI hardware attributes */
1570     int32_t                retVal;
1571
1572     hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
1573
1574     /* Disable Direct Access Controller */
1575     CSL_ospiDacEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
1576
1577     /* Configure Flash Command Control Register to issue VCR write to FLASH memory to enable/disable XIP mode */
1578     CSL_ospiFlashStig((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), cmd, addr, data);
1579     retVal = OSPI_flashExecCmd((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr));
1580     if (retVal == 0)
1581     {
1582         OSPI_delay(OSPI_XIP_SETUP_DELAY);
1583
1584         /* Clear the XIP mode bits in the Mode Bit Configuration Register. */
1585         CSL_ospiSetModeBits((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), 0x00);
1586
1587         /* Enable the local controllers XIP mode */
1588         CSL_ospiXipEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
1589     }
1590
1591     /* Re-enable the Direct Access Controller */
1592     CSL_ospiDacEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
1593     return (retVal);
1594 }
1595
1596 static int32_t OSPI_configDummyCycle(SPI_Handle handle, uint32_t cmd, uint32_t addr, uint32_t data);
1597 static int32_t OSPI_configDummyCycle(SPI_Handle handle, uint32_t cmd, uint32_t addr, uint32_t data)
1598 {
1599     OSPI_v0_HwAttrs const *hwAttrs; /* OSPI hardware attributes */
1600     int32_t                retVal;
1601
1602     hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
1603     CSL_ospiFlashStig((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), cmd, addr, data);
1604     retVal = OSPI_flashExecCmd((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr));
1605
1606     return (retVal);
1607 }
1608
1609 /*
1610  *  ======== OSPI_control_v0 ========
1611  */
1612 static int32_t OSPI_control_v0(SPI_Handle handle, uint32_t cmd, const void *arg)
1613 {
1614     OSPI_v0_HwAttrs       *hwAttrs; /* OSPI hardware attributes */
1615     OSPI_v0_Object        *object;  /* OSPI object */
1616     int32_t                retVal = SPI_STATUS_ERROR;
1617     const uint32_t        *ctrlData = (const uint32_t *)arg;
1618     uint32_t               nvcrCmd;
1619     uint32_t               addr;
1620     uint32_t               data;
1621     uint32_t               extOpcodeLo;
1622     uint32_t               extOpcodeUp;
1623
1624     if (handle != NULL)
1625     {
1626         /* Get the pointer to the object */
1627         object = (OSPI_v0_Object *)handle->object;
1628         hwAttrs = (OSPI_v0_HwAttrs *)handle->hwAttrs;
1629
1630         switch (cmd)
1631         {
1632             case SPI_V0_CMD_XFER_OPCODE:
1633             {
1634                 object->transferCmd = *ctrlData;
1635                 ctrlData++;
1636                 CSL_ospiConfigRead((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1637                                    object->transferCmd,
1638                                    object->xferLines,
1639                                    object->rdDummyClks);
1640                 object->transferCmd = *ctrlData;
1641                 ctrlData++;
1642                 CSL_ospiWriteSetup((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1643                                    object->transferCmd,
1644                                    object->xferLines);
1645                 object->rdStatusCmd = *ctrlData;
1646                 retVal = SPI_STATUS_SUCCESS;
1647                 break;
1648             }
1649
1650             case SPI_V0_CMD_XFER_OPCODE_EXT:
1651             {
1652                 extOpcodeLo  = *ctrlData++; /* EXT_STIG_OPCODE_FLD */
1653                 extOpcodeLo |= (*ctrlData++ << 8); /* EXT_POLL_OPCODE_FLD */
1654                 extOpcodeLo |= (*ctrlData++ << 16); /* EXT_WRITE_OPCODE_FLD */
1655                 extOpcodeLo |= (*ctrlData++ << 24); /* EXT_READ_OPCODE_FLD */
1656
1657                 extOpcodeUp  = (*ctrlData++ << 16); /* EXT_WEL_OPCODE_FLD */
1658                 extOpcodeUp |= (*ctrlData << 24); /* WEL_OPCODE_FLD */
1659
1660                 CSL_ospiExtOpcodeSet((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1661                                      extOpcodeLo,
1662                                      extOpcodeUp);
1663                 CSL_ospiSetDualByteOpcodeMode((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1664                                               TRUE);
1665                 retVal = SPI_STATUS_SUCCESS;
1666                 break;
1667             }
1668
1669             case SPI_V0_CMD_XFER_MODE_RW:
1670             {
1671                 object->transactionType = *ctrlData;
1672                 retVal = SPI_STATUS_SUCCESS;
1673                 break;
1674             }
1675
1676             case SPI_V0_CMD_SET_CFG_MODE:
1677             {
1678                 object->ospiMode = (uint32_t)OSPI_OPER_MODE_CFG;
1679                 retVal = SPI_STATUS_SUCCESS;
1680                 break;
1681             }
1682
1683             case SPI_V0_CMD_SET_XFER_MODE:
1684             {
1685                 if (hwAttrs->dacEnable)
1686                 {
1687                     object->ospiMode = (uint32_t)OSPI_OPER_MODE_DAC_XFER;
1688                 }
1689                 else
1690                 {
1691                     object->ospiMode = (uint32_t)OSPI_OPER_MODE_IND_XFER;
1692                 }
1693                 retVal = SPI_STATUS_SUCCESS;
1694                 break;
1695             }
1696
1697             case SPI_V0_CMD_SET_XFER_LINES:
1698             {
1699                 uint32_t numAddrBytes;
1700                 object->xferLines = *ctrlData;
1701                 numAddrBytes = CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_3;
1702                 if ((object->xferLines == OSPI_XFER_LINES_OCTAL) && (hwAttrs->dtrEnable))
1703                 {
1704                     numAddrBytes = CSL_OSPI_MEM_MAP_NUM_ADDR_BYTES_4;
1705                 }
1706
1707                 /* Set device size cofigurations */
1708                 CSL_ospiSetDevSize((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1709                                    numAddrBytes,
1710                                    hwAttrs->pageSize,
1711                                    hwAttrs->blkSize);
1712                 retVal = SPI_STATUS_SUCCESS;
1713                 break;
1714             }
1715
1716             case SPI_V0_CMD_RD_DUMMY_CLKS:
1717             {
1718                 object->rdDummyClks = *ctrlData;
1719                 retVal = SPI_STATUS_SUCCESS;
1720                 break;
1721             }
1722
1723             case SPI_V0_CMD_EXT_RD_DUMMY_CLKS:
1724             {
1725                 object->extRdDummyClks = *ctrlData;
1726                 retVal = SPI_STATUS_SUCCESS;
1727                 break;
1728             }
1729
1730             case SPI_V0_CMD_CFG_PHY:
1731             {
1732                 uint32_t phyEnable = *ctrlData++;
1733                 if (phyEnable == TRUE)
1734                 {
1735                     if (hwAttrs->phyEnable == (bool)false)
1736                     {
1737                         CSL_ospiSetPreScaler((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1738                                              CSL_OSPI_BAUD_RATE_DIVISOR(2U));
1739                         /* Enable PHY mode */
1740                         CSL_ospiPhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
1741                         hwAttrs->phyEnable = (bool)true;
1742                     }
1743                     uint32_t txDelay = *ctrlData++;
1744                     uint32_t rxDelay = *ctrlData;
1745                     CSL_ospiConfigPhyDLL((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1746                                          txDelay, rxDelay);
1747                 }
1748                 else
1749                 {
1750                     if (hwAttrs->phyEnable == (bool)true)
1751                     {
1752                         /* Disable high speed mode when PHY is disabled */
1753                         CSL_ospiSetPreScaler((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1754                                              CSL_OSPI_BAUD_RATE_DIVISOR_DEFAULT);
1755                         CSL_ospiPhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
1756                         hwAttrs->phyEnable = (bool)false;
1757                     }
1758                 }
1759                 retVal = SPI_STATUS_SUCCESS;
1760                 break;
1761             }
1762
1763             case SPI_V0_CMD_ENABLE_DDR:
1764             case SPI_V0_CMD_ENABLE_SDR:
1765             {
1766                 nvcrCmd = *ctrlData;
1767                 ctrlData++;
1768                 addr   = *ctrlData;
1769                 ctrlData++;
1770                 data   = *ctrlData;
1771                 retVal = OSPI_configDdr(handle, nvcrCmd, addr, data);
1772                 break;
1773             }
1774
1775             case SPI_V0_CMD_CFG_XIP:
1776             {
1777                 if (hwAttrs->xipEnable == (bool)true) {
1778                     nvcrCmd = *ctrlData;
1779                     ctrlData++;
1780                     addr = *ctrlData;
1781                     ctrlData++;
1782                     data = *ctrlData;
1783
1784                     (void)OSPI_enableXip(handle, nvcrCmd , addr, data);
1785                 }
1786                 /* Enable PHY pipeline mode for read */
1787                 CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);
1788                 break;
1789             }
1790
1791             case SPI_V0_CMD_CFG_RD_DELAY:
1792             {
1793                 uint32_t rdDelay = *ctrlData;
1794                 CSL_ospiSetDataReadCapDelay((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
1795                                             rdDelay);
1796                 retVal = SPI_STATUS_SUCCESS;
1797                 break;
1798             }
1799
1800             case SPI_V0_CMD_CFG_DUMMY_CYCLE:
1801             {
1802                 nvcrCmd = *ctrlData;
1803                 ctrlData++;
1804                 addr   = *ctrlData;
1805                 ctrlData++;
1806                 data   = *ctrlData;
1807                 retVal = OSPI_configDummyCycle(handle, nvcrCmd, addr, data);
1808                 break;
1809             }
1810
1811             default:
1812                 retVal = SPI_STATUS_UNDEFINEDCMD;
1813             break;
1814         }
1815     }
1816
1817     return retVal;
1818 }
1819
1820
1821 /*
1822  *  ======== OSPI_transferCancel_v0 ========
1823  */
1824 static void OSPI_transferCancel_v0(SPI_Handle handle)
1825 {
1826     (void)handle;
1827     return;
1828 }