[processor-sdk/pdk.git] / packages / ti / drv / spi / test / ospi_flash / j7200 / non_cached / baremetal_mpu_config.c
1 /**\r
2 * \file baremetal_mpu_config.c\r
3 *\r
4 * \brief File to override the mpu config in baremetal builds\r
5 *\r
6 */\r
7 \r
8 /*\r
9 * Copyright (C) 2017 - 2020 Texas Instruments Incorporated - http://www.ti.com/\r
10 *\r
11 * Redistribution and use in source and binary forms, with or without\r
12 * modification, are permitted provided that the following conditions\r
13 * are met:\r
14 *\r
15 * Redistributions of source code must retain the above copyright\r
16 * notice, this list of conditions and the following disclaimer.\r
17 *\r
18 * Redistributions in binary form must reproduce the above copyright\r
19 * notice, this list of conditions and the following disclaimer in the\r
20 * documentation and/or other materials provided with the\r
21 * distribution.\r
22 *\r
23 * Neither the name of Texas Instruments Incorporated nor the names of\r
24 * its contributors may be used to endorse or promote products derived\r
25 * from this software without specific prior written permission.\r
26 *\r
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38 *\r
39 */\r
40 \r
41 #include <ti/csl/arch/csl_arch.h>\r
42 \r
43 const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =\r
44 {\r
45 {\r
46 /* Region 0 configuration: complete 32 bit address space = 4Gbits */\r
47 .regionId = 0U,\r
48 .enable = 1U,\r
49 .baseAddr = 0x0U,\r
50 .size = CSL_ARM_R5_MPU_REGION_SIZE_4GB,\r
51 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
52 .exeNeverControl = 1U,\r
53 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
54 .shareable = 0U,\r
55 .cacheable = (uint32_t)FALSE,\r
56 .cachePolicy = 0U,\r
57 .memAttr = 0U,\r
58 },\r
59 {\r
60 /* Region 1 configuration: 128 bytes memory for exception vector execution */\r
61 .regionId = 1U,\r
62 .enable = 1U,\r
63 .baseAddr = 0x0U,\r
64 .size = CSL_ARM_R5_MPU_REGION_SIZE_128B,\r
65 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
66 .exeNeverControl = 0U,\r
67 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
68 .shareable = 0U,\r
69 .cacheable = (uint32_t)TRUE,\r
70 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
71 .memAttr = 0U,\r
72 },\r
73 {\r
74 /* Region 2 configuration: 1MB KB MCU MSRAM */\r
75 .regionId = 2U,\r
76 .enable = 1U,\r
77 .baseAddr = 0x41C00000,\r
78 .size = CSL_ARM_R5_MPU_REGION_SIZE_1MB,\r
79 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
80 .exeNeverControl = 0U,\r
81 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
82 .shareable = 0U,\r
83 .cacheable = (uint32_t)TRUE,\r
84 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
85 .memAttr = 0U,\r
86 },\r
87 {\r
88 /* Region 3 configuration: 1 MB MCMS3 RAM */\r
89 .regionId = 3U,\r
90 .enable = 1U,\r
91 .baseAddr = 0x70000000,\r
92 .size = CSL_ARM_R5_MPU_REGION_SIZE_1MB,\r
93 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
94 .exeNeverControl = 0U,\r
95 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
96 .shareable = 0U,\r
97 .cacheable = (uint32_t)TRUE,\r
98 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
99 .memAttr = 0U,\r
100 },\r
101 {\r
102 /* Region 4 configuration: 2 GB DDR RAM */\r
103 .regionId = 4U,\r
104 .enable = 1U,\r
105 .baseAddr = 0x80000000,\r
106 .size = CSL_ARM_R5_MPU_REGION_SIZE_2GB,\r
107 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
108 .exeNeverControl = 0U,\r
109 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
110 .shareable = 0U,\r
111 .cacheable = (uint32_t)TRUE,\r
112 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
113 .memAttr = 0U,\r
114 },\r
115 {\r
116 /* Region 5 configuration: 32 KB BTCM */\r
117 /* Address of ATCM/BTCM are configured via MCU_SEC_MMR registers\r
118 It can either be '0x0' or '0x41010000'. Application/Boot-loader shall\r
119 take care this configurations and linker command file shall be\r
120 in sync with this. For either of the above configurations,\r
121 MPU configurations will not changes as both regions will have same\r
122 set of permissions in almost all scenarios.\r
123 Application can chose to overwrite this MPU configuration if needed.\r
124 The same is true for the region corresponding to ATCM. */\r
125 .regionId = 5U,\r
126 .enable = 1U,\r
127 .baseAddr = 0x41010000,\r
128 .size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,\r
129 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
130 .exeNeverControl = 0U,\r
131 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
132 .shareable = 0U,\r
133 .cacheable = (uint32_t)TRUE,\r
134 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,\r
135 .memAttr = 0U,\r
136 },\r
137 {\r
138 /* Region 6 configuration: 32 KB ATCM */\r
139 .regionId = 6U,\r
140 .enable = 1U,\r
141 .baseAddr = 0x0,\r
142 .size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,\r
143 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
144 .exeNeverControl = 0U,\r
145 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
146 .shareable = 0U,\r
147 .cacheable = (uint32_t)TRUE,\r
148 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,\r
149 .memAttr = 0U,\r
150 },\r
151 };\r