b58e8c2cd6f48cdf3a4817dcb5cd49b2eb3e6ec1
[processor-sdk/pdk.git] / packages / ti / drv / spi / test / ospi_flash / j721e / cached / baremetal_mpu_config.c
1 #include <ti/csl/arch/csl_arch.h>\r
2 \r
3 const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =\r
4 {\r
5     {\r
6         /* Region 0 configuration: complete 32 bit address space = 4Gbits */\r
7         .regionId         = 0U,\r
8         .enable           = 1U,\r
9         .baseAddr         = 0x0U,\r
10         .size             = CSL_ARM_R5_MPU_REGION_SIZE_4GB,\r
11         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
12         .exeNeverControl  = 1U,\r
13         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
14         .shareable        = 0U,\r
15         .cacheable        = (uint32_t)FALSE,\r
16         .cachePolicy      = 0U,\r
17         .memAttr          = 0U,\r
18     },\r
19     {\r
20         /* Region 1 configuration: 128 bytes memory for exception vector execution */\r
21         .regionId         = 1U,\r
22         .enable           = 1U,\r
23         .baseAddr         = 0x0U,\r
24         .size             = CSL_ARM_R5_MPU_REGION_SIZE_128B,\r
25         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
26         .exeNeverControl  = 0U,\r
27         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
28         .shareable        = 0U,\r
29         .cacheable        = (uint32_t)TRUE,\r
30         .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
31         .memAttr          = 0U,\r
32     },\r
33     {\r
34         /* Region 2 configuration: 1MB KB MCU MSRAM */\r
35         .regionId         = 2U,\r
36         .enable           = 1U,\r
37         .baseAddr         = 0x41C00000,\r
38         .size             = CSL_ARM_R5_MPU_REGION_SIZE_1MB,\r
39         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
40         .exeNeverControl  = 0U,\r
41         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
42         .shareable        = 0U,\r
43         .cacheable        = (uint32_t)TRUE,\r
44         .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
45         .memAttr          = 0U,\r
46     },\r
47     {\r
48         /* Region 3 configuration: 8 MB MCMS3 RAM */\r
49         .regionId         = 3U,\r
50         .enable           = 1U,\r
51         .baseAddr         = 0x70000000,\r
52         .size             = CSL_ARM_R5_MPU_REGION_SIZE_8MB,\r
53         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
54         .exeNeverControl  = 0U,\r
55         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
56         .shareable        = 0U,\r
57         .cacheable        = (uint32_t)TRUE,\r
58         .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
59         .memAttr          = 0U,\r
60     },\r
61     {\r
62         /* Region 4 configuration: 2 GB DDR RAM */\r
63         .regionId         = 4U,\r
64         .enable           = 1U,\r
65         .baseAddr         = 0x80000000,\r
66         .size             = CSL_ARM_R5_MPU_REGION_SIZE_2GB,\r
67         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
68         .exeNeverControl  = 0U,\r
69         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
70         .shareable        = 0U,\r
71         .cacheable        = (uint32_t)TRUE,\r
72         .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
73         .memAttr          = 0U,\r
74     },\r
75     {\r
76         /* Region 5 configuration: 32 KB BTCM */\r
77         /* Address of ATCM/BTCM are configured via MCU_SEC_MMR registers\r
78            It can either be '0x0' or '0x41010000'. Application/Boot-loader shall\r
79            take care this configurations and linker command file shall be\r
80            in sync with this. For either of the above configurations,\r
81            MPU configurations will not changes as both regions will have same\r
82            set of permissions in almost all scenarios.\r
83            Application can chose to overwrite this MPU configuration if needed.\r
84            The same is true for the region corresponding to ATCM. */\r
85         .regionId         = 5U,\r
86         .enable           = 1U,\r
87         .baseAddr         = 0x41010000,\r
88         .size             = CSL_ARM_R5_MPU_REGION_SIZE_32KB,\r
89         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
90         .exeNeverControl  = 0U,\r
91         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
92         .shareable        = 0U,\r
93         .cacheable        = (uint32_t)TRUE,\r
94         .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,\r
95         .memAttr          = 0U,\r
96     },\r
97     {\r
98         /* Region 6 configuration: 32 KB ATCM */\r
99         .regionId         = 6U,\r
100         .enable           = 1U,\r
101         .baseAddr         = 0x0,\r
102         .size             = CSL_ARM_R5_MPU_REGION_SIZE_32KB,\r
103         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
104         .exeNeverControl  = 0U,\r
105         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
106         .shareable        = 0U,\r
107         .cacheable        = (uint32_t)TRUE,\r
108         .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,\r
109         .memAttr          = 0U,\r
110     },\r
111     {\r
112         //Region 7 configuration: Covers first 32MB of EVM Flash (FSS DAT0) *\r
113         .regionId         = 7U,\r
114         .enable           = 1U,\r
115         .baseAddr         = 0x50000000,\r
116         .size             = CSL_ARM_R5_MPU_REGION_SIZE_64MB,\r
117         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
118         .exeNeverControl  = 0U,\r
119         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
120         .shareable        = 0U,\r
121         .cacheable        = (uint32_t)TRUE,\r
122         .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
123         .memAttr          = 0U,\r
124     },\r
125     {\r
126         //Region 8 configuration (Cahched or Non-cached for PHY tuning data based on macro): Covers last 256KB of EVM Flash (FSS DAT0) *\r
127         .regionId         = 8U,\r
128         .enable           = 1U,\r
129         .baseAddr         = 0x53FE0000,\r
130         .size             = CSL_ARM_R5_MPU_REGION_SIZE_128KB,\r
131         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
132         .exeNeverControl  = 0U,\r
133         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
134         .shareable        = 0U,\r
135         /* OSPI PHY tuning algorithm which runs in DAC mode needs\r
136          * cache to be disabled for this section of FSS data region.\r
137          */\r
138         .cacheable        = (uint32_t)FALSE,\r
139         .cachePolicy      = 0U,\r
140         .memAttr          = 0U,\r
141     },\r
142 };\r