[processor-sdk/pdk.git] / packages / ti / drv / spi / test / ospi_flash / src / main_ospi_flash_test.c
1 /**
2 * \file main_ospi_flash_test.c
3 *
4 * \brief Test application main file. This application will write and read
5 * the data to/from OSPI NOR flash through Board flash interface.
6 *
7 */
9 /*
10 * Copyright (C) 2017 - 2020 Texas Instruments Incorporated - http://www.ti.com/
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the
22 * distribution.
23 *
24 * Neither the name of Texas Instruments Incorporated nor the names of
25 * its contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 */
42 #ifdef USE_BIOS
43 /* XDCtools Header files */
44 #include <xdc/std.h>
45 #include <xdc/runtime/System.h>
46 #include <xdc/runtime/Error.h>
47 #include <stdio.h>
49 /* BIOS Header files */
50 #include <ti/sysbios/knl/Task.h>
51 #include <ti/sysbios/BIOS.h>
52 #include <ti/sysbios/utils/Load.h>
53 #if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X)
54 #if defined (__aarch64__)
55 #include <ti/sysbios/family/arm/v8a/Mmu.h>
56 #endif
57 #endif
58 #endif /* #ifdef USE_BIOS */
60 /* TI-RTOS Header files */
61 #include <ti/drv/spi/SPI.h>
62 #include <ti/drv/spi/src/SPI_osal.h>
63 #include <ti/drv/spi/soc/SPI_soc.h>
64 #include <ti/drv/spi/test/src/SPI_log.h>
66 #include <ti/board/board.h>
67 #include <ti/board/board_cfg.h>
68 #include <ti/board/src/flash/include/board_flash.h>
69 #include <ti/board/src/flash/nor/ospi/nor_spi_patterns.h>
70 #if defined(SOC_J7200) || defined(SOC_AM64X)
71 #include <ti/board/src/flash/nor/ospi/nor_xspi.h>
72 #else
73 #include <ti/board/src/flash/nor/ospi/nor_ospi.h>
74 #endif
76 #ifdef SPI_DMA_ENABLE
77 #include <ti/osal/CacheP.h>
78 #endif
80 #if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X)
81 #include <ti/csl/cslr_fss.h>
82 #include <ti/csl/csl_rat.h>
83 #include <ti/csl/arch/csl_arch.h>
84 #include <ti/drv/sciclient/sciclient.h>
85 #ifdef SPI_DMA_ENABLE
86 #include <ti/drv/udma/udma.h>
87 #endif
88 #if defined(SOC_AM64X) || defined(SOC_J7200)
89 #include <ti/board/src/flash/nor/device/s28hs512t.h>
90 #else
91 #include <ti/board/src/flash/nor/device/m35xu512.h>
92 #endif
94 #if defined(SOC_AM65XX)
95 #include <ti/csl/soc/am65xx/src/cslr_soc_baseaddress.h>
96 #include <ti/csl/soc/am65xx/src/cslr_mcu_ctrl_mmr.h>
97 #include <ti/csl/soc/am65xx/src/cslr_mcu_pll_mmr.h>
98 #include <ti/csl/soc/am65xx/src/cslr_wkup_ctrl_mmr.h>
99 #endif
101 #if defined(SOC_J721E)
102 #include <ti/csl/soc/j721e/src/cslr_soc_baseaddress.h>
103 #include <ti/csl/soc/j721e/src/cslr_mcu_ctrl_mmr.h>
104 #include <ti/csl/soc/j721e/src/cslr_mcu_pll_mmr.h>
105 #include <ti/csl/soc/j721e/src/cslr_wkup_ctrl_mmr.h>
106 #endif
108 #if defined(SOC_J7200)
109 #include <ti/csl/soc/j7200/src/cslr_soc_baseaddress.h>
110 #include <ti/csl/soc/j7200/src/cslr_mcu_ctrl_mmr.h>
111 #include <ti/csl/soc/j7200/src/cslr_mcu_pll_mmr.h>
112 #include <ti/csl/soc/j7200/src/cslr_wkup_ctrl_mmr.h>
113 #endif
115 #endif
118 /* Define the OSPI test interface */
119 typedef struct OSPI_Tests_s
120 {
121 bool (*testFunc)(void *);
122 int32_t testId;
123 bool dacMode;
124 bool dmaMode;
125 uint32_t clk;
126 char testDesc[80];
128 } OSPI_Tests;
130 /**********************************************************************
131 ************************** Macros ************************************
132 **********************************************************************/
133 #define OSPI_PROFILE /* Enable profiling */
134 #define OSPI_WRITE /* Enable write */
135 #define OSPI_WRITE_TUNING /* Enable write tuning data pattern to the falsh */
136 #undef OSPI_QSPI_FLASH /* Enable QSPI flash test using OSPI controller */
138 /* OSPI test ID definitions */
139 #define OSPI_TEST_ID_DAC_133M 0 /* OSPI flash test in Direct Acess Controller mode at 133MHz RCLK */
140 #define OSPI_TEST_ID_INDAC_133M 1 /* OSPI flash test in Indirect Acess Controller mode at 133MHz RCLK */
141 #define OSPI_TEST_ID_DAC_DMA_133M 2 /* OSPI flash test in Direct Acess Controller DMA mode at 133MHz RCLK */
142 #define OSPI_TEST_ID_DAC_166M 3 /* OSPI flash test in Direct Acess Controller mode at 166MHz RCLK */
143 #define OSPI_TEST_ID_INDAC_166M 4 /* OSPI flash test in Indirect Acess Controller mode at 166MHz RCLK */
144 #define OSPI_TEST_ID_DAC_DMA_166M 5 /* OSPI flash test in Direct Acess Controller DMA mode at 166MHz RCLK */
145 #define OSPI_TEST_ID_DAC_133M_SPI 6 /* OSPI flash test in Direct Acess Controller legacy SPI mode at 133MHz RCLK */
146 #define OSPI_TEST_ID_WR_TUNING 7 /* OSPI flash test in Direct Acess Controller legacy SPI mode to write tuning data */
148 /* OSPI NOR flash offset address for read/write test */
149 #define TEST_ADDR_OFFSET (0U)
151 /* Test read/write buffer length in bytes */
152 #define TEST_BUF_LEN (0x100000U)
154 /* Total read/write length in bytes */
155 #define TEST_DATA_LEN (TEST_BUF_LEN)
157 /* Read/write sengment length in bytes */
158 #define TEST_XFER_SEG_LEN (TEST_BUF_LEN)
160 /* Flash offset where the PHY tuning data pattern stored */
161 #define TEST_TUNE_PATTERN_OFFSET (NOR_TUNING_DATA_OFFSET)
163 /**********************************************************************
164 ************************** Internal functions ************************
165 **********************************************************************/
167 /* Function to generate known data */
168 static void GeneratePattern(uint8_t *txBuf, uint8_t *rxBuf, uint32_t length);
170 /* Data compare function */
171 bool VerifyData(uint8_t *expData,
172 uint8_t *rxData,
173 uint32_t length);
175 /**********************************************************************
176 ************************** Global Variables **************************
177 **********************************************************************/
178 #ifdef USE_BIOS
179 /* Test application stack */
180 #define APP_TSK_STACK_MAIN (16U * 1024U)
181 static uint8_t gAppTskStackMain[APP_TSK_STACK_MAIN] __attribute__((aligned(32)));;
182 #endif
184 /* Buffer containing the known data that needs to be written to flash */
185 #if defined(SOC_AM65XX) || defined(SOC_AM64X)
186 #ifdef SPI_DMA_ENABLE
187 uint8_t txBuf[TEST_BUF_LEN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT))) __attribute__((section(".benchmark_buffer")));
188 #else
189 uint8_t txBuf[TEST_BUF_LEN] __attribute__((aligned(128))) __attribute__((section(".benchmark_buffer")));
190 #endif
191 #endif
193 #if defined(SOC_J721E) || defined(SOC_J7200)
194 #ifdef SPI_DMA_ENABLE
195 uint8_t txBuf[TEST_BUF_LEN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT))) __attribute__((section(".benchmark_buffer")));
196 #else
197 uint8_t txBuf[TEST_BUF_LEN] __attribute__((aligned(128))) __attribute__((section(".benchmark_buffer")));
198 #endif
199 #endif
201 /* Buffer containing the received data */
202 #if defined(SOC_AM65XX) || defined(SOC_AM64X)
203 #ifdef SPI_DMA_ENABLE
204 uint8_t rxBuf[TEST_BUF_LEN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT))) __attribute__((section(".benchmark_buffer")));
205 #else
206 uint8_t rxBuf[TEST_BUF_LEN] __attribute__((aligned(128))) __attribute__((section(".benchmark_buffer")));
207 #endif
208 #endif
210 #if defined(SOC_J721E) || defined(SOC_J7200)
211 #ifdef SPI_DMA_ENABLE
212 uint8_t rxBuf[TEST_BUF_LEN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT))) __attribute__((section(".benchmark_buffer")));
213 #else
214 uint8_t rxBuf[TEST_BUF_LEN] __attribute__((aligned(128))) __attribute__((section(".benchmark_buffer")));
215 #endif
216 #endif
218 #if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X)
220 #ifdef SPI_DMA_ENABLE
221 /*
222 * Ring parameters
223 */
224 /** \brief Number of ring entries - we can prime this much memcpy operations */
225 #define UDMA_TEST_APP_RING_ENTRIES (1U)
226 /** \brief Size (in bytes) of each ring entry (Size of pointer - 64-bit) */
227 #define UDMA_TEST_APP_RING_ENTRY_SIZE (sizeof(uint64_t))
228 /** \brief Total ring memory */
229 #define UDMA_TEST_APP_RING_MEM_SIZE (UDMA_TEST_APP_RING_ENTRIES * \
230 UDMA_TEST_APP_RING_ENTRY_SIZE)
231 /** \brief This ensures every channel memory is aligned */
232 #define UDMA_TEST_APP_RING_MEM_SIZE_ALIGN ((UDMA_TEST_APP_RING_MEM_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
233 /**
234 * \brief UDMA TR packet descriptor memory.
235 * This contains the CSL_UdmapCppi5TRPD + Padding to sizeof(CSL_UdmapTR15) +
236 * one Type_15 TR (CSL_UdmapTR15) + one TR response of 4 bytes.
237 * Since CSL_UdmapCppi5TRPD is less than CSL_UdmapTR15, size is just two times
238 * CSL_UdmapTR15 for alignment.
239 */
240 #define UDMA_TEST_APP_TRPD_SIZE ((sizeof(CSL_UdmapTR15) * 2U) + 4U)
242 /** \brief This ensures every channel memory is aligned */
243 #define UDMA_TEST_APP_TRPD_SIZE_ALIGN ((UDMA_TEST_APP_TRPD_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
245 /*
246 * UDMA driver objects
247 */
248 struct Udma_DrvObj gUdmaDrvObj;
249 struct Udma_ChObj gUdmaChObj;
250 struct Udma_EventObj gUdmaCqEventObj;
252 Udma_DrvHandle gDrvHandle = NULL;
253 /*
254 * UDMA Memories
255 */
256 static uint8_t gTxRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
257 static uint8_t gTxCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
258 static uint8_t gTxTdCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
259 static uint8_t gUdmaTprdMem[UDMA_TEST_APP_TRPD_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
260 static OSPI_dmaInfo gUdmaInfo;
262 static void App_print(const char *str)
263 {
264 UART_printf("%s", str);
265 return;
266 }
268 int32_t Ospi_udma_init(OSPI_v0_HwAttrs *cfg)
269 {
270 int32_t retVal = UDMA_SOK;
271 Udma_InitPrms initPrms;
272 uint32_t instId;
274 if (gDrvHandle == NULL)
275 {
276 /* UDMA driver init */
277 #if defined (SOC_AM64X)
278 /* Use Block Copy DMA instance for AM64x */
279 instId = UDMA_INST_ID_BCDMA_0;
280 #else
281 /* Use MCU NAVSS for MCU domain cores. Rest cores all uses Main NAVSS */
282 #if defined (BUILD_MCU1_0) || defined (BUILD_MCU1_1)
283 instId = UDMA_INST_ID_MCU_0;
284 #else
285 instId = UDMA_INST_ID_MAIN_0;
286 #endif
287 #endif
289 UdmaInitPrms_init(instId, &initPrms);
290 initPrms.printFxn = &App_print;
291 retVal = Udma_init(&gUdmaDrvObj, &initPrms);
292 if(UDMA_SOK == retVal)
293 {
294 gDrvHandle = &gUdmaDrvObj;
295 }
296 }
298 if(gDrvHandle != NULL)
299 {
300 gUdmaInfo.drvHandle = (void *)gDrvHandle;
301 gUdmaInfo.chHandle = (void *)&gUdmaChObj;
302 gUdmaInfo.ringMem = (void *)&gTxRingMem[0];
303 gUdmaInfo.cqRingMem = (void *)&gTxCompRingMem[0];
304 gUdmaInfo.tdCqRingMem = (void *)&gTxTdCompRingMem[0];
305 gUdmaInfo.tprdMem = (void *)&gUdmaTprdMem[0];
306 gUdmaInfo.eventHandle = (void *)&gUdmaCqEventObj;
307 cfg->dmaInfo = &gUdmaInfo;
308 }
310 return (retVal);
311 }
313 int32_t Ospi_udma_deinit(void)
314 {
315 int32_t retVal = UDMA_SOK;
317 if (gDrvHandle != NULL)
318 {
319 retVal = Udma_deinit(gDrvHandle);
320 if(UDMA_SOK == retVal)
321 {
322 gDrvHandle = NULL;
323 }
324 }
326 return (retVal);
327 }
328 #endif
330 #ifdef USE_BIOS
332 #if defined(BUILD_MPU) || defined (__C7100__)
333 extern void Osal_initMmuDefault(void);
334 void InitMmu(void)
335 {
336 Osal_initMmuDefault();
337 }
338 #endif
340 #endif
341 #endif
343 #if defined(SOC_AM65XX)
344 /* define the unlock and lock values */
345 #define KICK0_UNLOCK_VAL 0x68EF3490
346 #define KICK1_UNLOCK_VAL 0xD172BC5A
347 #define KICK_LOCK_VAL 0x00000000
349 //
350 #define MAIN_MMR_BASE_ADDRESS CSL_CTRL_MMR0_CFG0_BASE
351 #define MCU_MMR_BASE_ADDRESS CSL_MCU_CTRL_MMR0_CFG0_BASE
352 #define WKUP_MMR_BASE_ADDRESS CSL_WKUP_CTRL_MMR0_CFG0_BASE
354 #define CSL2PTR (uint32_t *)(uintptr_t)
356 uint32_t MMR_unlock_one(uint32_t * kick0, uint32_t * kick1)
357 {
358 // initialize the status variable
359 uint32_t status = 1;
361 // if either of the kick lock registers are locked
362 if (!(*kick0 & 0x1) | !(*kick1 & 0x1))
363 {
364 // unlock the partition by writing the unlock values to the kick lock registers
365 *kick0 = KICK0_UNLOCK_VAL;
366 *kick1 = KICK1_UNLOCK_VAL;
367 }
369 // check to see if either of the kick registers are unlocked.
370 if (!(*kick0 & 0x1))
371 {
372 status = 0;
373 }
375 // return the status to the calling program
376 return status;
378 }
380 uint32_t MMR_lock_one(uint32_t * kick0, uint32_t * kick1)
381 {
382 // create status return variable
383 uint32_t status = 1;
385 // check to see if either of the kick registers are unlocked.
386 if ((*kick0 & 0x1))
387 {
388 // write the kick lock value to the kick lock registers to lock the partition
389 *kick0 = KICK_LOCK_VAL;
390 *kick1 = KICK_LOCK_VAL;
391 }
393 // check to see if either of the kick registers are still unlocked.
394 if ((*kick0 & 0x1))
395 {
396 status = 0;
397 }
398 // return success or failure
399 return status;
400 }
402 uint32_t MCU_CTRL_MMR_unlock_all()
403 {
405 // initialize the status variable
406 uint32_t status = 1;
408 // Unlock the 0th partition
409 status &= MMR_unlock_one(
410 CSL2PTR ( MCU_MMR_BASE_ADDRESS
411 + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK0),
412 CSL2PTR ( MCU_MMR_BASE_ADDRESS
413 + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK1));
415 // Unlock the 1st partition
416 status &= MMR_unlock_one(
417 CSL2PTR ( MCU_MMR_BASE_ADDRESS
418 + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK0),
419 CSL2PTR ( MCU_MMR_BASE_ADDRESS
420 + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK1));
422 // Unlock the 2nd partition
423 status &= MMR_unlock_one(
424 CSL2PTR ( MCU_MMR_BASE_ADDRESS
425 + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK0),
426 CSL2PTR ( MCU_MMR_BASE_ADDRESS
427 + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK1));
429 // Unlock the 3rd partition
430 status &= MMR_unlock_one(
431 CSL2PTR ( MCU_MMR_BASE_ADDRESS
432 + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK0),
433 CSL2PTR ( MCU_MMR_BASE_ADDRESS
434 + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK1));
436 // Unlock the 4th partition
437 status &= MMR_unlock_one(
438 CSL2PTR ( MCU_MMR_BASE_ADDRESS
439 + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK0),
440 CSL2PTR ( MCU_MMR_BASE_ADDRESS
441 + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK1));
442 return status;
443 }
445 uint32_t MCU_CTRL_MMR_lock_all()
446 {
448 // initialize the status variable
449 uint32_t status = 1;
451 // lock the 0th partition
452 status &= MMR_lock_one(
453 CSL2PTR (MCU_MMR_BASE_ADDRESS
454 + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK0),
455 CSL2PTR (MCU_MMR_BASE_ADDRESS
456 + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK1));
458 // lock the 1st partition
459 status &= MMR_lock_one(
460 CSL2PTR (MCU_MMR_BASE_ADDRESS
461 + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK0),
462 CSL2PTR (MCU_MMR_BASE_ADDRESS
463 + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK1));
464 // lock the 2nd partition
465 status &= MMR_lock_one(
466 CSL2PTR (MCU_MMR_BASE_ADDRESS
467 + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK0),
468 CSL2PTR (MCU_MMR_BASE_ADDRESS
469 + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK1));
470 // lock the 3rd partition
471 status &= MMR_lock_one(
472 CSL2PTR (MCU_MMR_BASE_ADDRESS
473 + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK0),
474 CSL2PTR (MCU_MMR_BASE_ADDRESS
475 + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK1));
476 // lock the 4th partition
477 status &= MMR_lock_one(
478 CSL2PTR (MCU_MMR_BASE_ADDRESS
479 + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK0),
480 CSL2PTR (MCU_MMR_BASE_ADDRESS
481 + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK1));
482 return status;
483 }
485 void OSPI_configClk(uint32_t freq, bool usePHY)
486 {
487 uint32_t divider = 0x12;
489 MCU_CTRL_MMR_unlock_all();
492 if(freq == OSPI_MODULE_CLK_166M)
493 {
494 /* Select CPSWHSDIV4 */
495 *(uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_MCU_OSPI0_CLKSEL) = 1;
497 if (usePHY)
498 divider = 0xC; /* 2000/12 = 166 */
499 else
500 divider = 0x6;
502 *(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CLKDIV) = \
503 (*(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CLKDIV) & 0x00FFFFFF) | ((divider-1) << 24);
505 /* Load new values on 0->1 transition of bit 31 of tenabldiv */
506 *(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CTRL) &= 0x7FFFFFFF;
507 Osal_delay(1);
508 *(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CTRL) |= 0x80000000;
509 }
510 else
511 {
512 /* Select MCUPLL0HSDIV4 */
513 *(uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_MCU_OSPI0_CLKSEL) = 0;
515 if(freq == OSPI_MODULE_CLK_133M)
516 divider = 18; /* 2400/18 = 133 */
517 if(freq == OSPI_MODULE_CLK_160M)
518 divider = 15; /* 2400/15 = 160 */
519 if(freq == OSPI_MODULE_CLK_200M)
520 divider = 12; /* 2400/12 = 200 */
522 *(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL0_HSDIV_CLKDIV) = \
523 (*(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL0_HSDIV_CLKDIV) & 0x00FFFFFF) | ((divider-1) << 24);
525 /* Load new values on 0->1 transition of bit 31 of tenabldiv */
526 *(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL0_HSDIV_CTRL) &= 0x7FFFFFFF;
527 Osal_delay(1);
528 *(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL0_HSDIV_CTRL) |= 0x80000000;
529 }
530 MCU_CTRL_MMR_lock_all();
532 SPI_log("\n OSPI RCLK running at %d MHz. \n", freq);
533 return;
535 }
536 #endif
538 #if defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X)
539 void OSPI_configClk(uint32_t freq, bool usePHY)
540 {
541 OSPI_v0_HwAttrs ospi_cfg;
542 int32_t retVal;
543 uint64_t ospi_rclk_freq;
544 uint32_t parClk;
545 #if defined (SOC_AM64X)
546 uint32_t clkID[] = {
547 TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK,
548 };
549 uint32_t devID[] = {
550 TISCI_DEV_FSS0_OSPI_0,
551 };
552 #else
553 uint32_t clkID[] = {
554 TISCI_DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK,
555 TISCI_DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK
556 };
557 uint32_t devID[] = {
558 TISCI_DEV_MCU_FSS0_OSPI_0,
559 TISCI_DEV_MCU_FSS0_OSPI_1
560 };
561 #endif
563 /* Get the default SPI init configurations */
564 OSPI_socGetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
566 retVal = Sciclient_pmModuleClkRequest(devID[BOARD_OSPI_NOR_INSTANCE],
567 clkID[BOARD_OSPI_NOR_INSTANCE],
568 TISCI_MSG_VALUE_CLOCK_SW_STATE_REQ,
569 TISCI_MSG_FLAG_AOP,
570 SCICLIENT_SERVICE_WAIT_FOREVER);
571 if (retVal != CSL_PASS)
572 {
573 SPI_log("\n Sciclient_pmModuleClkRequest failed");
574 goto clk_cfg_exit;
575 }
577 /* Max clocks */
578 if (freq == OSPI_MODULE_CLK_166M)
579 {
580 #if defined (SOC_AM64X)
581 parClk = TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK;
582 #else
583 parClk = TISCI_DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK;
584 #endif
586 retVal = Sciclient_pmSetModuleClkParent(devID[BOARD_OSPI_NOR_INSTANCE],
587 clkID[BOARD_OSPI_NOR_INSTANCE],
588 parClk,
589 SCICLIENT_SERVICE_WAIT_FOREVER);
590 }
591 else
592 {
593 #if defined (SOC_AM64X)
594 parClk = TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK;
595 #else
596 parClk = TISCI_DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK;
597 #endif
598 retVal = Sciclient_pmSetModuleClkParent(devID[BOARD_OSPI_NOR_INSTANCE],
599 clkID[BOARD_OSPI_NOR_INSTANCE],
600 parClk,
601 SCICLIENT_SERVICE_WAIT_FOREVER);
602 }
604 if (retVal != CSL_PASS)
605 {
606 SPI_log("\n Sciclient_pmSetModuleClkParent failed");
607 goto clk_cfg_exit;
608 }
610 ospi_cfg.funcClk = freq;
611 OSPI_socSetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
613 ospi_rclk_freq = (uint64_t)freq;
614 retVal = Sciclient_pmSetModuleClkFreq(devID[BOARD_OSPI_NOR_INSTANCE],
615 clkID[BOARD_OSPI_NOR_INSTANCE],
616 ospi_rclk_freq,
617 TISCI_MSG_FLAG_AOP,
618 SCICLIENT_SERVICE_WAIT_FOREVER);
620 if (retVal != CSL_PASS)
621 {
622 SPI_log("\n Sciclient_pmSetModuleClkFreq failed");
623 goto clk_cfg_exit;
624 }
626 ospi_rclk_freq = 0;
627 retVal = Sciclient_pmGetModuleClkFreq(devID[BOARD_OSPI_NOR_INSTANCE],
628 clkID[BOARD_OSPI_NOR_INSTANCE],
629 &ospi_rclk_freq,
630 SCICLIENT_SERVICE_WAIT_FOREVER);
631 if (retVal != CSL_PASS)
632 {
633 SPI_log("\n Sciclient_pmGetModuleClkFreq failed");
634 goto clk_cfg_exit;
635 }
637 SPI_log("\n OSPI RCLK running at %d MHz. \n", (uint32_t)ospi_rclk_freq);
639 clk_cfg_exit:
640 return;
641 }
642 #endif
644 void OSPI_initConfig(OSPI_Tests *test)
645 {
646 OSPI_v0_HwAttrs ospi_cfg;
648 #if defined (BUILD_MCU)
649 /* Change interrupt number based on core */
650 OSPI_socInit();
651 #endif
653 /* Get the default OSPI init configurations */
654 OSPI_socGetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
656 #ifdef OSPI_QSPI_FLASH
657 ospi_cfg.xferLines = OSPI_XFER_LINES_QUAD;
658 #endif
660 /* Modify the default OSPI configurations */
661 ospi_cfg.dacEnable = test->dacMode;
662 if (test->dacMode)
663 {
664 ospi_cfg.dmaEnable = test->dmaMode;
665 /* Enable PHY in DAC mode */
666 ospi_cfg.phyEnable = true;
667 ospi_cfg.intrEnable = false;
668 #ifdef SPI_DMA_ENABLE
669 if (ospi_cfg.dmaEnable)
670 {
671 Ospi_udma_init(&ospi_cfg);
672 }
673 #endif
674 }
675 else
676 {
677 /* Enable interrupt in INDAC mode */
678 ospi_cfg.intrEnable = true;
679 /* Disable PHY in INDAC mode */
680 ospi_cfg.phyEnable = false;
681 ospi_cfg.dmaEnable = false;
682 }
684 if (test->testId == OSPI_TEST_ID_DAC_133M_SPI)
685 {
686 /* Disable PHY in legacy SPI mode (1-1-1) */
687 ospi_cfg.phyEnable = false;
688 ospi_cfg.dtrEnable = false;
689 ospi_cfg.xferLines = OSPI_XFER_LINES_SINGLE;
690 }
691 else
692 {
693 ospi_cfg.dtrEnable = true;
694 ospi_cfg.xferLines = OSPI_XFER_LINES_OCTAL;
695 }
697 if (test->testId == OSPI_TEST_ID_WR_TUNING)
698 {
699 ospi_cfg.phyEnable = false;
700 }
702 ospi_cfg.funcClk = test->clk;
704 if (ospi_cfg.funcClk == OSPI_MODULE_CLK_133M)
705 {
706 ospi_cfg.devDelays[3] = OSPI_DEV_DELAY_CSDA;
707 }
708 else
709 {
710 ospi_cfg.devDelays[3] = OSPI_DEV_DELAY_CSDA_3;
711 }
713 if(ospi_cfg.intrEnable)
714 {
715 /* Set interrupt path */
716 if(OSPI_configSocIntrPath(&ospi_cfg, TRUE) != CSL_PASS)
717 {
718 SPI_log("\n Set interrupt path failed!\n");
719 }
720 else
721 {
722 SPI_log("\n The interrupt path has been set with interrupt number %d", ospi_cfg.intrNum);
723 }
724 }
726 /* Set the default OSPI init configurations */
727 OSPI_socSetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
728 }
730 void OSPI_deInitConfig(OSPI_Tests *test)
731 {
732 OSPI_v0_HwAttrs ospi_cfg;
734 /* Get the default OSPI init configurations */
735 OSPI_socGetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
737 /* Release interrupt path */
738 OSPI_configSocIntrPath(&ospi_cfg, FALSE);
739 }
741 /*
742 * ======== OSPI unit test function ========
743 */
744 static bool OSPI_flash_test(void *arg)
745 {
746 Board_flashHandle boardHandle;
747 Board_FlashInfo *flashInfo;
748 #ifdef OSPI_WRITE
749 uint32_t blockNum; /* flash block number */
750 uint32_t pageNum; /* flash page number */
751 #endif
752 bool testPassed = true; /* return value */
753 uint32_t writeMode = OSPI_FLASH_OCTAL_PAGE_PROG;
754 uint32_t readMode = OSPI_FLASH_OCTAL_READ;
755 uint32_t deviceId; /* flash device ID */
756 OSPI_Tests *test = (OSPI_Tests *)arg;
757 uint32_t i;
758 uint32_t offset;
759 uint32_t xferLen;
760 uint32_t testLen = TEST_DATA_LEN;
761 uint32_t testSegLen = TEST_XFER_SEG_LEN;
762 #ifdef OSPI_PROFILE
763 uint64_t startTime; /* start time stamp in usec */
764 uint64_t elapsedTime; /* elapsed time in usec */
765 float xferRate;
766 uint32_t xferRateInt;
767 #ifdef USE_BIOS
768 uint32_t cpuLoad;
769 #endif
770 #endif
771 uint32_t startOffset;
772 uint8_t *pBuf;
773 uint32_t tuneEnable;
775 if (test->testId == OSPI_TEST_ID_WR_TUNING)
776 {
777 testLen = NOR_ATTACK_VECTOR_SIZE;
778 startOffset = TEST_TUNE_PATTERN_OFFSET;
779 }
780 else
781 {
782 testLen = TEST_DATA_LEN;
783 startOffset = TEST_ADDR_OFFSET;
784 }
786 if(test->dacMode)
787 {
788 tuneEnable = TRUE;
789 }
790 else
791 {
792 tuneEnable = FALSE;
793 }
795 OSPI_initConfig(test);
797 /* Default Device, SoC's specifics overrides shall follow */
798 deviceId = BOARD_FLASH_ID_MT35XU512ABA1G12;
800 #if defined(SOC_J7200) || defined(SOC_AM64X)
801 deviceId = BOARD_FLASH_ID_S28HS512T;
802 #endif
804 #ifdef OSPI_PROFILE
805 /* Get start time stamp for the Board_flashOpen measurement */
806 startTime = TimerP_getTimeInUsecs();
807 #endif
808 /* Open the Board OSPI NOR device with OSPI port 0
809 and use default OSPI configurations */
810 boardHandle = Board_flashOpen(deviceId,
811 BOARD_OSPI_NOR_INSTANCE, (void *)(&tuneEnable));
813 #ifdef OSPI_PROFILE
814 /* Get elapsed time for the Board_flashOpen measurement */
815 elapsedTime = TimerP_getTimeInUsecs() - startTime;
816 SPI_log("\n Board_flashOpen elpased time %d us \n", (uint32_t)elapsedTime);
817 #endif
818 if (!boardHandle)
819 {
820 SPI_log("\n Board_flashOpen failed. \n");
821 testPassed = false;
822 goto err;
823 }
824 else
825 {
826 flashInfo = (Board_FlashInfo *)boardHandle;
827 SPI_log("\n OSPI NOR device ID: 0x%x, manufacturer ID: 0x%x \n",
828 flashInfo->device_id, flashInfo->manufacturer_id);
829 }
831 /* Generate the data */
832 GeneratePattern(txBuf, rxBuf, testLen);
833 if (test->testId == OSPI_TEST_ID_WR_TUNING)
834 {
835 pBuf = nor_attack_vector;
836 }
837 else
838 {
839 pBuf = txBuf;
840 }
841 #ifdef SPI_DMA_ENABLE
842 if (test->dmaMode)
843 {
844 CacheP_wbInv((void *)pBuf, (int32_t)testLen);
845 CacheP_wbInv((void *)rxBuf, (int32_t)testLen);
846 }
847 #endif
849 #ifdef OSPI_WRITE
850 #if defined(SOC_J7200) || defined(SOC_AM64X)
851 if (test->dacMode) /* DAC writes are not supported on Cypress xSPI Flash - Switch to INDAC mode for write as WA to PDK-7115 */
852 {
853 SPI_log("\n The Cypress xSPI Flash does not support DAC writes, switching to INDAC mode. \n");
854 OSPI_v0_HwAttrs ospi_cfg;
855 Board_flashClose(boardHandle);
856 #if SPI_DMA_ENABLE
857 if (test->dmaMode)
858 {
859 Ospi_udma_deinit();
860 }
861 #endif
862 OSPI_socGetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
863 ospi_cfg.dacEnable = false;
864 ospi_cfg.phyEnable = false;
865 ospi_cfg.dmaEnable = false;
866 ospi_cfg.intrEnable = true;
867 OSPI_socSetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
868 boardHandle = Board_flashOpen(deviceId, BOARD_OSPI_NOR_INSTANCE, (void *)(&tuneEnable));
869 }
870 #endif
871 for (i = 0; i < testLen; i += NOR_BLOCK_SIZE)
872 {
873 offset = startOffset + i;
874 if (Board_flashOffsetToBlkPage(boardHandle, offset,
875 &blockNum, &pageNum))
876 {
877 SPI_log("\n Board_flashOffsetToBlkPage failed. \n");
878 testPassed = false;
879 goto err;
880 }
882 /* Erase block, to which data has to be written */
883 if (Board_flashEraseBlk(boardHandle, blockNum))
884 {
885 SPI_log("\n Board_flashEraseBlk failed. \n");
886 testPassed = false;
887 goto err;
888 }
889 }
890 #ifdef OSPI_PROFILE
891 #ifdef USE_BIOS
892 Load_reset( );
893 #endif
894 /* Get start time stamp for the write performance measurement */
895 startTime = TimerP_getTimeInUsecs();
896 #endif
897 for (i = 0; i < testLen; i += testSegLen)
898 {
899 offset = startOffset + i;
900 if ((testLen - i) < testSegLen)
901 {
902 xferLen = testLen - i;
903 }
904 else
905 {
906 xferLen = testSegLen;
907 }
908 /* Write buffer to flash */
909 if (Board_flashWrite(boardHandle, offset, &pBuf[i],
910 xferLen, (void *)(&writeMode)))
911 {
912 SPI_log("\n Board_flashWrite failed. \n");
913 testPassed = false;
914 goto err;
915 }
916 }
918 #ifdef OSPI_PROFILE
919 elapsedTime = TimerP_getTimeInUsecs() - startTime;
920 #ifdef USE_BIOS
921 Load_update( );
922 cpuLoad = Load_getCPULoad();
923 #endif
924 /* calculate the write transfer rate in Kbps */
925 xferRate = (float) (((float) (testLen * 8)) / elapsedTime) * 1000U;
926 xferRateInt = (uint32_t)xferRate;
927 SPI_log("\n Board_flashWrite %d bytes at transfer rate %d Kbps \n", testLen, xferRateInt);
928 #ifdef USE_BIOS
929 SPI_log("\n Board_flashWrite CPU load %d%% \n", cpuLoad);
930 #endif
931 #endif
932 #endif /* OSPI_WRITE */
934 #if defined(SOC_J7200) || defined(SOC_AM64X)
935 if (test->dacMode) /* DAC reads are supported - switching back to DAC mode */
936 {
937 SPI_log("\n The Cypress xSPI Flash supports DAC reads, switching back to DAC mode. \n");
938 OSPI_v0_HwAttrs ospi_cfg;
939 Board_flashClose(boardHandle);
940 OSPI_socGetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
941 if (test->testId == OSPI_TEST_ID_DAC_133M_SPI)
942 {
943 /* Disable PHY in legacy SPI mode (1-1-1) */
944 ospi_cfg.phyEnable = false;
945 ospi_cfg.dtrEnable = false;
946 ospi_cfg.xferLines = OSPI_XFER_LINES_SINGLE;
947 }
948 else
949 {
950 /* Enable PHY in octal SPI mode (8-8-8) */
951 ospi_cfg.phyEnable = true;
952 ospi_cfg.dtrEnable = true;
953 ospi_cfg.xferLines = OSPI_XFER_LINES_OCTAL;
954 }
956 ospi_cfg.dacEnable = true;
957 ospi_cfg.dmaEnable = test->dmaMode;
958 ospi_cfg.intrEnable = false;
959 #ifdef SPI_DMA_ENABLE
960 if (ospi_cfg.dmaEnable)
961 {
962 Ospi_udma_init(&ospi_cfg);
963 }
964 #endif
965 OSPI_socSetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
966 boardHandle = Board_flashOpen(deviceId, BOARD_OSPI_NOR_INSTANCE, (void *)(&tuneEnable));
967 }
968 #endif
969 #ifdef OSPI_PROFILE
970 #ifdef USE_BIOS
971 Load_reset( );
972 #endif
973 /* Get start time stamp for the read performance measurement */
974 startTime = TimerP_getTimeInUsecs();
975 #endif
976 for (i = 0; i < testLen; i += testSegLen)
977 {
978 offset = startOffset + i;
979 if ((testLen - i) < testSegLen)
980 {
981 xferLen = testLen - i;
982 }
983 else
984 {
985 xferLen = testSegLen;
986 }
987 if (Board_flashRead(boardHandle, offset, &rxBuf[i],
988 xferLen, (void *)(&readMode)))
989 {
990 SPI_log("\n Board_flashRead failed. \n");
991 testPassed = false;
992 goto err;
993 }
994 }
996 #ifdef OSPI_PROFILE
997 elapsedTime = TimerP_getTimeInUsecs() - startTime;
998 #ifdef USE_BIOS
999 Load_update( );
1000 cpuLoad = Load_getCPULoad();
1001 #endif
1002 /* calculate the write transfer rate in Kbps */
1003 xferRate = (float) (((float) (testLen * 8)) / elapsedTime);
1004 xferRateInt = (uint32_t)xferRate;
1005 SPI_log("\n Board_flashRead %d bytes at transfer rate %d Mbps \n", testLen, xferRateInt);
1006 #ifdef USE_BIOS
1007 SPI_log("\n Board_flashRead CPU load %d%% \n", cpuLoad);
1008 #endif
1009 #endif
1011 #ifdef OSPI_WRITE
1012 /* Verify Data */
1013 if (VerifyData(pBuf, rxBuf, testLen) == false)
1014 {
1015 SPI_log("\n Data mismatch. \n");
1016 testPassed = false;
1017 goto err;
1018 }
1019 #endif
1021 err:
1022 OSPI_deInitConfig(test);
1024 if (boardHandle != 0U)
1025 {
1026 Board_flashClose(boardHandle);
1027 }
1029 #if SPI_DMA_ENABLE
1030 if (test->dmaMode)
1031 {
1032 Ospi_udma_deinit();
1033 }
1034 #endif
1036 return (testPassed);
1037 }
1039 void OSPI_test_print_test_desc(OSPI_Tests *test)
1040 {
1041 char testId[16] = {0, };
1043 /* Print unit test ID */
1044 sprintf(testId, "%d", test->testId);
1045 SPI_log("\r\n OSPI UT %s\r\n", testId);
1047 /* Print test description */
1048 SPI_log("\r\n %s\r\n", test->testDesc);
1049 }
1051 OSPI_Tests Ospi_tests[] =
1052 {
1053 #ifdef OSPI_WRITE_TUNING
1054 #if defined(SOC_J7200) || defined(SOC_AM64X)
1055 /* testFunc testID dacMode dmaMode clk testDesc */
1056 {OSPI_flash_test, OSPI_TEST_ID_WR_TUNING, false, false, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave to write tuning data to flash"},
1057 #else
1058 {OSPI_flash_test, OSPI_TEST_ID_WR_TUNING, true, false, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave to write tuning data to flash"},
1059 #endif
1060 #endif
1061 {OSPI_flash_test, OSPI_TEST_ID_DAC_133M, true, false, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in DAC mode at 133MHz RCLK"},
1062 {OSPI_flash_test, OSPI_TEST_ID_INDAC_133M, false, false, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in INDAC mode at 133MHz RCLK"},
1063 #ifdef SPI_DMA_ENABLE
1064 {OSPI_flash_test, OSPI_TEST_ID_DAC_DMA_133M, true, true, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in DAC DMA mode at 133MHz RCLK"},
1065 #endif
1066 {OSPI_flash_test, OSPI_TEST_ID_DAC_166M, true, false, OSPI_MODULE_CLK_166M, "\r\n OSPI flash test slave in DAC mode at 166MHz RCLK"},
1067 {OSPI_flash_test, OSPI_TEST_ID_INDAC_166M, false, false, OSPI_MODULE_CLK_166M, "\r\n OSPI flash test slave in INDAC mode at 166MHz RCLK"},
1068 #ifdef SPI_DMA_ENABLE
1069 {OSPI_flash_test, OSPI_TEST_ID_DAC_DMA_166M, true, true, OSPI_MODULE_CLK_166M, "\r\n OSPI flash test slave in DAC DMA mode at 166MHz RCLK"},
1070 #endif
1071 {OSPI_flash_test, OSPI_TEST_ID_DAC_133M_SPI, true, false, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in DAC Legacy SPI mode at 133MHz RCLK"},
1072 {NULL, }
1073 };
1075 /*
1076 * ======== test function ========
1077 */
1078 #ifdef USE_BIOS
1079 void spi_test(UArg arg0, UArg arg1)
1080 #else
1081 void spi_test()
1082 #endif
1083 {
1084 uint32_t i;
1085 bool testFail = false;
1086 OSPI_Tests *test;
1088 /* Init SPI driver */
1089 SPI_init();
1091 for (i = 0; ; i++)
1092 {
1093 test = &Ospi_tests[i];
1094 if (test->testFunc == NULL)
1095 {
1096 break;
1097 }
1099 OSPI_configClk(test->clk, true);
1101 OSPI_test_print_test_desc(test);
1103 if (test->testFunc((void *)test) == true)
1104 {
1105 SPI_log("\r\n %s have passed\r\n", test->testDesc);
1106 }
1107 else
1108 {
1109 SPI_log("\r\n %s have failed\r\n", test->testDesc);
1110 testFail = true;
1111 break;
1112 }
1113 }
1115 if(testFail == true)
1116 {
1117 SPI_log("\n Some tests have failed. \n");
1118 }
1119 else
1120 {
1121 SPI_log("\n All tests have passed. \n");
1122 }
1124 SPI_log("Done\n");
1126 while (true)
1127 {
1128 }
1129 }
1131 /*
1132 * ======== main ========
1133 */
1134 int main(void)
1135 {
1136 /* Call board init functions */
1137 Board_initCfg boardCfg;
1138 #ifdef USE_BIOS
1139 Task_Handle task;
1140 Error_Block eb;
1141 Task_Params taskParams;
1142 #endif
1143 boardCfg = BOARD_INIT_PINMUX_CONFIG |
1144 BOARD_INIT_MODULE_CLOCK |
1145 BOARD_INIT_UART_STDIO;
1146 #if defined (SOC_J7200)
1147 /* Need to do PLL config through board init for proper clock input on J7200 */
1148 boardCfg |= BOARD_INIT_PLL;
1149 #endif
1151 Board_init(boardCfg);
1153 #ifdef USE_BIOS
1155 Error_init(&eb);
1156 /* Initialize the task params */
1157 Task_Params_init(&taskParams);
1158 /* Set the task priority higher than the default priority (1) */
1159 taskParams.priority = 2;
1160 taskParams.stack = gAppTskStackMain;
1161 taskParams.stackSize = sizeof (gAppTskStackMain);
1163 /* Start BIOS */
1164 task = Task_create(spi_test, &taskParams, &eb);
1165 if (task == NULL) {
1166 System_printf("Task_create() failed!\n");
1167 BIOS_exit(0);
1168 }
1169 BIOS_start();
1170 #else
1171 spi_test();
1172 #endif
1173 return (0);
1174 }
1176 /*
1177 * ======== CompareData ========
1178 */
1179 bool VerifyData(uint8_t *expData,
1180 uint8_t *rxData,
1181 uint32_t length)
1182 {
1183 uint32_t idx = 0;
1184 uint32_t match = 1;
1185 bool retVal = false;
1187 for(idx = 0; ((idx < length) && (match != 0)); idx++)
1188 {
1189 if(*expData != *rxData)
1190 {
1191 match = 0;
1192 SPI_log("Data mismatch at idx %d\n", idx);
1193 }
1194 expData++;
1195 rxData++;
1196 }
1198 if(match == 1)
1199 {
1200 retVal = true;
1201 }
1203 return retVal;
1204 }
1206 /*
1207 * ======== GeneratePattern ========
1208 */
1209 static void GeneratePattern(uint8_t *txBuf, uint8_t *rxBuf, uint32_t length)
1210 {
1211 volatile uint32_t idx;
1212 volatile uint8_t *txPtr = txBuf;
1213 volatile uint8_t *rxPtr = rxBuf;
1215 for(idx = 0; idx < length; idx++)
1216 {
1217 if (idx < (length/2))
1218 {
1219 *txPtr++ = (uint8_t)idx;
1220 }
1221 else if (idx < (length/4*3))
1222 {
1223 *txPtr++ = 0xaa;
1224 }
1225 else
1226 {
1227 *txPtr++ = 0x55;
1228 }
1229 *rxPtr++ = (uint8_t)0U;
1230 }
1231 }