[processor-sdk/pdk.git] / packages / ti / drv / spi / test / ospi_flash / src / main_ospi_flash_test.c
1 /**
2 * \file main_ospi_flash_test.c
3 *
4 * \brief Test application main file. This application will write and read
5 * the data to/from OSPI NOR flash through Board flash interface.
6 *
7 */
9 /*
10 * Copyright (C) 2017 - 2020 Texas Instruments Incorporated - http://www.ti.com/
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the
22 * distribution.
23 *
24 * Neither the name of Texas Instruments Incorporated nor the names of
25 * its contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 */
42 #ifdef USE_BIOS
43 /* XDCtools Header files */
44 #include <xdc/std.h>
45 #include <xdc/runtime/System.h>
46 #include <xdc/runtime/Error.h>
47 #include <stdio.h>
49 /* BIOS Header files */
50 #include <ti/sysbios/knl/Task.h>
51 #include <ti/sysbios/BIOS.h>
52 #include <ti/sysbios/utils/Load.h>
53 #if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X)
54 #if defined (__aarch64__)
55 #include <ti/sysbios/family/arm/v8a/Mmu.h>
56 #endif
57 #endif
58 #endif /* #ifdef USE_BIOS */
60 /* TI-RTOS Header files */
61 #include <ti/drv/spi/SPI.h>
62 #include <ti/drv/spi/src/SPI_osal.h>
63 #include <ti/drv/spi/soc/SPI_soc.h>
64 #include <ti/drv/spi/test/src/SPI_log.h>
66 #include <ti/board/board.h>
67 #include <ti/board/board_cfg.h>
68 #include <ti/board/src/flash/include/board_flash.h>
69 #include <ti/board/src/flash/nor/ospi/nor_spi_patterns.h>
70 #if defined(SOC_J7200) || defined(SOC_AM64X)
71 #include <ti/board/src/flash/nor/ospi/nor_xspi.h>
72 #else
73 #include <ti/board/src/flash/nor/ospi/nor_ospi.h>
74 #endif
76 #ifdef SPI_DMA_ENABLE
77 #include <ti/osal/CacheP.h>
78 #endif
80 #if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X)
81 #include <ti/csl/cslr_fss.h>
82 #include <ti/csl/csl_rat.h>
83 #include <ti/csl/arch/csl_arch.h>
84 #include <ti/drv/sciclient/sciclient.h>
85 #ifdef SPI_DMA_ENABLE
86 #include <ti/drv/udma/udma.h>
87 #endif
88 #if defined(SOC_AM64X) || defined(SOC_J7200)
89 #include <ti/board/src/flash/nor/device/s28hs512t.h>
90 #else
91 #include <ti/board/src/flash/nor/device/m35xu512.h>
92 #endif
94 #if defined(SOC_AM65XX)
95 #include <ti/csl/soc/am65xx/src/cslr_soc_baseaddress.h>
96 #include <ti/csl/soc/am65xx/src/cslr_mcu_ctrl_mmr.h>
97 #include <ti/csl/soc/am65xx/src/cslr_mcu_pll_mmr.h>
98 #include <ti/csl/soc/am65xx/src/cslr_wkup_ctrl_mmr.h>
99 #endif
101 #if defined(SOC_J721E)
102 #include <ti/csl/soc/j721e/src/cslr_soc_baseaddress.h>
103 #include <ti/csl/soc/j721e/src/cslr_mcu_ctrl_mmr.h>
104 #include <ti/csl/soc/j721e/src/cslr_mcu_pll_mmr.h>
105 #include <ti/csl/soc/j721e/src/cslr_wkup_ctrl_mmr.h>
106 #endif
108 #if defined(SOC_J7200)
109 #include <ti/csl/soc/j7200/src/cslr_soc_baseaddress.h>
110 #include <ti/csl/soc/j7200/src/cslr_mcu_ctrl_mmr.h>
111 #include <ti/csl/soc/j7200/src/cslr_mcu_pll_mmr.h>
112 #include <ti/csl/soc/j7200/src/cslr_wkup_ctrl_mmr.h>
113 #endif
115 #endif
118 /* Define the OSPI test interface */
119 typedef struct OSPI_Tests_s
120 {
121 bool (*testFunc)(void *);
122 int32_t testId;
123 bool dacMode;
124 bool dmaMode;
125 uint32_t clk;
126 char testDesc[80];
128 } OSPI_Tests;
130 /**********************************************************************
131 ************************** Macros ************************************
132 **********************************************************************/
133 #define OSPI_PROFILE /* Enable profiling */
134 #define OSPI_WRITE /* Enable write */
135 #define OSPI_WRITE_TUNING /* Enable write tuning data pattern to the falsh */
136 #undef OSPI_QSPI_FLASH /* Enable QSPI flash test using OSPI controller */
138 /* OSPI test ID definitions */
139 #define OSPI_TEST_ID_DAC_133M 0 /* OSPI flash test in Direct Acess Controller mode at 133MHz RCLK */
140 #define OSPI_TEST_ID_INDAC_133M 1 /* OSPI flash test in Indirect Acess Controller mode at 133MHz RCLK */
141 #define OSPI_TEST_ID_DAC_DMA_133M 2 /* OSPI flash test in Direct Acess Controller DMA mode at 133MHz RCLK */
142 #define OSPI_TEST_ID_DAC_166M 3 /* OSPI flash test in Direct Acess Controller mode at 166MHz RCLK */
143 #define OSPI_TEST_ID_INDAC_166M 4 /* OSPI flash test in Indirect Acess Controller mode at 166MHz RCLK */
144 #define OSPI_TEST_ID_DAC_DMA_166M 5 /* OSPI flash test in Direct Acess Controller DMA mode at 166MHz RCLK */
145 #define OSPI_TEST_ID_DAC_133M_SPI 6 /* OSPI flash test in Direct Acess Controller legacy SPI mode at 133MHz RCLK */
146 #define OSPI_TEST_ID_WR_TUNING 7 /* OSPI flash test in Direct Acess Controller legacy SPI mode to write tuning data */
148 /* OSPI NOR flash offset address for read/write test */
149 #define TEST_ADDR_OFFSET (0U)
151 /* Test read/write buffer length in bytes */
152 #define TEST_BUF_LEN (0x100000U)
154 /* Total read/write length in bytes */
155 #define TEST_DATA_LEN (TEST_BUF_LEN)
157 /* Read/write sengment length in bytes */
158 #define TEST_XFER_SEG_LEN (TEST_BUF_LEN)
160 /* Flash offset where the PHY tuning data pattern stored */
161 #define TEST_TUNE_PATTERN_OFFSET (NOR_TUNING_DATA_OFFSET)
163 /**********************************************************************
164 ************************** Internal functions ************************
165 **********************************************************************/
167 /* Function to generate known data */
168 static void GeneratePattern(uint8_t *txBuf, uint8_t *rxBuf, uint32_t length);
170 /* Data compare function */
171 bool VerifyData(uint8_t *expData,
172 uint8_t *rxData,
173 uint32_t length);
175 /**********************************************************************
176 ************************** Global Variables **************************
177 **********************************************************************/
178 #ifdef USE_BIOS
179 /* Test application stack */
180 #define APP_TSK_STACK_MAIN (16U * 1024U)
181 static uint8_t gAppTskStackMain[APP_TSK_STACK_MAIN] __attribute__((aligned(32)));;
182 #endif
184 /* Buffer containing the known data that needs to be written to flash */
185 #if defined(SOC_AM65XX) || defined(SOC_AM64X)
186 #ifdef SPI_DMA_ENABLE
187 uint8_t txBuf[TEST_BUF_LEN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT))) __attribute__((section(".benchmark_buffer")));
188 #else
189 uint8_t txBuf[TEST_BUF_LEN] __attribute__((aligned(128))) __attribute__((section(".benchmark_buffer")));
190 #endif
191 #endif
193 #if defined(SOC_J721E) || defined(SOC_J7200)
194 #ifdef SPI_DMA_ENABLE
195 uint8_t txBuf[TEST_BUF_LEN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
196 #else
197 uint8_t txBuf[TEST_BUF_LEN] __attribute__((aligned(128)));
198 #endif
199 #endif
201 /* Buffer containing the received data */
202 #if defined(SOC_AM65XX) || defined(SOC_AM64X)
203 #ifdef SPI_DMA_ENABLE
204 uint8_t rxBuf[TEST_BUF_LEN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT))) __attribute__((section(".benchmark_buffer")));
205 #else
206 uint8_t rxBuf[TEST_BUF_LEN] __attribute__((aligned(128))) __attribute__((section(".benchmark_buffer")));
207 #endif
208 #endif
210 #if defined(SOC_J721E) || defined(SOC_J7200)
211 #ifdef SPI_DMA_ENABLE
212 uint8_t rxBuf[TEST_BUF_LEN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
213 #else
214 uint8_t rxBuf[TEST_BUF_LEN] __attribute__((aligned(128)));
215 #endif
216 #endif
218 #if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X)
220 #ifdef SPI_DMA_ENABLE
221 /*
222 * Ring parameters
223 */
224 /** \brief Number of ring entries - we can prime this much memcpy operations */
225 #define UDMA_TEST_APP_RING_ENTRIES (1U)
226 /** \brief Size (in bytes) of each ring entry (Size of pointer - 64-bit) */
227 #define UDMA_TEST_APP_RING_ENTRY_SIZE (sizeof(uint64_t))
228 /** \brief Total ring memory */
229 #define UDMA_TEST_APP_RING_MEM_SIZE (UDMA_TEST_APP_RING_ENTRIES * \
230 UDMA_TEST_APP_RING_ENTRY_SIZE)
231 /** \brief This ensures every channel memory is aligned */
232 #define UDMA_TEST_APP_RING_MEM_SIZE_ALIGN ((UDMA_TEST_APP_RING_MEM_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
233 /**
234 * \brief UDMA TR packet descriptor memory.
235 * This contains the CSL_UdmapCppi5TRPD + Padding to sizeof(CSL_UdmapTR15) +
236 * one Type_15 TR (CSL_UdmapTR15) + one TR response of 4 bytes.
237 * Since CSL_UdmapCppi5TRPD is less than CSL_UdmapTR15, size is just two times
238 * CSL_UdmapTR15 for alignment.
239 */
240 #define UDMA_TEST_APP_TRPD_SIZE ((sizeof(CSL_UdmapTR15) * 2U) + 4U)
242 /** \brief This ensures every channel memory is aligned */
243 #define UDMA_TEST_APP_TRPD_SIZE_ALIGN ((UDMA_TEST_APP_TRPD_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
245 /*
246 * UDMA driver objects
247 */
248 struct Udma_DrvObj gUdmaDrvObj;
249 struct Udma_ChObj gUdmaChObj;
250 struct Udma_EventObj gUdmaCqEventObj;
252 Udma_DrvHandle gDrvHandle = NULL;
253 /*
254 * UDMA Memories
255 */
256 static uint8_t gTxRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
257 static uint8_t gTxCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
258 static uint8_t gTxTdCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
259 static uint8_t gUdmaTprdMem[UDMA_TEST_APP_TRPD_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
260 static OSPI_dmaInfo gUdmaInfo;
262 int32_t Ospi_udma_init(OSPI_v0_HwAttrs *cfg)
263 {
264 int32_t retVal = UDMA_SOK;
265 Udma_InitPrms initPrms;
266 uint32_t instId;
268 if (gDrvHandle == NULL)
269 {
270 /* UDMA driver init */
271 #if defined (SOC_AM64X)
272 /* Use Block Copy DMA instance for AM64x */
273 instId = UDMA_INST_ID_BCDMA_0;
274 #else
275 /* Use MCU NAVSS for MCU domain cores. Rest cores all uses Main NAVSS */
276 #if defined (BUILD_MCU1_0) || defined (BUILD_MCU1_1)
277 instId = UDMA_INST_ID_MCU_0;
278 #else
279 instId = UDMA_INST_ID_MAIN_0;
280 #endif
281 #endif
283 UdmaInitPrms_init(instId, &initPrms);
284 retVal = Udma_init(&gUdmaDrvObj, &initPrms);
285 if(UDMA_SOK == retVal)
286 {
287 gDrvHandle = &gUdmaDrvObj;
288 }
289 }
291 if(gDrvHandle != NULL)
292 {
293 gUdmaInfo.drvHandle = (void *)gDrvHandle;
294 gUdmaInfo.chHandle = (void *)&gUdmaChObj;
295 gUdmaInfo.ringMem = (void *)&gTxRingMem[0];
296 gUdmaInfo.cqRingMem = (void *)&gTxCompRingMem[0];
297 gUdmaInfo.tdCqRingMem = (void *)&gTxTdCompRingMem[0];
298 gUdmaInfo.tprdMem = (void *)&gUdmaTprdMem[0];
299 gUdmaInfo.eventHandle = (void *)&gUdmaCqEventObj;
300 cfg->dmaInfo = &gUdmaInfo;
301 }
303 return (retVal);
304 }
306 int32_t Ospi_udma_deinit(void)
307 {
308 int32_t retVal = UDMA_SOK;
310 if (gDrvHandle != NULL)
311 {
312 retVal = Udma_deinit(gDrvHandle);
313 if(UDMA_SOK == retVal)
314 {
315 gDrvHandle = NULL;
316 }
317 }
319 return (retVal);
320 }
321 #endif
323 #ifdef USE_BIOS
325 #if defined(BUILD_MPU) || defined (__C7100__)
326 extern void Osal_initMmuDefault(void);
327 void InitMmu(void)
328 {
329 Osal_initMmuDefault();
330 }
331 #endif
333 #endif
334 #endif
336 #if defined(SOC_AM65XX)
337 /* define the unlock and lock values */
338 #define KICK0_UNLOCK_VAL 0x68EF3490
339 #define KICK1_UNLOCK_VAL 0xD172BC5A
340 #define KICK_LOCK_VAL 0x00000000
342 //
343 #define MAIN_MMR_BASE_ADDRESS CSL_CTRL_MMR0_CFG0_BASE
344 #define MCU_MMR_BASE_ADDRESS CSL_MCU_CTRL_MMR0_CFG0_BASE
345 #define WKUP_MMR_BASE_ADDRESS CSL_WKUP_CTRL_MMR0_CFG0_BASE
347 #define CSL2PTR (uint32_t *)(uintptr_t)
349 uint32_t MMR_unlock_one(uint32_t * kick0, uint32_t * kick1)
350 {
351 // initialize the status variable
352 uint32_t status = 1;
354 // if either of the kick lock registers are locked
355 if (!(*kick0 & 0x1) | !(*kick1 & 0x1))
356 {
357 // unlock the partition by writing the unlock values to the kick lock registers
358 *kick0 = KICK0_UNLOCK_VAL;
359 *kick1 = KICK1_UNLOCK_VAL;
360 }
362 // check to see if either of the kick registers are unlocked.
363 if (!(*kick0 & 0x1))
364 {
365 status = 0;
366 }
368 // return the status to the calling program
369 return status;
371 }
373 uint32_t MMR_lock_one(uint32_t * kick0, uint32_t * kick1)
374 {
375 // create status return variable
376 uint32_t status = 1;
378 // check to see if either of the kick registers are unlocked.
379 if ((*kick0 & 0x1))
380 {
381 // write the kick lock value to the kick lock registers to lock the partition
382 *kick0 = KICK_LOCK_VAL;
383 *kick1 = KICK_LOCK_VAL;
384 }
386 // check to see if either of the kick registers are still unlocked.
387 if ((*kick0 & 0x1))
388 {
389 status = 0;
390 }
391 // return success or failure
392 return status;
393 }
395 uint32_t MCU_CTRL_MMR_unlock_all()
396 {
398 // initialize the status variable
399 uint32_t status = 1;
401 // Unlock the 0th partition
402 status &= MMR_unlock_one(
403 CSL2PTR ( MCU_MMR_BASE_ADDRESS
404 + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK0),
405 CSL2PTR ( MCU_MMR_BASE_ADDRESS
406 + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK1));
408 // Unlock the 1st partition
409 status &= MMR_unlock_one(
410 CSL2PTR ( MCU_MMR_BASE_ADDRESS
411 + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK0),
412 CSL2PTR ( MCU_MMR_BASE_ADDRESS
413 + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK1));
415 // Unlock the 2nd partition
416 status &= MMR_unlock_one(
417 CSL2PTR ( MCU_MMR_BASE_ADDRESS
418 + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK0),
419 CSL2PTR ( MCU_MMR_BASE_ADDRESS
420 + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK1));
422 // Unlock the 3rd partition
423 status &= MMR_unlock_one(
424 CSL2PTR ( MCU_MMR_BASE_ADDRESS
425 + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK0),
426 CSL2PTR ( MCU_MMR_BASE_ADDRESS
427 + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK1));
429 // Unlock the 4th partition
430 status &= MMR_unlock_one(
431 CSL2PTR ( MCU_MMR_BASE_ADDRESS
432 + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK0),
433 CSL2PTR ( MCU_MMR_BASE_ADDRESS
434 + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK1));
435 return status;
436 }
438 uint32_t MCU_CTRL_MMR_lock_all()
439 {
441 // initialize the status variable
442 uint32_t status = 1;
444 // lock the 0th partition
445 status &= MMR_lock_one(
446 CSL2PTR (MCU_MMR_BASE_ADDRESS
447 + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK0),
448 CSL2PTR (MCU_MMR_BASE_ADDRESS
449 + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK1));
451 // lock the 1st partition
452 status &= MMR_lock_one(
453 CSL2PTR (MCU_MMR_BASE_ADDRESS
454 + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK0),
455 CSL2PTR (MCU_MMR_BASE_ADDRESS
456 + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK1));
457 // lock the 2nd partition
458 status &= MMR_lock_one(
459 CSL2PTR (MCU_MMR_BASE_ADDRESS
460 + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK0),
461 CSL2PTR (MCU_MMR_BASE_ADDRESS
462 + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK1));
463 // lock the 3rd partition
464 status &= MMR_lock_one(
465 CSL2PTR (MCU_MMR_BASE_ADDRESS
466 + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK0),
467 CSL2PTR (MCU_MMR_BASE_ADDRESS
468 + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK1));
469 // lock the 4th partition
470 status &= MMR_lock_one(
471 CSL2PTR (MCU_MMR_BASE_ADDRESS
472 + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK0),
473 CSL2PTR (MCU_MMR_BASE_ADDRESS
474 + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK1));
475 return status;
476 }
478 void OSPI_configClk(uint32_t freq, bool usePHY)
479 {
480 uint32_t divider = 0x12;
482 MCU_CTRL_MMR_unlock_all();
485 if(freq == OSPI_MODULE_CLK_166M)
486 {
487 /* Select CPSWHSDIV4 */
488 *(uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_MCU_OSPI0_CLKSEL) = 1;
490 if (usePHY)
491 divider = 0xC; /* 2000/12 = 166 */
492 else
493 divider = 0x6;
495 *(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CLKDIV) = \
496 (*(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CLKDIV) & 0x00FFFFFF) | ((divider-1) << 24);
498 /* Load new values on 0->1 transition of bit 31 of tenabldiv */
499 *(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CTRL) &= 0x7FFFFFFF;
500 Osal_delay(1);
501 *(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CTRL) |= 0x80000000;
502 }
503 else
504 {
505 /* Select MCUPLL0HSDIV4 */
506 *(uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_MCU_OSPI0_CLKSEL) = 0;
508 if(freq == OSPI_MODULE_CLK_133M)
509 divider = 18; /* 2400/18 = 133 */
510 if(freq == OSPI_MODULE_CLK_160M)
511 divider = 15; /* 2400/15 = 160 */
512 if(freq == OSPI_MODULE_CLK_200M)
513 divider = 12; /* 2400/12 = 200 */
515 *(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL0_HSDIV_CLKDIV) = \
516 (*(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL0_HSDIV_CLKDIV) & 0x00FFFFFF) | ((divider-1) << 24);
518 /* Load new values on 0->1 transition of bit 31 of tenabldiv */
519 *(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL0_HSDIV_CTRL) &= 0x7FFFFFFF;
520 Osal_delay(1);
521 *(uint32_t*)(CSL_MCU_PLL0_CFG_BASE+CSL_MCU_PLL_MMR_CFG_PLL0_HSDIV_CTRL) |= 0x80000000;
522 }
523 MCU_CTRL_MMR_lock_all();
525 SPI_log("\n OSPI RCLK running at %d MHz. \n", freq);
526 return;
528 }
529 #endif
531 #if defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X)
532 void OSPI_configClk(uint32_t freq, bool usePHY)
533 {
534 OSPI_v0_HwAttrs ospi_cfg;
535 int32_t retVal;
536 uint64_t ospi_rclk_freq;
537 uint32_t parClk;
538 #if defined (SOC_AM64X)
539 uint32_t clkID[] = {
540 TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK,
541 };
542 uint32_t devID[] = {
543 TISCI_DEV_FSS0_OSPI_0,
544 };
545 #else
546 uint32_t clkID[] = {
547 TISCI_DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK,
548 TISCI_DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK
549 };
550 uint32_t devID[] = {
551 TISCI_DEV_MCU_FSS0_OSPI_0,
552 TISCI_DEV_MCU_FSS0_OSPI_1
553 };
554 #endif
556 /* Get the default SPI init configurations */
557 OSPI_socGetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
559 retVal = Sciclient_pmModuleClkRequest(devID[BOARD_OSPI_NOR_INSTANCE],
560 clkID[BOARD_OSPI_NOR_INSTANCE],
561 TISCI_MSG_VALUE_CLOCK_SW_STATE_REQ,
562 TISCI_MSG_FLAG_AOP,
563 SCICLIENT_SERVICE_WAIT_FOREVER);
564 if (retVal != CSL_PASS)
565 {
566 SPI_log("\n Sciclient_pmModuleClkRequest failed");
567 goto clk_cfg_exit;
568 }
570 /* Max clocks */
571 if (freq == OSPI_MODULE_CLK_166M)
572 {
573 #if defined (SOC_AM64X)
574 parClk = TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK;
575 #else
576 parClk = TISCI_DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK;
577 #endif
579 retVal = Sciclient_pmSetModuleClkParent(devID[BOARD_OSPI_NOR_INSTANCE],
580 clkID[BOARD_OSPI_NOR_INSTANCE],
581 parClk,
582 SCICLIENT_SERVICE_WAIT_FOREVER);
583 }
584 else
585 {
586 #if defined (SOC_AM64X)
587 parClk = TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK;
588 #else
589 parClk = TISCI_DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK;
590 #endif
591 retVal = Sciclient_pmSetModuleClkParent(devID[BOARD_OSPI_NOR_INSTANCE],
592 clkID[BOARD_OSPI_NOR_INSTANCE],
593 parClk,
594 SCICLIENT_SERVICE_WAIT_FOREVER);
595 }
597 if (retVal != CSL_PASS)
598 {
599 SPI_log("\n Sciclient_pmSetModuleClkParent failed");
600 goto clk_cfg_exit;
601 }
603 ospi_cfg.funcClk = freq;
604 OSPI_socSetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
606 ospi_rclk_freq = (uint64_t)freq;
607 retVal = Sciclient_pmSetModuleClkFreq(devID[BOARD_OSPI_NOR_INSTANCE],
608 clkID[BOARD_OSPI_NOR_INSTANCE],
609 ospi_rclk_freq,
610 TISCI_MSG_FLAG_AOP,
611 SCICLIENT_SERVICE_WAIT_FOREVER);
613 if (retVal != CSL_PASS)
614 {
615 SPI_log("\n Sciclient_pmSetModuleClkFreq failed");
616 goto clk_cfg_exit;
617 }
619 ospi_rclk_freq = 0;
620 retVal = Sciclient_pmGetModuleClkFreq(devID[BOARD_OSPI_NOR_INSTANCE],
621 clkID[BOARD_OSPI_NOR_INSTANCE],
622 &ospi_rclk_freq,
623 SCICLIENT_SERVICE_WAIT_FOREVER);
624 if (retVal != CSL_PASS)
625 {
626 SPI_log("\n Sciclient_pmGetModuleClkFreq failed");
627 goto clk_cfg_exit;
628 }
630 SPI_log("\n OSPI RCLK running at %d MHz. \n", (uint32_t)ospi_rclk_freq);
632 clk_cfg_exit:
633 return;
634 }
635 #endif
637 void OSPI_initConfig(OSPI_Tests *test)
638 {
639 OSPI_v0_HwAttrs ospi_cfg;
641 /* Get the default OSPI init configurations */
642 OSPI_socGetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
644 #ifdef OSPI_QSPI_FLASH
645 ospi_cfg.xferLines = OSPI_XFER_LINES_QUAD;
646 #endif
648 /* Modify the default OSPI configurations */
649 ospi_cfg.dacEnable = test->dacMode;
650 if (test->dacMode)
651 {
652 ospi_cfg.dmaEnable = test->dmaMode;
653 /* Enable PHY in DAC mode */
654 ospi_cfg.phyEnable = true;
655 ospi_cfg.intrEnable = false;
656 #ifdef SPI_DMA_ENABLE
657 if (ospi_cfg.dmaEnable)
658 {
659 Ospi_udma_init(&ospi_cfg);
660 }
661 #endif
662 }
663 else
664 {
665 /* Enable interrupt in INDAC mode */
666 #if (defined(SOC_J7200) && (defined(BUILD_MCU2_0)||defined(BUILD_MCU2_1)))
667 ospi_cfg.intrEnable = false;
668 #elif (defined(SOC_J721E) && (defined(BUILD_MCU2_0)||defined(BUILD_MCU2_1)||defined(BUILD_MCU3_0)||defined(BUILD_MCU3_1))) /* Work Around until PDK-8607 is addressed */
669 ospi_cfg.intrEnable = false;
670 #else
671 ospi_cfg.intrEnable = true;
672 #endif
673 /* Disable PHY in INDAC mode */
674 ospi_cfg.phyEnable = false;
675 ospi_cfg.dmaEnable = false;
676 }
678 if (test->testId == OSPI_TEST_ID_DAC_133M_SPI)
679 {
680 /* Disable PHY in legacy SPI mode (1-1-1) */
681 ospi_cfg.phyEnable = false;
682 ospi_cfg.dtrEnable = false;
683 ospi_cfg.xferLines = OSPI_XFER_LINES_SINGLE;
684 }
685 else
686 {
687 ospi_cfg.dtrEnable = true;
688 ospi_cfg.xferLines = OSPI_XFER_LINES_OCTAL;
689 }
691 if (test->testId == OSPI_TEST_ID_WR_TUNING)
692 {
693 ospi_cfg.phyEnable = false;
694 }
696 ospi_cfg.funcClk = test->clk;
698 if (ospi_cfg.funcClk == OSPI_MODULE_CLK_133M)
699 {
700 ospi_cfg.devDelays[3] = OSPI_DEV_DELAY_CSDA;
701 }
702 else
703 {
704 ospi_cfg.devDelays[3] = OSPI_DEV_DELAY_CSDA_3;
705 }
707 /* Set the default OSPI init configurations */
708 OSPI_socSetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
709 }
711 /*
712 * ======== OSPI unit test function ========
713 */
714 static bool OSPI_flash_test(void *arg)
715 {
716 Board_flashHandle boardHandle;
717 Board_FlashInfo *flashInfo;
718 #ifdef OSPI_WRITE
719 uint32_t blockNum; /* flash block number */
720 uint32_t pageNum; /* flash page number */
721 #endif
722 bool testPassed = true; /* return value */
723 uint32_t writeMode = OSPI_FLASH_OCTAL_PAGE_PROG;
724 uint32_t readMode = OSPI_FLASH_OCTAL_READ;
725 uint32_t deviceId; /* flash device ID */
726 OSPI_Tests *test = (OSPI_Tests *)arg;
727 uint32_t i;
728 uint32_t offset;
729 uint32_t xferLen;
730 uint32_t testLen = TEST_DATA_LEN;
731 uint32_t testSegLen = TEST_XFER_SEG_LEN;
732 #ifdef OSPI_PROFILE
733 uint64_t startTime; /* start time stamp in usec */
734 uint64_t elapsedTime; /* elapsed time in usec */
735 float xferRate;
736 uint32_t xferRateInt;
737 #ifdef USE_BIOS
738 uint32_t cpuLoad;
739 #endif
740 #endif
741 uint32_t startOffset;
742 uint8_t *pBuf;
743 uint32_t tuneEnable;
745 if (test->testId == OSPI_TEST_ID_WR_TUNING)
746 {
747 testLen = NOR_ATTACK_VECTOR_SIZE;
748 startOffset = TEST_TUNE_PATTERN_OFFSET;
749 }
750 else
751 {
752 testLen = TEST_DATA_LEN;
753 startOffset = TEST_ADDR_OFFSET;
754 }
756 if(test->dacMode)
757 {
758 tuneEnable = TRUE;
759 }
760 else
761 {
762 tuneEnable = FALSE;
763 }
765 OSPI_initConfig(test);
767 /* Default Device, SoC's specifics overrides shall follow */
768 deviceId = BOARD_FLASH_ID_MT35XU512ABA1G12;
770 #if defined(SOC_J7200) || defined(SOC_AM64X)
771 deviceId = BOARD_FLASH_ID_S28HS512T;
772 #endif
774 #ifdef OSPI_PROFILE
775 /* Get start time stamp for the Board_flashOpen measurement */
776 startTime = TimerP_getTimeInUsecs();
777 #endif
778 /* Open the Board OSPI NOR device with OSPI port 0
779 and use default OSPI configurations */
780 boardHandle = Board_flashOpen(deviceId,
781 BOARD_OSPI_NOR_INSTANCE, (void *)(&tuneEnable));
783 #ifdef OSPI_PROFILE
784 /* Get elapsed time for the Board_flashOpen measurement */
785 elapsedTime = TimerP_getTimeInUsecs() - startTime;
786 SPI_log("\n Board_flashOpen elpased time %d us \n", (uint32_t)elapsedTime);
787 #endif
788 if (!boardHandle)
789 {
790 SPI_log("\n Board_flashOpen failed. \n");
791 testPassed = false;
792 goto err;
793 }
794 else
795 {
796 flashInfo = (Board_FlashInfo *)boardHandle;
797 SPI_log("\n OSPI NOR device ID: 0x%x, manufacturer ID: 0x%x \n",
798 flashInfo->device_id, flashInfo->manufacturer_id);
799 }
801 /* Generate the data */
802 GeneratePattern(txBuf, rxBuf, testLen);
803 if (test->testId == OSPI_TEST_ID_WR_TUNING)
804 {
805 pBuf = nor_attack_vector;
806 }
807 else
808 {
809 pBuf = txBuf;
810 }
811 #ifdef SPI_DMA_ENABLE
812 if (test->dmaMode)
813 {
814 CacheP_wbInv((void *)pBuf, (int32_t)testLen);
815 CacheP_wbInv((void *)rxBuf, (int32_t)testLen);
816 }
817 #endif
819 #ifdef OSPI_WRITE
820 #if defined(SOC_J7200) || defined(SOC_AM64X)
821 if (test->dacMode) /* DAC writes are not supported on Cypress xSPI Flash - Switch to INDAC mode for write as WA to PDK-7115 */
822 {
823 SPI_log("\n The Cypress xSPI Flash does not support DAC writes, switching to INDAC mode. \n");
824 OSPI_v0_HwAttrs ospi_cfg;
825 Board_flashClose(boardHandle);
826 OSPI_socGetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
827 ospi_cfg.dacEnable = false;
828 ospi_cfg.phyEnable = false;
829 ospi_cfg.dmaEnable = false;
830 ospi_cfg.intrEnable = true;
831 OSPI_socSetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
832 boardHandle = Board_flashOpen(deviceId, BOARD_OSPI_NOR_INSTANCE, (void *)(&tuneEnable));
833 }
834 #endif
835 for (i = 0; i < testLen; i += NOR_BLOCK_SIZE)
836 {
837 offset = startOffset + i;
838 if (Board_flashOffsetToBlkPage(boardHandle, offset,
839 &blockNum, &pageNum))
840 {
841 SPI_log("\n Board_flashOffsetToBlkPage failed. \n");
842 testPassed = false;
843 goto err;
844 }
846 /* Erase block, to which data has to be written */
847 if (Board_flashEraseBlk(boardHandle, blockNum))
848 {
849 SPI_log("\n Board_flashEraseBlk failed. \n");
850 testPassed = false;
851 goto err;
852 }
853 }
854 #ifdef OSPI_PROFILE
855 #ifdef USE_BIOS
856 Load_reset( );
857 #endif
858 /* Get start time stamp for the write performance measurement */
859 startTime = TimerP_getTimeInUsecs();
860 #endif
861 for (i = 0; i < testLen; i += testSegLen)
862 {
863 offset = startOffset + i;
864 if ((testLen - i) < testSegLen)
865 {
866 xferLen = testLen - i;
867 }
868 else
869 {
870 xferLen = testSegLen;
871 }
872 /* Write buffer to flash */
873 if (Board_flashWrite(boardHandle, offset, &pBuf[i],
874 xferLen, (void *)(&writeMode)))
875 {
876 SPI_log("\n Board_flashWrite failed. \n");
877 testPassed = false;
878 goto err;
879 }
880 }
882 #ifdef OSPI_PROFILE
883 elapsedTime = TimerP_getTimeInUsecs() - startTime;
884 #ifdef USE_BIOS
885 Load_update( );
886 cpuLoad = Load_getCPULoad();
887 #endif
888 /* calculate the write transfer rate in Kbps */
889 xferRate = (float) (((float) (testLen * 8)) / elapsedTime) * 1000U;
890 xferRateInt = (uint32_t)xferRate;
891 SPI_log("\n Board_flashWrite %d bytes at transfer rate %d Kbps \n", testLen, xferRateInt);
892 #ifdef USE_BIOS
893 SPI_log("\n Board_flashWrite CPU load %d%% \n", cpuLoad);
894 #endif
895 #endif
896 #endif /* OSPI_WRITE */
898 #if defined(SOC_J7200) || defined(SOC_AM64X)
899 if (test->dacMode) /* DAC reads are supported - switching back to DAC mode */
900 {
901 SPI_log("\n The Cypress xSPI Flash supports DAC reads, switching back to DAC mode. \n");
902 OSPI_v0_HwAttrs ospi_cfg;
903 Board_flashClose(boardHandle);
904 OSPI_socGetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
905 if (test->testId == OSPI_TEST_ID_DAC_133M_SPI)
906 {
907 /* Disable PHY in legacy SPI mode (1-1-1) */
908 ospi_cfg.phyEnable = false;
909 ospi_cfg.dtrEnable = false;
910 ospi_cfg.xferLines = OSPI_XFER_LINES_SINGLE;
911 }
912 else
913 {
914 /* Enable PHY in octal SPI mode (8-8-8) */
915 ospi_cfg.phyEnable = true;
916 ospi_cfg.dtrEnable = true;
917 ospi_cfg.xferLines = OSPI_XFER_LINES_OCTAL;
918 }
920 /* Would be enabled when PDK-8724 is fixed */
921 ospi_cfg.phyEnable = false;
923 ospi_cfg.dacEnable = true;
924 ospi_cfg.dmaEnable = test->dmaMode;
925 ospi_cfg.intrEnable = false;
926 OSPI_socSetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
927 boardHandle = Board_flashOpen(deviceId, BOARD_OSPI_NOR_INSTANCE, (void *)(&tuneEnable));
928 }
929 #endif
930 #ifdef OSPI_PROFILE
931 #ifdef USE_BIOS
932 Load_reset( );
933 #endif
934 /* Get start time stamp for the read performance measurement */
935 startTime = TimerP_getTimeInUsecs();
936 #endif
937 for (i = 0; i < testLen; i += testSegLen)
938 {
939 offset = startOffset + i;
940 if ((testLen - i) < testSegLen)
941 {
942 xferLen = testLen - i;
943 }
944 else
945 {
946 xferLen = testSegLen;
947 }
948 if (Board_flashRead(boardHandle, offset, &rxBuf[i],
949 xferLen, (void *)(&readMode)))
950 {
951 SPI_log("\n Board_flashRead failed. \n");
952 testPassed = false;
953 goto err;
954 }
955 }
957 #ifdef OSPI_PROFILE
958 elapsedTime = TimerP_getTimeInUsecs() - startTime;
959 #ifdef USE_BIOS
960 Load_update( );
961 cpuLoad = Load_getCPULoad();
962 #endif
963 /* calculate the write transfer rate in Kbps */
964 xferRate = (float) (((float) (testLen * 8)) / elapsedTime);
965 xferRateInt = (uint32_t)xferRate;
966 SPI_log("\n Board_flashRead %d bytes at transfer rate %d Mbps \n", testLen, xferRateInt);
967 #ifdef USE_BIOS
968 SPI_log("\n Board_flashRead CPU load %d%% \n", cpuLoad);
969 #endif
970 #endif
972 #ifdef OSPI_WRITE
973 /* Verify Data */
974 if (VerifyData(pBuf, rxBuf, testLen) == false)
975 {
976 SPI_log("\n Data mismatch. \n");
977 testPassed = false;
978 goto err;
979 }
980 #endif
982 err:
983 if (boardHandle != 0U)
984 {
985 Board_flashClose(boardHandle);
986 }
988 #if SPI_DMA_ENABLE
989 if (test->dmaMode)
990 {
991 Ospi_udma_deinit();
992 }
993 #endif
995 return (testPassed);
996 }
998 void OSPI_test_print_test_desc(OSPI_Tests *test)
999 {
1000 char testId[16] = {0, };
1002 /* Print unit test ID */
1003 sprintf(testId, "%d", test->testId);
1004 SPI_log("\r\n OSPI UT %s\r\n", testId);
1006 /* Print test description */
1007 SPI_log("\r\n %s\r\n", test->testDesc);
1008 }
1010 /* The order of tests has been changed to 166MHz followed by 133MHz as a work around to PDK-8724 */
1011 OSPI_Tests Ospi_tests[] =
1012 {
1013 #ifdef OSPI_WRITE_TUNING
1014 #if defined(SOC_J7200) || defined(SOC_AM64X)
1015 /* testFunc testID dacMode dmaMode clk testDesc */
1016 {OSPI_flash_test, OSPI_TEST_ID_WR_TUNING, false, false, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave to write tuning data to flash"},
1017 #else
1018 {OSPI_flash_test, OSPI_TEST_ID_WR_TUNING, true, false, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave to write tuning data to flash"},
1019 #endif
1020 #endif
1021 {OSPI_flash_test, OSPI_TEST_ID_DAC_133M, true, false, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in DAC mode at 133MHz RCLK"},
1022 {OSPI_flash_test, OSPI_TEST_ID_INDAC_133M, false, false, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in INDAC mode at 133MHz RCLK"},
1023 #ifdef SPI_DMA_ENABLE
1024 {OSPI_flash_test, OSPI_TEST_ID_DAC_DMA_133M, true, true, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in DAC DMA mode at 133MHz RCLK"},
1025 #endif
1026 {OSPI_flash_test, OSPI_TEST_ID_DAC_166M, true, false, OSPI_MODULE_CLK_166M, "\r\n OSPI flash test slave in DAC mode at 166MHz RCLK"},
1027 {OSPI_flash_test, OSPI_TEST_ID_INDAC_166M, false, false, OSPI_MODULE_CLK_166M, "\r\n OSPI flash test slave in INDAC mode at 166MHz RCLK"},
1028 #ifdef SPI_DMA_ENABLE
1029 {OSPI_flash_test, OSPI_TEST_ID_DAC_DMA_166M, true, true, OSPI_MODULE_CLK_166M, "\r\n OSPI flash test slave in DAC DMA mode at 166MHz RCLK"},
1030 #endif
1031 {OSPI_flash_test, OSPI_TEST_ID_DAC_133M_SPI, true, false, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in DAC Legacy SPI mode at 133MHz RCLK"},
1032 {NULL, }
1033 };
1035 /*
1036 * ======== test function ========
1037 */
1038 #ifdef USE_BIOS
1039 void spi_test(UArg arg0, UArg arg1)
1040 #else
1041 void spi_test()
1042 #endif
1043 {
1044 uint32_t i;
1045 bool testFail = false;
1046 OSPI_Tests *test;
1048 /* Init SPI driver */
1049 SPI_init();
1051 for (i = 0; ; i++)
1052 {
1053 test = &Ospi_tests[i];
1054 if (test->testFunc == NULL)
1055 {
1056 break;
1057 }
1059 OSPI_configClk(test->clk, true);
1061 OSPI_test_print_test_desc(test);
1063 if (test->testFunc((void *)test) == true)
1064 {
1065 SPI_log("\r\n %s have passed\r\n", test->testDesc);
1066 }
1067 else
1068 {
1069 SPI_log("\r\n %s have failed\r\n", test->testDesc);
1070 testFail = true;
1071 break;
1072 }
1073 }
1075 if(testFail == true)
1076 {
1077 SPI_log("\n Some tests have failed. \n");
1078 }
1079 else
1080 {
1081 SPI_log("\n All tests have passed. \n");
1082 }
1084 SPI_log("Done\n");
1086 while (true)
1087 {
1088 }
1089 }
1091 /*
1092 * ======== main ========
1093 */
1094 int main(void)
1095 {
1096 /* Call board init functions */
1097 Board_initCfg boardCfg;
1098 #ifdef USE_BIOS
1099 Task_Handle task;
1100 Error_Block eb;
1101 Task_Params taskParams;
1102 #endif
1103 boardCfg = BOARD_INIT_PINMUX_CONFIG |
1104 BOARD_INIT_MODULE_CLOCK |
1105 BOARD_INIT_UART_STDIO;
1106 #if defined (SOC_J7200)
1107 /* Need to do PLL config through board init for proper clock input on J7200 */
1108 boardCfg |= BOARD_INIT_PLL;
1109 #endif
1111 Board_init(boardCfg);
1113 #ifdef USE_BIOS
1115 Error_init(&eb);
1116 /* Initialize the task params */
1117 Task_Params_init(&taskParams);
1118 /* Set the task priority higher than the default priority (1) */
1119 taskParams.priority = 2;
1120 taskParams.stack = gAppTskStackMain;
1121 taskParams.stackSize = sizeof (gAppTskStackMain);
1123 /* Start BIOS */
1124 task = Task_create(spi_test, &taskParams, &eb);
1125 if (task == NULL) {
1126 System_printf("Task_create() failed!\n");
1127 BIOS_exit(0);
1128 }
1129 BIOS_start();
1130 #else
1131 spi_test();
1132 #endif
1133 return (0);
1134 }
1136 /*
1137 * ======== CompareData ========
1138 */
1139 bool VerifyData(uint8_t *expData,
1140 uint8_t *rxData,
1141 uint32_t length)
1142 {
1143 uint32_t idx = 0;
1144 uint32_t match = 1;
1145 bool retVal = false;
1147 for(idx = 0; ((idx < length) && (match != 0)); idx++)
1148 {
1149 if(*expData != *rxData)
1150 {
1151 match = 0;
1152 SPI_log("Data mismatch at idx %d\n", idx);
1153 }
1154 expData++;
1155 rxData++;
1156 }
1158 if(match == 1)
1159 {
1160 retVal = true;
1161 }
1163 return retVal;
1164 }
1166 /*
1167 * ======== GeneratePattern ========
1168 */
1169 static void GeneratePattern(uint8_t *txBuf, uint8_t *rxBuf, uint32_t length)
1170 {
1171 volatile uint32_t idx;
1172 volatile uint8_t *txPtr = txBuf;
1173 volatile uint8_t *rxPtr = rxBuf;
1175 for(idx = 0; idx < length; idx++)
1176 {
1177 if (idx < (length/2))
1178 {
1179 *txPtr++ = (uint8_t)idx;
1180 }
1181 else if (idx < (length/4*3))
1182 {
1183 *txPtr++ = 0xaa;
1184 }
1185 else
1186 {
1187 *txPtr++ = 0x55;
1188 }
1189 *rxPtr++ = (uint8_t)0U;
1190 }
1191 }