1 /*
2 * Copyright (c) 2019, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /*
34 * file: icss_uart.h
35 *
36 * brief: This is a common header file for shared definitions for the UART LLD & UART PRU FW.
37 *
38 */
40 #ifndef _ICSS_UART_H_
41 #define _ICSS_UART_H_
44 // TX and RX buffer size; assumptions are made based on 8-bit rollover
45 #define BUFF_SIZE ( 0x100 )
48 //
49 // Firmware UART instance registers
50 //
52 // UART instance register addresses
54 // UART configuration register offsets
55 #define UART_CTRL_OFFSET ( 0 ) // UART control offset
56 #define UART_CFG_OFFSET ( 4 ) // UART configuration offset
57 #define UART_RD_WR_PTRS_OFFSET ( 8 ) // Tx/Rx read/write buffer pointers offset
58 #define UART_TX_PIN_INT_OFFSET ( 12 ) // Tx pin/int offset
59 #define UART_RX_PIN_INT_OFFSET ( 16 ) // Rx pin/int offset
60 // UART register sizes (bytes)
61 #define UART_CTRL_SZ ( 4 ) // UART control size
62 #define UART_CFG_SZ ( 4 ) // UART configuration size
63 #define UART_RD_WR_PTRS_SZ ( 4 ) // Tx/Rx read/write buffer pointers size
64 #define UART_TX_PIN_INT_SZ ( 4 ) // Tx pin/int size
65 #define UART_RX_PIN_INT_SZ ( 4 ) // Rx pin/int size
67 // UART0 addresses
68 #define ICSS_UART0_CFG_ADDR ( 0x0014 )
69 #define UART0_CTRL ( ICSS_UART0_CFG_ADDR + UART_CTRL_OFFSET ) // UART0_CTRL FW register, UART control
70 #define UART0_CFG ( ICSS_UART0_CFG_ADDR + UART_CFG_OFFSET ) // UART0_CFG FW register, UART configuration
71 #define UART0_RD_WR_PTRS ( ICSS_UART0_CFG_ADDR + UART_RD_WR_PTRS_OFFSET ) // UART0_RD_WR_PTRS FW register, Tx/Rx Buffer Read/Write Pointers
72 #define UART0_TX_PIN_INT_CFG ( ICSS_UART0_CFG_ADDR + UART_TX_PIN_INT_OFFSET ) // UART0_TX_PIN_INT_CFG register, Tx pin/interrupt configuration
73 #define UART0_RX_PIN_INT_CFG ( ICSS_UART0_CFG_ADDR + UART_RX_PIN_INT_OFFSET ) // UART0_RX_PIN_INT_CFG register, Rx pin/interrupt configuration
74 #define UART0_TX_BUFFER ( 0x0100 ) // UART0 Tx buffer address
75 #define UART0_RX_BUFFER ( 0x0200 ) // UART0 Rx buffer address
77 // UART1 addresses
78 #define ICSS_UART1_CFG_ADDR ( 0x0028 )
79 #define UART1_CTRL ( ICSS_UART1_CFG_ADDR + UART_CTRL_OFFSET ) // UART1_CTRL FW register, UART control
80 #define UART1_CFG ( ICSS_UART1_CFG_ADDR + UART_CFG_OFFSET ) // UART1_CFG FW register, UART configuration
81 #define UART1_RD_WR_PTRS ( ICSS_UART1_CFG_ADDR + UART_RD_WR_PTRS_OFFSET ) // UART1_RD_WR_PTRS FW register, Tx/Rx Buffer Read/Write Pointers
82 #define UART1_TX_PIN_INT_CFG ( ICSS_UART1_CFG_ADDR + UART_TX_PIN_INT_OFFSET ) // UART1_TX_PIN_INT_CFG register, Tx pin/interrupt configuration
83 #define UART1_RX_PIN_INT_CFG ( ICSS_UART1_CFG_ADDR + UART_RX_PIN_INT_OFFSET ) // UART1_RX_PIN_INT_CFG register, Rx pin/interrupt configuration
84 #define UART1_TX_BUFFER ( 0x0300 ) // UART1 Tx buffer address
85 #define UART1_RX_BUFFER ( 0x0400 ) // UART1 Rx buffer address
87 // UART2 addresses
88 #define ICSS_UART2_CFG_ADDR ( 0x003C )
89 #define UART2_CTRL ( ICSS_UART2_CFG_ADDR + UART_CTRL_OFFSET ) // UART2_CTRL FW register, UART control
90 #define UART2_CFG ( ICSS_UART2_CFG_ADDR + UART_CFG_OFFSET ) // UART2_CFG FW register, UART configuration
91 #define UART2_RD_WR_PTRS ( ICSS_UART2_CFG_ADDR + UART_RD_WR_PTRS_OFFSET ) // UART2_RD_WR_PTRS FW register, Tx/Rx Buffer Read/Write Pointers
92 #define UART2_TX_PIN_INT_CFG ( ICSS_UART2_CFG_ADDR + UART_TX_PIN_INT_OFFSET ) // UART2_TX_PIN_INT_CFG register, Tx pin/interrupt configuration
93 #define UART2_RX_PIN_INT_CFG ( ICSS_UART2_CFG_ADDR + UART_RX_PIN_INT_OFFSET ) // UART2_RX_PIN_INT_CFG register, Rx pin/interrupt configuration
94 #define UART2_TX_BUFFER ( 0x0500 ) // UART2 Tx buffer address
95 #define UART2_RX_BUFFER ( 0x0600 ) // UART2 Rx buffer address
98 // UART instance register bit fields
100 // UARTn_CTRL FW register bit fields
101 #define UART_CTRL__EN_SHIFT ( 0 ) // UART enable bit-field shift
102 #define UART_CTRL__EN_MASK ( 0x1 << UART_CTRL__EN_SHIFT ) // UART enable bit-field mask
103 #define UART_CTRL__TX_EN_ACK_SHIFT ( 8 ) // UART Tx enable-ack bit-field shift
104 #define UART_CTRL__TX_EN_ACK_MASK ( 0x1 << UART_CTRL__TX_EN_ACK_SHIFT ) // UART Tx enable-ack bit-field mask
105 #define UART_CTRL__RX_EN_ACK_SHIFT ( 9 ) // UART Tx enable-ack bit-field shift
106 #define UART_CTRL__RX_EN_ACK_MASK ( 0x1 << UART_CTRL__RX_EN_ACK_SHIFT ) // UART Rx enable-ack bit-field mask
108 // UARTn_CFG FW register bit fields
109 #define UART_CFG__BAUD_RATE_SHIFT ( 0 ) // Baud rate bit-field shift
110 #define UART_CFG__BAUD_RATE_MASK ( 0xF << UART_CFG__BAUD_RATE_SHIFT ) // Baud rate bit-field mask
111 #define UART_CFG__NO_BITS_PER_CHAR_SHIFT ( 4 ) // Number of bits per character shift
112 #define UART_CFG__NO_BITS_PER_CHAR_MASK ( 0x7 << UART_CFG__NO_BITS_PER_CHAR_SHIFT ) // Number of bits per character mask
113 #define UART_CFG__STOP_BIT_SZ_SHIFT ( 7 ) // Stop bit shift
114 #define UART_CFG__STOP_BIT_SZ_MASK ( 0x3 << UART_CFG__STOP_BIT_SZ_SHIFT ) // Stop bit size mask
115 #define UART_CFG__PARITY_EN_SHIFT ( 9 ) // Parity enable shift
116 #define UART_CFG__PARITY_EN_MASK ( 0x1 << UART_CFG__PARITY_EN_SHIFT) // Parity enable mask
117 #define UART_CFG__PARITY_TYPE_SHIFT ( 10 ) // Parity enable shift
118 #define UART_CFG__PARITY_TYPE_MASK ( 0x1 << UART_CFG__PARITY_TYPE_SHIFT ) // Parity enable mask
119 #define UART_CFG__FC_EN_SHIFT ( 12 ) // Flow Control enable shift
120 #define UART_CFG__FC_EN_MASK ( 0x1 << UART_CFG__FC_EN_SHIFT ) // Flow Control enable mask
121 #define UART_CFG__FC_TYPE_SHIFT ( 13 ) // Flow Control type shift
122 #define UART_CFG__FC_TYPE_MASK ( 0x1 << UART_CFG__FC_TYPE_SHIFT ) // Flow Control type mask
123 #define UART_CFG__HW_FC_THR_SHIFT ( 16 ) // HW Flow Control threshold shift
124 #define UART_CFG__HW_FC_THR_MASK ( 0xFF << UART_CFG__HW_FC_THR_SHIFT ) // HW Flow Control threshold mask
126 // UARTn_RD_WR_PTRS FW register bit fields
127 #define TX_BUFF_RD_IDX_BYTEN ( 0 )
128 #define TX_BUFF_RD_IDX_SHIFT ( 0 )
129 #define TX_BUFF_RD_IDX_MASK ( 0xFF )
130 #define UART_RD_WR_PTRS__TX_BUFF_RD_IDX_SHIFT ( TX_BUFF_RD_IDX_BYTEN*8 + TX_BUFF_RD_IDX_SHIFT ) // Tx buffer read index shift
131 #define UART_RD_WR_PTRS__TX_BUFF_RD_IDX_MASK ( TX_BUFF_RD_IDX_MASK << UART_RD_WR_PTRS__TX_BUFF_RD_IDX_SHIFT ) // Tx buffer read index mask
132 #define TX_BUFF_WR_IDX_BYTEN ( 1 )
133 #define TX_BUFF_WR_IDX_SHIFT ( 0 )
134 #define TX_BUFF_WR_IDX_MASK ( 0xFF )
135 #define UART_RD_WR_PTRS__TX_BUFF_WR_IDX_SHIFT ( TX_BUFF_WR_IDX_BYTEN*8 + TX_BUFF_WR_IDX_SHIFT ) // Tx buffer write index shift
136 #define UART_RD_WR_PTRS__TX_BUFF_WR_IDX_MASK ( TX_BUFF_WR_IDX_MASK << UART_RD_WR_PTRS__TX_BUFF_WR_IDX_SHIFT ) // Tx buffer write index mask
137 #define RX_BUFF_RD_IDX_BYTEN ( 2 )
138 #define RX_BUFF_RD_IDX_SHIFT ( 0 )
139 #define RX_BUFF_RD_IDX_MASK ( 0xFF )
140 #define UART_RD_WR_PTRS__RX_BUFF_RD_IDX_SHIFT ( TX_BUFF_RD_IDX_BYTEN*8 + TX_BUFF_RD_IDX_SHIFT ) // Rx buffer read index shift
141 #define UART_RD_WR_PTRS__RX_BUFF_RD_IDX_MASK ( TX_BUFF_RD_IDX_MASK << UART_RD_WR_PTRS__RX_BUFF_RD_IDX_SHIFT ) // Rx buffer read index mask
142 #define RX_BUFF_WR_IDX_BYTEN ( 3 )
143 #define RX_BUFF_WR_IDX_SHIFT ( 0 )
144 #define RX_BUFF_WR_IDX_MASK ( 0xFF )
145 #define UART_RD_WR_PTRS__RX_BUFF_WR_IDX_SHIFT ( RX_BUFF_WR_IDX_BYTEN*8 + RX_BUFF_WR_IDX_SHIFT ) // Rx buffer write index shift
146 #define UART_RD_WR_PTRS__RX_BUFF_WR_IDX_MASK ( RX_BUFF_WR_IDX_MASK << UART_RD_WR_PTRS__RX_BUFF_WR_IDX_SHIFT ) // Rx buffer write index mask
148 // UARTn_TX_PIN_INT_CFG FW register bit fields
149 #define TX_INT_NUM_BYTEN ( 0 )
150 #define TX_INT_NUM_SHIFT ( 0 )
151 #define TX_INT_NUM_MASK ( 0xF )
152 #define UART_TX_PIN_INT_CFG__TX_INT_NUM_SHIFT ( TX_INT_NUM_BYTEN*8 + TX_INT_NUM_SHIFT ) // Tx interrupt (System Event) number shift
153 #define UART_TX_PIN_INT_CFG__TX_INT_NUM_MASK ( TX_INT_NUM_MASK << UART_TX_PIN_INT_CFG__TX_INT_NUM_SHIFT ) // Tx interrupt (System Event) number mask
154 #define TX_INT_EN_BYTEN ( 1 )
155 #define TX_INT_EN_SHIFT ( 0 )
156 #define TX_INT_EN_MASK ( 0x1 )
157 #define UART_TX_PIN_INT_CFG__TX_INT_EN_SHIFT ( TX_INT_EN_BYTEN*8 + TX_INT_EN_SHIFT ) // Tx interrupt enable shift
158 #define UART_TX_PIN_INT_CFG__TX_INT_EN_MASK ( TX_INT_EN_MASK << UART_TX_PIN_INT_CFG__TX_INT_EN_SHIFT ) // Tx interrupt enable mask
159 #define TX_PIN_BYTEN ( 2 )
160 #define TX_PIN_SHIFT ( 0 )
161 #define TX_PIN_MASK ( 0xFF )
162 #define UART_TX_PIN_INT_CFG__TX_PIN_SHIFT ( TX_PIN_BYTEN*8 + TX_PIN_SHIFT ) // Tx pin number shift
163 #define UART_TX_PIN_INT_CFG__TX_PIN_MASK ( TX_PIN_MASK << UART_TX_PIN_INT_CFG__TX_PIN_SHIFT ) // Tx pin number mask
164 #define CTS_PIN_BYTEN ( 3 )
165 #define CTS_PIN_SHIFT ( 0 )
166 #define CTS_PIN_MASK ( 0xFF )
167 #define UART_TX_PIN_INT_CFG__CTS_PIN_SHIFT ( CTS_PIN_BYTEN*8 + CTS_PIN_SHIFT ) // Tx CTS pin shift
168 #define UART_TX_PIN_INT_CFG__CTS_PIN_MASK ( CTS_PIN_MASK << UART_TX_PIN_INT_CFG__CTS_PIN_SHIFT ) // Tx CTS pin mask
170 // UARTn_RX_PIN_INT_CFG FW register bit fields
171 #define RX_INT_NUM_BYTEN ( 0 )
172 #define RX_INT_NUM_SHIFT ( 0 )
173 #define RX_INT_NUM_MASK ( 0xF )
174 #define UART_RX_PIN_INT_CFG__RX_INT_NUM_SHIFT ( RX_INT_NUM_BYTEN*8 + RX_INT_NUM_SHIFT ) // Rx interrupt (System Event) number shift
175 #define UART_RX_PIN_INT_CFG__RX_INT_NUM_MASK ( RX_INT_NUM_MASK << UART_RX_PIN_INT_CFG__RX_INT_NUM_SHIFT ) // Rx interrupt (System Event) number mask
176 #define RX_INT_EN_BYTEN ( 1 )
177 #define RX_INT_EN_SHIFT ( 0 )
178 #define RX_INT_EN_MASK ( 0x1 )
179 #define UART_RX_PIN_INT_CFG__RX_INT_EN_SHIFT ( RX_INT_EN_BYTEN*8 + RX_INT_EN_SHIFT ) // Rx interrupt enable shift
180 #define UART_RX_PIN_INT_CFG__RX_INT_EN_MASK ( RX_INT_EN_MASK << UART_RX_PIN_INT_CFG__RX_INT_EN_SHIFT ) // Rx interrupt enable mask
181 #define RX_PIN_BYTEN ( 2 )
182 #define RX_PIN_SHIFT ( 0 )
183 #define RX_PIN_MASK ( 0xFF )
184 #define UART_RX_PIN_INT_CFG__RX_PIN_SHIFT ( RX_PIN_BYTEN*8 + RX_PIN_SHIFT ) // Rx pin number shift
185 #define UART_RX_PIN_INT_CFG__RX_PIN_MASK ( RX_PIN_MASK << UART_RX_PIN_INT_CFG__RX_PIN_SHIFT ) // Rx pin number mask
186 #define RTS_PIN_BYTEN ( 3 )
187 #define RTS_PIN_SHIFT ( 0 )
188 #define RTS_PIN_MASK ( 0xFF )
189 #define UART_RX_PIN_INT_CFG__RTS_PIN_SHIFT ( RTS_PIN_BYTEN*8 + RTS_PIN_SHIFT ) // Rx RTS pin shift
190 #define UART_RX_PIN_INT_CFG__RTS_PIN_MASK ( RTS_PIN_MASK << UART_RX_PIN_INT_CFG__RTS_PIN_SHIFT ) // Rx RTS pin mask
192 // Error bit locations in Rx character
193 #define RX_CHAR_FRAMING_ERR_SHIFT ( 14 ) // Rx character framing error shift
194 #define RX_CHAR_FRAMING_ERR_MASK ( 1 << RX_CHAR_FRAMING_ERR_SHIFT ) // Rx character frame error mask
195 #define RX_CHAR_PARITY_ERR_SHIFT ( 15 ) // Rx character parity error shift
196 #define RX_CHAR_PARITY_ERR_MASK ( 1 << RX_CHAR_PARITY_ERR_SHIFT ) // Rx character parity error mask
197 #define RX_CHAR_ERR_MASK ( RX_CHAR_FRAMING_ERR_MASK | RX_CHAR_PARITY_ERR_MASK )
200 // UART instance bit field settings
202 // UART control
203 #define UART_CTRL__EN_DISABLE ( 0 ) // UART disabled
204 #define UART_CTRL__EN_ENABLE ( 1 ) // UART enable
205 #define UART_CTRL__EN_ACK_DISABLE ( 0 ) // UART disable ack
206 #define UART_CTRL__EN_ACK_ENABLE ( 1 ) // UART enable ack
208 // Baud Rate
209 #define UART_CFG__BAUD_RATE_300 ( 0 ) // 300 baud / sec
210 #define UART_CFG__BAUD_RATE_600 ( 1 ) // 600 baud / sec
211 #define UART_CFG__BAUD_RATE_1200 ( 2 ) // 1200 baud / sec
212 #define UART_CFG__BAUD_RATE_2400 ( 3 ) // 2400 baud / sec
213 #define UART_CFG__BAUD_RATE_4800 ( 4 ) // 4800 baud / sec
214 #define UART_CFG__BAUD_RATE_9600 ( 5 ) // 9600 baud / sec
215 #define UART_CFG__BAUD_RATE_14400 ( 6 ) // 14400 baud / sec
216 #define UART_CFG__BAUD_RATE_19200 ( 7 ) // 19200 baud / sec
217 #define UART_CFG__BAUD_RATE_28800 ( 8 ) // 28800 baud / sec
218 #define UART_CFG__BAUD_RATE_38400 ( 9 ) // 38400 baud / sec
219 #define UART_CFG__BAUD_RATE_57600 ( 10 ) // 57600 baud / sec
220 #define UART_CFG__BAUD_RATE_115200 ( 11 ) // 115200 baud / sec
222 // Number of Bit per Character
223 #define UART_CFG__NUM_BITS_PER_CHAR_5 ( 0 ) // 5 bits per char
224 #define UART_CFG__NUM_BITS_PER_CHAR_6 ( 1 ) // 6 bits per char
225 #define UART_CFG__NUM_BITS_PER_CHAR_7 ( 2 ) // 7 bits per char
226 #define UART_CFG__NUM_BITS_PER_CHAR_8 ( 3 ) // 8 bits per char
227 #define UART_CFG__NUM_BITS_PER_CHAR_9 ( 4 ) // 9 bits per char
229 // Stop Bit Size
230 #define UART_CFG__STOP_BIT_SZ_1 ( 0 ) // 1 stop bit size
231 #define UART_CFG__STOP_BIT_SZ_1_5 ( 1 ) // 1.5 stop bit size
232 #define UART_CFG__STOP_BIT_SZ_2 ( 2 ) // 2 stop bit size
234 // Parity Enable
235 #define UART_CFG__PARITY_EN_DISABLE ( 0 ) // parity disable
236 #define UART_CFG__PARITY_EN_ENABLE ( 1 ) // parity enable
238 // Parity Type
239 #define UART_CFG__PARITY_TYPE_EVEN ( 0 ) // parity even
240 #define UART_CFG__PARITY_TYPE_ODD ( 1 ) // parity odd
242 // Flow Control Enable
243 #define UART_CFG__FC_EN_DISABLE ( 0 ) // flow control disable
244 #define UART_CFG__FC_EN_ENABLE ( 1 ) // flow control enable
247 //
248 // Firmware global registers
249 //
251 // Global register
253 #define ICSS_UART_GCFG_ADDR ( 0x0050 )
254 #define ICSS_UART_CGFG_OFFSET ( 0 )
255 #define ICSS_UART_GCFG_SZ ( 4 ) // bytes
257 // Firmware global register bit fields
259 #define PRU_ID_MASK ( 0x1 )
260 #define FW_INIT_MASK ( 0x1 )
262 #define ICSS_UART_GCFG__PRU_ID_SHIFT ( 0 ) // PRU ID bit-field shift
263 #define ICSS_UART_GCFG__PRU_ID_MASK ( PRU_ID_MASK << ICSS_UART_GCFG__PRU_ID_SHIFT ) // PRU ID bit-field mask
264 #define ICSS_UART_GCFG__FW_INIT_SHIFT ( 1 ) // FW init bit-field shift
265 #define ICSS_UART_GCFG__FW_INIT_MASK ( FW_INIT_MASK << ICSS_UART_GCFG__FW_INIT_SHIFT ) // FW init bit-field mask
267 #define ICSS_UART_GCFG__FW_INIT_FALSE ( 0 ) // FW not initialized
268 #define ICSS_UART_GCFG__FW_INIT_TRUE ( 1 ) // FW initialized
271 #endif // _ICSS_UART_H_