1 /**
2 * @file UART_soc.c
3 *
4 * @brief This file defines the UART interface structure specific to OMAPL137
5 */
6 /*
7 * Copyright (c) 2015 - 2018, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37 /** ============================================================================*/
39 #include <ti/csl/csl_utils.h>
40 #include <ti/csl/soc.h>
41 #include <ti/csl/csl_device_interrupt.h>
42 #include <ti/drv/uart/UART.h>
43 #ifdef UART_DMA_ENABLE
44 #include <ti/sdo/edma3/drv/edma3_drv.h>
45 #endif
46 #include <ti/drv/uart/soc/UART_soc.h>
48 /* UART configuration structure */
49 UART_HwAttrs uartInitCfg[CSL_UART_CNT] =
50 {
51 {
52 CSL_UART_0_REGS, /* UART base address */
53 #ifdef _TMS320C6X
54 OSAL_REGINT_INTVEC_EVENT_COMBINER, /* default DSP Interrupt vector number, can be set in UART_socSetInitCfg() API */
55 38, /* default DSP INTC UART Event ID, can be set in UART_socSetInitCfg() API */
56 UART_INVALID_INTC_MUX_NUM, /* CIC number */
57 #else
58 25, /* UART int number for ARM GIC INTC */
59 0, /* Event ID not used for ARM INTC */
60 UART_INVALID_INTC_MUX_NUM, /* CIC num not used in ARM GIC */
61 #endif
62 CSL_INTC_EVENTID_UARTINT2, /* CIC UART Event ID */
63 0, /* default CIC Host Interrupt, map to CIC_0_OUT32 event */
64 CSL_EDMA3_CHA_UART0_RX,
65 CSL_EDMA3_CHA_UART0_TX,
66 CSL_EDMA3_CHA_UART0_TX,
67 CSL_EDMA3_CHA_UART0_RX,
68 0,
69 0,
70 300000000/2, /* default UART frequency, system clock/6 */
71 0, /* version */
72 NULL,
73 TRUE, /* dmaMode */
74 FALSE, /* loopback */
75 TRUE, /* enableInterrupt */
76 UART_RXTRIGLVL_1, /* rxTrigLvl */
77 1, /* txTrigLvl */
78 UART16x_OPER_MODE, /* operMode, 16x over sampling mode by default */
79 },
80 {
81 CSL_UART_1_REGS,
82 #ifdef _TMS320C6X
83 OSAL_REGINT_INTVEC_EVENT_COMBINER,
84 46,
85 UART_INVALID_INTC_MUX_NUM,
86 #else
87 53,
88 0,
89 UART_INVALID_INTC_MUX_NUM, /* CIC num not used in ARM GIC */
90 #endif
91 CSL_INTC_EVENTID_UARTINT2,
92 0,
93 CSL_EDMA3_CHA_UART1_RX,
94 CSL_EDMA3_CHA_UART1_TX,
95 CSL_EDMA3_CHA_UART1_TX,
96 CSL_EDMA3_CHA_UART1_RX,
97 0,
98 0,
99 300000000/2,
100 0,
101 NULL,
102 TRUE,
103 FALSE,
104 TRUE,
105 UART_RXTRIGLVL_1,
106 1,
107 UART16x_OPER_MODE,
108 },
109 {
110 CSL_UART_2_REGS,
111 #ifdef _TMS320C6X
112 OSAL_REGINT_INTVEC_EVENT_COMBINER,
113 69,
114 UART_INVALID_INTC_MUX_NUM,
115 #else
116 0x3D,
117 16,
118 UART_INVALID_INTC_MUX_NUM, /* CIC num not used in ARM GIC */
119 #endif
120 CSL_INTC_EVENTID_UARTINT2,
121 0,
122 CSL_EDMA3_CHA_UART2_RX,
123 CSL_EDMA3_CHA_UART2_TX,
124 CSL_EDMA3_CHA_UART2_TX,
125 CSL_EDMA3_CHA_UART2_RX,
126 0,
127 1,
128 300000000/2,
129 0,
130 NULL,
131 TRUE,
132 FALSE,
133 TRUE,
134 UART_RXTRIGLVL_1,
135 1,
136 UART16x_OPER_MODE,
137 },
138 };
140 /* UART objects */
141 UART_V0_Object UartObjects[CSL_UART_CNT];
143 /* UART configuration structure */
144 CSL_PUBLIC_CONST UART_Config UART_config[CSL_UART_CNT + 1U] =
145 {
146 {
147 &UART_FxnTable_v0,
148 &UartObjects[0],
149 &uartInitCfg[0]
150 },
152 {
153 &UART_FxnTable_v0,
154 &UartObjects[1],
155 &uartInitCfg[1]
156 },
158 {
159 &UART_FxnTable_v0,
160 &UartObjects[2],
161 &uartInitCfg[2]
162 },
164 {
165 NULL,
166 NULL,
167 NULL
168 }
169 };
171 /**
172 * \brief This API gets the SoC level of UART intial configuration
173 *
174 * \param index UART instance index.
175 * \param cfg Pointer to UART SOC initial config.
176 *
177 * \return 0 success: -1: error
178 *
179 */
180 int32_t UART_socGetInitCfg(uint32_t index, UART_HwAttrs *cfg)
181 {
182 int32_t ret = 0;
184 if (index < CSL_UART_CNT)
185 {
186 *cfg = uartInitCfg[index];
187 }
188 else
189 {
190 ret = -1;
191 }
193 return ret;
194 }
196 /**
197 * \brief This API sets the SoC level of UART intial configuration
198 *
199 * \param index UART instance index.
200 * \param cfg Pointer to UART SOC initial config.
201 *
202 * \return 0 success: -1: error
203 *
204 */
205 int32_t UART_socSetInitCfg(uint32_t index, const UART_HwAttrs *cfg)
206 {
207 int32_t ret = 0;
209 if (index < CSL_UART_CNT)
210 {
211 uartInitCfg[index] = *cfg;
212 }
213 else
214 {
215 ret = -1;
216 }
218 return ret;
219 }
221 #ifdef UART_DMA_ENABLE
222 /**
223 * \brief This API gets the SoC specific EDMA3 info
224 *
225 * \param index UART instance index.
226 * \param edma3Id pointer to EDMA3CC #.
227 * \param edma3Event pointer to EDMA3 event array.
228 *
229 * \return none
230 *
231 */
232 void UART_getEdmaInfo(uint32_t index, uint32_t *edma3Id, uint32_t *edma3Event)
233 {
234 const uint32_t edma3id[CSL_UART_CNT] = {0, 0, 0};
235 const uint32_t edma3RxEvent[CSL_UART_CNT] =
236 {
237 CSL_EDMA3_CHA_UART0_RX,
238 CSL_EDMA3_CHA_UART1_RX,
239 CSL_EDMA3_CHA_UART2_RX
240 };
241 const uint32_t edma3TxEvent[CSL_UART_CNT] =
242 {
243 CSL_EDMA3_CHA_UART0_TX,
244 CSL_EDMA3_CHA_UART1_TX,
245 CSL_EDMA3_CHA_UART2_TX
246 };
248 *edma3Id = edma3id[index];
249 edma3Event[0] = edma3RxEvent[index];
250 edma3Event[1] = edma3TxEvent[index];
251 }
252 #endif