1 /*
2 * Copyright (c) 2014-2019, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /** ============================================================================
33 * @file UART_v1.h
34 *
35 * @brief UART DMA and non-DMA driver implementation for IP V1 UART controller
36 *
37 *
38 * ============================================================================
39 */
41 #ifndef ti_drivers_uart_UARTv1__include
42 #define ti_drivers_uart_UARTv1__include
44 #include <stdbool.h>
45 #include <ti/drv/uart/UART.h>
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
53 /* UART function table pointer */
54 extern const UART_FxnTable UART_FxnTable_v1;
56 /*!
57 * @brief Function to set interrupt path
58 *
59 * This function will configure the interrupt path to the destination CPU
60 * using DMSC firmware via sciclient. if setIntrPath is set to TRUE,
61 * a path is set, else the interrupt path is released
62 */
63 typedef int32_t (*UART_socCfgIntrPathFxn)(const void *pHwAttrs, bool setIntrPath);
66 /*!
67 * @brief UART_V1 Object
68 *
69 * The application must not access any member variables of this structure!
70 */
71 typedef struct UART_V1_Object_s
72 {
73 /* UART control variables */
74 UART_Params params; /* Configured UART parameters */
76 /* UART SYS/BIOS objects */
77 void* hwi; /* Hwi object */
78 void* writeSem; /* UART write semaphore*/
79 void* readSem; /* UART read semaphore */
80 /* UART write variables */
81 const void *writeBuf; /* Buffer data pointer */
82 size_t writeCount; /* Number of Chars sent */
83 size_t writeSize; /* Chars remaining in buffer */
84 uint32_t writeCR; /* Write a return character */
86 /* UART receive variables */
87 void *readBuf; /* Buffer data pointer */
88 size_t readCount; /* Number of Chars read */
89 size_t readSize; /* Chars remaining in buffer */
91 uint32_t isOpen; /* flag to indicate module is open */
93 uint32_t edmaLinkChPhyAddr;
94 uint32_t edmaLinkChId;
95 uint32_t txTcc;
96 uint32_t rxTcc;
97 UART_Transaction *readTrans; /* Pointer to the current read transaction */
98 UART_Transaction *writeTrans; /* Pointer to the current write transaction */
99 uint32_t rxTimeoutCnt; /* Receive timeout error count */
100 uint32_t txDataSent; /* flag to indicate all the data are
101 written to the TX FIFO */
103 uint32_t readDmaSize; /* read operation DMA size in bytes */
105 UART_Transaction rdTrans; /* read transaction data used for old read API */
106 UART_Transaction wrTrans; /* write transaction data used for old write API */
108 }UART_V1_Object, *UART_V1_Handle;
110 /**
111 *
112 * \brief UART Rx Trigger Level Param
113 * IMP: The enum values should not be changed since it represents the
114 * actual register configuration values used to configure the UART in
115 * this SoC by the UART driver
116 */
117 typedef enum
118 {
119 UART_RXTRIGLVL_8 = 8,
120 /**< Trigger Level 8 */
121 UART_RXTRIGLVL_16 = 16,
122 /**< Trigger Level 16 */
123 UART_RXTRIGLVL_56 = 56,
124 /**< Trigger Level 56 */
125 UART_RXTRIGLVL_60 = 60
126 /**< Trigger Level 60 */
127 } UART_RxTrigLvl;
129 /**
130 *
131 * \brief UART Tx Trigger Level Param
132 * IMP: The enum values should not be changed since it represents the
133 * actual register configuration values used to configure the UART in
134 * this SoC by the UART driver
135 */
136 typedef enum
137 {
138 UART_TXTRIGLVL_8 = 8,
139 /**< Trigger Level 8 */
140 UART_TXTRIGLVL_16 = 16,
141 /**< Trigger Level 16 */
142 UART_TXTRIGLVL_32 = 32,
143 /**< Trigger Level 32 */
144 UART_TXTRIGLVL_56 = 56
145 /**< Trigger Level 56 */
146 } UART_TxTrigLvl;
148 /*!
149 * @brief UART UDMA info structure
150 */
151 typedef struct UART_dmaInfo_s {
152 /*! UDMA TX channel handle */
153 void *txChHandle;
154 /*! UDMA RX channel handle */
155 void *rxChHandle;
156 /*! UDMA TX ring memory pointers */
157 void *txRingMem;
158 /*! UDMA TX completion queue ring memory pointer */
159 void *cqTxRingMem;
160 /*! UDMA TX tear down completion queue ring memory pointer */
161 void *tdCqTxRingMem;
162 /*! UDMA RX ring memory pointers */
163 void *rxRingMem;
164 /*! UDMA RX completion queue ring memory pointer */
165 void *cqRxRingMem;
166 /*! UDMA RX tear down completion queue ring memory pointer */
167 void *tdCqRxRingMem;
168 /*! UDMA TX PD memory pointers */
169 void *txHpdMem;
170 /*! UDMA RX PD memory pointers */
171 void *rxHpdMem;
172 /*! UDMA TX event handle */
173 void *txEventHandle;
174 /*! UDMA RX event handles */
175 void *rxEventHandle;
177 } UART_dmaInfo;
179 typedef struct UART_HWAttrs {
180 /*UART Peripheral's base address */
181 uint32_t baseAddr;
182 /*UART Interrupt number */
183 uint32_t intNum;
184 /*UART EventID */
185 uint32_t eventId;
186 /*UART Input frequency */
187 uint32_t frequency;
189 /*EDMA related Hardware configuration details*/
190 uint32_t rxDmaEventNumber;
191 /**< edma3: EDMA event number of Receiver, udma: RX PDMA thread # */
192 uint32_t txDmaEventNumber;
193 /**< edma3: EDMA event number of Transmitter, udma: TX PDMA thread # */
194 uint32_t edmaTxTCC;
195 /**< EDMA Transfer Controller No.of TX channel*/
196 uint32_t edmaRxTCC;
197 /**< EDMA Transfer Controller No.of Rx channel*/
198 uint32_t edmaTxTC;
199 /**< EDMA Transfer Controller No.of TX channel*/
200 uint32_t edmaRxTC;
201 /**< EDMA Transfer Controller No.of Rx channel*/
202 uint32_t version;
203 void* edmaHandle;
204 /**< edma3: EDMA handle, udma: udma driver handle */
205 UART_RxTrigLvl rxTrigLvl;
206 /**< refer #UART_RxTrigLvl for valid values */
207 UART_TxTrigLvl txTrigLvl;
208 /**< refer #UART_TxTrigLvl for valid values */
209 uint32_t dmaMode;
210 /**< flag to indicate in DMA mode */
211 uint32_t loopback;
212 /**< flag to indicate in loopback mode */
214 /**< flag to enable interrupt */
215 uint32_t enableInterrupt;
217 /**< UART operation mode */
218 uint32_t operMode;
220 /*! UDMA configuration info */
221 UART_dmaInfo *dmaInfo;
223 /*! Function pointer to set interrupt router path */
224 UART_socCfgIntrPathFxn configSocIntrPath;
226 } UART_HwAttrs;
228 extern void UART_v1_callback(UART_Handle uartHnd, bool readTrans);
230 #ifdef UART_DMA_ENABLE
231 extern void UART_receiveDMA(UART_Handle handle, const void *buffer, size_t size);
232 extern void UART_transmitDMA(UART_Handle handle, const void *buffer, size_t size);
233 extern int32_t UART_configDMA(UART_Handle handle);
234 extern void UART_disableDmaChannel(UART_Handle handle, bool txCha);
235 extern void UART_freeDmaChannel(UART_Handle handle);
236 #endif
238 #ifdef __cplusplus
239 }
240 #endif
242 #endif /* ti_drivers_uart_UARTv1__include */