1 /*
2 * Copyright (c) Texas Instruments Incorporated 2018
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /**
34 * \ingroup DRV_UDMA_MODULE
35 * \defgroup DRV_UDMA_CH_MODULE UDMA Driver Channel API
36 * This is UDMA driver channel related configuration parameters and
37 * API
38 *
39 * @{
40 */
42 /**
43 * \file udma_ch.h
44 *
45 * \brief UDMA Channel related parameters and API.
46 */
48 #ifndef UDMA_CH_H_
49 #define UDMA_CH_H_
51 /* ========================================================================== */
52 /* Include Files */
53 /* ========================================================================== */
55 /* None */
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
61 /* ========================================================================== */
62 /* Macros & Typedefs */
63 /* ========================================================================== */
65 /**
66 * \brief Macro used to specify that DMA Channel ID is invalid.
67 * Used in the API #Udma_chOpen.
68 */
69 #define UDMA_DMA_CH_INVALID ((uint32_t) 0xFFFF0000U)
70 /**
71 * \brief Macro used to specify any available DMA Channel while requesting
72 * one. Used in the API #Udma_chOpen.
73 */
74 #define UDMA_DMA_CH_ANY ((uint32_t) 0xFFFF0001U)
75 /**
76 * \brief Macro used to specify that the DMA Channel is not applicable for a
77 * particular mode.
78 */
79 #define UDMA_DMA_CH_NA ((uint32_t) 0xFFFF0002U)
80 /** \brief Macro used to specify that the UTC ID is invalid. */
81 #define UDMA_UTC_ID_INVALID ((uint32_t) 0xFFFF0003U)
82 /** \brief Macro used to specify that the Mapped Channel Group is invalid. */
83 #define UDMA_MAPPED_GROUP_INVALID ((uint32_t) 0xFFFF0004U)
85 /**
86 * \anchor Udma_ChFlag
87 * \name UDMA Channel Flag
88 *
89 * UDMA channel flags bit field used to form the channel type.
90 *
91 * @{
92 */
93 /** \brief TX channel flag */
94 #define UDMA_CH_FLAG_TX ((uint32_t) 0x0001U)
95 /** \brief RX channel flag */
96 #define UDMA_CH_FLAG_RX ((uint32_t) 0x0002U)
97 /** \brief Block copy mode channel flag */
98 #define UDMA_CH_FLAG_BLK_COPY ((uint32_t) 0x0004U)
99 /** \brief PDMA channel flag */
100 #define UDMA_CH_FLAG_PDMA ((uint32_t) 0x0008U)
101 /** \brief PSIL channel flag meant for periperals like Ethernet, SA2UL */
102 #define UDMA_CH_FLAG_PSIL ((uint32_t) 0x0010U)
103 /** \brief UTC channel flag */
104 #define UDMA_CH_FLAG_UTC ((uint32_t) 0x0020U)
105 /** \brief High capacity channel flag */
106 #define UDMA_CH_FLAG_HC ((uint32_t) 0x0040U)
107 /** \brief Ultra high capacity channel flag */
108 #define UDMA_CH_FLAG_UHC ((uint32_t) 0x0080U)
109 /** \brief Mapped TX/RX channel flag */
110 #define UDMA_CH_FLAG_MAPPED ((uint32_t) 0x0100U)
111 /* @} */
113 /**
114 * \anchor Udma_ChType
115 * \name UDMA Channel Type
116 *
117 * UDMA channel type formed based on channel flags.
118 *
119 * @{
120 */
121 /** \brief TR block copy type - TX/RX pair */
122 #define UDMA_CH_TYPE_TR_BLK_COPY (UDMA_CH_FLAG_BLK_COPY | \
123 UDMA_CH_FLAG_TX | \
124 UDMA_CH_FLAG_RX)
125 /** \brief High capacity TR block copy type - TX/RX pair */
126 #define UDMA_CH_TYPE_TR_BLK_COPY_HC (UDMA_CH_FLAG_BLK_COPY | \
127 UDMA_CH_FLAG_TX | \
128 UDMA_CH_FLAG_RX | \
129 UDMA_CH_FLAG_HC)
130 /** \brief Ultra high capacity TR block copy type - TX/RX pair */
131 #define UDMA_CH_TYPE_TR_BLK_COPY_UHC (UDMA_CH_FLAG_BLK_COPY | \
132 UDMA_CH_FLAG_TX | \
133 UDMA_CH_FLAG_RX | \
134 UDMA_CH_FLAG_UHC)
135 /** \brief TX channel type */
136 #define UDMA_CH_TYPE_TX (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL)
137 /** \brief High capacity TX channel type */
138 #define UDMA_CH_TYPE_TX_HC (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_HC)
139 /** \brief Ultra high capacity TX channel type */
140 #define UDMA_CH_TYPE_TX_UHC (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_UHC)
142 /** \brief RX channel type */
143 #define UDMA_CH_TYPE_RX (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL)
144 /** \brief High capacity RX channel type */
145 #define UDMA_CH_TYPE_RX_HC (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_HC)
146 /** \brief Ultra high capacity RX channel type */
147 #define UDMA_CH_TYPE_RX_UHC (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_UHC)
149 /** \brief PDMA TX channel type */
150 #define UDMA_CH_TYPE_PDMA_TX (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PDMA)
151 /** \brief High capacity PDMA TX channel type */
152 #define UDMA_CH_TYPE_PDMA_TX_HC (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_HC)
153 /** \brief Ultra high capacity PDMA TX channel type */
154 #define UDMA_CH_TYPE_PDMA_TX_UHC (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_UHC)
156 /** \brief PDMA RX channel type */
157 #define UDMA_CH_TYPE_PDMA_RX (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PDMA)
158 /** \brief High capacity PDMA RX channel type */
159 #define UDMA_CH_TYPE_PDMA_RX_HC (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_HC)
160 /** \brief Ultra high capacity PDMA RX channel type */
161 #define UDMA_CH_TYPE_PDMA_RX_UHC (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_UHC)
163 /**
164 * \brief Mapped TX channel.
165 * This could be different type of mapped TX channels.
166 * See \ref Udma_MappedTxGrpSoc for differnt types of SOC specific mapped TX channels.
167 */
168 #define UDMA_CH_TYPE_TX_MAPPED (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_MAPPED)
169 /**
170 * \brief Mapped RX channel.
171 * This could be different type of mapped RX channels.
172 * See \ref Udma_MappedRxGrpSoc for differnt types of SOC specific mapped RX channels.
173 */
174 #define UDMA_CH_TYPE_RX_MAPPED (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_MAPPED)
176 /**
177 * \brief UTC channel. This could be
178 * - UTC with descriptor posted through UDMA external channel like VPAC/DMPAC
179 * - DRU channel with direct mode with descriptor posted through direct
180 * DRU register writes or with indirect mode through External channel
181 */
182 #define UDMA_CH_TYPE_UTC (UDMA_CH_FLAG_UTC)
183 /* @} */
185 /**
186 * \anchor Udma_PdmaElemSize
187 * \name UDMA PDMA element size
188 *
189 * @{
190 */
191 /** \brief 8-bits Element size */
192 #define UDMA_PDMA_ES_8BITS ((uint32_t) 0x00U)
193 /** \brief 16-bits Element size */
194 #define UDMA_PDMA_ES_16BITS ((uint32_t) 0x01U)
195 /** \brief 24-bits Element size */
196 #define UDMA_PDMA_ES_24BITS ((uint32_t) 0x02U)
197 /** \brief 32-bits Element size */
198 #define UDMA_PDMA_ES_32BITS ((uint32_t) 0x03U)
199 /** \brief 64-bits Element size */
200 #define UDMA_PDMA_ES_64BITS ((uint32_t) 0x04U)
201 /** \brief Set this for MCAN element size - not applicable */
202 #define UDMA_PDMA_ES_DONTCARE ((uint32_t) 0x00U)
203 /* @} */
205 /* ========================================================================== */
206 /* Structure Declarations */
207 /* ========================================================================== */
209 /**
210 * \brief UDMA channel open parameters.
211 */
212 typedef struct
213 {
214 uint32_t chNum;
215 /**< [IN] UDMAP channel to allocate.
216 *
217 * Set to #UDMA_DMA_CH_ANY if the channel to allocate and open
218 * could be any from the free pool.
219 * Set to the actual DMA channel when specific DMA channel need to be
220 * allocated. This channel number is relative to the channel type
221 * (TX, RX or External). The driver will internally calculate the
222 * respective offset to get the actual UDMAP channel number.
223 */
224 uint32_t peerChNum;
225 /**< [IN] The peer channel to link the #chNum using PSILCFG.
226 *
227 * Incase of PDMA peripherals this represent the PDMA channel to which the
228 * UDMA channel should pair with. Refer \ref Udma_PdmaCh macros.
229 *
230 * Incase of other PSIL master peripherals this represent the thread ID
231 * to which the UDMA channel should pair with. Refer \ref Udma_PsilCh macros.
232 *
233 * Incase of Block copy channel type (#UDMA_CH_TYPE_TR_BLK_COPY), set
234 * this to #UDMA_DMA_CH_NA, as the corresponding RX channel (same
235 * index as TX channel) is assumed to be paired with and the driver
236 * internally sets this up. The #UdmaChPrms_init API takes care of
237 * this.
238 *
239 * Incase of UTC channel type (#UDMA_CH_TYPE_UTC), set this to
240 * #UDMA_DMA_CH_NA.
241 */
242 uint32_t utcId;
243 /**< [IN] The UTC instance to use when channel type is #UDMA_CH_TYPE_UTC.
244 * Refer \ref Udma_UtcIdSoc macro for details.
245 *
246 * For other channel type set to #UDMA_UTC_ID_INVALID
247 */
248 uint32_t mappedChGrp;
249 /**< [IN] The Mapped channel group to use when channel type is
250 * #UDMA_CH_TYPE_TX_MAPPED or #UDMA_CH_TYPE_RX_MAPPED.
251 * Refer \ref Udma_MappedTxGrpSoc macro for details about mapped TX channel groups
252 * or \ref Udma_MappedRxGrpSoc macro for details about mapped RX channel groups.
253 *
254 * For other channel type set to #UDMA_MAPPED_GROUP_INVALID
255 */
256 void *appData;
257 /**< [IN] Application/caller context pointer passed back in all the channel
258 * callback functions. This could be used by the caller to identify
259 * the channel for which the callback is called.
260 * This can be set to NULL, if not required by caller. */
261 Udma_RingPrms fqRingPrms;
262 /**< [IN] Free queue ring params where descriptors are queued */
263 Udma_RingPrms cqRingPrms;
264 /**< [IN] Completion queue ring params where descriptors are dequeued
265 * This is not used for AM64x kind of devices, but even if the application
266 * sets this it will be ignored. But its not required to be set.
267 */
268 Udma_RingPrms tdCqRingPrms;
269 /**< [IN] Teardown completion queue ring params where teardown
270 * response and TR response incase of direct TR mode are received from
271 * UDMA
272 * This is not used for AM64x kind of devices, but even if the application
273 * sets this it will be ignored. But its not required to be set.
274 */
275 } Udma_ChPrms;
277 /**
278 * \brief UDMA TX channel parameters.
279 */
280 typedef struct
281 {
282 uint8_t pauseOnError;
283 /**< [IN] Bool: When set (TRUE), pause channel on error */
284 uint8_t filterEinfo;
285 /**< [IN] Bool: When set (TRUE), filter out extended info */
286 uint8_t filterPsWords;
287 /**< [IN] Bool: When set (TRUE), filter out protocl specific words */
288 uint8_t addrType;
289 /**< [IN] Address type for this channel.
290 * Refer \ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_atype */
291 uint8_t chanType;
292 /**< [IN] Channel type. Refer \ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_chan_type */
293 uint16_t fetchWordSize;
294 /**< [IN] Descriptor/TR Size in 32-bit words */
295 uint8_t busPriority;
296 /**< [IN] 3-bit priority value (0=highest, 7=lowest) */
297 uint8_t busQos;
298 /**< [IN] 3-bit qos value (0=highest, 7=lowest) */
299 uint8_t busOrderId;
300 /**< [IN] 4-bit orderid value */
301 uint8_t dmaPriority;
302 /**< [IN] This field selects which scheduling bin the channel will be
303 * placed in for bandwidth allocation of the Tx DMA units.
304 * Refer \ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_sched_priority */
305 uint8_t txCredit;
306 /**< [IN] TX credit for external channels */
307 uint16_t fifoDepth;
308 /**< [IN] The fifo depth is used to specify how many FIFO data phases
309 * deep the Tx per channel FIFO will be for the channel.
310 * While the maximum depth of the Tx FIFO is set at design time,
311 * the FIFO depth can be artificially reduced in order to control the
312 * maximum latency which can be introduced due to buffering effects.
313 *
314 * The maximum FIFO depth suppported depends on the channel type as
315 * given below:
316 * Normal Capacity Channel - CSL_NAVSS_UDMAP_TX_CHANS_FDEPTH (128 bytes)
317 * High Capacity Channel - CSL_NAVSS_UDMAP_TX_HC_CHANS_FDEPTH (1024 bytes)
318 * Ultra High Capacity Channel - CSL_NAVSS_UDMAP_TX_UHC_CHANS_FDEPTH (4096 bytes)
319 *
320 * The default init API will set this paramater as per the channel type.
321 */
322 uint8_t burstSize;
323 /**< [IN] Specifies the nominal burst size and alignment for data transfers
324 * on this channel.
325 * Refer \ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_burst_size.
326 * Note1: This parameter should be set less than or equal to the FIFO
327 * depth parameter set for UTC channel i.e.
328 * fifoDepth >= burstSize
329 * Note2: In case of packet mode TX channels, the Tx fifoDepth must be at
330 * least 2 PSI-L data phases (32 bytes) larger than the burst size given
331 * in this field in order to hold the packet info and extended packet info
332 * header which is placed at the front of the data packet in addition
333 * to the payload i.e.
334 * fifoDepth >= (burstSize + 32 bytes)
335 *
336 * Below are the supported burst sizes for various channel types
337 * Normal Capacity Channel - 64 bytes
338 * High Capacity Channel - 64, 128 or 256 bytes
339 * Ultra High Capacity Channel - 64, 128 or 256 bytes
340 */
341 uint8_t supressTdCqPkt;
342 /**< [IN] Bool: Specifies whether or not the channel should suppress
343 * sending the single data phase teardown packet when teardown is
344 * complete.
345 * FALSE = TD packet is sent
346 * TRUE = Suppress sending TD packet
347 * TODO: Should we allocate tdCq based on this flag?
348 */
349 } Udma_ChTxPrms;
351 /**
352 * \brief UDMA RX channel parameters.
353 */
354 typedef struct
355 {
356 uint8_t pauseOnError;
357 /**< [IN] Bool: When set (TRUE), pause channel on error */
358 uint8_t addrType;
359 /**< [IN] Address type for this channel.
360 * Refer \ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_atype */
361 uint8_t chanType;
362 /**< [IN] Channel type. Refer \ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type */
363 uint16_t fetchWordSize;
364 /**< [IN] Descriptor/TR Size in 32-bit words */
365 uint8_t busPriority;
366 /**< [IN] 3-bit priority value (0=highest, 7=lowest) */
367 uint8_t busQos;
368 /**< [IN] 3-bit qos value (0=highest, 7=lowest) */
369 uint8_t busOrderId;
370 /**< [IN] 4-bit orderid value */
371 uint8_t dmaPriority;
372 /**< [IN] This field selects which scheduling bin the channel will be
373 * placed in for bandwidth allocation of the Tx DMA units.
374 * Refer \ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority */
375 uint16_t flowIdFwRangeStart;
376 /**< [IN] Starting flow ID value for firewall check */
377 uint16_t flowIdFwRangeCnt;
378 /**< [IN] Number of valid flow ID's starting from flowIdFwRangeStart
379 * for firewall check */
380 uint8_t ignoreShortPkts;
381 /**< [IN] Bool: This field controls whether or not short packets will be
382 * treated as exceptions (FALSE) or ignored (TRUE) for the channel.
383 * This field is only used when the channel is in split UTC mode. */
384 uint8_t ignoreLongPkts;
385 /**< [IN] Bool: This field controls whether or not long packets will be
386 * treated as exceptions (FALSE) or ignored (TRUE) for the channel.
387 * This field is only used when the channel is in split UTC mode. */
388 uint32_t configDefaultFlow;
389 /**< [IN] Bool: This field controls whether or not to program the default
390 * flow.
391 * TRUE - Configures the default flow equal to the RX channel number
392 * FALSE - Doesn't configure the default flow of channel.
393 * The caller can allocate and use other generic flows or get the
394 * default flow handle and configure the flow using #Udma_flowConfig
395 * API at a later point of time */
396 uint8_t burstSize;
397 /**< [IN] Specifies the nominal burst size and alignment for data transfers
398 * on this channel.
399 * Refer \ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size.
400 * Note1: This parameter should be set less than or equal to the FIFO
401 * depth parameter set for UTC channel i.e.
402 * fifoDepth >= burstSize
403 * Note2: In case of packet mode TX channels, the Tx fifoDepth must be at
404 * least 2 PSI-L data phases (32 bytes) larger than the burst size given
405 * in this field in order to hold the packet info and extended packet info
406 * header which is placed at the front of the data packet in addition
407 * to the payload i.e.
408 * fifoDepth >= (burstSize + 32 bytes)
409 *
410 * Below are the supported burst sizes for various channel types
411 * Normal Capacity Channel - 64 bytes
412 * High Capacity Channel - 64, 128 or 256 bytes
413 * Ultra High Capacity Channel - 64, 128 or 256 bytes
414 */
415 } Udma_ChRxPrms;
417 /**
418 * \brief UDMA UTC channel parameters.
419 */
420 typedef struct
421 {
422 uint8_t pauseOnError;
423 /**< [IN] Bool: When set (TRUE), pause channel on error */
424 uint8_t addrType;
425 /**< [IN] Address type for this channel.
426 * Refer \ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_atype */
427 uint8_t chanType;
428 /**< [IN] Channel type. Refer \ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_chan_type */
429 uint16_t fetchWordSize;
430 /**< [IN] Descriptor/TR Size in 32-bit words */
431 uint8_t busPriority;
432 /**< [IN] 3-bit priority value (0=highest, 7=lowest) */
433 uint8_t busQos;
434 /**< [IN] 3-bit qos value (0=highest, 7=lowest) */
435 uint8_t busOrderId;
436 /**< [IN] 4-bit orderid value */
437 uint8_t dmaPriority;
438 /**< [IN] This field selects which scheduling bin the channel will be
439 * placed in for bandwidth allocation of the Tx DMA units.
440 * Refer \ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_sched_priority */
441 uint8_t burstSize;
442 /**< [IN] Specifies the nominal burst size and alignment for data transfers
443 * on this channel.
444 * Refer \ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_burst_size.
445 * Note1: This parameter should be set less than or equal to the FIFO
446 * depth parameter set i.e.
447 * fifoDepth >= burstSize
448 *
449 * Below are the supported burst sizes for various channel types
450 * Normal Capacity Channel - 64 or 128 bytes
451 * High Capacity Channel - 64, 128 or 256 bytes
452 * Ultra High Capacity Channel - 64, 128 or 256 bytes
453 */
454 uint8_t supressTdCqPkt;
455 /**< [IN] Bool: Specifies whether or not the channel should suppress
456 * sending the single data phase teardown packet when teardown is
457 * complete.
458 * FALSE = TD packet is sent
459 * TRUE = Suppress sending TD packet
460 * TODO: Should we allocate tdCq based on this flag?
461 */
462 #if (UDMA_NUM_UTC_INSTANCE > 0)
463 /* Below fields are applicable only for DRU UTC */
464 uint64_t druOwner;
465 /**< [IN] This field controls how the TR is received by the DRU.
466 * Refer \ref CSL_DruOwner. This only applicable for DRU UTC type
467 * Note: This mode once set cannot be changed after a channel is enabled.
468 * One can't switch the submission mode dynamically when the channel is
469 * enabled. It can changed only after a successful teardown/disable
470 * sequence.
471 */
472 uint32_t druQueueId;
473 /**< [IN] Channel scheduling queue to be used. Refer \ref CSL_DruQueueId.
474 * This only applicable for DRU UTC type
475 * All the DRUs only have 5 queues implemented in the current design.
476 * 1 Priority queue and 4 round robin queues.
477 * The priority queue is queue 0 the round robin
478 * queues are queues 1 - 4.
479 */
480 #endif
481 } Udma_ChUtcPrms;
483 /**
484 * \brief UDMA PDMA channel Static TR parameters.
485 */
486 typedef struct
487 {
488 uint32_t elemSize;
489 /**< [IN] Element size. This field specifies how much data is transferred
490 * in each write which is performed by the PDMA.
491 * This is the X static TR parameter of PDMA.
492 *
493 * In case of MCAN TX/RX PDMA channel, this is not used and should be
494 * set to 0.
495 *
496 * Refer \ref Udma_PdmaElemSize for supported values. */
497 uint32_t elemCnt;
498 /**< [IN] Element count. This field specifies how many elements to
499 * transfer each time a trigger is received on the PDMA channel.
500 * This is the Y static TR parameter of PDMA.
501 *
502 * In case of MCAN PDMA channel, this represents the buffer size.
503 * In case of MCAN TX, this field specifies how many bytes should be
504 * written to an MCAN TX buffer. This field includes the 8 byte MCAN
505 * header on the initial packet fragment. The PDMA will break up the
506 * source packet into fragments of this buffer size, copying the 8 byte
507 * MCAN header for the initial fragment, and then skipping it for each
508 * additional fragment and thus reusing the header from the first
509 * fragment. A buffer size less than 16 is treated as 16, and a buffer
510 * size greater than 72 is treated as 72.
511 * In case of MCAN RX, this field specifies how many bytes should be
512 * read from an MCAN RX buffer. This field includes the 8 byte MCAN
513 * header on the initial packet fragment. A buffer size less than 16
514 * is treated as 16, and a buffer size greater than 72 is treated as 72.
515 */
516 uint32_t fifoCnt;
517 /**< [IN] FIFO count. This field specifies how many full FIFO operations
518 * comprise a complete packet. When the count has been reached, the
519 * PDMA will close the packet with an 'EOP' indication. If this parameter
520 * is set to 0, then no packet delineation is supplied by the PDMA and
521 * all framing is controlled via the UDMA TR.
522 *
523 * This is the Z static TR parameter of PDMA.
524 * This is NA for TX and should be set to 0.
525 * In case of MCAN RX, this represents the buffer count. This field
526 * specifies how many MCAN RX buffers should be read before closing the
527 * CPPI packet with an 'EOP' indication. When this count is greater
528 * than 1, multiple MCAN RX buffers will be read into a single CPPI
529 * packet buffer. The 8 byte MCAN header will be skipped on subsequent
530 * MCAN buffer reads. Setting this field to NULL will suppress all
531 * packet delineation, and should be avoided.
532 */
533 } Udma_ChPdmaPrms;
535 /**
536 * \brief UDMA channel statistics.
537 */
538 typedef struct
539 {
540 uint32_t packetCnt;
541 /**< [OUT] Current completed packet count for the channel */
542 uint32_t completedByteCnt;
543 /**< [OUT] Current completed payload byte count for the channel */
544 uint32_t startedByteCnt;
545 /**< [OUT] Current started byte count for the channel */
546 } Udma_ChStats;
548 /* ========================================================================== */
549 /* Function Declarations */
550 /* ========================================================================== */
552 /**
553 * \brief UDMA open channel.
554 *
555 * Opens the UDMA channel based on the channel parameters. This also does
556 * the PSILCFG pairing based on the peer thread ID provided.
557 *
558 * Requirement: DOX_REQ_TAG(PDK-2578)
559 *
560 * \param drvHandle [IN] UDMA driver handle pointer passed during
561 * #Udma_init
562 * \param chHandle [IN/OUT] UDMA channel handle. The caller need to
563 * allocate memory for this object and pass this
564 * pointer to all further APIs. The caller should
565 * not change any parameters as this is owned and
566 * maintained by the driver.
567 * This parameter can't be NULL.
568 * \param chType [IN] UDMA channel type. Refer \ref Udma_ChType.
569 * \param chPrms [IN] UDMA channel parameters.
570 * This parameter can't be NULL.
571 *
572 * \return \ref Udma_ErrorCodes
573 */
574 int32_t Udma_chOpen(Udma_DrvHandle drvHandle,
575 Udma_ChHandle chHandle,
576 uint32_t chType,
577 const Udma_ChPrms *chPrms);
579 /**
580 * \brief UDMA close channel.
581 *
582 * Closes the UDMA channel and frees all associated resources.
583 *
584 * Requirement: DOX_REQ_TAG(PDK-2579)
585 *
586 * \param chHandle [IN] UDMA channel handle.
587 * This parameter can't be NULL.
588 *
589 * \return \ref Udma_ErrorCodes
590 */
591 int32_t Udma_chClose(Udma_ChHandle chHandle);
593 /**
594 * \brief UDMA configure TX channel.
595 *
596 * Configures the TX channel parameters. Note: This is applicable only
597 * when the channel type is TX
598 *
599 * Note: This API can't be called after channel enable.
600 *
601 * Requirement: DOX_REQ_TAG(PDK-2580)
602 *
603 * \param chHandle [IN] UDMA channel handle.
604 * This parameter can't be NULL.
605 * \param txPrms [IN] UDMA TX channel parameter.
606 * Refer #Udma_ChTxPrms.
607 *
608 * \return \ref Udma_ErrorCodes
609 */
610 int32_t Udma_chConfigTx(Udma_ChHandle chHandle, const Udma_ChTxPrms *txPrms);
612 /**
613 * \brief UDMA configure RX channel.
614 *
615 * Configures the RX channel parameters. Note: This is applicable only
616 * when the channel type is RX
617 * In case of BCDMA Block Copy, there is no need to configure RX Channel.
618 * Therfore the function returns gracefully, without doing anything.
619 *
620 * Note: This API can't be called after channel enable.
621 *
622 * Requirement: DOX_REQ_TAG(PDK-2581)
623 *
624 * \param chHandle [IN] UDMA channel handle.
625 * This parameter can't be NULL.
626 * \param rxPrms [IN] UDMA RX channel parameter.
627 * Refer #Udma_ChRxPrms.
628 *
629 * \return \ref Udma_ErrorCodes
630 */
631 int32_t Udma_chConfigRx(Udma_ChHandle chHandle, const Udma_ChRxPrms *rxPrms);
633 /**
634 * \brief UDMA configure UTC channel.
635 *
636 * Configures the UTC channel parameters. Note: This is applicable only
637 * when the channel type is UTC
638 *
639 * Note: This API can't be called after channel enable.
640 *
641 * Requirement: DOX_REQ_TAG(PDK-2582)
642 *
643 * \param chHandle [IN] UDMA channel handle.
644 * This parameter can't be NULL.
645 * \param utcPrms [IN] UDMA UTC channel parameter.
646 * Refer #Udma_ChUtcPrms.
647 *
648 * \return \ref Udma_ErrorCodes
649 */
650 int32_t Udma_chConfigUtc(Udma_ChHandle chHandle, const Udma_ChUtcPrms *utcPrms);
652 /**
653 * \brief UDMA configure PDMA channel (peerChNum as part of #Udma_ChPrms)
654 * paired with the UDMAP channel.
655 *
656 * This configures the PDMA channel static X,Y,Z parameters.
657 *
658 * Requirement: DOX_REQ_TAG(PDK-2583)
659 *
660 * \param chHandle [IN] UDMA channel handle.
661 * This parameter can't be NULL.
662 * \param pdmaPrms [IN] UDMA RX channel parameter.
663 * Refer #Udma_ChPdmaPrms.
664 *
665 * \return \ref Udma_ErrorCodes
666 */
667 int32_t Udma_chConfigPdma(Udma_ChHandle chHandle,
668 const Udma_ChPdmaPrms *pdmaPrms);
670 /**
671 * \brief UDMA channel enable API.
672 *
673 * This function will enable the UDMA channel.
674 *
675 * Requirement: DOX_REQ_TAG(PDK-2584)
676 *
677 * \param chHandle [IN] UDMA channel handle.
678 * This parameter can't be NULL.
679 *
680 * \return \ref Udma_ErrorCodes
681 */
682 int32_t Udma_chEnable(Udma_ChHandle chHandle);
684 /**
685 * \brief UDMA channel teardown and disable API.
686 *
687 * This function will perform the channel teardown and eventually disables
688 * the UDMA channel.
689 * This initiates the force teardown sequence based on the channel type and
690 * wait for teardown to complete gracefully.
691 * If the teardown doesn't complete within the timeout provided, then this
692 * will initiate a force teardown sequence.
693 *
694 * Caution: This API is blocking. Hence cannot be called from ISR context!!
695 *
696 * Requirement: DOX_REQ_TAG(PDK-2585)
697 *
698 * \param chHandle [IN] UDMA channel handle.
699 * This parameter can't be NULL.
700 * \param timeout [IN] Timeout in ms.
701 * Use #UDMA_WAIT_FOREVER to wait forever.
702 *
703 * \return \ref Udma_ErrorCodes
704 */
705 int32_t Udma_chDisable(Udma_ChHandle chHandle, uint32_t timeout);
707 /**
708 * \brief UDMA channel pause API.
709 *
710 * This function will pause the UDMA channel by setting the pause bit of the
711 * UDMAP runtime register.
712 *
713 * Requirement: DOX_REQ_TAG(PDK-2977)
714 *
715 * \param chHandle [IN] UDMA channel handle.
716 * This parameter can't be NULL.
717 *
718 * \return \ref Udma_ErrorCodes
719 */
720 int32_t Udma_chPause(Udma_ChHandle chHandle);
722 /**
723 * \brief UDMA channel resume API.
724 *
725 * This function will resume the UDMA channel by clearing the pause bit of the
726 * UDMAP runtime register.
727 *
728 * Requirement: DOX_REQ_TAG(PDK-2977)
729 *
730 * \param chHandle [IN] UDMA channel handle.
731 * This parameter can't be NULL.
732 *
733 * \return \ref Udma_ErrorCodes
734 */
735 int32_t Udma_chResume(Udma_ChHandle chHandle);
737 /**
738 * \brief Returns the channel number offset with in a channel type - TX, RX
739 * and External (UTC) channel types.
740 *
741 * In case of UTC type, this returns the relative offset from the start
742 * of UTC it belongs to (and not from the external channel start).
743 *
744 * Requirement: TODO
745 *
746 * \param chHandle [IN] UDMA channel handle.
747 * This parameter can't be NULL.
748 *
749 * \return Channel number. Returns #UDMA_DMA_CH_INVALID for error.
750 */
751 uint32_t Udma_chGetNum(Udma_ChHandle chHandle);
753 /**
754 * \brief Returns the default free ring handle of the channel.
755 *
756 * Requirement: TODO
757 *
758 * \param chHandle [IN] UDMA channel handle.
759 * This parameter can't be NULL.
760 *
761 * \return Free ring handle. Returns NULL for error.
762 */
763 Udma_RingHandle Udma_chGetFqRingHandle(Udma_ChHandle chHandle);
765 /**
766 * \brief Returns the default completion ring handle of the channel.
767 *
768 * Requirement: TODO
769 *
770 * \param chHandle [IN] UDMA channel handle.
771 * This parameter can't be NULL.
772 *
773 * \return Completion ring handle. Returns NULL for error.
774 */
775 Udma_RingHandle Udma_chGetCqRingHandle(Udma_ChHandle chHandle);
777 /**
778 * \brief Returns the teardown completion ring handle of the channel.
779 *
780 * Requirement: TODO
781 *
782 * \param chHandle [IN] UDMA channel handle.
783 * This parameter can't be NULL.
784 *
785 * \return Teardown completion ring handle. Returns NULL for error.
786 */
787 Udma_RingHandle Udma_chGetTdCqRingHandle(Udma_ChHandle chHandle);
789 /**
790 * \brief Returns the default free ring number to be programmed
791 * in descriptor.
792 *
793 * Requirement: TODO
794 *
795 * \param chHandle [IN] UDMA channel handle.
796 * This parameter can't be NULL.
797 *
798 * \return Free ring number. Returns #UDMA_RING_INVALID for error.
799 */
800 uint16_t Udma_chGetFqRingNum(Udma_ChHandle chHandle);
802 /**
803 * \brief Returns the default completion ring number to be programmed in
804 * descriptor.
805 *
806 * Requirement: DOX_REQ_TAG(PDK-2586)
807 *
808 * \param chHandle [IN] UDMA channel handle.
809 * This parameter can't be NULL.
810 *
811 * \return Completion ring number. Returns #UDMA_RING_INVALID for error.
812 */
813 uint16_t Udma_chGetCqRingNum(Udma_ChHandle chHandle);
815 /**
816 * \brief Returns the default flow handle of the RX channel.
817 *
818 * Requirement: TODO
819 *
820 * \param chHandle [IN] UDMA channel handle.
821 * This parameter can't be NULL.
822 *
823 * \return Default flow handle. Returns NULL for error.
824 */
825 Udma_FlowHandle Udma_chGetDefaultFlowHandle(Udma_ChHandle chHandle);
827 /**
828 * \brief UDMA dequeue response from teardown completion ring.
829 *
830 * This function will pop the response from the teardown completion ring.
831 * This is non-blocking and will return timeout error #UDMA_ETIMEOUT
832 * when the queue is empty.
833 * Note: When executing a teardown sequence, the teardown ring should be
834 * popped using this API to avoid ring overflow.
835 * Note: In case of devices like AM64x where there is no teardown function,
836 * this API is not supported and will return error.
837 *
838 * Requirement: DOX_REQ_TAG(PDK-2589)
839 *
840 * \param chHandle [IN] UDMA channel handle.
841 * This parameter can't be NULL.
842 * \param tdResponse [OUT] Teardown response received in the ring.
843 *
844 * \return \ref Udma_ErrorCodes
845 */
846 int32_t Udma_chDequeueTdResponse(Udma_ChHandle chHandle,
847 CSL_UdmapTdResponse *tdResponse);
849 /**
850 * \brief Sets the software trigger register based on the trigger mode
851 * provided.
852 *
853 * This function will set the appropriate SW trigger register.
854 * Incase of UDMAP channels, it will set in the TX SWTRIG register.
855 * Incase of DRU channels, it will set in the DRU CHRT_SWTRIG register.
856 *
857 * Notes: SW trigger is not supported for RX channels.
858 * Incase of TX channels, only global trigger 0 is supported.
859 * Incase of DRU channels, global trigger 0/1 and local events are
860 * supported.
861 *
862 * Requirement: DOX_REQ_TAG(PDK-2594)
863 *
864 * \param chHandle [IN] UDMA channel handle.
865 * This parameter can't be NULL.
866 * \param trigger [IN] Global0 or Global 1 Trigger - refer
867 * \ref CSL_UdmapTrFlagsTrigger
868 *
869 * \return \ref Udma_ErrorCodes
870 */
871 int32_t Udma_chSetSwTrigger(Udma_ChHandle chHandle, uint32_t trigger);
873 /**
874 * \brief Chains the trigger channel with the chained channel.
875 *
876 * This programs the trigger channel TR event register (OES) to the global
877 * trigger (0 or 1) event of the chained channel.
878 *
879 * Once this is done, the application should set the TR trigger (0 or 1)
880 * of the trigger channel while submitting TR to the trigger channel.
881 * Based on the trigger type (full, ICNT0, INCT1, ICNT3), the trigger
882 * channel will trigger the "chained" channel through the channel OES.
883 *
884 * Note: Only global0 and global1 triggers are supported.
885 *
886 * Requirement: TODO
887 *
888 * \param triggerChHandle [IN] UDMA channel handle which triggers the chain.
889 * This parameter can't be NULL.
890 * \param chainedChHandle [IN] UDMA channel handle which gets triggered.
891 * This parameter can't be NULL.
892 * \param trigger [IN] Global0 or Global 1 Trigger - refer
893 * \ref CSL_UdmapTrFlagsTrigger
894 *
895 * \return \ref Udma_ErrorCodes
896 */
897 int32_t Udma_chSetChaining(Udma_ChHandle triggerChHandle,
898 Udma_ChHandle chainedChHandle,
899 uint32_t trigger);
901 /**
902 * \brief Breaks the chaining by resetting the trigger channel's OES.
903 *
904 * Note: Only global0 and global1 triggers are supported.
905 *
906 * Requirement: TODO
907 *
908 * \param triggerChHandle [IN] UDMA channel handle which triggers the chain.
909 * This parameter can't be NULL.
910 * \param chainedChHandle [IN] UDMA channel handle which gets triggered.
911 * This parameter can't be NULL.
912 *
913 * \return \ref Udma_ErrorCodes
914 */
915 int32_t Udma_chBreakChaining(Udma_ChHandle triggerChHandle,
916 Udma_ChHandle chainedChHandle);
918 /*
919 * Structure Init functions
920 */
921 /**
922 * \brief Udma_ChPrms structure init function.
923 *
924 * \param chPrms [IN] Pointer to #Udma_ChPrms structure.
925 * \param chType [IN] UDMA channel type. Refer \ref Udma_ChType.
926 *
927 */
928 void UdmaChPrms_init(Udma_ChPrms *chPrms, uint32_t chType);
930 /**
931 * \brief Udma_ChTxPrms structure init function.
932 *
933 * \param txPrms [IN] Pointer to #Udma_ChTxPrms structure.
934 * \param chType [IN] UDMA channel type. Refer \ref Udma_ChType.
935 *
936 */
937 void UdmaChTxPrms_init(Udma_ChTxPrms *txPrms, uint32_t chType);
939 /**
940 * \brief Udma_ChRxPrms structure init function.
941 *
942 * \param rxPrms [IN] Pointer to #Udma_ChRxPrms structure.
943 * \param chType [IN] UDMA channel type. Refer \ref Udma_ChType.
944 *
945 */
946 void UdmaChRxPrms_init(Udma_ChRxPrms *rxPrms, uint32_t chType);
948 /**
949 * \brief Udma_ChUtcPrms structure init function.
950 *
951 * \param utcPrms [IN] Pointer to #Udma_ChUtcPrms structure.
952 *
953 */
954 void UdmaChUtcPrms_init(Udma_ChUtcPrms *utcPrms);
956 /**
957 * \brief Udma_ChPdmaPrms structure init function.
958 *
959 * \param pdmaPrms [IN] Pointer to #Udma_ChPdmaPrms structure.
960 *
961 */
962 void UdmaChPdmaPrms_init(Udma_ChPdmaPrms *pdmaPrms);
964 /**
965 * \brief Get real-time channel statistics.
966 *
967 * Requirement: PRSDK-5609
968 *
969 * \param chHandle [IN] UDMA channel handle.
970 * This parameter can't be NULL.
971 * \param chStats [IN] Pointer to #Udma_ChStats.
972 * This parameter can't be NULL.
973 *
974 * \return \ref Udma_ErrorCodes
975 */
976 int32_t Udma_chGetStats(Udma_ChHandle chHandle, Udma_ChStats *chStats);
978 /* ========================================================================== */
979 /* Static Function Definitions */
980 /* ========================================================================== */
982 /* None */
984 /* ========================================================================== */
985 /* Internal/Private Structure Declarations */
986 /* ========================================================================== */
988 #if (UDMA_NUM_UTC_INSTANCE > 0)
989 /**
990 * \brief UDMA UTC instance information.
991 *
992 * Note: This is an internal/private driver structure and should not be
993 * used or modified by caller.
994 */
995 typedef struct
996 {
997 uint32_t utcId;
998 /**< The UTC instance ID for which this info is stored.
999 * Refer \ref Udma_UtcIdSoc macro for details. */
1000 uint32_t utcType;
1001 /**< The UTC type for which this info is stored.
1002 * Refer \ref Udma_UtcType macro for details. */
1003 uint32_t startCh;
1004 /**< UDMA external channel start number to which this UTC maps to.
1005 * This is relative to the external channel start */
1006 uint32_t numCh;
1007 /**< Number of channels present in the UTC */
1008 uint32_t startThreadId;
1009 /**< PSILCFG thread ID for the start channel */
1010 uint8_t txCredit;
1011 /**< TX credit for external channels */
1012 CSL_DRU_t *druRegs;
1013 /**< DRU register overlay - applicable only for DRU type UTC. Else this
1014 * will be set to NULL */
1015 uint32_t numQueue;
1016 /**< Number of queues present in a DRU*/
1017 } Udma_UtcInstInfo;
1018 #endif
1020 /**
1021 * \brief UDMA channel object.
1022 *
1023 * Note: This is an internal/private driver structure and should not be
1024 * used or modified by caller.
1025 */
1026 struct Udma_ChObj
1027 {
1028 uint32_t chType;
1029 /**< UDMA channel type. Refer \ref Udma_ChType. */
1030 Udma_ChPrms chPrms;
1031 /**< Object to store the channel params. */
1032 Udma_DrvHandle drvHandle;
1033 /**< Pointer to global driver handle. */
1034 #if (UDMA_NUM_UTC_INSTANCE > 0)
1035 const Udma_UtcInstInfo *utcInfo;
1036 /**< Pointer to global UTC instance info. */
1037 #endif
1039 uint32_t txChNum;
1040 /**< Allocated TX channel number - this is relative channel number from
1041 * base TX channel. This is valid only when the channel is opened for
1042 * TX and block copy mode */
1043 uint32_t rxChNum;
1044 /**< Allocated RX channel number - this is relative channel number from
1045 * base RX channel. This is valid only when the channel is opened for
1046 * RX and block copy mode */
1047 uint32_t extChNum;
1048 /**< Allocated Ext channel number - this is relative channel number from
1049 * base External channel. This is valid only when the channel is opened
1050 * for UTC mode */
1051 uint32_t pdmaChNum;
1052 /**< Allocated peer PDMA channel number. This is valid only when the
1053 * channel is opened for PDMA mode */
1054 uint32_t peerThreadId;
1055 /**< Peer channel thread ID - this is or'ed with thread offset. */
1057 Udma_RingHandle fqRing;
1058 /**< Free queue ring handle */
1059 Udma_RingHandle cqRing;
1060 /**< Completion queue ring handle
1061 * For AM64x kind of devices, where there is no seperate Completion queue,
1062 * this points to fqRing itself.
1063 */
1064 Udma_RingHandle tdCqRing;
1065 /**< Teardown completion queue ring handle */
1067 struct Udma_RingObj fqRingObj;
1068 /**< Free queue ring object */
1069 struct Udma_RingObj cqRingObj;
1070 /**< Completion queue ring object
1071 * Not used for AM64x kind of devices, where there is no seperate Completion queue.
1072 */
1073 struct Udma_RingObj tdCqRingObj;
1074 /**< Teardown completion queue ring object
1075 * Not used for AM64x kind of devices, where teardown function is not present.
1076 */
1078 Udma_FlowHandle defaultFlow;
1079 /**< Default flow handle */
1080 struct Udma_FlowObj defaultFlowObj;
1081 /**< Default flow object - Flow ID equal to the RX channel is reserved
1082 * as the default flow for the channel. This object is used for
1083 * providing handle to the caller to re-program the default flow using
1084 * the standard flow API's */
1086 Udma_ChTxPrms txPrms;
1087 /**< TX channel parameter passed during channel config. */
1088 Udma_ChRxPrms rxPrms;
1089 /**< RX channel parameter passed during channel config. */
1090 Udma_ChUtcPrms utcPrms;
1091 /**< UTC channel parameter passed during channel config. */
1094 #if (UDMA_SOC_CFG_UDMAP_PRESENT == 1)
1095 /* Below UDMAP register overlay pointers provided for debug purpose to
1096 * readily view the registers */
1097 volatile CSL_udmap_txccfgRegs_chan *pTxCfgRegs;
1098 /**< Pointer to UDMAP TX config register overlay */
1099 volatile CSL_udmap_txcrtRegs_chan *pTxRtRegs;
1100 /**< Pointer to UDMAP TX RT config register overlay */
1101 volatile CSL_udmap_rxccfgRegs_chan *pRxCfgRegs;
1102 /**< Pointer to UDMAP RX config register overlay */
1103 volatile CSL_udmap_rxcrtRegs_chan *pRxRtRegs;
1104 /**< Pointer to UDMAP RX RT config register overlay */
1105 volatile CSL_udmap_txccfgRegs_chan *pExtCfgRegs;
1106 /**< Pointer to UDMAP External config register overlay */
1107 volatile CSL_udmap_txcrtRegs_chan *pExtRtRegs;
1108 /**< Pointer to UDMAP External RT config register overlay */
1109 #endif
1110 #if (UDMA_SOC_CFG_LCDMA_PRESENT == 1)
1111 /* Below BCDMA register overlay pointers provided for debug purpose to
1112 * readily view the registers */
1113 volatile CSL_bcdma_bccfgRegs_chan *pBcdmaBcCfgRegs;
1114 /**< Pointer to BCDMA Block copy config register overlay */
1115 volatile CSL_bcdma_bcrtRegs_chan *pBcdmaBcRtRegs;
1116 /**< Pointer to BCDMA Block copy RT config register overlay */
1117 volatile CSL_bcdma_txccfgRegs_chan *pBcdmaTxCfgRegs;
1118 /**< Pointer to BCDMA TX config register overlay */
1119 volatile CSL_bcdma_txcrtRegs_chan *pBcdmaTxRtRegs;
1120 /**< Pointer to BCDMA TX RT config register overlay */
1121 volatile CSL_bcdma_rxccfgRegs_chan *pBcdmaRxCfgRegs;
1122 /**< Pointer to BCDMA RX config register overlay */
1123 volatile CSL_bcdma_rxcrtRegs_chan *pBcdmaRxRtRegs;
1124 /**< Pointer to BCDMA RX RT config register overlay */
1126 /* Below PKTDMA register overlay pointers provided for debug purpose to
1127 * readily view the registers */
1128 volatile CSL_pktdma_txccfgRegs_chan *pPktdmaTxCfgRegs;
1129 /**< Pointer to PKTDMA TX config register overlay */
1130 volatile CSL_pktdma_txcrtRegs_chan *pPktdmaTxRtRegs;
1131 /**< Pointer to PKTDMA TX RT config register overlay */
1132 volatile CSL_pktdma_rxccfgRegs_chan *pPktdmaRxCfgRegs;
1133 /**< Pointer to PKTDMA RX config register overlay */
1134 volatile CSL_pktdma_rxcrtRegs_chan *pPktdmaRxRtRegs;
1135 /**< Pointer to PKTDMA RX RT config register overlay */
1136 volatile CSL_pktdma_txccfgRegs_chan *pPktdmaExtCfgRegs;
1137 /**< Pointer to PKTDMA External config register overlay */
1138 volatile CSL_pktdma_txcrtRegs_chan *pPktdmaExtRtRegs;
1139 /**< Pointer to PKTDMA External RT config register overlay */
1140 #endif
1142 #if (UDMA_NUM_UTC_INSTANCE > 0)
1143 volatile CSL_DRU_CHNRTRegs_CHNRT *pDruNrtRegs;
1144 /**< Pointer to DRU Non RT config register overlay */
1145 volatile CSL_DRU_CHRTRegs_CHRT *pDruRtRegs;
1146 /**< Pointer to DRU RT config register overlay */
1147 #endif
1149 uint32_t chInitDone;
1150 /**< Flag to set the channel object is init. */
1151 uint32_t chOesAllocDone;
1152 /**< Flag to check if the channel's OES is allocated. This is required
1153 * because the channel OES is used for chaining as well as for
1154 * TR event registeration. This allows to check for error when both
1155 * are requested by user on the same channel */
1156 uint32_t trigger;
1157 /**< Channel trigger used when chaining channels - needed at the time of
1158 * breaking the chaining */
1159 };
1161 #ifdef __cplusplus
1162 }
1163 #endif
1165 #endif /* #ifndef UDMA_CH_H_ */
1167 /* @} */