1 /*
2 * Copyright (c) Texas Instruments Incorporated 2020
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /**
34 * \file udma_soc.c
35 *
36 * \brief File containing the UDMA driver SOC related configuration functions.
37 *
38 */
40 /* ========================================================================== */
41 /* Include Files */
42 /* ========================================================================== */
44 #include <ti/drv/udma/src/udma_priv.h>
46 /* ========================================================================== */
47 /* Macros & Typedefs */
48 /* ========================================================================== */
50 /* None */
52 /* ========================================================================== */
53 /* Structure Declarations */
54 /* ========================================================================== */
56 /* None */
58 /* ========================================================================== */
59 /* Function Declarations */
60 /* ========================================================================== */
62 /* None */
64 /* ========================================================================== */
65 /* Global Variables */
66 /* ========================================================================== */
68 const Udma_MappedChRingAttributes gUdmaTxMappedChRingAttributes[CSL_DMSS_PKTDMA_NUM_TX_CHANS - CSL_DMSS_PKTDMA_TX_CHANS_UNMAPPED_CNT] =
69 {
70 {16U, 8U}, // Channel 16 - UDMA_MAPPED_TX_GROUP_CPSW Ch 0
71 {24U, 8U}, // Channel 17 - UDMA_MAPPED_TX_GROUP_CPSW Ch 1
72 {32U, 8U}, // Channel 18 - UDMA_MAPPED_TX_GROUP_CPSW Ch 2
73 {40U, 8U}, // Channel 19 - UDMA_MAPPED_TX_GROUP_CPSW Ch 3
74 {48U, 8U}, // Channel 20 - UDMA_MAPPED_TX_GROUP_CPSW Ch 4
75 {56U, 8U}, // Channel 21 - UDMA_MAPPED_TX_GROUP_CPSW Ch 5
76 {64U, 8U}, // Channel 22 - UDMA_MAPPED_TX_GROUP_CPSW Ch 6
77 {72U, 8U}, // Channel 23 - UDMA_MAPPED_TX_GROUP_CPSW Ch 7
78 {80U, 8U}, // Channel 24 - UDMA_MAPPED_TX_GROUP_SAUL Ch 0
79 {88U, 8U}, // Channel 25 - UDMA_MAPPED_TX_GROUP_SAUL Ch 1
80 {96U, 1U}, // Channel 26 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 0
81 {97U, 1U}, // Channel 27 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 1
82 {98U, 1U}, // Channel 28 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 2
83 {99U, 8U}, // Channel 29 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 3
84 {100U, 1U}, // Channel 30 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 4
85 {101U, 1U}, // Channel 31 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 5
86 {102U, 1U}, // Channel 32 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 6
87 {103U, 1U}, // Channel 33 - UDMA_MAPPED_TX_GROUP_ICSSG_0 Ch 7
88 {104U, 1U}, // Channel 34 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 0
89 {105U, 1U}, // Channel 35 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 1
90 {106U, 1U}, // Channel 36 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 2
91 {107U, 1U}, // Channel 37 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 3
92 {108U, 1U}, // Channel 38 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 4
93 {109U, 1U}, // Channel 39 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 5
94 {110U, 1U}, // Channel 40 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 6
95 {111U, 1U}, // Channel 41 - UDMA_MAPPED_TX_GROUP_ICSSG_1 Ch 7
96 };
98 const Udma_MappedChRingAttributes gUdmaRxMappedChRingAttributes[CSL_DMSS_PKTDMA_NUM_RX_CHANS - CSL_DMSS_PKTDMA_RX_CHANS_UNMAPPED_CNT] =
99 {
100 /*RX Ring Offset of 112U added to the startRing */
101 {128U, 16U}, // Channel 16 - UDMA_MAPPED_RX_GROUP_CPSW Ch 0
102 {144U, 8U}, // Channel 17 - UDMA_MAPPED_RX_GROUP_SAUL Ch 0
103 {144U, 8U}, // Channel 18 - UDMA_MAPPED_RX_GROUP_SAUL Ch 1
104 {152U, 8U}, // Channel 19 - UDMA_MAPPED_RX_GROUP_SAUL Ch 2
105 {152U, 8U}, // Channel 20 - UDMA_MAPPED_RX_GROUP_SAUL Ch 3
106 {160U, 16U}, // Channel 21 - UDMA_MAPPED_RX_GROUP_ICSSG_0 Ch 0
107 {176U, 16U}, // Channel 22 - UDMA_MAPPED_RX_GROUP_ICSSG_0 Ch 1
108 {192U, 16U}, // Channel 23 - UDMA_MAPPED_RX_GROUP_ICSSG_0 Ch 2
109 {208U, 16U}, // Channel 24 - UDMA_MAPPED_RX_GROUP_ICSSG_0 Ch 3
110 {224U, 16U}, // Channel 25 - UDMA_MAPPED_RX_GROUP_ICSSG_1 Ch 0
111 {240U, 16U}, // Channel 26 - UDMA_MAPPED_RX_GROUP_ICSSG_1 Ch 1
112 {256U, 16U}, // Channel 27 - UDMA_MAPPED_RX_GROUP_ICSSG_1 Ch 2
113 {272U, 16U}, // Channel 28 - UDMA_MAPPED_RX_GROUP_ICSSG_1 Ch 3
114 };
116 /* ========================================================================== */
117 /* Function Definitions */
118 /* ========================================================================== */
121 void Udma_initDrvHandle(Udma_DrvHandle drvHandle)
122 {
123 uint32_t instId;
124 CSL_BcdmaCfg *pBcdmaRegs;
125 CSL_PktdmaCfg *pPktdmaRegs;
126 CSL_LcdmaRingaccCfg *pLcdmaRaRegs;
127 CSL_IntaggrCfg *pIaRegs;
129 instId = drvHandle->initPrms.instId;
130 /*
131 * BCDMA/PKTDMA config init
132 */
133 /* Init the config structure - one time step */
134 if(UDMA_INST_ID_BCDMA_0 == instId)
135 {
136 drvHandle->instType = UDMA_INST_TYPE_LCDMA_BCDMA;
137 pBcdmaRegs = &drvHandle->bcdmaRegs;
138 pBcdmaRegs->pGenCfgRegs = ((CSL_bcdma_gcfgRegs *) CSL_DMASS0_BCDMA_GCFG_BASE);
139 pBcdmaRegs->pBcChanCfgRegs = ((CSL_bcdma_bccfgRegs *) CSL_DMASS0_BCDMA_BCHAN_BASE);
140 pBcdmaRegs->pTxChanCfgRegs = ((CSL_bcdma_txccfgRegs *) CSL_DMASS0_BCDMA_TCHAN_BASE);
141 pBcdmaRegs->pRxChanCfgRegs = ((CSL_bcdma_rxccfgRegs *) CSL_DMASS0_BCDMA_RCHAN_BASE);
142 pBcdmaRegs->pBcChanRtRegs = ((CSL_bcdma_bcrtRegs *) CSL_DMASS0_BCDMA_BCHANRT_BASE);
143 pBcdmaRegs->pTxChanRtRegs = ((CSL_bcdma_txcrtRegs *) CSL_DMASS0_BCDMA_TCHANRT_BASE);
144 pBcdmaRegs->pRxChanRtRegs = ((CSL_bcdma_rxcrtRegs *) CSL_DMASS0_BCDMA_RCHANRT_BASE);
145 drvHandle->trigGemOffset = CSL_DMSS_GEM_BCDMA_TRIGGER_OFFSET;
146 /* Fill other SOC specific parameters by reading from UDMA config
147 * registers */
148 CSL_bcdmaGetCfg(pBcdmaRegs);
150 pPktdmaRegs = &drvHandle->pktdmaRegs;
151 memset(pPktdmaRegs, 0, sizeof(*pPktdmaRegs));
152 }
153 else
154 {
155 drvHandle->instType = UDMA_INST_TYPE_LCDMA_PKTDMA;
156 pPktdmaRegs = &drvHandle->pktdmaRegs;
157 pPktdmaRegs->pGenCfgRegs = ((CSL_pktdma_gcfgRegs *) CSL_DMASS0_PKTDMA_GCFG_BASE);
158 pPktdmaRegs->pRxFlowCfgRegs = ((CSL_pktdma_rxfcfgRegs *) CSL_DMASS0_PKTDMA_RFLOW_BASE);
159 pPktdmaRegs->pTxChanCfgRegs = ((CSL_pktdma_txccfgRegs *) CSL_DMASS0_PKTDMA_TCHAN_BASE);
160 pPktdmaRegs->pRxChanCfgRegs = ((CSL_pktdma_rxccfgRegs *) CSL_DMASS0_PKTDMA_RCHAN_BASE);
161 pPktdmaRegs->pTxChanRtRegs = ((CSL_pktdma_txcrtRegs *) CSL_DMASS0_PKTDMA_TCHANRT_BASE);
162 pPktdmaRegs->pRxChanRtRegs = ((CSL_pktdma_rxcrtRegs *) CSL_DMASS0_PKTDMA_RCHANRT_BASE);
163 drvHandle->trigGemOffset = 0;
164 /* Fill other SOC specific parameters by reading from UDMA config
165 * registers */
166 CSL_pktdmaGetCfg(pPktdmaRegs);
168 pBcdmaRegs = &drvHandle->bcdmaRegs;
169 memset(pBcdmaRegs, 0, sizeof(*pBcdmaRegs));
170 }
172 /*
173 * RA config init
174 */
175 drvHandle->raType = UDMA_RA_TYPE_LCDMA;
176 pLcdmaRaRegs = &drvHandle->lcdmaRaRegs;
177 if(UDMA_INST_ID_BCDMA_0 == instId)
178 {
179 pLcdmaRaRegs->pRingCfgRegs = (CSL_lcdma_ringacc_ring_cfgRegs *) CSL_DMASS0_BCDMA_RING_BASE;
180 pLcdmaRaRegs->pRingRtRegs = (CSL_lcdma_ringacc_ringrtRegs *) CSL_DMASS0_BCDMA_RINGRT_BASE;
181 pLcdmaRaRegs->pCredRegs = (CSL_lcdma_ringacc_credRegs *) CSL_DMASS0_BCDMA_CRED_BASE;
182 pLcdmaRaRegs->maxRings = CSL_DMSS_BCDMA_NUM_BC_CHANS + CSL_DMSS_BCDMA_NUM_TX_CHANS + CSL_DMSS_BCDMA_NUM_RX_CHANS;
183 }
184 else
185 {
186 pLcdmaRaRegs->pRingCfgRegs = (CSL_lcdma_ringacc_ring_cfgRegs *) CSL_DMASS0_PKTDMA_RING_BASE;
187 pLcdmaRaRegs->pRingRtRegs = (CSL_lcdma_ringacc_ringrtRegs *) CSL_DMASS0_PKTDMA_RINGRT_BASE;
188 pLcdmaRaRegs->pCredRegs = (CSL_lcdma_ringacc_credRegs *) CSL_DMASS0_PKTDMA_CRED_BASE;
189 pLcdmaRaRegs->maxRings = CSL_DMSS_PKTDMA_NUM_RX_FLOWS + CSL_DMSS_PKTDMA_NUM_TX_FLOWS;
190 }
191 drvHandle->ringDequeueRaw = &Udma_ringDequeueRawLcdma;
192 drvHandle->ringQueueRaw = &Udma_ringQueueRawLcdma;
193 drvHandle->ringFlushRaw = &Udma_ringFlushRawLcdma;
194 drvHandle->ringGetElementCnt = &Udma_ringGetElementCntLcdma;
195 drvHandle->ringGetMemPtr = &Udma_ringGetMemPtrLcdma;
196 drvHandle->ringGetMode = &Udma_ringGetModeLcdma;
197 drvHandle->ringGetForwardRingOcc = &Udma_ringGetForwardRingOccLcdma;
198 drvHandle->ringGetReverseRingOcc = &Udma_ringGetReverseRingOccLcdma;
199 drvHandle->ringGetWrIdx = &Udma_ringGetWrIdxLcdma;
200 drvHandle->ringGetRdIdx = &Udma_ringGetRdIdxLcdma;
201 drvHandle->ringPrime = &Udma_ringPrimeLcdma;
202 drvHandle->ringPrimeRead = &Udma_ringPrimeReadLcdma;
203 drvHandle->ringSetDoorBell = &Udma_ringSetDoorBellLcdma;
204 drvHandle->ringSetCfg = &Udma_ringSetCfgLcdma;
205 drvHandle->ringHandleClearRegs = &Udma_ringHandleClearRegsLcdma;
207 /* IA config init */
208 pIaRegs = &drvHandle->iaRegs;
209 pIaRegs->pCfgRegs = (CSL_intaggr_cfgRegs *) CSL_DMASS0_INTAGGR_CFG_BASE;
210 pIaRegs->pImapRegs = (CSL_intaggr_imapRegs *) CSL_DMASS0_INTAGGR_IMAP_BASE;
211 pIaRegs->pIntrRegs = (CSL_intaggr_intrRegs *) CSL_DMASS0_INTAGGR_INTR_BASE;
212 pIaRegs->pL2gRegs = (CSL_intaggr_l2gRegs *) CSL_DMASS0_INTAGGR_L2G_BASE;
213 pIaRegs->pMcastRegs = (CSL_intaggr_mcastRegs *) CSL_DMASS0_INTAGGR_MCAST_BASE;
214 pIaRegs->pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) CSL_DMASS0_INTAGGR_GCNTCFG_BASE;
215 pIaRegs->pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) CSL_DMASS0_INTAGGR_GCNTRTI_BASE;
216 CSL_intaggrGetCfg(pIaRegs);
218 drvHandle->iaGemOffset = CSL_DMSS_GEM_INTA0_SEVI_OFFSET;
219 drvHandle->devIdIa = TISCI_DEV_DMASS0_INTAGGR_0;
221 #if defined (BUILD_MCU1_0)
222 drvHandle->devIdCore = TISCI_DEV_R5FSS0_CORE0;
223 #endif
225 #if defined (BUILD_MCU1_1)
226 drvHandle->devIdCore = TISCI_DEV_R5FSS0_CORE1;
227 #endif
229 #if defined (BUILD_MPU1_0)
230 drvHandle->devIdCore = TISCI_DEV_A53SS0_CORE_0;
231 #endif
233 #if defined (BUILD_MCU2_0)
234 drvHandle->devIdCore = TISCI_DEV_R5FSS1_CORE0;
235 #endif
237 #if defined (BUILD_MCU2_1)
238 drvHandle->devIdCore = TISCI_DEV_R5FSS1_CORE1;
239 #endif
241 #if defined (BUILD_M4F_0)
242 drvHandle->devIdCore = TISCI_DEV_MCU_M4FSS0_CORE0;
243 #endif
245 /* Init other variables */
246 if(UDMA_INST_ID_BCDMA_0 == instId)
247 {
248 /* DMSC differentiates block copy channel from split tr tx, if the index have an offset of 32.
249 * The offset of 32 is chosen because it’s the next power of 2 above the max split tr tx channel (19).
250 */
251 drvHandle->blkCopyChOffset = 32U;
252 drvHandle->txChOffset = pBcdmaRegs->bcChanCnt;
253 drvHandle->rxChOffset = drvHandle->txChOffset + pBcdmaRegs->splitTxChanCnt;
254 /* The srcIdx passed to Sciclient_rmIrqset API, will be ringNum + the corresponding following offset.
255 * So setting the offset as TISCI Start Idx - corresponding ringNum Offset (if any) */
256 drvHandle->blkCopyRingIrqOffset = TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START;
257 drvHandle->txRingIrqOffset = TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START - drvHandle->txChOffset;
258 drvHandle->rxRingIrqOffset = TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START - drvHandle->rxChOffset;
259 drvHandle->udmapSrcThreadOffset = CSL_PSILCFG_DMSS_BCDMA_STRM_PSILS_THREAD_OFFSET;
260 drvHandle->udmapDestThreadOffset= CSL_PSILCFG_DMSS_BCDMA_STRM_PSILD_THREAD_OFFSET;
261 drvHandle->maxRings = CSL_DMSS_BCDMA_NUM_BC_CHANS + CSL_DMSS_BCDMA_NUM_TX_CHANS + CSL_DMSS_BCDMA_NUM_RX_CHANS;
262 drvHandle->devIdRing = TISCI_DEV_DMASS0_BCDMA_0;
263 drvHandle->devIdUdma = TISCI_DEV_DMASS0_BCDMA_0;
264 }
265 else
266 {
267 drvHandle->blkCopyChOffset = 0U; /* Not used for PktDMA Instance */
268 drvHandle->txChOffset = CSL_DMSS_PKTDMA_TX_FLOWS_UNMAPPED_START; /* Need to be updated, Since Special channels present */
269 drvHandle->rxChOffset = CSL_DMSS_PKTDMA_RX_FLOWS_UNMAPPED_START; /* Need to be updated, Since Special channels present */
270 drvHandle->blkCopyRingIrqOffset = 0U; /* Not used for PktDMA Instance */
271 drvHandle->txRingIrqOffset = TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START - drvHandle->txChOffset; /* Need to be updated, Since Special channels present */
272 drvHandle->rxRingIrqOffset = TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START - drvHandle->rxChOffset; /* Need to be updated, Since Special channels present */
273 drvHandle->udmapSrcThreadOffset = CSL_PSILCFG_DMSS_PKTDMA_STRM_PSILS_THREAD_OFFSET;
274 drvHandle->udmapDestThreadOffset= CSL_PSILCFG_DMSS_PKTDMA_STRM_PSILD_THREAD_OFFSET;
275 drvHandle->maxRings = CSL_DMSS_PKTDMA_NUM_RX_FLOWS + CSL_DMSS_PKTDMA_NUM_TX_FLOWS;
276 drvHandle->devIdRing = TISCI_DEV_DMASS0_PKTDMA_0;
277 drvHandle->devIdUdma = TISCI_DEV_DMASS0_PKTDMA_0;
278 }
279 drvHandle->devIdPsil = TISCI_DEV_DMASS0;
280 drvHandle->maxProxy = 0U;
281 drvHandle->maxRingMon = CSL_DMSS_RINGACC_NUM_MONITORS;
282 drvHandle->extChOffset = 0U;
283 drvHandle->srcIdRingIrq = drvHandle->devIdIa;
285 return;
286 }
288 void UdmaRmInitPrms_init(uint32_t instId, Udma_RmInitPrms *rmInitPrms)
289 {
290 const Udma_RmInitPrms *rmInitDefaultCfg;
292 if(NULL_PTR != rmInitPrms)
293 {
294 rmInitDefaultCfg = Udma_rmGetDefaultCfg(instId);
295 (void) memcpy(rmInitPrms, rmInitDefaultCfg, sizeof (Udma_RmInitPrms));
296 }
298 return;
299 }
301 uint32_t Udma_getCoreId(void)
302 {
303 uint32_t coreId;
305 #if defined (BUILD_MPU1_0)
306 coreId = UDMA_CORE_ID_MPU1_0;
307 #endif
308 #if defined (BUILD_MCU2_0)
309 coreId = UDMA_CORE_ID_MCU2_0;
310 #endif
311 #if defined (BUILD_MCU2_1)
312 coreId = UDMA_CORE_ID_MCU2_1;
313 #endif
314 #if defined (BUILD_MCU1_0)
315 coreId = UDMA_CORE_ID_MCU1_0;
316 #endif
317 #if defined (BUILD_MCU1_1)
318 coreId = UDMA_CORE_ID_MCU1_1;
319 #endif
320 #if defined (BUILD_M4F_0)
321 coreId = UDMA_CORE_ID_M4F_0;
322 #endif
324 return (coreId);
325 }
327 uint32_t Udma_isCacheCoherent(void)
328 {
329 uint32_t isCacheCoherent;
331 #if defined (BUILD_MPU1_0)
332 isCacheCoherent = TRUE;
333 #else
334 isCacheCoherent = FALSE;
335 #endif
337 return (isCacheCoherent);
338 }
340 void Udma_getMappedChRingAttributes(Udma_DrvHandle drvHandle, uint32_t chNum, uint32_t mappedGrp, Udma_MappedChRingAttributes *chAttr)
341 {
342 const Udma_MappedChRingAttributes *mappedChRingAttributes;
343 uint32_t index = 0U;
345 if(mappedGrp < UDMA_NUM_MAPPED_TX_GROUP) /* Mapped TX Channel */
346 {
347 /* Calculate index by subtracting the start idx of mapped channels
348 * (For AM64x, mapped channel starts with CPSW channel.) */
349 index = chNum - CSL_DMSS_PKTDMA_TX_CHANS_CPSW_START;
350 /* Check that, index is less than total no.of mapped TX channels */
351 Udma_assert(drvHandle, index < (CSL_DMSS_PKTDMA_NUM_TX_CHANS - CSL_DMSS_PKTDMA_TX_CHANS_UNMAPPED_CNT));
352 mappedChRingAttributes = &gUdmaTxMappedChRingAttributes[index];
353 }
354 else /* Mapped RX Channel */
355 {
356 /* Calculate index by subtracting the start idx of mapped channels
357 * (For AM64x, mapped channel starts with CPSW channel.) */
358 index = chNum - CSL_DMSS_PKTDMA_RX_CHANS_CPSW_START;
359 /* Check that, index is less than total no.of mapped RX channels */
360 Udma_assert(drvHandle, index < (CSL_DMSS_PKTDMA_NUM_RX_CHANS - CSL_DMSS_PKTDMA_RX_CHANS_UNMAPPED_CNT));
361 mappedChRingAttributes = &gUdmaRxMappedChRingAttributes[index];
362 }
363 (void) memcpy(chAttr, mappedChRingAttributes, sizeof (Udma_MappedChRingAttributes));
365 return ;
366 }