1 /*
2 * Copyright (c) Texas Instruments Incorporated 2018
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /**
34 * \file udma_soc.c
35 *
36 * \brief File containing the UDMA driver SOC related configuration functions.
37 *
38 */
40 /* ========================================================================== */
41 /* Include Files */
42 /* ========================================================================== */
44 #include <ti/drv/udma/src/udma_priv.h>
46 /* ========================================================================== */
47 /* Macros & Typedefs */
48 /* ========================================================================== */
50 /* None */
52 /* ========================================================================== */
53 /* Structure Declarations */
54 /* ========================================================================== */
56 /* None */
58 /* ========================================================================== */
59 /* Function Declarations */
60 /* ========================================================================== */
62 /* None */
64 /* ========================================================================== */
65 /* Global Variables */
66 /* ========================================================================== */
67 #if defined (LOKI_BUILD)
68 #define HOST_EMULATION (1U)
69 #endif
71 #if defined (HOST_EMULATION)
72 /* These variables are defined for supporting host emulation ( PC emulation ) and
73 will not be used for target*/
74 CSL_udmap_gcfgRegs gHost_udmap_gcfgRegs;
75 CSL_udmap_rxfcfgRegs gHost_udmap_rxfcfgRegs;
76 CSL_udmap_txccfgRegs gHost_udmap_txccfgRegs;
77 CSL_udmap_rxccfgRegs gHost_udmap_rxccfgRegs;
78 CSL_udmap_txcrtRegs gHost_udmap_txcrtRegs;
79 CSL_udmap_rxcrtRegs gHost_udmap_rxcrtRegs;
80 CSL_ringacc_gcfgRegs gHost_ringacc_gcfgRegs;
81 CSL_ringacc_cfgRegs gHost_ringacc_cfgRegs;
82 CSL_ringacc_rtRegs gHost_ringacc_rtRegs;
83 CSL_ringacc_monitorRegs gHost_ringacc_monitorRegs;
84 CSL_ringacc_fifosRegs gHost_ringacc_fifosRegs;
85 CSL_ringacc_iscRegs gHost_ringacc_iscRegs;
86 CSL_psilcfgRegs gHost_psilcfgRegs;
87 CSL_intaggr_cfgRegs gHost_intaggr_cfgRegs;
88 CSL_intaggr_imapRegs gHost_intaggr_imapRegs;
89 CSL_intaggr_intrRegs gHost_intaggr_intrRegs;
90 CSL_intaggr_l2gRegs gHost_intaggr_l2gRegs;
91 CSL_intaggr_mcastRegs gHost_intaggr_mcastRegs;
92 CSL_intaggr_gcntcfgRegs gHost_intaggr_gcntcfgRegs;
93 CSL_intaggr_gcntrtiRegs gHost_intaggr_gcntrtiRegs;
94 CSL_intr_router_cfgRegs gHost_intr_router_cfgRegs;
95 CSL_CLEC_EVTRegs gHost_clec_evtRegs;
97 CSL_DRU_t gHost_DRU_t;
98 #define UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE (&gHost_udmap_gcfgRegs)
99 #define UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE (&gHost_udmap_rxfcfgRegs)
100 #define UDMA_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE (&gHost_udmap_txccfgRegs)
101 #define UDMA_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE (&gHost_udmap_rxccfgRegs)
102 #define UDMA_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE (&gHost_udmap_txcrtRegs)
103 #define UDMA_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE (&gHost_udmap_rxcrtRegs)
105 #define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_BASE (&gHost_udmap_gcfgRegs)
106 #define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE (&gHost_udmap_rxfcfgRegs)
107 #define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE (&gHost_udmap_txccfgRegs)
108 #define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE (&gHost_udmap_rxccfgRegs)
109 #define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE (&gHost_udmap_txcrtRegs)
110 #define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE (&gHost_udmap_rxcrtRegs)
112 #define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE (&gHost_ringacc_gcfgRegs)
113 #define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE (&gHost_ringacc_cfgRegs)
114 #define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE (&gHost_ringacc_rtRegs)
115 #define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE (&gHost_ringacc_monitorRegs)
116 #define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE (&gHost_ringacc_fifosRegs)
117 #define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE (&gHost_ringacc_iscRegs)
119 #define UDMA_NAVSS0_UDMASS_RINGACC0_GCFG_BASE (&gHost_ringacc_gcfgRegs)
120 #define UDMA_NAVSS0_UDMASS_RINGACC0_CFG_BASE (&gHost_ringacc_cfgRegs)
121 #define UDMA_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE (&gHost_ringacc_rtRegs)
122 #define UDMA_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE (&gHost_ringacc_monitorRegs)
123 #define UDMA_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE (&gHost_ringacc_fifosRegs)
124 #define UDMA_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE (&gHost_ringacc_iscRegs)
126 #define UDMA_MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY_BASE (&gHost_psilcfgRegs)
127 #define UDMA_NAVSS0_UDMASS_PSILCFG0_CFG_PROXY_BASE (&gHost_psilcfgRegs)
129 #define UDMA_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE (&gHost_intaggr_cfgRegs )
130 #define UDMA_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE (&gHost_intaggr_imapRegs)
131 #define UDMA_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE (&gHost_intaggr_intrRegs)
132 #define UDMA_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_BASE (&gHost_intaggr_l2gRegs)
133 #define UDMA_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE (&gHost_intaggr_mcastRegs)
134 #define UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE (&gHost_intaggr_gcntcfgRegs)
135 #define UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE (&gHost_intaggr_gcntrtiRegs)
137 #define UDMA_MCU_NAVSS0_INTR0_CFG_BASE (&gHost_intr_router_cfgRegs)
139 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_BASE (&gHost_intaggr_cfgRegs )
140 #define UDMA_NAVSS0_UDMASS_INTA0_IMAP_BASE (&gHost_intaggr_imapRegs)
141 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE (&gHost_intaggr_intrRegs)
142 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE (&gHost_intaggr_l2gRegs)
143 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE (&gHost_intaggr_mcastRegs)
144 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE (&gHost_intaggr_gcntcfgRegs)
145 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE (&gHost_intaggr_gcntrtiRegs)
147 #define UDMA_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE (&gHost_intr_router_cfgRegs)
149 /** \brief DRU0 UTC baseaddress */
150 #define UDMA_UTC_BASE_DRU0 (&gHost_DRU_t)
151 #define UDMA_COMPUTE_CLUSTER0_CLEC_REGS_BASE (&gHost_clec_evtRegs)
153 #else
155 #define UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE (CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE)
156 #define UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE (CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE)
157 #define UDMA_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE (CSL_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE)
158 #define UDMA_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE (CSL_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE)
159 #define UDMA_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE (CSL_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE)
160 #define UDMA_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE (CSL_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE)
162 #define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_BASE (CSL_NAVSS0_UDMASS_UDMAP0_CFG_BASE)
163 #define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE (CSL_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE)
164 #define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE (CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE)
165 #define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE (CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE)
166 #define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE (CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE)
167 #define UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE (CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE)
169 #define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE (CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE)
170 #define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE (CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE)
171 #define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE (CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE)
172 #define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE (CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE)
173 #define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE (CSL_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE)
174 #define UDMA_MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE (CSL_MCU_NAVSS0_UDMASS_RINGACC0_ISC_BASE)
176 #define UDMA_NAVSS0_UDMASS_RINGACC0_GCFG_BASE (CSL_NAVSS0_UDMASS_RINGACC0_GCFG_BASE)
177 #define UDMA_NAVSS0_UDMASS_RINGACC0_CFG_BASE (CSL_NAVSS0_UDMASS_RINGACC0_CFG_BASE)
178 #define UDMA_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE (CSL_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE)
179 #define UDMA_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE (CSL_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE)
180 #define UDMA_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE (CSL_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE)
181 #define UDMA_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE (CSL_NAVSS0_UDMASS_RINGACC0_ISC_BASE)
183 #define UDMA_MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY_BASE (CSL_MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY_BASE)
184 #define UDMA_NAVSS0_UDMASS_PSILCFG0_CFG_PROXY_BASE (CSL_NAVSS0_UDMASS_PSILCFG0_CFG_PROXY_BASE)
186 #define UDMA_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE (CSL_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE)
187 #define UDMA_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE (CSL_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE)
188 #define UDMA_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE (CSL_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE)
189 #define UDMA_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_BASE (CSL_MCU_NAVSS0_UDMASS_INTA0_I2G_BASE)
190 #define UDMA_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE (CSL_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE)
191 #define UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE (CSL_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE)
192 #define UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE (CSL_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE)
194 #define UDMA_MCU_NAVSS0_INTR0_CFG_BASE (CSL_MCU_NAVSS0_INTR0_CFG_BASE)
196 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_BASE (CSL_NAVSS0_UDMASS_INTA0_CFG_BASE)
197 #define UDMA_NAVSS0_UDMASS_INTA0_IMAP_BASE (CSL_NAVSS0_UDMASS_INTA0_IMAP_BASE)
198 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE (CSL_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE)
199 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE (CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE)
200 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE (CSL_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE)
201 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE (CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE)
202 #define UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE (CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE)
204 #define UDMA_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE (CSL_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE)
205 /** \brief DRU0 UTC baseaddress */
206 #define UDMA_UTC_BASE_DRU0 (CSL_COMPUTE_CLUSTER0_DRU_BASE)
207 #define UDMA_COMPUTE_CLUSTER0_CLEC_REGS_BASE (CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE)
208 #endif
209 /* None */
211 /* ========================================================================== */
212 /* Function Definitions */
213 /* ========================================================================== */
215 void Udma_initDrvHandle(Udma_DrvHandle drvHandle)
216 {
217 uint32_t instId;
218 CSL_UdmapCfg *pUdmapRegs;
219 CSL_RingAccCfg *pRaRegs;
220 CSL_IntaggrCfg *pIaRegs;
221 Udma_UtcInstInfo *utcInfo;
222 CSL_ProxyCfg *pProxyCfg;
223 CSL_ProxyTargetParams *pProxyTargetRing;
225 instId = drvHandle->initPrms.instId;
227 drvHandle->instType = UDMA_INST_TYPE_NORMAL;
229 #if defined (HOST_EMULATION)
230 gHost_udmap_gcfgRegs.CAP0 = 0x000B800F;
231 gHost_udmap_gcfgRegs.CAP1 = 0;
232 gHost_udmap_gcfgRegs.CAP2 = 0x02584078;
233 gHost_udmap_gcfgRegs.CAP3 = 0x0000012C;
235 gHost_intaggr_cfgRegs.INTCAP = 0x0000000001001200;
236 gHost_intaggr_cfgRegs.AUXCAP = 0x0000020000040200;
237 #endif
239 /*
240 * UDMA config init
241 */
242 /* Init the config structure - one time step */
243 pUdmapRegs = &drvHandle->udmapRegs;
244 if(UDMA_INST_ID_MCU_0 == instId)
245 {
246 pUdmapRegs->pGenCfgRegs = ((CSL_udmap_gcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE);
247 pUdmapRegs->pRxFlowCfgRegs = ((CSL_udmap_rxfcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE);
248 pUdmapRegs->pTxChanCfgRegs = ((CSL_udmap_txccfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE);
249 pUdmapRegs->pRxChanCfgRegs = ((CSL_udmap_rxccfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE);
250 pUdmapRegs->pTxChanRtRegs = ((CSL_udmap_txcrtRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE);
251 pUdmapRegs->pRxChanRtRegs = ((CSL_udmap_rxcrtRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE);
252 drvHandle->trigGemOffset = CSL_NAVSS_GEM_MCU_UDMA_TRIGGER_OFFSET;
253 }
254 else
255 {
256 pUdmapRegs->pGenCfgRegs = ((CSL_udmap_gcfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_BASE);
257 pUdmapRegs->pRxFlowCfgRegs = ((CSL_udmap_rxfcfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE);
258 pUdmapRegs->pTxChanCfgRegs = ((CSL_udmap_txccfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE);
259 pUdmapRegs->pRxChanCfgRegs = ((CSL_udmap_rxccfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE);
260 pUdmapRegs->pTxChanRtRegs = ((CSL_udmap_txcrtRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE);
261 pUdmapRegs->pRxChanRtRegs = ((CSL_udmap_rxcrtRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE);
262 drvHandle->trigGemOffset = CSL_NAVSS_GEM_MAIN_UDMA_TRIGGER_OFFSET;
263 }
264 drvHandle->clecRegs = (CSL_CLEC_EVTRegs *) UDMA_COMPUTE_CLUSTER0_CLEC_REGS_BASE;
265 /* UDMA not present in CC QT build. Only DRU is present */
266 #ifndef CC_QT_BUILD
267 /* Fill other SOC specific parameters by reading from UDMA config
268 * registers */
269 CSL_udmapGetCfg(pUdmapRegs);
270 #endif
272 /*
273 * RA config init
274 */
275 drvHandle->raType = UDMA_RA_TYPE_NORMAL;
276 pRaRegs = &drvHandle->raRegs;
277 if(UDMA_INST_ID_MCU_0 == instId)
278 {
279 pRaRegs->pGlbRegs = (CSL_ringacc_gcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE;
280 pRaRegs->pCfgRegs = (CSL_ringacc_cfgRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE;
281 pRaRegs->pRtRegs = (CSL_ringacc_rtRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE;
282 pRaRegs->pMonRegs = (CSL_ringacc_monitorRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE;
283 pRaRegs->pFifoRegs = (CSL_ringacc_fifosRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE;
284 pRaRegs->pIscRegs = (CSL_ringacc_iscRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE;
285 pRaRegs->maxRings = CSL_NAVSS_MCU_RINGACC_RING_CNT;
286 }
287 else
288 {
289 pRaRegs->pGlbRegs = (CSL_ringacc_gcfgRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_GCFG_BASE;
290 pRaRegs->pCfgRegs = (CSL_ringacc_cfgRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_CFG_BASE;
291 pRaRegs->pRtRegs = (CSL_ringacc_rtRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE;
292 pRaRegs->pMonRegs = (CSL_ringacc_monitorRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE;
293 pRaRegs->pFifoRegs = (CSL_ringacc_fifosRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE;
294 pRaRegs->pIscRegs = (CSL_ringacc_iscRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE;
295 pRaRegs->maxRings = CSL_NAVSS_MAIN_RINGACC_RING_CNT;
296 }
297 pRaRegs->maxMonitors = CSL_RINGACC_MAX_MONITORS;
298 pRaRegs->bTraceSupported = (bool)true;
300 drvHandle->ringDequeueRaw = &Udma_ringDequeueRawNormal;
301 drvHandle->ringQueueRaw = &Udma_ringQueueRawNormal;
302 drvHandle->ringFlushRaw = &Udma_ringFlushRawNormal;
303 drvHandle->ringGetElementCnt = &Udma_ringGetElementCntNormal;
304 drvHandle->ringGetMemPtr = &Udma_ringGetMemPtrNormal;
305 drvHandle->ringGetMode = &Udma_ringGetModeNormal;
306 drvHandle->ringGetForwardRingOcc = &Udma_ringGetRingOccNormal;
307 drvHandle->ringGetReverseRingOcc = &Udma_ringGetRingOccNormal;
308 drvHandle->ringGetWrIdx = &Udma_ringGetWrIdxNormal;
309 drvHandle->ringGetRdIdx = &Udma_ringGetRdIdxNormal;
310 drvHandle->ringPrime = &Udma_ringPrimeNormal;
311 drvHandle->ringPrimeRead = &Udma_ringPrimeReadNormal;
312 drvHandle->ringSetDoorBell = &Udma_ringSetDoorBellNormal;
313 drvHandle->ringSetCfg = &Udma_ringSetCfgNormal;
314 drvHandle->ringHandleClearRegs = &Udma_ringHandleClearRegsNormal;
316 /*
317 * All interrupt related config should be based on core and not
318 * based on NAVSS instance
319 */
320 #if defined (BUILD_MCU1_0) || defined (BUILD_MCU1_1)
321 /* IA config init */
322 pIaRegs = &drvHandle->iaRegs;
323 pIaRegs->pCfgRegs = (CSL_intaggr_cfgRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE;
324 pIaRegs->pImapRegs = (CSL_intaggr_imapRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE;
325 pIaRegs->pIntrRegs = (CSL_intaggr_intrRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE;
326 pIaRegs->pL2gRegs = (CSL_intaggr_l2gRegs *) UDMA_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_BASE;
327 pIaRegs->pMcastRegs = (CSL_intaggr_mcastRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE;
328 pIaRegs->pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE;
329 pIaRegs->pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE;
330 CSL_intaggrGetCfg(pIaRegs);
332 drvHandle->iaGemOffset = CSL_NAVSS_GEM_MCU_UDMA_INTA0_SEVI_OFFSET;
333 drvHandle->devIdIa = TISCI_DEV_MCU_NAVSS0_UDMASS_INTA_0;
334 drvHandle->devIdIr = TISCI_DEV_MCU_NAVSS0_INTR_0;
335 #if defined (BUILD_MCU1_0)
336 drvHandle->devIdCore = TISCI_DEV_MCU_R5FSS0_CORE0;
337 drvHandle->druCoreId = UDMA_DRU_CORE_ID_MCU1_0;
338 #else
339 drvHandle->devIdCore = TISCI_DEV_MCU_R5FSS0_CORE1;
340 drvHandle->druCoreId = UDMA_DRU_CORE_ID_MCU1_1;
341 #endif
342 #else
343 /* IA config init */
344 pIaRegs = &drvHandle->iaRegs;
345 pIaRegs->pCfgRegs = (CSL_intaggr_cfgRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_BASE;
346 pIaRegs->pImapRegs = (CSL_intaggr_imapRegs *) UDMA_NAVSS0_UDMASS_INTA0_IMAP_BASE;
347 pIaRegs->pIntrRegs = (CSL_intaggr_intrRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE;
348 pIaRegs->pL2gRegs = (CSL_intaggr_l2gRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE;
349 pIaRegs->pMcastRegs = (CSL_intaggr_mcastRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE;
350 pIaRegs->pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE;
351 pIaRegs->pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE;
352 /* UDMA not present in CC QT build. Only DRU is present */
353 #ifndef CC_QT_BUILD
354 CSL_intaggrGetCfg(pIaRegs);
355 #endif
357 drvHandle->iaGemOffset = CSL_NAVSS_GEM_MAIN_UDMA_INTA0_SEVI_OFFSET;
358 drvHandle->devIdIa = TISCI_DEV_NAVSS0_UDMASS_INTAGGR_0;
359 drvHandle->devIdIr = TISCI_DEV_NAVSS0_INTR_ROUTER_0;
360 drvHandle->clecRtMap = CSL_CLEC_RTMAP_DISABLE;
361 drvHandle->clecOffset = 0U;
362 #if defined (BUILD_MPU1_0)
363 drvHandle->devIdCore = TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS;
364 drvHandle->druCoreId = UDMA_DRU_CORE_ID_MPU1_0;
365 #endif
366 #if defined (BUILD_MCU2_0)
367 drvHandle->devIdCore = TISCI_DEV_R5FSS0_CORE0;
368 drvHandle->druCoreId = UDMA_DRU_CORE_ID_MCU2_0;
369 #endif
370 #if defined (BUILD_MCU2_1)
371 drvHandle->devIdCore = TISCI_DEV_R5FSS0_CORE1;
372 drvHandle->druCoreId = UDMA_DRU_CORE_ID_MCU2_1;
373 #endif
374 #if defined (BUILD_MCU3_0)
375 drvHandle->devIdCore = TISCI_DEV_R5FSS1_CORE0;
376 drvHandle->druCoreId = UDMA_DRU_CORE_ID_MCU3_0;
377 #endif
378 #if defined (BUILD_MCU3_1)
379 drvHandle->devIdCore = TISCI_DEV_R5FSS1_CORE1;
380 drvHandle->druCoreId = UDMA_DRU_CORE_ID_MCU3_1;
381 #endif
382 #if defined (BUILD_C66X_1)
383 drvHandle->devIdCore = TISCI_DEV_C66SS0_CORE0;
384 drvHandle->druCoreId = UDMA_DRU_CORE_ID_C66X_1;
385 #endif
386 #if defined (BUILD_C66X_2)
387 drvHandle->devIdCore = TISCI_DEV_C66SS1_CORE0;
388 drvHandle->druCoreId = UDMA_DRU_CORE_ID_C66X_2;
389 #endif
390 #if defined (BUILD_C7X_1)
391 drvHandle->devIdCore = TISCI_DEV_COMPUTE_CLUSTER0_CLEC;
392 drvHandle->druCoreId = UDMA_DRU_CORE_ID_C7X_1;
393 drvHandle->clecRtMap = CSL_CLEC_RTMAP_CPU_4; /* CPU4 is C7x_1 in J721E */
394 /* CLEC interrupt number 1024 is connected to GIC interrupt number 32 in J721E.
395 * Due to this for CLEC programming one needs to add an offset of 992 (1024 - 32)
396 * to the event number which is shared between GIC and CLEC. */
397 drvHandle->clecOffset = 1024U - 32U;
398 #endif
399 #endif
401 /*
402 * UTC config init
403 */
404 /* Each UTC config */
405 utcInfo = &drvHandle->utcInfo[UDMA_UTC_ID_MSMC_DRU0];
406 utcInfo->utcId = UDMA_UTC_ID_MSMC_DRU0;
407 utcInfo->utcType = UDMA_UTC_TYPE_DRU;
408 utcInfo->startCh = UDMA_UTC_START_CH_DRU0;
409 utcInfo->numCh = UDMA_UTC_NUM_CH_DRU0;
410 utcInfo->startThreadId = UDMA_UTC_START_THREAD_ID_DRU0;
411 utcInfo->txCredit = 2U;
412 utcInfo->druRegs = ((CSL_DRU_t *) UDMA_UTC_BASE_DRU0);
413 utcInfo->numQueue = CSL_NAVSS_UTC_MSMC_DRU_QUEUE_CNT;
415 utcInfo = &drvHandle->utcInfo[UDMA_UTC_ID_VPAC_TC0];
416 utcInfo->utcId = UDMA_UTC_ID_VPAC_TC0;
417 utcInfo->utcType = UDMA_UTC_TYPE_DRU_VHWA;
418 utcInfo->startCh = UDMA_UTC_START_CH_VPAC_TC0;
419 utcInfo->numCh = UDMA_UTC_NUM_CH_VPAC_TC0;
420 utcInfo->startThreadId = UDMA_UTC_START_THREAD_ID_VPAC_TC0;
421 utcInfo->txCredit = 3U;
422 utcInfo->druRegs = ((CSL_DRU_t *) CSL_VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_BASE);
423 utcInfo->numQueue = CSL_NAVSS_UTC_VPAC_TC0_QUEUE_CNT;
425 utcInfo = &drvHandle->utcInfo[UDMA_UTC_ID_VPAC_TC1];
426 utcInfo->utcId = UDMA_UTC_ID_VPAC_TC1;
427 utcInfo->utcType = UDMA_UTC_TYPE_DRU_VHWA;
428 utcInfo->startCh = UDMA_UTC_START_CH_VPAC_TC1;
429 utcInfo->numCh = UDMA_UTC_NUM_CH_VPAC_TC1;
430 utcInfo->startThreadId = UDMA_UTC_START_THREAD_ID_VPAC_TC1;
431 utcInfo->txCredit = 3U;
432 utcInfo->druRegs = ((CSL_DRU_t *) CSL_VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_BASE);
433 utcInfo->numQueue = CSL_NAVSS_UTC_VPAC_TC1_QUEUE_CNT;
435 utcInfo = &drvHandle->utcInfo[UDMA_UTC_ID_DMPAC_TC0];
436 utcInfo->utcId = UDMA_UTC_ID_DMPAC_TC0;
437 utcInfo->utcType = UDMA_UTC_TYPE_DRU_VHWA;
438 utcInfo->startCh = UDMA_UTC_START_CH_DMPAC_TC0;
439 utcInfo->numCh = UDMA_UTC_NUM_CH_DMPAC_TC0;
440 utcInfo->startThreadId = UDMA_UTC_START_THREAD_ID_DMPAC_TC0;
441 utcInfo->txCredit = 3U;
442 utcInfo->druRegs = ((CSL_DRU_t *) CSL_DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_BASE);
443 utcInfo->numQueue = CSL_NAVSS_UTC_DMPAC_QUEUE_CNT;
445 /*
446 * Proxy init
447 */
448 pProxyCfg = &drvHandle->proxyCfg;
449 pProxyTargetRing = &drvHandle->proxyTargetRing;
450 if(UDMA_INST_ID_MCU_0 == instId)
451 {
452 pProxyTargetRing->pTargetRegs = (CSL_proxy_target0Regs *) CSL_MCU_NAVSS0_PROXY0_TARGET0_DATA_BASE;
453 pProxyTargetRing->numChns = CSL_NAVSS_MCU_PROXY_TARGET_RINGACC0_NUM_CHANNELS;
454 pProxyTargetRing->chnSizeBytes = CSL_NAVSS_MCU_PROXY_TARGET_RINGACC0_NUM_CHANNEL_SIZE_BYTES;
456 pProxyCfg->pGlbRegs = (CSL_proxyRegs *) CSL_MCU_NAVSS0_PROXY_CFG_GCFG_BASE;
457 pProxyCfg->pCfgRegs = (CSL_proxy_cfgRegs *) CSL_MCU_NAVSS0_PROXY0_BUF_CFG_BASE;
458 pProxyCfg->bufferSizeBytes = CSL_NAVSS_MCU_PROXY_BUFFER_SIZE_BYTES;
459 pProxyCfg->numTargets = 1U;
460 pProxyCfg->pProxyTargetParams = pProxyTargetRing;
462 drvHandle->proxyTargetNumRing = CSL_NAVSS_MCU_PROXY_TARGET_NUM_RINGACC0;
463 }
464 else
465 {
466 pProxyTargetRing->pTargetRegs = (CSL_proxy_target0Regs *) CSL_NAVSS0_PROXY_TARGET0_DATA_BASE;
467 pProxyTargetRing->numChns = CSL_NAVSS_MAIN_PROXY_TARGET_RINGACC0_NUM_CHANNELS;
468 pProxyTargetRing->chnSizeBytes = CSL_NAVSS_MAIN_PROXY_TARGET_RINGACC0_NUM_CHANNEL_SIZE_BYTES;
470 pProxyCfg->pGlbRegs = (CSL_proxyRegs *) CSL_NAVSS0_PROXY0_CFG_BUF_CFG_BASE;
471 pProxyCfg->pCfgRegs = (CSL_proxy_cfgRegs *) CSL_NAVSS0_PROXY0_BUF_CFG_BASE;
472 pProxyCfg->bufferSizeBytes = CSL_NAVSS_MAIN_PROXY_BUFFER_SIZE_BYTES;
473 pProxyCfg->numTargets = 1U;
474 pProxyCfg->pProxyTargetParams = pProxyTargetRing;
476 drvHandle->proxyTargetNumRing = CSL_NAVSS_MAIN_PROXY_TARGET_NUM_RINGACC0;
477 }
479 /* Init other variables */
480 if(UDMA_INST_ID_MCU_0 == instId)
481 {
482 drvHandle->udmapSrcThreadOffset = CSL_PSILCFG_NAVSS_MCU_UDMAP0_TSTRM_THREAD_OFFSET;
483 drvHandle->udmapDestThreadOffset= CSL_PSILCFG_NAVSS_MCU_UDMAP0_RSTRM_THREAD_OFFSET;
484 drvHandle->maxRings = CSL_NAVSS_MCU_RINGACC_RING_CNT;
485 drvHandle->maxProxy = CSL_NAVSS_MCU_PROXY_NUM_PROXIES;
486 drvHandle->maxRingMon = CSL_NAVSS_MCU_RINGACC_NUM_MONITORS;
487 drvHandle->devIdRing = TISCI_DEV_MCU_NAVSS0_RINGACC0;
488 drvHandle->devIdProxy = TISCI_DEV_MCU_NAVSS0_PROXY0;
489 drvHandle->devIdUdma = TISCI_DEV_MCU_NAVSS0_UDMAP_0;
490 drvHandle->devIdPsil = TISCI_DEV_MCU_NAVSS0;
491 }
492 else
493 {
494 drvHandle->udmapSrcThreadOffset = CSL_PSILCFG_NAVSS_MAIN_UDMAP0_TSTRM_THREAD_OFFSET;
495 drvHandle->udmapDestThreadOffset= CSL_PSILCFG_NAVSS_MAIN_UDMAP0_RSTRM_THREAD_OFFSET;
496 drvHandle->maxRings = CSL_NAVSS_MAIN_RINGACC_RING_CNT;
497 drvHandle->maxProxy = CSL_NAVSS_MAIN_PROXY_NUM_PROXIES;
498 drvHandle->maxRingMon = CSL_NAVSS_MAIN_RINGACC_NUM_MONITORS;
499 drvHandle->devIdRing = TISCI_DEV_NAVSS0_RINGACC_0;
500 drvHandle->devIdProxy = TISCI_DEV_NAVSS0_PROXY_0;
501 drvHandle->devIdUdma = TISCI_DEV_NAVSS0_UDMAP_0;
502 drvHandle->devIdPsil = TISCI_DEV_NAVSS0;
503 }
504 drvHandle->srcIdRingIrq = drvHandle->devIdRing;
505 drvHandle->blkCopyRingIrqOffset = TISCI_RINGACC0_OES_IRQ_SRC_IDX_START;
506 drvHandle->txRingIrqOffset = TISCI_RINGACC0_OES_IRQ_SRC_IDX_START;
507 drvHandle->rxRingIrqOffset = TISCI_RINGACC0_OES_IRQ_SRC_IDX_START;
508 drvHandle->srcIdTrIrq = drvHandle->devIdUdma;
509 drvHandle->blkCopyTrIrqOffset = TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START;
510 drvHandle->txTrIrqOffset = TISCI_UDMAP0_TX_OES_IRQ_SRC_IDX_START;
511 drvHandle->rxTrIrqOffset = TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START;
512 drvHandle->txChOffset = 0U;
513 drvHandle->extChOffset = drvHandle->txChOffset + pUdmapRegs->txChanCnt;
514 drvHandle->rxChOffset =
515 drvHandle->extChOffset + pUdmapRegs->txExtUtcChanCnt;
517 return;
518 }
520 uint32_t Udma_getCoreId(void)
521 {
522 uint32_t coreId;
524 #if defined (BUILD_MPU1_0)
525 coreId = UDMA_CORE_ID_MPU1_0;
526 #endif
527 #if defined (BUILD_MCU2_0)
528 coreId = UDMA_CORE_ID_MCU2_0;
529 #endif
530 #if defined (BUILD_MCU2_1)
531 coreId = UDMA_CORE_ID_MCU2_1;
532 #endif
533 #if defined (BUILD_MCU3_0)
534 coreId = UDMA_CORE_ID_MCU3_0;
535 #endif
536 #if defined (BUILD_MCU3_1)
537 coreId = UDMA_CORE_ID_MCU3_1;
538 #endif
539 #if defined (BUILD_C7X_1)
540 coreId = UDMA_CORE_ID_C7X_1;
541 #endif
542 #if defined (BUILD_C66X_1)
543 coreId = UDMA_CORE_ID_C66X_1;
544 #endif
545 #if defined (BUILD_C66X_2)
546 coreId = UDMA_CORE_ID_C66X_2;
547 #endif
548 #if defined (BUILD_MCU1_0)
549 coreId = UDMA_CORE_ID_MCU1_0;
550 #endif
551 #if defined (BUILD_MCU1_1)
552 coreId = UDMA_CORE_ID_MCU1_1;
553 #endif
555 return (coreId);
556 }
558 uint32_t Udma_isCacheCoherent(void)
559 {
560 uint32_t isCacheCoherent;
562 #if defined (BUILD_MPU1_0)
563 isCacheCoherent = TRUE;
564 #else
565 isCacheCoherent = FALSE;
566 #endif
568 return (isCacheCoherent);
569 }