1 /*
2 * Copyright (c) Texas Instruments Incorporated 2018-2022
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /**
34 * \file udma_soc.h
35 *
36 * \brief UDMA Low Level Driver J784S4 SOC specific file.
37 */
39 #ifndef UDMA_SOC_H_
40 #define UDMA_SOC_H_
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
46 /* None */
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
52 /* ========================================================================== */
53 /* Macros & Typedefs */
54 /* ========================================================================== */
57 /* Macro to find maximum of given values */
58 #define UDMA_MAX(X,Y) (X>Y ? X:Y)
59 /**
60 * \anchor Udma_InstanceIdSoc
61 * \name UDMA Instance ID specific to SOC
62 *
63 * UDMA instance ID - Main/MCU NAVSS
64 *
65 * @{
66 */
67 /** \brief Main NAVSS UDMA instance */
68 #define UDMA_INST_ID_MAIN_0 (UDMA_INST_ID_0)
69 /** \brief MCU NAVSS UDMA instance */
70 #define UDMA_INST_ID_MCU_0 (UDMA_INST_ID_1)
71 /** \brief BCDMA instance */
72 #define UDMA_INST_ID_BCDMA_0 (UDMA_INST_ID_2)
73 /** \brief Start of UDMA instance */
74 #define UDMA_INST_ID_START (UDMA_INST_ID_0)
75 /** \brief Maximum number of UDMA instance */
76 #define UDMA_INST_ID_MAX (UDMA_INST_ID_2)
77 /** \brief Total number of UDMA instances */
78 #define UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U)
79 /* @} */
81 /**
82 * \anchor Udma_SocCfg
83 * \name UDMA SOC Configuration
84 *
85 * UDMA Soc Cfg - Flags to indicate the presnce of various SOC specific modules.
86 *
87 * @{
88 */
89 /** \brief Flag to indicate UDMAP module is present or not in the SOC*/
90 #define UDMA_SOC_CFG_UDMAP_PRESENT (1U)
92 /** \brief Flag to indicate BCDMA module is present or not in the SOC*/
93 #define UDMA_SOC_CFG_BCDMA_PRESENT (1U)
95 /** \brief Flag to indicate PKTDMA module is present or not in the SOC*/
96 #define UDMA_SOC_CFG_PKTDMA_PRESENT (0U)
98 /** \brief Flag to indicate Proxy is present or not in the SOC*/
99 #define UDMA_SOC_CFG_PROXY_PRESENT (1U)
101 /** \brief Flag to indicate Interrupt Router is present or not in the SOC*/
102 #define UDMA_SOC_CFG_INTR_ROUTER_PRESENT (1U)
104 /** \brief Flag to indicate Clec is present or not in the SOC*/
105 #define UDMA_SOC_CFG_CLEC_PRESENT (1U)
107 /** \brief Flag to indicate Normal RA is present or not in the SOC*/
108 #define UDMA_SOC_CFG_RA_NORMAL_PRESENT (1U)
110 /** \brief Flag to indicate LCDMA RA is present or not in the SOC*/
111 #define UDMA_SOC_CFG_RA_LCDMA_PRESENT (1U)
113 /** \brief Flag to indicate Ring Monitor is present or not in the SOC*/
114 #define UDMA_SOC_CFG_RING_MON_PRESENT (1U)
116 /** \brief Flag to indicate VPAC1 is present or not in the SOC*/
117 #define UDMA_SOC_CFG_VPAC1_PRESENT (1U)
119 /** \brief Flag to indicate the SOC needs ring reset workaround */
120 #define UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U)
122 /* Flag to indicate DRU local to C7X cores is present or not in the SoC */
123 #define UDMA_LOCAL_C7X_DRU_PRESENT (1U)
124 /* @} */
126 /**
127 * \anchor Udma_TxChFdepth
128 * \name UDMA Tx Channels FDEPTH
129 *
130 * UDMA Tx Ch Fdepth - Fdepth of various types of channels present in the SOC.
131 *
132 * @{
133 */
134 /** \brief Tx Ultra High Capacity Channel FDEPTH*/
135 #define UDMA_TX_UHC_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_UHC_CHANS_FDEPTH)
136 /** \brief Tx High Capacity Channel FDEPTH*/
137 #define UDMA_TX_HC_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_HC_CHANS_FDEPTH)
138 /** \brief Tx Normal Channel FDEPTH*/
139 #define UDMA_TX_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_CHANS_FDEPTH)
140 /* @} */
142 /**
143 * \anchor Udma_RingAccAselEndpointSoc
144 * \name UDMA Ringacc address select (asel) endpoint
145 *
146 * List of all valid address select (asel) endpoints in the SOC.
147 *
148 * @{
149 */
150 /** \brief Physical address (normal) */
151 #define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR (0U)
152 /* @} */
154 /** \brief Invalid Ring Mode*/
155 #define UDMA_RING_MODE_INVALID (CSL_RINGACC_RING_MODE_INVALID)
157 /** \brief Number of Mapped TX Group */
158 #define UDMA_NUM_MAPPED_TX_GROUP (0U)
159 /**
160 * \anchor Udma_MappedTxGrpSoc
161 * \name Mapped TX Group specific to a SOC
162 *
163 * List of all mapped TX groups present in the SOC.
164 *
165 * @{
166 */
167 /* No mapped TX channels/rings in J784S4 */
168 /* @} */
170 /** \brief Number of Mapped RX Group */
171 #define UDMA_NUM_MAPPED_RX_GROUP (0U)
172 /**
173 * \anchor Udma_MappedRxGrpSoc
174 * \name Mapped RX Group specific to a SOC
175 *
176 * List of all mapped RX groups present in the SOC.
177 *
178 * @{
179 */
180 /* No mapped RX channels/rings in J784S4 */
181 /* @} */
183 /** \brief Number of UTC instance */
184 #define UDMA_NUM_UTC_INSTANCE (CSL_NAVSS_UTC_CNT)
186 /**
187 * \anchor Udma_UtcIdSoc
188 * \name UTC ID specific to a SOC
189 *
190 * List of all UTC's present in the SOC.
191 *
192 * @{
193 */
194 #define UDMA_UTC_ID_MSMC_DRU0 (UDMA_UTC_ID0)
195 #define UDMA_UTC_ID_VPAC_TC0 (UDMA_UTC_ID1)
196 #define UDMA_UTC_ID_VPAC_TC1 (UDMA_UTC_ID2)
197 #define UDMA_UTC_ID_VPAC1_TC0 (UDMA_UTC_ID3)
198 #define UDMA_UTC_ID_VPAC1_TC1 (UDMA_UTC_ID4)
199 #define UDMA_UTC_ID_DMPAC_TC0 (UDMA_UTC_ID5)
200 /* List of DRUs local to C7X */
201 #define UDMA_UTC_ID_C7X_MSMC_DRU4 (UDMA_UTC_ID6)
202 #define UDMA_UTC_ID_C7X_MSMC_DRU5 (UDMA_UTC_ID7)
203 #define UDMA_UTC_ID_C7X_MSMC_DRU6 (UDMA_UTC_ID8)
204 #define UDMA_UTC_ID_C7X_MSMC_DRU7 (UDMA_UTC_ID9)
205 #define UDMA_LOCAL_UTC_START (UDMA_UTC_ID_C7X_MSMC_DRU4)
206 #define UDMA_LOCAL_UTC_MAX (UDMA_UTC_ID_C7X_MSMC_DRU7)
207 #define UDMA_LOCAL_UTC_NUM (UDMA_LOCAL_UTC_MAX - UDMA_LOCAL_UTC_START + 1U)
208 /* @} */
209 /** \brief External start channel of DRU0 UTC */
210 #define UDMA_UTC_START_CH_DRU0 (0U)
211 /** \brief Number of channels present in DRU0 UTC */
212 #define UDMA_UTC_NUM_CH_DRU0 (CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILS_THREAD_CNT)
213 /** \brief Start thread ID of DRU0 UTC */
214 #define UDMA_UTC_START_THREAD_ID_DRU0 (CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILD_THREAD_OFFSET)
216 /** \brief External start channel of VPAC TC0 UTC */
217 #define UDMA_UTC_START_CH_VPAC_TC0 (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_OFFSET \
218 - CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILS_THREAD_OFFSET)
219 /** \brief Number of channels present in VPAC TC0 UTC */
220 #define UDMA_UTC_NUM_CH_VPAC_TC0 (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_CNT)
221 /** \brief Start thread ID of VPAC TC0 UTC */
222 #define UDMA_UTC_START_THREAD_ID_VPAC_TC0 (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILD_THREAD_OFFSET)
224 /** \brief External start channel of VPAC TC1 UTC */
225 #define UDMA_UTC_START_CH_VPAC_TC1 (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILS_THREAD_OFFSET \
226 - CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILS_THREAD_OFFSET)
227 /** \brief Number of channels present in VPAC TC1 UTC */
228 #define UDMA_UTC_NUM_CH_VPAC_TC1 (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILS_THREAD_CNT)
229 /** \brief Start thread ID of VPAC TC1 UTC */
230 #define UDMA_UTC_START_THREAD_ID_VPAC_TC1 (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILD_THREAD_OFFSET)
232 /** \brief External start channel of VPAC1 TC0 UTC */
233 #define UDMA_UTC_START_CH_VPAC1_TC0 (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC0_CC_PSILS_THREAD_OFFSET \
234 - CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILS_THREAD_OFFSET)
235 /** \brief Number of channels present in VPAC1 TC0 UTC */
236 #define UDMA_UTC_NUM_CH_VPAC1_TC0 (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC0_CC_PSILS_THREAD_CNT)
237 /** \brief Start thread ID of VPAC1 TC0 UTC */
238 #define UDMA_UTC_START_THREAD_ID_VPAC1_TC0 (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC0_CC_PSILD_THREAD_OFFSET)
240 /** \brief External start channel of VPAC1 TC1 UTC */
241 #define UDMA_UTC_START_CH_VPAC1_TC1 (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC1_CC_PSILS_THREAD_OFFSET \
242 - CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILS_THREAD_OFFSET)
243 /** \brief Number of channels present in VPAC TC1 UTC */
244 #define UDMA_UTC_NUM_CH_VPAC1_TC1 (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC1_CC_PSILS_THREAD_CNT)
245 /** \brief Start thread ID of VPAC1 TC1 UTC */
246 #define UDMA_UTC_START_THREAD_ID_VPAC1_TC1 (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC1_CC_PSILD_THREAD_OFFSET)
248 /** \brief External start channel of DMPAC TC0 UTC */
249 #define UDMA_UTC_START_CH_DMPAC_TC0 (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILS_THREAD_OFFSET \
250 - CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILS_THREAD_OFFSET)
251 /** \brief Number of channels present in DMPAC TC0 UTC */
252 #define UDMA_UTC_NUM_CH_DMPAC_TC0 (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILS_THREAD_CNT)
253 /** \brief Start thread ID of DMPAC TC0 UTC */
254 #define UDMA_UTC_START_THREAD_ID_DMPAC_TC0 (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILD_THREAD_OFFSET)
255 /* Channel information for local DRU channels */
256 /** \brief Start channel of DRU4 UTC */
257 #define UDMA_UTC_START_CH_DRU4 (0U)
258 /** \brief Number of channels present in DRU4 UTC */
259 #define UDMA_UTC_NUM_CH_DRU4 (32U)
260 /** \brief Start channel of DRU5 UTC */
261 #define UDMA_UTC_START_CH_DRU5 (0U)
262 /** \brief Number of channels present in DRU5 UTC */
263 #define UDMA_UTC_NUM_CH_DRU5 (32U)
264 /** \brief Start channel of DRU6 UTC */
265 #define UDMA_UTC_START_CH_DRU6 (0U)
266 /** \brief Number of channels present in DRU6 UTC */
267 #define UDMA_UTC_NUM_CH_DRU6 (32U)
268 /** \brief Start channel of DRU7 UTC */
269 #define UDMA_UTC_START_CH_DRU7 (0U)
270 /** \brief Number of channels present in DRU7 UTC */
271 #define UDMA_UTC_NUM_CH_DRU7 (32U)
273 /**
274 * \anchor Udma_CoreId
275 * \name Core ID specific to a SOC
276 *
277 * List of all cores present in the SOC.
278 *
279 * @{
280 */
281 /*
282 * Locally used core ID to define default RM configuration.
283 * Not to be used by caller
284 */
285 /* Main domain cores */
286 #define UDMA_CORE_ID_MPU1_0 (0U)
287 #define UDMA_CORE_ID_MCU2_0 (1U)
288 #define UDMA_CORE_ID_MCU2_1 (2U)
289 #define UDMA_CORE_ID_MCU3_0 (3U)
290 #define UDMA_CORE_ID_MCU3_1 (4U)
291 #define UDMA_CORE_ID_MCU4_0 (5U)
292 #define UDMA_CORE_ID_MCU4_1 (6U)
293 #define UDMA_CORE_ID_C7X_1 (7U)
294 #define UDMA_CORE_ID_C7X_2 (8U)
295 #define UDMA_CORE_ID_C7X_3 (9U)
296 #define UDMA_CORE_ID_C7X_4 (10U)
297 #define UDMA_NUM_C7X_CORE (UDMA_CORE_ID_C7X_4 - UDMA_CORE_ID_C7X_1 + 1U)
298 #define UDMA_NUM_MAIN_CORE (11U)
299 /* MCU domain cores - Note: This should be after all main domain cores */
300 #define UDMA_CORE_ID_MCU1_0 (UDMA_NUM_MAIN_CORE + 0U)
301 #define UDMA_CORE_ID_MCU1_1 (UDMA_NUM_MAIN_CORE + 1U)
302 #define UDMA_NUM_MCU_CORE (2U)
303 /* Total number of cores */
304 #define UDMA_NUM_CORE (UDMA_NUM_MAIN_CORE + UDMA_NUM_MCU_CORE)
305 /* @} */
307 /**
308 * \anchor Udma_DruSubmitCoreId
309 * \name DRU core ID register to use for direct TR submission.
310 * Each CPU should have a unique submit register to avoid corrupting
311 * submit word when SW is running from multiple CPU at the same time.
312 *
313 * Note: Since only 3 submit register set is present, we need to share some
314 * of them across cores. This means that Direct TR from these cores can't
315 * run simultaneously.
316 * In this case C7x1 and C7x2 are provided unique ID which are more likely to
317 * use direct TR mode and other cores share the same core ID.
318 *
319 * List of all DRU cores ID to use for all the CPUs present in the SOC.
320 *
321 * @{
322 */
323 #define UDMA_DRU_CORE_ID_MPU1_0 (CSL_DRU_CORE_ID_2)
324 #define UDMA_DRU_CORE_ID_MCU2_0 (CSL_DRU_CORE_ID_2)
325 #define UDMA_DRU_CORE_ID_MCU2_1 (CSL_DRU_CORE_ID_2)
326 #define UDMA_DRU_CORE_ID_MCU3_0 (CSL_DRU_CORE_ID_2)
327 #define UDMA_DRU_CORE_ID_MCU3_1 (CSL_DRU_CORE_ID_2)
328 #define UDMA_DRU_CORE_ID_MCU4_0 (CSL_DRU_CORE_ID_2)
329 #define UDMA_DRU_CORE_ID_MCU4_1 (CSL_DRU_CORE_ID_2)
330 #define UDMA_DRU_CORE_ID_C7X_1 (CSL_DRU_CORE_ID_0)
331 #define UDMA_DRU_CORE_ID_C7X_2 (CSL_DRU_CORE_ID_1)
332 #define UDMA_DRU_CORE_ID_C7X_3 (CSL_DRU_CORE_ID_2)
333 #define UDMA_DRU_CORE_ID_C7X_4 (CSL_DRU_CORE_ID_2)
334 #define UDMA_DRU_CORE_ID_MCU1_0 (CSL_DRU_CORE_ID_2)
335 #define UDMA_DRU_CORE_ID_MCU1_1 (CSL_DRU_CORE_ID_2)
336 /* @} */
338 /**
339 * \anchor Udma_RmResId
340 * \name UDMA Resources ID
341 *
342 * List of all UDMA Resources Id's.
343 *
344 * @{
345 */
347 /** \brief Ultra High Capacity Block Copy Channels */
348 #define UDMA_RM_RES_ID_BC_UHC (0U)
349 /** \brief High Capacity Block Copy Channels */
350 #define UDMA_RM_RES_ID_BC_HC (1U)
351 /** \brief Normal Capacity Block Copy Channels */
352 #define UDMA_RM_RES_ID_BC (2U)
353 /* List of all UDMAP and BCDMA TX/RX Channel Resource Id's */
354 /** \brief Ultra High Capacity TX and Block Copy Channels */
355 #define UDMA_RM_RES_ID_TX_UHC (3U)
356 /** \brief High Capacity TX and Block Copy Channels */
357 #define UDMA_RM_RES_ID_TX_HC (4U)
358 /** \brief Normal Capacity TX and Block Copy Channels */
359 #define UDMA_RM_RES_ID_TX (5U)
360 /** \brief Ultra High Capacity RX Channels */
361 #define UDMA_RM_RES_ID_RX_UHC (6U)
362 /** \brief High Capacity RX Channels */
363 #define UDMA_RM_RES_ID_RX_HC (7U)
364 /** \brief Normal Capacity RX Channels */
365 #define UDMA_RM_RES_ID_RX (8U)
367 /* List of all Resources Id's shared between all Instances */
368 /** \brief Global Event */
369 #define UDMA_RM_RES_ID_GLOBAL_EVENT (9U)
370 /** \brief Virtual Interrupts */
371 #define UDMA_RM_RES_ID_VINTR (10U)
372 /** \brief Interrupt Router Interrupts */
373 #define UDMA_RM_RES_ID_IR_INTR (11U)
375 /** \brief UTC - Extended Channels (MSMC_DRU/VPAC_TC0/VPAC_TC1/DMPAC) */
376 #define UDMA_RM_RES_ID_UTC (12U)
377 /** \brief Free Flows */
378 #define UDMA_RM_RES_ID_RX_FLOW (13U)
379 /** \brief Free Rings */
380 #define UDMA_RM_RES_ID_RING (14U)
381 /** \brief Proxy */
382 #define UDMA_RM_RES_ID_PROXY (15U)
383 /** \brief Ring Monitors */
384 #define UDMA_RM_RES_ID_RING_MON (16U)
386 #if defined (BUILD_C7X)
387 /* List of all DRUs local to C7X */
388 /** \brief DRU4 local to C7X cluster */
389 #define UDMA_RM_C7X_MSMC_DRU4 (17U)
390 /** \brief DRU5 local to C7X cluster */
391 #define UDMA_RM_C7X_MSMC_DRU5 (18U)
392 /** \brief DRU6 local to C7X cluster */
393 #define UDMA_RM_C7X_MSMC_DRU6 (19U)
394 /** \brief DRU7 local to C7X cluster */
395 #define UDMA_RM_C7X_MSMC_DRU7 (20U)
396 /** \brief Start of local DRUs */
397 #define UDMA_RM_START_C7X_DRU (UDMA_RM_C7X_MSMC_DRU4)
398 /** \brief MAX of local DRUs */
399 #define UDMA_RM_MAX_C7X_DRU (UDMA_RM_C7X_MSMC_DRU7)
400 /** \brief Total number of local DRUs */
401 #define UDMA_RM_NUM_C7X_DRU (UDMA_RM_MAX_C7X_DRU - UDMA_RM_START_C7X_DRU + 1U)
402 #endif
404 /** \brief Total number of BCDMA resources */
405 #define UDMA_RM_NUM_BCDMA_RES (12U)
406 /** \brief Total number of UDMAP resources */
407 #define UDMA_RM_NUM_UDMAP_RES (17U)
410 /** \brief Total number of resources for which the range need to be queried from default BoardCfg */
411 #define UDMA_RM_DEFAULT_BOARDCFG_NUM_RES UDMA_MAX(UDMA_RM_NUM_UDMAP_RES, UDMA_RM_NUM_BCDMA_RES)
413 /* @} */
415 /** \brief Total number of shared resources -
416 * Free_Flows/Global_Event/IR Intr/VINT */
417 #if defined (BUILD_C7X)
418 /* Additional DRUs local to C7X */
419 #define UDMA_RM_NUM_SHARED_RES (8U)
420 #else
421 #define UDMA_RM_NUM_SHARED_RES (4U)
422 #endif
423 /** \brief Maximum no.of instances to split a shared resource.
424 * This should be max(UDMA_NUM_CORE,UDMA_NUM_INST_ID) */
425 #define UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE)
427 /* Start of C7x events associated to CLEC that UDMA Driver will manage */
428 /* Events 0 - 32 : left for other drivers
429 * Events 16 - 47 : For routing DRU Local Events from CLEC (done by Vision Apps/TIDL)
430 * Events 48 - 63 : managed by UDMA for routing various UDMA events to C7x */
431 #define UDMA_C7X_CORE_INTR_OFFSET (48U)
433 /**
434 * \anchor Udma_PsilCh
435 * \name PSIL Channels
436 *
437 * List of all PSIL channels across MCU and main domains
438 *
439 * @{
440 */
442 /**
443 * \anchor Udma_PsilChMain
444 * \name Main PSIL Channels
445 *
446 * List of all Main PSIL channels and the corresponding counts
447 *
448 * @{
449 */
450 #define UDMA_PSIL_CH_MAIN_SAUL0_TX (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILD_THREAD_OFFSET)
451 #define UDMA_PSIL_CH_MAIN_VPAC_TC0_TX (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILD_THREAD_OFFSET)
452 #define UDMA_PSIL_CH_MAIN_VPAC_TC1_TX (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILD_THREAD_OFFSET)
453 #define UDMA_PSIL_CH_MAIN_VPAC1_TC0_TX (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC0_CC_PSILD_THREAD_OFFSET)
454 #define UDMA_PSIL_CH_MAIN_VPAC1_TC1_TX (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC1_CC_PSILD_THREAD_OFFSET)
455 #define UDMA_PSIL_CH_MAIN_DMPAC_TC0_TX (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILD_THREAD_OFFSET)
456 #define UDMA_PSIL_CH_MAIN_CSI_TX (CSL_PSILCFG_NAVSS_MAIN_CSI_PSILD_THREAD_OFFSET)
457 #define UDMA_PSIL_CH_MAIN_CPSW2_TX (CSL_PSILCFG_NAVSS_MAIN_CPSW2_PSILD_THREAD_OFFSET)
458 #define UDMA_PSIL_CH_MAIN_CPSW_TX (CSL_PSILCFG_NAVSS_MAIN_CPSW_PSILD_THREAD_OFFSET)
460 #define UDMA_PSIL_CH_MAIN_SAUL0_RX (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILS_THREAD_OFFSET)
461 #define UDMA_PSIL_CH_MAIN_VPAC_TC0_RX (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_OFFSET)
462 #define UDMA_PSIL_CH_MAIN_VPAC_TC1_RX (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILS_THREAD_OFFSET)
463 #define UDMA_PSIL_CH_MAIN_VPAC1_TC0_RX (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC0_CC_PSILS_THREAD_OFFSET)
464 #define UDMA_PSIL_CH_MAIN_VPAC1_TC1_RX (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC1_CC_PSILS_THREAD_OFFSET)
465 #define UDMA_PSIL_CH_MAIN_DMPAC_TC0_RX (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILS_THREAD_OFFSET)
466 #define UDMA_PSIL_CH_MAIN_CSI_RX (CSL_PSILCFG_NAVSS_MAIN_CSI_PSILS_THREAD_OFFSET)
467 #define UDMA_PSIL_CH_MAIN_CPSW2_RX (CSL_PSILCFG_NAVSS_MAIN_CPSW2_PSILS_THREAD_OFFSET)
468 #define UDMA_PSIL_CH_MAIN_CPSW_RX (CSL_PSILCFG_NAVSS_MAIN_CPSW_PSILS_THREAD_OFFSET)
470 #define UDMA_PSIL_CH_MAIN_SAUL0_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILD_THREAD_CNT)
471 #define UDMA_PSIL_CH_MAIN_VPAC_TC0_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILD_THREAD_CNT)
472 #define UDMA_PSIL_CH_MAIN_VPAC_TC1_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILD_THREAD_CNT)
473 #define UDMA_PSIL_CH_MAIN_VPAC1_TC0_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC0_CC_PSILD_THREAD_CNT)
474 #define UDMA_PSIL_CH_MAIN_VPAC1_TC1_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC1_CC_PSILD_THREAD_CNT)
475 #define UDMA_PSIL_CH_MAIN_DMPAC_TC0_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILD_THREAD_CNT)
476 #define UDMA_PSIL_CH_MAIN_CSI_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_CSI_PSILD_THREAD_CNT)
477 #define UDMA_PSIL_CH_MAIN_CPSW2_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_CPSW2_PSILD_THREAD_CNT)
478 #define UDMA_PSIL_CH_MAIN_CPSW_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_CPSW_PSILD_THREAD_CNT)
480 #define UDMA_PSIL_CH_MAIN_SAUL0_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILS_THREAD_CNT)
481 #define UDMA_PSIL_CH_MAIN_VPAC_TC0_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_CNT)
482 #define UDMA_PSIL_CH_MAIN_VPAC_TC1_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILS_THREAD_CNT)
483 #define UDMA_PSIL_CH_MAIN_VPAC1_TC0_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC0_CC_PSILS_THREAD_CNT)
484 #define UDMA_PSIL_CH_MAIN_VPAC1_TC1_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_VPAC1_TC1_CC_PSILS_THREAD_CNT)
485 #define UDMA_PSIL_CH_MAIN_DMPAC_TC0_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILS_THREAD_CNT)
486 #define UDMA_PSIL_CH_MAIN_CSI_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_CSI_PSILS_THREAD_CNT)
487 #define UDMA_PSIL_CH_MAIN_CPSW2_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_CPSW2_PSILS_THREAD_CNT)
488 #define UDMA_PSIL_CH_MAIN_CPSW_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_CPSW_PSILS_THREAD_CNT)
489 /* @} */
491 /**
492 * \anchor Udma_PsilChMcu
493 * \name Mcu PSIL Channels
494 *
495 * List of all Mcu PSIL channels and the corresponding counts
496 *
497 * @{
498 */
499 #define UDMA_PSIL_CH_MCU_CPSW0_TX (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_OFFSET)
500 #define UDMA_PSIL_CH_MCU_SAUL0_TX (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILD_THREAD_OFFSET)
502 #define UDMA_PSIL_CH_MCU_CPSW0_RX (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILS_THREAD_OFFSET)
503 #define UDMA_PSIL_CH_MCU_SAUL0_RX (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILS_THREAD_OFFSET)
505 #define UDMA_PSIL_CH_MCU_CPSW0_TX_CNT (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_CNT)
506 #define UDMA_PSIL_CH_MCU_SAUL0_TX_CNT (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILD_THREAD_CNT)
508 #define UDMA_PSIL_CH_MCU_CPSW0_RX_CNT (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILS_THREAD_CNT)
509 #define UDMA_PSIL_CH_MCU_SAUL0_RX_CNT (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILS_THREAD_CNT)
510 /* @} */
512 /* @} */
514 /**
515 * \anchor Udma_PdmaCh
516 * \name PDMA Channels
517 *
518 * List of all PDMA channels across MCU and main domains
519 *
520 * @{
521 */
523 /**
524 * \anchor Udma_PdmaChMainTx
525 * \name Main TX PDMA Channels
526 *
527 * List of all Main PDMA TX channels
528 *
529 * @{
530 */
531 /*
532 * PDMA Main McASP TX Channels
533 */
534 #define UDMA_PDMA_CH_MAIN_MCASP0_TX (CSL_PDMA_CH_MAIN_MCASP0_CH0_TX)
535 #define UDMA_PDMA_CH_MAIN_MCASP1_TX (CSL_PDMA_CH_MAIN_MCASP1_CH0_TX)
536 #define UDMA_PDMA_CH_MAIN_MCASP2_TX (CSL_PDMA_CH_MAIN_MCASP2_CH0_TX)
537 #define UDMA_PDMA_CH_MAIN_MCASP3_TX (CSL_PDMA_CH_MAIN_MCASP3_CH0_TX)
538 #define UDMA_PDMA_CH_MAIN_MCASP4_TX (CSL_PDMA_CH_MAIN_MCASP4_CH0_TX)
539 /*
540 * PDMA Main UART TX Channels
541 */
542 #define UDMA_PDMA_CH_MAIN_UART0_TX (CSL_PDMA_CH_MAIN_UART0_CH0_TX)
543 #define UDMA_PDMA_CH_MAIN_UART1_TX (CSL_PDMA_CH_MAIN_UART1_CH0_TX)
544 #define UDMA_PDMA_CH_MAIN_UART2_TX (CSL_PDMA_CH_MAIN_UART2_CH0_TX)
545 #define UDMA_PDMA_CH_MAIN_UART3_TX (CSL_PDMA_CH_MAIN_UART3_CH0_TX)
546 #define UDMA_PDMA_CH_MAIN_UART4_TX (CSL_PDMA_CH_MAIN_UART4_CH0_TX)
547 #define UDMA_PDMA_CH_MAIN_UART5_TX (CSL_PDMA_CH_MAIN_UART5_CH0_TX)
548 #define UDMA_PDMA_CH_MAIN_UART6_TX (CSL_PDMA_CH_MAIN_UART6_CH0_TX)
549 #define UDMA_PDMA_CH_MAIN_UART7_TX (CSL_PDMA_CH_MAIN_UART7_CH0_TX)
550 #define UDMA_PDMA_CH_MAIN_UART8_TX (CSL_PDMA_CH_MAIN_UART8_CH0_TX)
551 #define UDMA_PDMA_CH_MAIN_UART9_TX (CSL_PDMA_CH_MAIN_UART9_CH0_TX)
552 /*
553 * PDMA Main McSPI TX Channels
554 */
555 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH0_TX)
556 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH1_TX)
557 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH2_TX)
558 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH3_TX)
559 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH0_TX)
560 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH1_TX)
561 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH2_TX)
562 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH3_TX)
563 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH0_TX)
564 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH1_TX)
565 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH2_TX)
566 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH3_TX)
567 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH0_TX)
568 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH1_TX)
569 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH2_TX)
570 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH3_TX)
571 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH0_TX)
572 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH1_TX)
573 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH2_TX)
574 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH3_TX)
575 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH0_TX)
576 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH1_TX)
577 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH2_TX)
578 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH3_TX)
579 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH0_TX)
580 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH1_TX)
581 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH2_TX)
582 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH3_TX)
583 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH0_TX)
584 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH1_TX)
585 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH2_TX)
586 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH3_TX)
587 /*
588 * PDMA MAIN MCAN TX Channels
589 */
590 #define UDMA_PDMA_CH_MAIN_MCAN0_CH0_TX (CSL_PDMA_CH_MAIN_MCAN0_CH0_TX)
591 #define UDMA_PDMA_CH_MAIN_MCAN0_CH1_TX (CSL_PDMA_CH_MAIN_MCAN0_CH1_TX)
592 #define UDMA_PDMA_CH_MAIN_MCAN0_CH2_TX (CSL_PDMA_CH_MAIN_MCAN0_CH2_TX)
593 #define UDMA_PDMA_CH_MAIN_MCAN1_CH0_TX (CSL_PDMA_CH_MAIN_MCAN1_CH0_TX)
594 #define UDMA_PDMA_CH_MAIN_MCAN1_CH1_TX (CSL_PDMA_CH_MAIN_MCAN1_CH1_TX)
595 #define UDMA_PDMA_CH_MAIN_MCAN1_CH2_TX (CSL_PDMA_CH_MAIN_MCAN1_CH2_TX)
596 #define UDMA_PDMA_CH_MAIN_MCAN2_CH0_TX (CSL_PDMA_CH_MAIN_MCAN2_CH0_TX)
597 #define UDMA_PDMA_CH_MAIN_MCAN2_CH1_TX (CSL_PDMA_CH_MAIN_MCAN2_CH1_TX)
598 #define UDMA_PDMA_CH_MAIN_MCAN2_CH2_TX (CSL_PDMA_CH_MAIN_MCAN2_CH2_TX)
599 #define UDMA_PDMA_CH_MAIN_MCAN3_CH0_TX (CSL_PDMA_CH_MAIN_MCAN3_CH0_TX)
600 #define UDMA_PDMA_CH_MAIN_MCAN3_CH1_TX (CSL_PDMA_CH_MAIN_MCAN3_CH1_TX)
601 #define UDMA_PDMA_CH_MAIN_MCAN3_CH2_TX (CSL_PDMA_CH_MAIN_MCAN3_CH2_TX)
602 #define UDMA_PDMA_CH_MAIN_MCAN4_CH0_TX (CSL_PDMA_CH_MAIN_MCAN4_CH0_TX)
603 #define UDMA_PDMA_CH_MAIN_MCAN4_CH1_TX (CSL_PDMA_CH_MAIN_MCAN4_CH1_TX)
604 #define UDMA_PDMA_CH_MAIN_MCAN4_CH2_TX (CSL_PDMA_CH_MAIN_MCAN4_CH2_TX)
605 #define UDMA_PDMA_CH_MAIN_MCAN5_CH0_TX (CSL_PDMA_CH_MAIN_MCAN5_CH0_TX)
606 #define UDMA_PDMA_CH_MAIN_MCAN5_CH1_TX (CSL_PDMA_CH_MAIN_MCAN5_CH1_TX)
607 #define UDMA_PDMA_CH_MAIN_MCAN5_CH2_TX (CSL_PDMA_CH_MAIN_MCAN5_CH2_TX)
608 #define UDMA_PDMA_CH_MAIN_MCAN6_CH0_TX (CSL_PDMA_CH_MAIN_MCAN6_CH0_TX)
609 #define UDMA_PDMA_CH_MAIN_MCAN6_CH1_TX (CSL_PDMA_CH_MAIN_MCAN6_CH1_TX)
610 #define UDMA_PDMA_CH_MAIN_MCAN6_CH2_TX (CSL_PDMA_CH_MAIN_MCAN6_CH2_TX)
611 #define UDMA_PDMA_CH_MAIN_MCAN7_CH0_TX (CSL_PDMA_CH_MAIN_MCAN7_CH0_TX)
612 #define UDMA_PDMA_CH_MAIN_MCAN7_CH1_TX (CSL_PDMA_CH_MAIN_MCAN7_CH1_TX)
613 #define UDMA_PDMA_CH_MAIN_MCAN7_CH2_TX (CSL_PDMA_CH_MAIN_MCAN7_CH2_TX)
614 #define UDMA_PDMA_CH_MAIN_MCAN8_CH0_TX (CSL_PDMA_CH_MAIN_MCAN8_CH0_TX)
615 #define UDMA_PDMA_CH_MAIN_MCAN8_CH1_TX (CSL_PDMA_CH_MAIN_MCAN8_CH1_TX)
616 #define UDMA_PDMA_CH_MAIN_MCAN8_CH2_TX (CSL_PDMA_CH_MAIN_MCAN8_CH2_TX)
617 #define UDMA_PDMA_CH_MAIN_MCAN9_CH0_TX (CSL_PDMA_CH_MAIN_MCAN9_CH0_TX)
618 #define UDMA_PDMA_CH_MAIN_MCAN9_CH1_TX (CSL_PDMA_CH_MAIN_MCAN9_CH1_TX)
619 #define UDMA_PDMA_CH_MAIN_MCAN9_CH2_TX (CSL_PDMA_CH_MAIN_MCAN9_CH2_TX)
620 #define UDMA_PDMA_CH_MAIN_MCAN10_CH0_TX (CSL_PDMA_CH_MAIN_MCAN10_CH0_TX)
621 #define UDMA_PDMA_CH_MAIN_MCAN10_CH1_TX (CSL_PDMA_CH_MAIN_MCAN10_CH1_TX)
622 #define UDMA_PDMA_CH_MAIN_MCAN10_CH2_TX (CSL_PDMA_CH_MAIN_MCAN10_CH2_TX)
623 #define UDMA_PDMA_CH_MAIN_MCAN11_CH0_TX (CSL_PDMA_CH_MAIN_MCAN11_CH0_TX)
624 #define UDMA_PDMA_CH_MAIN_MCAN11_CH1_TX (CSL_PDMA_CH_MAIN_MCAN11_CH1_TX)
625 #define UDMA_PDMA_CH_MAIN_MCAN11_CH2_TX (CSL_PDMA_CH_MAIN_MCAN11_CH2_TX)
626 #define UDMA_PDMA_CH_MAIN_MCAN12_CH0_TX (CSL_PDMA_CH_MAIN_MCAN12_CH0_TX)
627 #define UDMA_PDMA_CH_MAIN_MCAN12_CH1_TX (CSL_PDMA_CH_MAIN_MCAN12_CH1_TX)
628 #define UDMA_PDMA_CH_MAIN_MCAN12_CH2_TX (CSL_PDMA_CH_MAIN_MCAN12_CH2_TX)
629 #define UDMA_PDMA_CH_MAIN_MCAN13_CH0_TX (CSL_PDMA_CH_MAIN_MCAN13_CH0_TX)
630 #define UDMA_PDMA_CH_MAIN_MCAN13_CH1_TX (CSL_PDMA_CH_MAIN_MCAN13_CH1_TX)
631 #define UDMA_PDMA_CH_MAIN_MCAN13_CH2_TX (CSL_PDMA_CH_MAIN_MCAN13_CH2_TX)
632 #define UDMA_PDMA_CH_MAIN_MCAN14_CH0_TX (CSL_PDMA_CH_MAIN_MCAN14_CH0_TX)
633 #define UDMA_PDMA_CH_MAIN_MCAN14_CH1_TX (CSL_PDMA_CH_MAIN_MCAN14_CH1_TX)
634 #define UDMA_PDMA_CH_MAIN_MCAN14_CH2_TX (CSL_PDMA_CH_MAIN_MCAN14_CH2_TX)
635 #define UDMA_PDMA_CH_MAIN_MCAN15_CH0_TX (CSL_PDMA_CH_MAIN_MCAN15_CH0_TX)
636 #define UDMA_PDMA_CH_MAIN_MCAN15_CH1_TX (CSL_PDMA_CH_MAIN_MCAN15_CH1_TX)
637 #define UDMA_PDMA_CH_MAIN_MCAN15_CH2_TX (CSL_PDMA_CH_MAIN_MCAN15_CH2_TX)
638 #define UDMA_PDMA_CH_MAIN_MCAN16_CH0_TX (CSL_PDMA_CH_MAIN_MCAN16_CH0_TX)
639 #define UDMA_PDMA_CH_MAIN_MCAN16_CH1_TX (CSL_PDMA_CH_MAIN_MCAN16_CH1_TX)
640 #define UDMA_PDMA_CH_MAIN_MCAN16_CH2_TX (CSL_PDMA_CH_MAIN_MCAN16_CH2_TX)
641 #define UDMA_PDMA_CH_MAIN_MCAN17_CH0_TX (CSL_PDMA_CH_MAIN_MCAN17_CH0_TX)
642 #define UDMA_PDMA_CH_MAIN_MCAN17_CH1_TX (CSL_PDMA_CH_MAIN_MCAN17_CH1_TX)
643 #define UDMA_PDMA_CH_MAIN_MCAN17_CH2_TX (CSL_PDMA_CH_MAIN_MCAN17_CH2_TX)
644 /* @} */
646 /**
647 * \anchor Udma_PdmaChMcuTx
648 * \name MCU TX PDMA Channels
649 *
650 * List of all MCU PDMA TX channels
651 *
652 * @{
653 */
654 /*
655 * PDMA MCU McSPI TX Channels
656 */
657 #define UDMA_PDMA_CH_MCU_MCSPI0_CH0_TX (CSL_PDMA_CH_MCU_MCSPI0_CH0_TX)
658 #define UDMA_PDMA_CH_MCU_MCSPI0_CH1_TX (CSL_PDMA_CH_MCU_MCSPI0_CH1_TX)
659 #define UDMA_PDMA_CH_MCU_MCSPI0_CH2_TX (CSL_PDMA_CH_MCU_MCSPI0_CH2_TX)
660 #define UDMA_PDMA_CH_MCU_MCSPI0_CH3_TX (CSL_PDMA_CH_MCU_MCSPI0_CH3_TX)
661 #define UDMA_PDMA_CH_MCU_MCSPI1_CH0_TX (CSL_PDMA_CH_MCU_MCSPI1_CH0_TX)
662 #define UDMA_PDMA_CH_MCU_MCSPI1_CH1_TX (CSL_PDMA_CH_MCU_MCSPI1_CH1_TX)
663 #define UDMA_PDMA_CH_MCU_MCSPI1_CH2_TX (CSL_PDMA_CH_MCU_MCSPI1_CH2_TX)
664 #define UDMA_PDMA_CH_MCU_MCSPI1_CH3_TX (CSL_PDMA_CH_MCU_MCSPI1_CH3_TX)
665 #define UDMA_PDMA_CH_MCU_MCSPI2_CH0_TX (CSL_PDMA_CH_MCU_MCSPI2_CH0_TX)
666 #define UDMA_PDMA_CH_MCU_MCSPI2_CH1_TX (CSL_PDMA_CH_MCU_MCSPI2_CH1_TX)
667 #define UDMA_PDMA_CH_MCU_MCSPI2_CH2_TX (CSL_PDMA_CH_MCU_MCSPI2_CH2_TX)
668 #define UDMA_PDMA_CH_MCU_MCSPI2_CH3_TX (CSL_PDMA_CH_MCU_MCSPI2_CH3_TX)
669 /*
670 * PDMA MCU MCAN TX Channels
671 */
672 #define UDMA_PDMA_CH_MCU_MCAN0_CH0_TX (CSL_PDMA_CH_MCU_MCAN0_CH0_TX)
673 #define UDMA_PDMA_CH_MCU_MCAN0_CH1_TX (CSL_PDMA_CH_MCU_MCAN0_CH1_TX)
674 #define UDMA_PDMA_CH_MCU_MCAN0_CH2_TX (CSL_PDMA_CH_MCU_MCAN0_CH2_TX)
675 #define UDMA_PDMA_CH_MCU_MCAN1_CH0_TX (CSL_PDMA_CH_MCU_MCAN1_CH0_TX)
676 #define UDMA_PDMA_CH_MCU_MCAN1_CH1_TX (CSL_PDMA_CH_MCU_MCAN1_CH1_TX)
677 #define UDMA_PDMA_CH_MCU_MCAN1_CH2_TX (CSL_PDMA_CH_MCU_MCAN1_CH2_TX)
678 /*
679 * PDMA MCU UART TX Channels
680 */
681 #define UDMA_PDMA_CH_MCU_UART0_TX (CSL_PDMA_CH_MCU_UART0_CH0_TX)
682 /* @} */
684 /**
685 * \anchor Udma_PdmaChMainRx
686 * \name Main RX PDMA Channels
687 *
688 * List of all Main PDMA RX channels
689 *
690 * @{
691 */
692 /*
693 * PDMA Main McASP RX Channels
694 */
695 #define UDMA_PDMA_CH_MAIN_MCASP0_RX (CSL_PDMA_CH_MAIN_MCASP0_CH0_RX)
696 #define UDMA_PDMA_CH_MAIN_MCASP1_RX (CSL_PDMA_CH_MAIN_MCASP1_CH0_RX)
697 #define UDMA_PDMA_CH_MAIN_MCASP2_RX (CSL_PDMA_CH_MAIN_MCASP2_CH0_RX)
698 #define UDMA_PDMA_CH_MAIN_MCASP3_RX (CSL_PDMA_CH_MAIN_MCASP3_CH0_RX)
699 #define UDMA_PDMA_CH_MAIN_MCASP4_RX (CSL_PDMA_CH_MAIN_MCASP4_CH0_RX)
700 /*
701 * PDMA Main UART RX Channels
702 */
703 #define UDMA_PDMA_CH_MAIN_UART0_RX (CSL_PDMA_CH_MAIN_UART0_CH0_RX)
704 #define UDMA_PDMA_CH_MAIN_UART1_RX (CSL_PDMA_CH_MAIN_UART1_CH0_RX)
705 #define UDMA_PDMA_CH_MAIN_UART2_RX (CSL_PDMA_CH_MAIN_UART2_CH0_RX)
706 #define UDMA_PDMA_CH_MAIN_UART3_RX (CSL_PDMA_CH_MAIN_UART3_CH0_RX)
707 #define UDMA_PDMA_CH_MAIN_UART4_RX (CSL_PDMA_CH_MAIN_UART4_CH0_RX)
708 #define UDMA_PDMA_CH_MAIN_UART5_RX (CSL_PDMA_CH_MAIN_UART5_CH0_RX)
709 #define UDMA_PDMA_CH_MAIN_UART6_RX (CSL_PDMA_CH_MAIN_UART6_CH0_RX)
710 #define UDMA_PDMA_CH_MAIN_UART7_RX (CSL_PDMA_CH_MAIN_UART7_CH0_RX)
711 #define UDMA_PDMA_CH_MAIN_UART8_RX (CSL_PDMA_CH_MAIN_UART8_CH0_RX)
712 #define UDMA_PDMA_CH_MAIN_UART9_RX (CSL_PDMA_CH_MAIN_UART9_CH0_RX)
713 /*
714 * PDMA Main McSPI RX Channels
715 */
716 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH0_RX)
717 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH1_RX)
718 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH2_RX)
719 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH3_RX)
720 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH0_RX)
721 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH1_RX)
722 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH2_RX)
723 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH3_RX)
724 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH0_RX)
725 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH1_RX)
726 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH2_RX)
727 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH3_RX)
728 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH0_RX)
729 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH1_RX)
730 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH2_RX)
731 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH3_RX)
732 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH0_RX)
733 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH1_RX)
734 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH2_RX)
735 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH3_RX)
736 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH0_RX)
737 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH1_RX)
738 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH2_RX)
739 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH3_RX)
740 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH0_RX)
741 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH1_RX)
742 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH2_RX)
743 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH3_RX)
744 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH0_RX)
745 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH1_RX)
746 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH2_RX)
747 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH3_RX)
748 /*
749 * PDMA MAIN MCAN RX Channels
750 */
751 #define UDMA_PDMA_CH_MAIN_MCAN0_CH0_RX (CSL_PDMA_CH_MAIN_MCAN0_CH0_RX)
752 #define UDMA_PDMA_CH_MAIN_MCAN0_CH1_RX (CSL_PDMA_CH_MAIN_MCAN0_CH1_RX)
753 #define UDMA_PDMA_CH_MAIN_MCAN0_CH2_RX (CSL_PDMA_CH_MAIN_MCAN0_CH2_RX)
754 #define UDMA_PDMA_CH_MAIN_MCAN1_CH0_RX (CSL_PDMA_CH_MAIN_MCAN1_CH0_RX)
755 #define UDMA_PDMA_CH_MAIN_MCAN1_CH1_RX (CSL_PDMA_CH_MAIN_MCAN1_CH1_RX)
756 #define UDMA_PDMA_CH_MAIN_MCAN1_CH2_RX (CSL_PDMA_CH_MAIN_MCAN1_CH2_RX)
757 #define UDMA_PDMA_CH_MAIN_MCAN2_CH0_RX (CSL_PDMA_CH_MAIN_MCAN2_CH0_RX)
758 #define UDMA_PDMA_CH_MAIN_MCAN2_CH1_RX (CSL_PDMA_CH_MAIN_MCAN2_CH1_RX)
759 #define UDMA_PDMA_CH_MAIN_MCAN2_CH2_RX (CSL_PDMA_CH_MAIN_MCAN2_CH2_RX)
760 #define UDMA_PDMA_CH_MAIN_MCAN3_CH0_RX (CSL_PDMA_CH_MAIN_MCAN3_CH0_RX)
761 #define UDMA_PDMA_CH_MAIN_MCAN3_CH1_RX (CSL_PDMA_CH_MAIN_MCAN3_CH1_RX)
762 #define UDMA_PDMA_CH_MAIN_MCAN3_CH2_RX (CSL_PDMA_CH_MAIN_MCAN3_CH2_RX)
763 #define UDMA_PDMA_CH_MAIN_MCAN4_CH0_RX (CSL_PDMA_CH_MAIN_MCAN4_CH0_RX)
764 #define UDMA_PDMA_CH_MAIN_MCAN4_CH1_RX (CSL_PDMA_CH_MAIN_MCAN4_CH1_RX)
765 #define UDMA_PDMA_CH_MAIN_MCAN4_CH2_RX (CSL_PDMA_CH_MAIN_MCAN4_CH2_RX)
766 #define UDMA_PDMA_CH_MAIN_MCAN5_CH0_RX (CSL_PDMA_CH_MAIN_MCAN5_CH0_RX)
767 #define UDMA_PDMA_CH_MAIN_MCAN5_CH1_RX (CSL_PDMA_CH_MAIN_MCAN5_CH1_RX)
768 #define UDMA_PDMA_CH_MAIN_MCAN5_CH2_RX (CSL_PDMA_CH_MAIN_MCAN5_CH2_RX)
769 #define UDMA_PDMA_CH_MAIN_MCAN6_CH0_RX (CSL_PDMA_CH_MAIN_MCAN6_CH0_RX)
770 #define UDMA_PDMA_CH_MAIN_MCAN6_CH1_RX (CSL_PDMA_CH_MAIN_MCAN6_CH1_RX)
771 #define UDMA_PDMA_CH_MAIN_MCAN6_CH2_RX (CSL_PDMA_CH_MAIN_MCAN6_CH2_RX)
772 #define UDMA_PDMA_CH_MAIN_MCAN7_CH0_RX (CSL_PDMA_CH_MAIN_MCAN7_CH0_RX)
773 #define UDMA_PDMA_CH_MAIN_MCAN7_CH1_RX (CSL_PDMA_CH_MAIN_MCAN7_CH1_RX)
774 #define UDMA_PDMA_CH_MAIN_MCAN7_CH2_RX (CSL_PDMA_CH_MAIN_MCAN7_CH2_RX)
775 #define UDMA_PDMA_CH_MAIN_MCAN8_CH0_RX (CSL_PDMA_CH_MAIN_MCAN8_CH0_RX)
776 #define UDMA_PDMA_CH_MAIN_MCAN8_CH1_RX (CSL_PDMA_CH_MAIN_MCAN8_CH1_RX)
777 #define UDMA_PDMA_CH_MAIN_MCAN8_CH2_RX (CSL_PDMA_CH_MAIN_MCAN8_CH2_RX)
778 #define UDMA_PDMA_CH_MAIN_MCAN9_CH0_RX (CSL_PDMA_CH_MAIN_MCAN9_CH0_RX)
779 #define UDMA_PDMA_CH_MAIN_MCAN9_CH1_RX (CSL_PDMA_CH_MAIN_MCAN9_CH1_RX)
780 #define UDMA_PDMA_CH_MAIN_MCAN9_CH2_RX (CSL_PDMA_CH_MAIN_MCAN9_CH2_RX)
781 #define UDMA_PDMA_CH_MAIN_MCAN10_CH0_RX (CSL_PDMA_CH_MAIN_MCAN10_CH0_RX)
782 #define UDMA_PDMA_CH_MAIN_MCAN10_CH1_RX (CSL_PDMA_CH_MAIN_MCAN10_CH1_RX)
783 #define UDMA_PDMA_CH_MAIN_MCAN10_CH2_RX (CSL_PDMA_CH_MAIN_MCAN10_CH2_RX)
784 #define UDMA_PDMA_CH_MAIN_MCAN11_CH0_RX (CSL_PDMA_CH_MAIN_MCAN11_CH0_RX)
785 #define UDMA_PDMA_CH_MAIN_MCAN11_CH1_RX (CSL_PDMA_CH_MAIN_MCAN11_CH1_RX)
786 #define UDMA_PDMA_CH_MAIN_MCAN11_CH2_RX (CSL_PDMA_CH_MAIN_MCAN11_CH2_RX)
787 #define UDMA_PDMA_CH_MAIN_MCAN12_CH0_RX (CSL_PDMA_CH_MAIN_MCAN12_CH0_RX)
788 #define UDMA_PDMA_CH_MAIN_MCAN12_CH1_RX (CSL_PDMA_CH_MAIN_MCAN12_CH1_RX)
789 #define UDMA_PDMA_CH_MAIN_MCAN12_CH2_RX (CSL_PDMA_CH_MAIN_MCAN12_CH2_RX)
790 #define UDMA_PDMA_CH_MAIN_MCAN13_CH0_RX (CSL_PDMA_CH_MAIN_MCAN13_CH0_RX)
791 #define UDMA_PDMA_CH_MAIN_MCAN13_CH1_RX (CSL_PDMA_CH_MAIN_MCAN13_CH1_RX)
792 #define UDMA_PDMA_CH_MAIN_MCAN13_CH2_RX (CSL_PDMA_CH_MAIN_MCAN13_CH2_RX)
793 #define UDMA_PDMA_CH_MAIN_MCAN14_CH0_RX (CSL_PDMA_CH_MAIN_MCAN14_CH0_RX)
794 #define UDMA_PDMA_CH_MAIN_MCAN14_CH1_RX (CSL_PDMA_CH_MAIN_MCAN14_CH1_RX)
795 #define UDMA_PDMA_CH_MAIN_MCAN14_CH2_RX (CSL_PDMA_CH_MAIN_MCAN14_CH2_RX)
796 #define UDMA_PDMA_CH_MAIN_MCAN15_CH0_RX (CSL_PDMA_CH_MAIN_MCAN15_CH0_RX)
797 #define UDMA_PDMA_CH_MAIN_MCAN15_CH1_RX (CSL_PDMA_CH_MAIN_MCAN15_CH1_RX)
798 #define UDMA_PDMA_CH_MAIN_MCAN15_CH2_RX (CSL_PDMA_CH_MAIN_MCAN15_CH2_RX)
799 #define UDMA_PDMA_CH_MAIN_MCAN16_CH0_RX (CSL_PDMA_CH_MAIN_MCAN16_CH0_RX)
800 #define UDMA_PDMA_CH_MAIN_MCAN16_CH1_RX (CSL_PDMA_CH_MAIN_MCAN16_CH1_RX)
801 #define UDMA_PDMA_CH_MAIN_MCAN16_CH2_RX (CSL_PDMA_CH_MAIN_MCAN16_CH2_RX)
802 #define UDMA_PDMA_CH_MAIN_MCAN17_CH0_RX (CSL_PDMA_CH_MAIN_MCAN17_CH0_RX)
803 #define UDMA_PDMA_CH_MAIN_MCAN17_CH1_RX (CSL_PDMA_CH_MAIN_MCAN17_CH1_RX)
804 #define UDMA_PDMA_CH_MAIN_MCAN17_CH2_RX (CSL_PDMA_CH_MAIN_MCAN17_CH2_RX)
805 /* @} */
807 /**
808 * \anchor Udma_PdmaChMcuRx
809 * \name MCU RX PDMA Channels
810 *
811 * List of all MCU PDMA RX channels
812 *
813 * @{
814 */
815 /*
816 * PDMA MCU ADC RX Channels
817 */
818 #define UDMA_PDMA_CH_MCU_ADC0_CH0_RX (CSL_PDMA_CH_MCU_ADC0_CH0_RX)
819 #define UDMA_PDMA_CH_MCU_ADC0_CH1_RX (CSL_PDMA_CH_MCU_ADC0_CH1_RX)
820 #define UDMA_PDMA_CH_MCU_ADC1_CH0_RX (CSL_PDMA_CH_MCU_ADC1_CH0_RX)
821 #define UDMA_PDMA_CH_MCU_ADC1_CH1_RX (CSL_PDMA_CH_MCU_ADC1_CH1_RX)
822 /*
823 * PDMA MCU McSPI RX Channels
824 */
825 #define UDMA_PDMA_CH_MCU_MCSPI0_CH0_RX (CSL_PDMA_CH_MCU_MCSPI0_CH0_RX)
826 #define UDMA_PDMA_CH_MCU_MCSPI0_CH1_RX (CSL_PDMA_CH_MCU_MCSPI0_CH1_RX)
827 #define UDMA_PDMA_CH_MCU_MCSPI0_CH2_RX (CSL_PDMA_CH_MCU_MCSPI0_CH2_RX)
828 #define UDMA_PDMA_CH_MCU_MCSPI0_CH3_RX (CSL_PDMA_CH_MCU_MCSPI0_CH3_RX)
829 #define UDMA_PDMA_CH_MCU_MCSPI1_CH0_RX (CSL_PDMA_CH_MCU_MCSPI1_CH0_RX)
830 #define UDMA_PDMA_CH_MCU_MCSPI1_CH1_RX (CSL_PDMA_CH_MCU_MCSPI1_CH1_RX)
831 #define UDMA_PDMA_CH_MCU_MCSPI1_CH2_RX (CSL_PDMA_CH_MCU_MCSPI1_CH2_RX)
832 #define UDMA_PDMA_CH_MCU_MCSPI1_CH3_RX (CSL_PDMA_CH_MCU_MCSPI1_CH3_RX)
833 #define UDMA_PDMA_CH_MCU_MCSPI2_CH0_RX (CSL_PDMA_CH_MCU_MCSPI2_CH0_RX)
834 #define UDMA_PDMA_CH_MCU_MCSPI2_CH1_RX (CSL_PDMA_CH_MCU_MCSPI2_CH1_RX)
835 #define UDMA_PDMA_CH_MCU_MCSPI2_CH2_RX (CSL_PDMA_CH_MCU_MCSPI2_CH2_RX)
836 #define UDMA_PDMA_CH_MCU_MCSPI2_CH3_RX (CSL_PDMA_CH_MCU_MCSPI2_CH3_RX)
837 /*
838 * PDMA MCU MCAN RX Channels
839 */
840 #define UDMA_PDMA_CH_MCU_MCAN0_CH0_RX (CSL_PDMA_CH_MCU_MCAN0_CH0_RX)
841 #define UDMA_PDMA_CH_MCU_MCAN0_CH1_RX (CSL_PDMA_CH_MCU_MCAN0_CH1_RX)
842 #define UDMA_PDMA_CH_MCU_MCAN0_CH2_RX (CSL_PDMA_CH_MCU_MCAN0_CH2_RX)
843 #define UDMA_PDMA_CH_MCU_MCAN1_CH0_RX (CSL_PDMA_CH_MCU_MCAN1_CH0_RX)
844 #define UDMA_PDMA_CH_MCU_MCAN1_CH1_RX (CSL_PDMA_CH_MCU_MCAN1_CH1_RX)
845 #define UDMA_PDMA_CH_MCU_MCAN1_CH2_RX (CSL_PDMA_CH_MCU_MCAN1_CH2_RX)
846 /*
847 * PDMA MCU UART RX Channels
848 */
849 #define UDMA_PDMA_CH_MCU_UART0_RX (CSL_PDMA_CH_MCU_UART0_CH0_RX)
850 /* @} */
852 /* @} */
854 /* ========================================================================== */
855 /* Structure Declarations */
856 /* ========================================================================== */
858 /* None */
860 /* ========================================================================== */
861 /* Function Declarations */
862 /* ========================================================================== */
864 /**
865 * \brief Returns the core ID
866 *
867 * \return Core ID \ref Udma_CoreId
868 */
869 uint32_t Udma_getCoreId(void);
871 /**
872 * \brief Returns the core tisci device ID
873 *
874 * \return Core tisci Dev ID
875 */
876 uint16_t Udma_getCoreSciDevId(void);
878 /**
879 * \brief Returns TRUE if the memory is cache coherent
880 *
881 * \return TRUE/FALSE
882 */
883 uint32_t Udma_isCacheCoherent(void);
885 /* ========================================================================== */
886 /* Static Function Definitions */
887 /* ========================================================================== */
889 /* None */
891 #ifdef __cplusplus
892 }
893 #endif
895 #endif /* #ifndef UDMA_SOC_H_ */