[processor-sdk/pdk.git] / packages / ti / drv / udma / unit_test / udma_ut / rtos / j721e / linker_mcu3_0.lds
1 /* linker options */
2 --fill_value=0
3 --stack_size=0x2000
4 --heap_size=0x1000
6 -e __VECS_ENTRY_POINT
8 MEMORY
9 {
10 R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000, LENGTH = 0x100
11 RESET_VECTORS(X) : ORIGIN = 0x41C44000, LENGTH = 0x100
12 R5F_TCMB0 (RWIX) : ORIGIN = 0x41010000, LENGTH = 0x00008000 /* 32 KB */
13 DDR0 (RWIX) : ORIGIN = 0xC0000000, LENGTH = 0x08000000 /* 128 MB per core */
14 OCMRAM (RWIX) : ORIGIN = 0x41C30000, LENGTH = 0x00008000 /* 32 KB per core */
15 MSMC3 (RWIX) : ORIGIN = 0x70300000, LENGTH = 0x00080000 /* 512 KB per core */
16 }
18 SECTIONS
19 {
20 .vecs : {
21 __VECS_ENTRY_POINT = .;
22 } palign(8) > RESET_VECTORS
23 .text_boot {
24 *boot.aer5f<*boot.o*>(.text)
25 } palign(8) > R5F_TCMB0
26 .text:xdc_runtime_Startup_reset__I : {} palign(8) > R5F_TCMB0
27 .text:ti_sysbios_family_arm_v7r_Cache* : {} palign(8) > R5F_TCMB0
28 .text:ti_sysbios_family_arm_MPU* : {} palign(8) > R5F_TCMB0
30 .text : {} palign(8) > DDR0
31 .cinit : {} palign(8) > DDR0
32 .bss : {} align(8) > DDR0
33 .const : {} palign(8) > DDR0
34 .data : {} palign(128) > DDR0
35 .sysmem : {} align(8) > DDR0
36 .stack : {} align(4) > DDR0
37 .data_buffer : {} palign(128) > DDR0
39 .udma_buffer_ddr : {} palign(128) > DDR0
40 .udma_buffer_ospi : {} palign(128) > DDR0
41 .udma_buffer_msmc : {} palign(128) > MSMC3
42 .udma_buffer_internal : {} palign(128) > OCMRAM
43 }