be4665ddc399584b3c91c9488a5f4716a0b63af1
1 /*
2 * Copyright (c) Texas Instruments Incorporated 2018
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /**
34 * \file udma_testcases.h
35 *
36 * \brief This file defines the test cases for UDMA UT.
37 */
39 #ifndef UDMA_TEST_CASES_H_
40 #define UDMA_TEST_CASES_H_
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
46 #include <udma_test.h>
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
52 /* ========================================================================== */
53 /* Macros & Typedefs */
54 /* ========================================================================== */
56 #define UDMA_TEST_NUM_TESTCASES ((sizeof (gUdmaTestCases)) / \
57 (sizeof (UdmaTestParams)))
59 #ifndef KB
60 #define KB (1024U)
61 #endif
63 #ifndef MB
64 #define MB (KB * KB)
65 #endif
67 /* ========================================================================== */
68 /* Function Declarations */
69 /* ========================================================================== */
71 /* None */
73 /* ========================================================================== */
74 /* Global Variables */
75 /* ========================================================================== */
77 /** \brief Defines the various UDMA test cases. */
78 static UdmaTestParams gUdmaTestCases[] =
79 {
80 {
81 .enableTest = TEST_ENABLE,
82 .tcId = 3467U,
83 .tcName = "Main NAVSS Blockcpy DDR to DDR in polling mode",
84 .disableInfo= NULL,
85 .printEnable= PRINT_ENABLE,
86 .prfEnable = PRF_DISABLE,
87 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
88 .dcEnable = DATA_CHECK_ENABLE,
89 .loopCnt = USE_DEF_LP_CNT,
90 .numTasks = 1U,
91 .testType = {UDMA_TT_BLK_CPY},
92 .testFxnPtr = {&udmaTestBlkcpyTc},
93 .pacingTime = {PACING_NONE},
94 .numCh = {1U},
95 .instId = {UDMA_INST_ID_MAIN_0},
96 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
97 .qdepth = {USE_DEF_QDEPTH},
98 .icnt = {
99 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
100 },
101 .dicnt = {
102 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
103 },
104 .dim = {
105 {0U, 0U, 0U}
106 },
107 .ddim = {
108 {0U, 0U, 0U}
109 },
110 .heapIdSrc = {DEF_HEAP_ID},
111 .heapIdDest = {DEF_HEAP_ID},
112 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
113 .destBufSize= {UDMA_TEST_DEF_DICNT0},
114 .runFlag = (UDMA_TEST_RF_MAIN_BC | UDMA_TEST_RF_CFG_DYN),
115 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
116 },
117 {
118 .enableTest = TEST_ENABLE,
119 .tcId = 3473U,
120 .tcName = "Main NAVSS Blockcpy DDR to DDR in interrupt mode",
121 .disableInfo= NULL,
122 .printEnable= PRINT_ENABLE,
123 .prfEnable = PRF_DISABLE,
124 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
125 .dcEnable = DATA_CHECK_ENABLE,
126 .loopCnt = USE_DEF_LP_CNT,
127 .numTasks = 1U,
128 .testType = {UDMA_TT_BLK_CPY},
129 .testFxnPtr = {&udmaTestBlkcpyTc},
130 .pacingTime = {PACING_NONE},
131 .numCh = {1U},
132 .instId = {UDMA_INST_ID_MAIN_0},
133 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
134 .qdepth = {USE_DEF_QDEPTH},
135 .icnt = {
136 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
137 },
138 .dicnt = {
139 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
140 },
141 .dim = {
142 {0U, 0U, 0U}
143 },
144 .ddim = {
145 {0U, 0U, 0U}
146 },
147 .heapIdSrc = {DEF_HEAP_ID},
148 .heapIdDest = {DEF_HEAP_ID},
149 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
150 .destBufSize= {UDMA_TEST_DEF_DICNT0},
151 .runFlag = (UDMA_TEST_RF_MAIN_BC | UDMA_TEST_RF_CFG_DYN),
152 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
153 },
154 {
155 .enableTest = TEST_ENABLE,
156 .tcId = 3474U,
157 .tcName = "MCU NAVSS Blockcpy DDR to DDR in polling mode",
158 .disableInfo= NULL,
159 .printEnable= PRINT_ENABLE,
160 .prfEnable = PRF_DISABLE,
161 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
162 .dcEnable = DATA_CHECK_ENABLE,
163 .loopCnt = USE_DEF_LP_CNT,
164 .numTasks = 1U,
165 .testType = {UDMA_TT_BLK_CPY},
166 .testFxnPtr = {&udmaTestBlkcpyTc},
167 .pacingTime = {PACING_NONE},
168 .numCh = {1U},
169 .instId = {UDMA_INST_ID_MCU_0},
170 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
171 .qdepth = {USE_DEF_QDEPTH},
172 .icnt = {
173 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
174 },
175 .dicnt = {
176 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
177 },
178 .dim = {
179 {0U, 0U, 0U}
180 },
181 .ddim = {
182 {0U, 0U, 0U}
183 },
184 .heapIdSrc = {DEF_HEAP_ID},
185 .heapIdDest = {DEF_HEAP_ID},
186 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
187 .destBufSize= {UDMA_TEST_DEF_DICNT0},
188 .runFlag = (UDMA_TEST_RF_MCU_BC | UDMA_TEST_RF_CFG_DYN),
189 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
190 },
191 {
192 .enableTest = TEST_ENABLE,
193 .tcId = 3475U,
194 .tcName = "MCU NAVSS Blockcpy DDR to DDR",
195 .disableInfo= NULL,
196 .printEnable= PRINT_ENABLE,
197 .prfEnable = PRF_DISABLE,
198 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
199 .dcEnable = DATA_CHECK_ENABLE,
200 .loopCnt = USE_DEF_LP_CNT,
201 .numTasks = 1U,
202 .testType = {UDMA_TT_BLK_CPY},
203 .testFxnPtr = {&udmaTestBlkcpyTc},
204 .pacingTime = {PACING_NONE},
205 .numCh = {1U},
206 .instId = {UDMA_INST_ID_MCU_0},
207 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
208 .qdepth = {USE_DEF_QDEPTH},
209 .icnt = {
210 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
211 },
212 .dicnt = {
213 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
214 },
215 .dim = {
216 {0U, 0U, 0U}
217 },
218 .ddim = {
219 {0U, 0U, 0U}
220 },
221 .heapIdSrc = {DEF_HEAP_ID},
222 .heapIdDest = {DEF_HEAP_ID},
223 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
224 .destBufSize= {UDMA_TEST_DEF_DICNT0},
225 .runFlag = (UDMA_TEST_RF_MCU_BC | UDMA_TEST_RF_CFG_DYN),
226 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
227 },
228 {
229 .enableTest = TEST_ENABLE,
230 .tcId = 3476U,
231 .tcName = "Main NAVSS Blockcpy DDR to DDR SW global 0 trigger test in polling mode",
232 .disableInfo= NULL,
233 .printEnable= PRINT_ENABLE,
234 .prfEnable = PRF_DISABLE,
235 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
236 .dcEnable = DATA_CHECK_ENABLE,
237 .loopCnt = USE_DEF_LP_CNT,
238 .numTasks = 1U,
239 .testType = {UDMA_TT_BLK_CPY},
240 .testFxnPtr = {&udmaTestBlkcpyTc},
241 .pacingTime = {PACING_NONE},
242 .numCh = {1U},
243 .instId = {UDMA_INST_ID_MAIN_0},
244 .chPrmId = {UDMA_TEST_CH_PRMID_TRIGGER_GLOBAL0},
245 .qdepth = {USE_DEF_QDEPTH},
246 .icnt = {
247 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
248 },
249 .dicnt = {
250 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
251 },
252 .dim = {
253 {0U, 0U, 0U}
254 },
255 .ddim = {
256 {0U, 0U, 0U}
257 },
258 .heapIdSrc = {DEF_HEAP_ID},
259 .heapIdDest = {DEF_HEAP_ID},
260 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
261 .destBufSize= {UDMA_TEST_DEF_DICNT0},
262 .runFlag = (UDMA_TEST_RF_MAIN_BC | UDMA_TEST_RF_CFG_DYN),
263 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
264 },
265 {
266 .enableTest = TEST_ENABLE,
267 .tcId = 3477U,
268 .tcName = "Main NAVSS Blockcpy DDR to DDR SW global 0 trigger test in interrupt mode",
269 .disableInfo= NULL,
270 .printEnable= PRINT_ENABLE,
271 .prfEnable = PRF_DISABLE,
272 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
273 .dcEnable = DATA_CHECK_ENABLE,
274 .loopCnt = USE_DEF_LP_CNT,
275 .numTasks = 1U,
276 .testType = {UDMA_TT_BLK_CPY},
277 .testFxnPtr = {&udmaTestBlkcpyTc},
278 .pacingTime = {PACING_NONE},
279 .numCh = {1U},
280 .instId = {UDMA_INST_ID_MAIN_0},
281 .chPrmId = {UDMA_TEST_CH_PRMID_TRIGGER_GLOBAL0_INTR},
282 .qdepth = {USE_DEF_QDEPTH},
283 .icnt = {
284 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
285 },
286 .dicnt = {
287 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
288 },
289 .dim = {
290 {0U, 0U, 0U}
291 },
292 .ddim = {
293 {0U, 0U, 0U}
294 },
295 .heapIdSrc = {DEF_HEAP_ID},
296 .heapIdDest = {DEF_HEAP_ID},
297 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
298 .destBufSize= {UDMA_TEST_DEF_DICNT0},
299 .runFlag = (UDMA_TEST_RF_MAIN_BC),
300 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
301 },
302 {
303 .enableTest = TEST_ENABLE,
304 .tcId = 3478U,
305 .tcName = "MCU NAVSS Blockcpy DDR to DDR SW global 0 trigger test in polling mode",
306 .disableInfo= NULL,
307 .printEnable= PRINT_ENABLE,
308 .prfEnable = PRF_DISABLE,
309 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
310 .dcEnable = DATA_CHECK_ENABLE,
311 .loopCnt = USE_DEF_LP_CNT,
312 .numTasks = 1U,
313 .testType = {UDMA_TT_BLK_CPY},
314 .testFxnPtr = {&udmaTestBlkcpyTc},
315 .pacingTime = {PACING_NONE},
316 .numCh = {1U},
317 .instId = {UDMA_INST_ID_MCU_0},
318 .chPrmId = {UDMA_TEST_CH_PRMID_TRIGGER_GLOBAL0},
319 .qdepth = {USE_DEF_QDEPTH},
320 .icnt = {
321 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
322 },
323 .dicnt = {
324 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
325 },
326 .dim = {
327 {0U, 0U, 0U}
328 },
329 .ddim = {
330 {0U, 0U, 0U}
331 },
332 .heapIdSrc = {DEF_HEAP_ID},
333 .heapIdDest = {DEF_HEAP_ID},
334 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
335 .destBufSize= {UDMA_TEST_DEF_DICNT0},
336 .runFlag = (UDMA_TEST_RF_MCU_BC),
337 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
338 },
339 {
340 .enableTest = TEST_ENABLE,
341 .tcId = 3479U,
342 .tcName = "MCU NAVSS Blockcpy DDR to DDR SW global 0 trigger test",
343 .disableInfo= NULL,
344 .printEnable= PRINT_ENABLE,
345 .prfEnable = PRF_DISABLE,
346 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
347 .dcEnable = DATA_CHECK_ENABLE,
348 .loopCnt = USE_DEF_LP_CNT,
349 .numTasks = 1U,
350 .testType = {UDMA_TT_BLK_CPY},
351 .testFxnPtr = {&udmaTestBlkcpyTc},
352 .pacingTime = {PACING_NONE},
353 .numCh = {1U},
354 .instId = {UDMA_INST_ID_MCU_0},
355 .chPrmId = {UDMA_TEST_CH_PRMID_TRIGGER_GLOBAL0_INTR},
356 .qdepth = {USE_DEF_QDEPTH},
357 .icnt = {
358 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
359 },
360 .dicnt = {
361 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
362 },
363 .dim = {
364 {0U, 0U, 0U}
365 },
366 .ddim = {
367 {0U, 0U, 0U}
368 },
369 .heapIdSrc = {DEF_HEAP_ID},
370 .heapIdDest = {DEF_HEAP_ID},
371 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
372 .destBufSize= {UDMA_TEST_DEF_DICNT0},
373 .runFlag = (UDMA_TEST_RF_MCU_BC),
374 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
375 },
376 {
377 .enableTest = TEST_ENABLE,
378 .tcId = 3480U,
379 .tcName = "MCU NAVSS Blockcpy circular 1KB DDR to DDR 1KB ICNT1 TR event type test",
380 .disableInfo= NULL,
381 .printEnable= PRINT_ENABLE,
382 .prfEnable = PRF_DISABLE,
383 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
384 .dcEnable = DATA_CHECK_ENABLE,
385 .loopCnt = 1U,
386 .numTasks = 1U,
387 .testType = {UDMA_TT_BLK_CPY},
388 .testFxnPtr = {&udmaTestBlkcpyTc},
389 .pacingTime = {PACING_NONE},
390 .numCh = {1U},
391 .instId = {UDMA_INST_ID_MCU_0},
392 .chPrmId = {UDMA_TEST_CH_PRMID_EVENTSIZE_ICNT1},
393 .qdepth = {USE_DEF_QDEPTH},
394 .icnt = {
395 {1*KB, 1U, 1U, 1U}
396 },
397 .dicnt = {
398 {1*KB, 1U, 1U, 1U}
399 },
400 .dim = {
401 {0U, 0U, 0U}
402 },
403 .ddim = {
404 {1*KB, 0U, 0U}
405 },
406 .heapIdSrc = {DEF_HEAP_ID},
407 .heapIdDest = {DEF_HEAP_ID},
408 .srcBufSize = {1*KB},
409 .destBufSize= {1*KB},
410 .runFlag = (UDMA_TEST_RF_MCU_BC),
411 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
412 },
413 {
414 .enableTest = TEST_ENABLE,
415 .tcId = 3481U,
416 .tcName = "MCU NAVSS Blockcpy circular 1KB DDR to DDR 1MB ICNT2 TR event type test",
417 .disableInfo= NULL,
418 .printEnable= PRINT_ENABLE,
419 .prfEnable = PRF_DISABLE,
420 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
421 .dcEnable = DATA_CHECK_ENABLE,
422 .loopCnt = 1U,
423 .numTasks = 1U,
424 .testType = {UDMA_TT_BLK_CPY},
425 .testFxnPtr = {&udmaTestBlkcpyTc},
426 .pacingTime = {PACING_NONE},
427 .numCh = {1U},
428 .instId = {UDMA_INST_ID_MCU_0},
429 .chPrmId = {UDMA_TEST_CH_PRMID_EVENTSIZE_ICNT2},
430 .qdepth = {USE_DEF_QDEPTH},
431 .icnt = {
432 {1*KB, 1U, 1*KB, 1U}
433 },
434 .dicnt = {
435 {1*KB, 1U, 1*KB, 1U}
436 },
437 .dim = {
438 {0U, 0U, 0U}
439 },
440 .ddim = {
441 {1*KB, 1*KB, 0U}
442 },
443 .heapIdSrc = {DEF_HEAP_ID},
444 .heapIdDest = {DEF_HEAP_ID},
445 .srcBufSize = {1*KB},
446 .destBufSize= {1*MB},
447 .runFlag = (UDMA_TEST_RF_MCU_BC),
448 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
449 },
450 {
451 .enableTest = TEST_ENABLE,
452 .tcId = 3482U,
453 .tcName = "MCU NAVSS Blockcpy circular 1KB DDR to DDR 1MB ICNT3 TR event type test",
454 .disableInfo= NULL,
455 .printEnable= PRINT_ENABLE,
456 .prfEnable = PRF_DISABLE,
457 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
458 .dcEnable = DATA_CHECK_ENABLE,
459 .loopCnt = 1U,
460 .numTasks = 1U,
461 .testType = {UDMA_TT_BLK_CPY},
462 .testFxnPtr = {&udmaTestBlkcpyTc},
463 .pacingTime = {PACING_NONE},
464 .numCh = {1U},
465 .instId = {UDMA_INST_ID_MCU_0},
466 .chPrmId = {UDMA_TEST_CH_PRMID_EVENTSIZE_ICNT3},
467 .qdepth = {USE_DEF_QDEPTH},
468 .icnt = {
469 {1*KB, 1U, 1*KB, 1U}
470 },
471 .dicnt = {
472 {1*KB, 1U, 1*KB, 1U}
473 },
474 .dim = {
475 {0U, 0U, 0U}
476 },
477 .ddim = {
478 {1*KB, 1*KB, 0U}
479 },
480 .heapIdSrc = {DEF_HEAP_ID},
481 .heapIdDest = {DEF_HEAP_ID},
482 .srcBufSize = {1*KB},
483 .destBufSize= {1*MB},
484 .runFlag = (UDMA_TEST_RF_MCU_BC),
485 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
486 },
487 {
488 .enableTest = TEST_ENABLE,
489 .tcId = 3516U,
490 .tcName = "Main NAVSS Blockcpy MSMC to MSMC in interrupt mode",
491 .disableInfo= NULL,
492 .printEnable= PRINT_ENABLE,
493 .prfEnable = PRF_DISABLE,
494 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
495 .dcEnable = DATA_CHECK_ENABLE,
496 .loopCnt = USE_DEF_LP_CNT,
497 .numTasks = 1U,
498 .testType = {UDMA_TT_BLK_CPY},
499 .testFxnPtr = {&udmaTestBlkcpyTc},
500 .pacingTime = {PACING_NONE},
501 .numCh = {1U},
502 .instId = {UDMA_INST_ID_MAIN_0},
503 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
504 .qdepth = {USE_DEF_QDEPTH},
505 .icnt = {
506 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
507 },
508 .dicnt = {
509 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
510 },
511 .dim = {
512 {0U, 0U, 0U}
513 },
514 .ddim = {
515 {0U, 0U, 0U}
516 },
517 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC},
518 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
519 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
520 .destBufSize= {UDMA_TEST_DEF_DICNT0},
521 .runFlag = (UDMA_TEST_RF_MAIN_BC),
522 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
523 },
524 {
525 .enableTest = TEST_ENABLE,
526 .tcId = 3483U,
527 .tcName = "MCU NAVSS Blockcpy MSMC to MSMC in interrupt mode",
528 .disableInfo= NULL,
529 .printEnable= PRINT_ENABLE,
530 .prfEnable = PRF_DISABLE,
531 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
532 .dcEnable = DATA_CHECK_ENABLE,
533 .loopCnt = USE_DEF_LP_CNT,
534 .numTasks = 1U,
535 .testType = {UDMA_TT_BLK_CPY},
536 .testFxnPtr = {&udmaTestBlkcpyTc},
537 .pacingTime = {PACING_NONE},
538 .numCh = {1U},
539 .instId = {UDMA_INST_ID_MCU_0},
540 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
541 .qdepth = {USE_DEF_QDEPTH},
542 .icnt = {
543 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
544 },
545 .dicnt = {
546 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
547 },
548 .dim = {
549 {0U, 0U, 0U}
550 },
551 .ddim = {
552 {0U, 0U, 0U}
553 },
554 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC},
555 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
556 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
557 .destBufSize= {UDMA_TEST_DEF_DICNT0},
558 .runFlag = (UDMA_TEST_RF_MCU_BC),
559 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
560 },
561 {
562 .enableTest = TEST_ENABLE,
563 .tcId = 3484U,
564 .tcName = "MCU NAVSS Blockcpy OCMC to OCMC in interrupt mode",
565 .disableInfo= NULL,
566 .printEnable= PRINT_ENABLE,
567 .prfEnable = PRF_DISABLE,
568 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
569 .dcEnable = DATA_CHECK_ENABLE,
570 .loopCnt = USE_DEF_LP_CNT,
571 .numTasks = 1U,
572 .testType = {UDMA_TT_BLK_CPY},
573 .testFxnPtr = {&udmaTestBlkcpyTc},
574 .pacingTime = {PACING_NONE},
575 .numCh = {1U},
576 .instId = {UDMA_INST_ID_MCU_0},
577 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
578 .qdepth = {USE_DEF_QDEPTH},
579 .icnt = {
580 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
581 },
582 .dicnt = {
583 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
584 },
585 .dim = {
586 {0U, 0U, 0U}
587 },
588 .ddim = {
589 {0U, 0U, 0U}
590 },
591 .heapIdSrc = {UTILS_MEM_HEAP_ID_INTERNAL},
592 .heapIdDest = {UTILS_MEM_HEAP_ID_INTERNAL},
593 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
594 .destBufSize= {UDMA_TEST_DEF_DICNT0},
595 .runFlag = (UDMA_TEST_RF_MCU_BC),
596 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
597 },
598 {
599 .enableTest = TEST_ENABLE,
600 .tcId = 3485U,
601 .tcName = "Main NAVSS Blockcpy DDR 1MB to DDR 1MB performance test",
602 .disableInfo= NULL,
603 .printEnable= PRINT_ENABLE,
604 .prfEnable = PRF_ENABLE,
605 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
606 .dcEnable = DATA_CHECK_DISABLE,
607 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
608 .numTasks = 1U,
609 .testType = {UDMA_TT_BLK_CPY},
610 .testFxnPtr = {&udmaTestBlkcpyTc},
611 .pacingTime = {PACING_NONE},
612 .numCh = {1U},
613 .instId = {UDMA_INST_ID_MAIN_0},
614 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
615 .qdepth = {UDMA_TEST_PERF_QDEPTH},
616 .icnt = {
617 {1*KB, 1U, 1*KB, 1U},
618 },
619 .dicnt = {
620 {1*KB, 1U, 1*KB, 1U},
621 },
622 .dim = {
623 {1*KB, 1*KB, 0U},
624 },
625 .ddim = {
626 {1*KB, 1*KB, 0U},
627 },
628 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR},
629 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR},
630 .srcBufSize = {1*MB},
631 .destBufSize= {1*MB},
632 .runFlag = (UDMA_TEST_RF_MAIN_BC),
633 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
634 },
635 {
636 .enableTest = TEST_ENABLE,
637 .tcId = 3486U,
638 .tcName = "Main NAVSS 2D Blockcpy MSMC circular 1KB to DDR 1MB performance test",
639 .disableInfo= NULL,
640 .printEnable= PRINT_ENABLE,
641 .prfEnable = PRF_ENABLE,
642 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
643 .dcEnable = DATA_CHECK_DISABLE,
644 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
645 .numTasks = 1U,
646 .testType = {UDMA_TT_BLK_CPY},
647 .testFxnPtr = {&udmaTestBlkcpyTc},
648 .pacingTime = {PACING_NONE},
649 .numCh = {1U},
650 .instId = {UDMA_INST_ID_MAIN_0},
651 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
652 .qdepth = {UDMA_TEST_DEF_QDEPTH},
653 .icnt = {
654 {1*KB, 1U, 1*KB, 1U}
655 },
656 .dicnt = {
657 {1*KB, 1U, 1*KB, 1U}
658 },
659 .dim = {
660 {0U, 0U, 0U}
661 },
662 .ddim = {
663 {1*KB, 1*KB, 0U}
664 },
665 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC},
666 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR},
667 .srcBufSize = {1*KB},
668 .destBufSize= {1*MB},
669 .runFlag = (UDMA_TEST_RF_MAIN_BC),
670 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
671 },
672 {
673 .enableTest = TEST_ENABLE,
674 .tcId = 3487U,
675 .tcName = "Main NAVSS 2D Blockcpy DDR 1MB to MSMC circular 1KB performance test",
676 .disableInfo= NULL,
677 .printEnable= PRINT_ENABLE,
678 .prfEnable = PRF_ENABLE,
679 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
680 .dcEnable = DATA_CHECK_DISABLE,
681 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
682 .numTasks = 1U,
683 .testType = {UDMA_TT_BLK_CPY},
684 .testFxnPtr = {&udmaTestBlkcpyTc},
685 .pacingTime = {PACING_NONE},
686 .numCh = {1U},
687 .instId = {UDMA_INST_ID_MAIN_0},
688 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
689 .qdepth = {UDMA_TEST_DEF_QDEPTH},
690 .icnt = {
691 {1*KB, 1U, 1*KB, 1U}
692 },
693 .dicnt = {
694 {1*KB, 1U, 1*KB, 1U}
695 },
696 .dim = {
697 {1*KB, 1*KB, 0U}
698 },
699 .ddim = {
700 {0U, 0U, 0U}
701 },
702 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR},
703 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
704 .srcBufSize = {1*MB},
705 .destBufSize= {1*KB},
706 .runFlag = (UDMA_TEST_RF_MAIN_BC),
707 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
708 },
709 {
710 .enableTest = TEST_ENABLE,
711 .tcId = 3488U,
712 .tcName = "Main NAVSS 2D Blockcpy MSMC circular 1KB to MSMC circular 1KB performance test",
713 .disableInfo= NULL,
714 .printEnable= PRINT_ENABLE,
715 .prfEnable = PRF_ENABLE,
716 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
717 .dcEnable = DATA_CHECK_DISABLE,
718 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
719 .numTasks = 1U,
720 .testType = {UDMA_TT_BLK_CPY},
721 .testFxnPtr = {&udmaTestBlkcpyTc},
722 .pacingTime = {PACING_NONE},
723 .numCh = {1U},
724 .instId = {UDMA_INST_ID_MAIN_0},
725 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
726 .qdepth = {UDMA_TEST_DEF_QDEPTH},
727 .icnt = {
728 {1*KB, 1U, 1*KB, 1U}
729 },
730 .dicnt = {
731 {1*KB, 1U, 1*KB, 1U}
732 },
733 .dim = {
734 {0U, 0U, 0U}
735 },
736 .ddim = {
737 {0U, 0U, 0U}
738 },
739 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC},
740 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
741 .srcBufSize = {1*KB},
742 .destBufSize= {1*KB},
743 .runFlag = (UDMA_TEST_RF_MAIN_BC),
744 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
745 },
746 {
747 .enableTest = TEST_ENABLE,
748 .tcId = 3489U,
749 .tcName = "MCU NAVSS 2D Blockcpy OCMC circular 1KB to OCMC circular 1KB performance test",
750 .disableInfo= NULL,
751 .printEnable= PRINT_ENABLE,
752 .prfEnable = PRF_ENABLE,
753 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
754 .dcEnable = DATA_CHECK_DISABLE,
755 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
756 .numTasks = 1U,
757 .testType = {UDMA_TT_BLK_CPY},
758 .testFxnPtr = {&udmaTestBlkcpyTc},
759 .pacingTime = {PACING_NONE},
760 .numCh = {1U},
761 .instId = {UDMA_INST_ID_MCU_0},
762 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
763 .qdepth = {UDMA_TEST_DEF_QDEPTH},
764 .icnt = {
765 {1*KB, 1U, 1*KB, 1U}
766 },
767 .dicnt = {
768 {1*KB, 1U, 1*KB, 1U}
769 },
770 .dim = {
771 {0U, 0U, 0U}
772 },
773 .ddim = {
774 {0U, 0U, 0U}
775 },
776 .heapIdSrc = {UTILS_MEM_HEAP_ID_INTERNAL},
777 .heapIdDest = {UTILS_MEM_HEAP_ID_INTERNAL},
778 .srcBufSize = {1*KB},
779 .destBufSize= {1*KB},
780 .runFlag = (UDMA_TEST_RF_MCU_BC),
781 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
782 },
783 {
784 .enableTest = TEST_ENABLE,
785 .tcId = 3490U,
786 .tcName = "MCU NAVSS Blockcpy DDR 1MB to DDR 1MB performance test",
787 .disableInfo= NULL,
788 .printEnable= PRINT_ENABLE,
789 .prfEnable = PRF_ENABLE,
790 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
791 .dcEnable = DATA_CHECK_DISABLE,
792 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
793 .numTasks = 1U,
794 .testType = {UDMA_TT_BLK_CPY},
795 .testFxnPtr = {&udmaTestBlkcpyTc},
796 .pacingTime = {PACING_NONE},
797 .numCh = {1U},
798 .instId = {UDMA_INST_ID_MCU_0},
799 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
800 .qdepth = {UDMA_TEST_PERF_QDEPTH},
801 .icnt = {
802 {1*KB, 1U, 1*KB, 1U},
803 },
804 .dicnt = {
805 {1*KB, 1U, 1*KB, 1U},
806 },
807 .dim = {
808 {1*KB, 1*KB, 0U},
809 },
810 .ddim = {
811 {1*KB, 1*KB, 0U},
812 },
813 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR},
814 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR},
815 .srcBufSize = {1*MB},
816 .destBufSize= {1*MB},
817 .runFlag = (UDMA_TEST_RF_MCU_BC),
818 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
819 },
820 {
821 .enableTest = TEST_ENABLE,
822 .tcId = 3491U,
823 .tcName = "MCU NAVSS 2D Blockcpy MSMC circular 1KB to DDR 1MB performance test",
824 .disableInfo= NULL,
825 .printEnable= PRINT_ENABLE,
826 .prfEnable = PRF_ENABLE,
827 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
828 .dcEnable = DATA_CHECK_DISABLE,
829 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
830 .numTasks = 1U,
831 .testType = {UDMA_TT_BLK_CPY},
832 .testFxnPtr = {&udmaTestBlkcpyTc},
833 .pacingTime = {PACING_NONE},
834 .numCh = {1U},
835 .instId = {UDMA_INST_ID_MCU_0},
836 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
837 .qdepth = {UDMA_TEST_DEF_QDEPTH},
838 .icnt = {
839 {1*KB, 1U, 1*KB, 1U}
840 },
841 .dicnt = {
842 {1*KB, 1U, 1*KB, 1U}
843 },
844 .dim = {
845 {0U, 0U, 0U}
846 },
847 .ddim = {
848 {1*KB, 1*KB, 0U}
849 },
850 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC},
851 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR},
852 .srcBufSize = {1*KB},
853 .destBufSize= {1*MB},
854 .runFlag = (UDMA_TEST_RF_MCU_BC),
855 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
856 },
857 {
858 .enableTest = TEST_ENABLE,
859 .tcId = 3492U,
860 .tcName = "MCU NAVSS 2D Blockcpy DDR 1MB to MSMC circular 1KB performance test",
861 .disableInfo= NULL,
862 .printEnable= PRINT_ENABLE,
863 .prfEnable = PRF_ENABLE,
864 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
865 .dcEnable = DATA_CHECK_DISABLE,
866 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
867 .numTasks = 1U,
868 .testType = {UDMA_TT_BLK_CPY},
869 .testFxnPtr = {&udmaTestBlkcpyTc},
870 .pacingTime = {PACING_NONE},
871 .numCh = {1U},
872 .instId = {UDMA_INST_ID_MCU_0},
873 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
874 .qdepth = {UDMA_TEST_DEF_QDEPTH},
875 .icnt = {
876 {1*KB, 1U, 1*KB, 1U}
877 },
878 .dicnt = {
879 {1*KB, 1U, 1*KB, 1U}
880 },
881 .dim = {
882 {1*KB, 1*KB, 0U}
883 },
884 .ddim = {
885 {0U, 0U, 0U}
886 },
887 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR},
888 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
889 .srcBufSize = {1*MB},
890 .destBufSize= {1*KB},
891 .runFlag = (UDMA_TEST_RF_MCU_BC),
892 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
893 },
894 {
895 .enableTest = TEST_ENABLE,
896 .tcId = 3493U,
897 .tcName = "MCU NAVSS 2D Blockcpy MSMC circular 1KB to MSMC circular 1KB performance test",
898 .disableInfo= NULL,
899 .printEnable= PRINT_ENABLE,
900 .prfEnable = PRF_ENABLE,
901 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
902 .dcEnable = DATA_CHECK_DISABLE,
903 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
904 .numTasks = 1U,
905 .testType = {UDMA_TT_BLK_CPY},
906 .testFxnPtr = {&udmaTestBlkcpyTc},
907 .pacingTime = {PACING_NONE},
908 .numCh = {1U},
909 .instId = {UDMA_INST_ID_MCU_0},
910 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
911 .qdepth = {UDMA_TEST_DEF_QDEPTH},
912 .icnt = {
913 {1*KB, 1U, 1*KB, 1U}
914 },
915 .dicnt = {
916 {1*KB, 1U, 1*KB, 1U}
917 },
918 .dim = {
919 {0U, 0U, 0U}
920 },
921 .ddim = {
922 {0U, 0U, 0U}
923 },
924 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC},
925 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
926 .srcBufSize = {1*KB},
927 .destBufSize= {1*KB},
928 .runFlag = (UDMA_TEST_RF_MCU_BC),
929 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
930 },
931 {
932 .enableTest = TEST_ENABLE,
933 .tcId = 3494U,
934 .tcName = "Main NAVSS Blockcpy DDR 1MB to DDR 1MB from multiple tasks",
935 .disableInfo= NULL,
936 .printEnable= PRINT_DISABLE,
937 .prfEnable = PRF_ENABLE,
938 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
939 .dcEnable = DATA_CHECK_DISABLE,
940 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
941 .numTasks = UDMA_TEST_MAX_MAIN_BC_CH,
942 .testType = {UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY},
943 .testFxnPtr = {&udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc},
944 .pacingTime = {PACING_NONE, PACING_NONE, PACING_NONE, PACING_NONE},
945 .numCh = {1U, 1U, 1U, 1U},
946 .instId = {UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0},
947 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF},
948 .qdepth = {UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH},
949 .icnt = {
950 {1*KB, 1U, 1*KB, 1U},
951 {1*KB, 1U, 1*KB, 1U},
952 {1*KB, 1U, 1*KB, 1U},
953 {1*KB, 1U, 1*KB, 1U},
954 },
955 .dicnt = {
956 {1*KB, 1U, 1*KB, 1U},
957 {1*KB, 1U, 1*KB, 1U},
958 {1*KB, 1U, 1*KB, 1U},
959 {1*KB, 1U, 1*KB, 1U},
960 },
961 .dim = {
962 {1*KB, 1*KB, 0U},
963 {1*KB, 1*KB, 0U},
964 {1*KB, 1*KB, 0U},
965 {1*KB, 1*KB, 0U},
966 },
967 .ddim = {
968 {1*KB, 1*KB, 0U},
969 {1*KB, 1*KB, 0U},
970 {1*KB, 1*KB, 0U},
971 {1*KB, 1*KB, 0U},
972 },
973 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR},
974 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR},
975 .srcBufSize = {1*MB, 1*MB, 1*MB, 1*MB},
976 .destBufSize= {1*MB, 1*MB, 1*MB, 1*MB},
977 .runFlag = (UDMA_TEST_RF_MAIN_BC_MT),
978 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
979 },
980 {
981 .enableTest = TEST_ENABLE,
982 .tcId = 3495U,
983 .tcName = "MCU NAVSS Blockcpy DDR 1MB to DDR 1MB from multiple tasks",
984 .disableInfo= NULL,
985 .printEnable= PRINT_DISABLE,
986 .prfEnable = PRF_ENABLE,
987 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
988 .dcEnable = DATA_CHECK_DISABLE,
989 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
990 .numTasks = UDMA_TEST_MAX_MCU_BC_CH,
991 .testType = {UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY},
992 .testFxnPtr = {&udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc},
993 .pacingTime = {PACING_NONE, PACING_NONE, PACING_NONE, PACING_NONE},
994 .numCh = {1U, 1U, 1U, 1U},
995 .instId = {UDMA_INST_ID_MCU_0, UDMA_INST_ID_MCU_0, UDMA_INST_ID_MCU_0, UDMA_INST_ID_MCU_0},
996 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF},
997 .qdepth = {UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH},
998 .icnt = {
999 {1*KB, 1U, 1*KB, 1U},
1000 {1*KB, 1U, 1*KB, 1U},
1001 {1*KB, 1U, 1*KB, 1U},
1002 {1*KB, 1U, 1*KB, 1U},
1003 },
1004 .dicnt = {
1005 {1*KB, 1U, 1*KB, 1U},
1006 {1*KB, 1U, 1*KB, 1U},
1007 {1*KB, 1U, 1*KB, 1U},
1008 {1*KB, 1U, 1*KB, 1U},
1009 },
1010 .dim = {
1011 {1*KB, 1*KB, 0U},
1012 {1*KB, 1*KB, 0U},
1013 {1*KB, 1*KB, 0U},
1014 {1*KB, 1*KB, 0U},
1015 },
1016 .ddim = {
1017 {1*KB, 1*KB, 0U},
1018 {1*KB, 1*KB, 0U},
1019 {1*KB, 1*KB, 0U},
1020 {1*KB, 1*KB, 0U},
1021 },
1022 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR},
1023 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR},
1024 .srcBufSize = {1*MB, 1*MB, 1*MB, 1*MB},
1025 .destBufSize= {1*MB, 1*MB, 1*MB, 1*MB},
1026 .runFlag = (UDMA_TEST_RF_MCU_BC_MT),
1027 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
1028 },
1029 {
1030 .enableTest = TEST_ENABLE,
1031 .tcId = 3496U,
1032 .tcName = "Main NAVSS Blockcpy MSMC to MSMC 1KBx1K (1MB) circular from multiple tasks",
1033 .disableInfo= NULL,
1034 .printEnable= PRINT_DISABLE,
1035 .prfEnable = PRF_ENABLE,
1036 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
1037 .dcEnable = DATA_CHECK_DISABLE,
1038 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
1039 .numTasks = UDMA_TEST_MAX_MAIN_BC_CH,
1040 .testType = {UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY},
1041 .testFxnPtr = {&udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc},
1042 .pacingTime = {PACING_NONE, PACING_NONE, PACING_NONE, PACING_NONE},
1043 .numCh = {1U, 1U, 1U, 1U},
1044 .instId = {UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0},
1045 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF},
1046 .qdepth = {UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH},
1047 .icnt = {
1048 {1*KB, 1U, 1*KB, 1U},
1049 {1*KB, 1U, 1*KB, 1U},
1050 {1*KB, 1U, 1*KB, 1U},
1051 {1*KB, 1U, 1*KB, 1U},
1052 },
1053 .dicnt = {
1054 {1*KB, 1U, 1*KB, 1U},
1055 {1*KB, 1U, 1*KB, 1U},
1056 {1*KB, 1U, 1*KB, 1U},
1057 {1*KB, 1U, 1*KB, 1U},
1058 },
1059 .dim = {
1060 {0U, 0U, 0U},
1061 {0U, 0U, 0U},
1062 {0U, 0U, 0U},
1063 {0U, 0U, 0U},
1064 },
1065 .ddim = {
1066 {0U, 0U, 0U},
1067 {0U, 0U, 0U},
1068 {0U, 0U, 0U},
1069 {0U, 0U, 0U},
1070 },
1071 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC},
1072 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC},
1073 .srcBufSize = {1*KB, 1*KB, 1*KB, 1*KB},
1074 .destBufSize= {1*KB, 1*KB, 1*KB, 1*KB},
1075 .runFlag = (UDMA_TEST_RF_MAIN_BC_MT),
1076 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
1077 },
1078 {
1079 .enableTest = TEST_ENABLE,
1080 .tcId = 3497U,
1081 .tcName = "MCU NAVSS Blockcpy MSMC to MSMC circular 1KBx1K (1MB) from multiple tasks",
1082 .disableInfo= NULL,
1083 .printEnable= PRINT_DISABLE,
1084 .prfEnable = PRF_ENABLE,
1085 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
1086 .dcEnable = DATA_CHECK_DISABLE,
1087 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
1088 .numTasks = UDMA_TEST_MAX_MCU_BC_CH,
1089 .testType = {UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY},
1090 .testFxnPtr = {&udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc},
1091 .pacingTime = {PACING_NONE, PACING_NONE, PACING_NONE, PACING_NONE},
1092 .numCh = {1U, 1U, 1U, 1U},
1093 .instId = {UDMA_INST_ID_MCU_0, UDMA_INST_ID_MCU_0, UDMA_INST_ID_MCU_0, UDMA_INST_ID_MCU_0},
1094 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF},
1095 .qdepth = {UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH},
1096 .icnt = {
1097 {1*KB, 1U, 1*KB, 1U},
1098 {1*KB, 1U, 1*KB, 1U},
1099 {1*KB, 1U, 1*KB, 1U},
1100 {1*KB, 1U, 1*KB, 1U},
1101 },
1102 .dicnt = {
1103 {1*KB, 1U, 1*KB, 1U},
1104 {1*KB, 1U, 1*KB, 1U},
1105 {1*KB, 1U, 1*KB, 1U},
1106 {1*KB, 1U, 1*KB, 1U},
1107 },
1108 .dim = {
1109 {0U, 0U, 0U},
1110 {0U, 0U, 0U},
1111 {0U, 0U, 0U},
1112 {0U, 0U, 0U},
1113 },
1114 .ddim = {
1115 {0U, 0U, 0U},
1116 {0U, 0U, 0U},
1117 {0U, 0U, 0U},
1118 {0U, 0U, 0U},
1119 },
1120 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC},
1121 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC},
1122 .srcBufSize = {1*KB, 1*KB, 1*KB, 1*KB},
1123 .destBufSize= {1*KB, 1*KB, 1*KB, 1*KB},
1124 .runFlag = (UDMA_TEST_RF_MCU_BC_MT),
1125 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
1126 },
1127 {
1128 .enableTest = TEST_ENABLE,
1129 .tcId = 3498U,
1130 .tcName = "Main NAVSS 2D Blockcpy DDR 4MB to MSMC circular 4KB at 20ms pacing for 10 seconds",
1131 .disableInfo= NULL,
1132 .printEnable= PRINT_ENABLE,
1133 .prfEnable = PRF_ENABLE,
1134 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL),
1135 .dcEnable = DATA_CHECK_DISABLE,
1136 .loopCnt = 500U,
1137 .numTasks = 1U,
1138 .testType = {UDMA_TT_BLK_CPY},
1139 .testFxnPtr = {&udmaTestBlkcpyTc},
1140 .pacingTime = {DEF_PACING},
1141 .numCh = {1U},
1142 .instId = {UDMA_INST_ID_MAIN_0},
1143 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
1144 .qdepth = {UDMA_TEST_DEF_QDEPTH},
1145 .icnt = {
1146 {1*KB, 4U, 1*KB, 1U}
1147 },
1148 .dicnt = {
1149 {1*KB, 4U, 1*KB, 1U}
1150 },
1151 .dim = {
1152 {1*KB, 4*KB, 4*MB}
1153 },
1154 .ddim = {
1155 {0U, 0U, 0U}
1156 },
1157 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR},
1158 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
1159 .srcBufSize = {4U*MB},
1160 .destBufSize= {4U*KB},
1161 .runFlag = (UDMA_TEST_RF_MAIN_BC_PACING),
1162 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
1163 },
1164 #if defined (UDMA_UTC_ID_MSMC_DRU0)
1165 {
1166 .enableTest = TEST_ENABLE,
1167 .tcId = 3499U,
1168 .tcName = "DRU Indirect Blockcpy DDR to DDR in polling mode",
1169 .disableInfo= NULL,
1170 .printEnable= PRINT_ENABLE,
1171 .prfEnable = PRF_DISABLE,
1172 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1173 .dcEnable = DATA_CHECK_ENABLE,
1174 .loopCnt = USE_DEF_LP_CNT,
1175 .numTasks = 1U,
1176 .testType = {UDMA_TT_DRU_INDIRECT},
1177 .testFxnPtr = {&udmaTestBlkcpyTc},
1178 .pacingTime = {PACING_NONE},
1179 .numCh = {1U},
1180 .instId = {UDMA_INST_ID_MAIN_0},
1181 .chPrmId = {UDMA_TEST_CH_PRMID_DRU_DEF},
1182 .qdepth = {USE_DEF_QDEPTH},
1183 .icnt = {
1184 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1185 },
1186 .dicnt = {
1187 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1188 },
1189 .dim = {
1190 {0U, 0U, 0U}
1191 },
1192 .ddim = {
1193 {0U, 0U, 0U}
1194 },
1195 .heapIdSrc = {DEF_HEAP_ID},
1196 .heapIdDest = {DEF_HEAP_ID},
1197 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1198 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1199 .runFlag = (UDMA_TEST_RF_DRU | UDMA_TEST_RF_CFG_DYN),
1200 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
1201 },
1202 {
1203 .enableTest = TEST_ENABLE,
1204 .tcId = 3500U,
1205 .tcName = "DRU Indirect Blockcpy DDR to DDR in interrupt mode",
1206 .disableInfo= NULL,
1207 .printEnable= PRINT_ENABLE,
1208 .prfEnable = PRF_DISABLE,
1209 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1210 .dcEnable = DATA_CHECK_ENABLE,
1211 .loopCnt = USE_DEF_LP_CNT,
1212 .numTasks = 1U,
1213 .testType = {UDMA_TT_DRU_INDIRECT},
1214 .testFxnPtr = {&udmaTestBlkcpyTc},
1215 .pacingTime = {PACING_NONE},
1216 .numCh = {1U},
1217 .instId = {UDMA_INST_ID_MAIN_0},
1218 .chPrmId = {UDMA_TEST_CH_PRMID_DRU_INTR_DEF},
1219 .qdepth = {USE_DEF_QDEPTH},
1220 .icnt = {
1221 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1222 },
1223 .dicnt = {
1224 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1225 },
1226 .dim = {
1227 {0U, 0U, 0U}
1228 },
1229 .ddim = {
1230 {0U, 0U, 0U}
1231 },
1232 .heapIdSrc = {DEF_HEAP_ID},
1233 .heapIdDest = {DEF_HEAP_ID},
1234 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1235 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1236 .runFlag = (UDMA_TEST_RF_DRU | UDMA_TEST_RF_CFG_DYN),
1237 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
1238 },
1239 {
1240 .enableTest = TEST_ENABLE,
1241 .tcId = 3501U,
1242 .tcName = "DRU Indirect Blockcpy DDR 1MB to DDR 1MB performance test",
1243 .disableInfo= NULL,
1244 .printEnable= PRINT_ENABLE,
1245 .prfEnable = PRF_ENABLE,
1246 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
1247 .dcEnable = DATA_CHECK_DISABLE,
1248 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
1249 .numTasks = 1U,
1250 .testType = {UDMA_TT_DRU_INDIRECT},
1251 .testFxnPtr = {&udmaTestBlkcpyTc},
1252 .pacingTime = {PACING_NONE},
1253 .numCh = {1U},
1254 .instId = {UDMA_INST_ID_MAIN_0},
1255 .chPrmId = {UDMA_TEST_CH_PRMID_DRU_INTR_DEF},
1256 .qdepth = {UDMA_TEST_PERF_QDEPTH},
1257 .icnt = {
1258 {1*KB, 1U, 1*KB, 1U},
1259 },
1260 .dicnt = {
1261 {1*KB, 1U, 1*KB, 1U},
1262 },
1263 .dim = {
1264 {1*KB, 1*KB, 0U},
1265 },
1266 .ddim = {
1267 {1*KB, 1*KB, 0U},
1268 },
1269 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR},
1270 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR},
1271 .srcBufSize = {1*MB},
1272 .destBufSize= {1*MB},
1273 .runFlag = (UDMA_TEST_RF_DRU),
1274 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
1275 },
1276 {
1277 .enableTest = TEST_ENABLE,
1278 .tcId = 3502U,
1279 .tcName = "DRU Indirect 2D Blockcpy MSMC circular 1KB to DDR 1MB performance test",
1280 .disableInfo= NULL,
1281 .printEnable= PRINT_ENABLE,
1282 .prfEnable = PRF_ENABLE,
1283 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
1284 .dcEnable = DATA_CHECK_DISABLE,
1285 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
1286 .numTasks = 1U,
1287 .testType = {UDMA_TT_DRU_INDIRECT},
1288 .testFxnPtr = {&udmaTestBlkcpyTc},
1289 .pacingTime = {PACING_NONE},
1290 .numCh = {1U},
1291 .instId = {UDMA_INST_ID_MAIN_0},
1292 .chPrmId = {UDMA_TEST_CH_PRMID_DRU_INTR_DEF},
1293 .qdepth = {UDMA_TEST_DEF_QDEPTH},
1294 .icnt = {
1295 {1*KB, 1U, 1*KB, 1U}
1296 },
1297 .dicnt = {
1298 {1*KB, 1U, 1*KB, 1U}
1299 },
1300 .dim = {
1301 {0U, 0U, 0U}
1302 },
1303 .ddim = {
1304 {1*KB, 1*KB, 0U}
1305 },
1306 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC},
1307 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR},
1308 .srcBufSize = {1*KB},
1309 .destBufSize= {1*MB},
1310 .runFlag = (UDMA_TEST_RF_DRU),
1311 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
1312 },
1313 {
1314 .enableTest = TEST_ENABLE,
1315 .tcId = 3503U,
1316 .tcName = "DRU Indirect 2D Blockcpy DDR 1MB to MSMC circular 1KB performance test",
1317 .disableInfo= NULL,
1318 .printEnable= PRINT_ENABLE,
1319 .prfEnable = PRF_ENABLE,
1320 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
1321 .dcEnable = DATA_CHECK_DISABLE,
1322 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
1323 .numTasks = 1U,
1324 .testType = {UDMA_TT_DRU_INDIRECT},
1325 .testFxnPtr = {&udmaTestBlkcpyTc},
1326 .pacingTime = {PACING_NONE},
1327 .numCh = {1U},
1328 .instId = {UDMA_INST_ID_MAIN_0},
1329 .chPrmId = {UDMA_TEST_CH_PRMID_DRU_INTR_DEF},
1330 .qdepth = {UDMA_TEST_DEF_QDEPTH},
1331 .icnt = {
1332 {1*KB, 1U, 1*KB, 1U}
1333 },
1334 .dicnt = {
1335 {1*KB, 1U, 1*KB, 1U}
1336 },
1337 .dim = {
1338 {1*KB, 1*KB, 0U}
1339 },
1340 .ddim = {
1341 {0U, 0U, 0U}
1342 },
1343 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR},
1344 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
1345 .srcBufSize = {1*MB},
1346 .destBufSize= {1*KB},
1347 .runFlag = (UDMA_TEST_RF_DRU),
1348 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
1349 },
1350 {
1351 .enableTest = TEST_ENABLE,
1352 .tcId = 3504U,
1353 .tcName = "DRU Indirect 2D Blockcpy MSMC circular 1KB to MSMC circular 1KB performance test",
1354 .disableInfo= NULL,
1355 .printEnable= PRINT_ENABLE,
1356 .prfEnable = PRF_ENABLE,
1357 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
1358 .dcEnable = DATA_CHECK_DISABLE,
1359 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
1360 .numTasks = 1U,
1361 .testType = {UDMA_TT_DRU_INDIRECT},
1362 .testFxnPtr = {&udmaTestBlkcpyTc},
1363 .pacingTime = {PACING_NONE},
1364 .numCh = {1U},
1365 .instId = {UDMA_INST_ID_MAIN_0},
1366 .chPrmId = {UDMA_TEST_CH_PRMID_DRU_INTR_DEF},
1367 .qdepth = {UDMA_TEST_DEF_QDEPTH},
1368 .icnt = {
1369 {1*KB, 1U, 1*KB, 1U}
1370 },
1371 .dicnt = {
1372 {1*KB, 1U, 1*KB, 1U}
1373 },
1374 .dim = {
1375 {0U, 0U, 0U}
1376 },
1377 .ddim = {
1378 {0U, 0U, 0U}
1379 },
1380 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC},
1381 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
1382 .srcBufSize = {1*KB},
1383 .destBufSize= {1*KB},
1384 .runFlag = (UDMA_TEST_RF_DRU),
1385 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
1386 },
1387 {
1388 .enableTest = TEST_ENABLE,
1389 .tcId = 3505U,
1390 .tcName = "DRU Indirect Blockcpy DDR 1MB to DDR 1MB from multiple tasks",
1391 .disableInfo= NULL,
1392 .printEnable= PRINT_DISABLE,
1393 .prfEnable = PRF_ENABLE,
1394 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
1395 .dcEnable = DATA_CHECK_DISABLE,
1396 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
1397 .numTasks = UDMA_TEST_MAX_DRU_CH,
1398 .testType = {UDMA_TT_DRU_INDIRECT, UDMA_TT_DRU_INDIRECT, UDMA_TT_DRU_INDIRECT, UDMA_TT_DRU_INDIRECT},
1399 .testFxnPtr = {&udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc},
1400 .pacingTime = {PACING_NONE, PACING_NONE, PACING_NONE, PACING_NONE},
1401 .numCh = {1U, 1U, 1U, 1U},
1402 .instId = {UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0},
1403 .chPrmId = {UDMA_TEST_CH_PRMID_DRU_INTR_DEF, UDMA_TEST_CH_PRMID_DRU_INTR_DEF, UDMA_TEST_CH_PRMID_DRU_INTR_DEF, UDMA_TEST_CH_PRMID_DRU_INTR_DEF},
1404 .qdepth = {UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH},
1405 .icnt = {
1406 {1*KB, 1U, 1*KB, 1U},
1407 {1*KB, 1U, 1*KB, 1U},
1408 {1*KB, 1U, 1*KB, 1U},
1409 {1*KB, 1U, 1*KB, 1U},
1410 },
1411 .dicnt = {
1412 {1*KB, 1U, 1*KB, 1U},
1413 {1*KB, 1U, 1*KB, 1U},
1414 {1*KB, 1U, 1*KB, 1U},
1415 {1*KB, 1U, 1*KB, 1U},
1416 },
1417 .dim = {
1418 {1*KB, 1*KB, 0U},
1419 {1*KB, 1*KB, 0U},
1420 {1*KB, 1*KB, 0U},
1421 {1*KB, 1*KB, 0U},
1422 },
1423 .ddim = {
1424 {1*KB, 1*KB, 0U},
1425 {1*KB, 1*KB, 0U},
1426 {1*KB, 1*KB, 0U},
1427 {1*KB, 1*KB, 0U},
1428 },
1429 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR},
1430 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR},
1431 .srcBufSize = {1*MB, 1*MB, 1*MB, 1*MB},
1432 .destBufSize= {1*MB, 1*MB, 1*MB, 1*MB},
1433 .runFlag = (UDMA_TEST_RF_DRU_MT),
1434 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
1435 },
1436 {
1437 .enableTest = TEST_ENABLE,
1438 .tcId = 3506U,
1439 .tcName = "DRU Indirect Blockcpy MSMC to MSMC 1KBx1K (1MB) circular from multiple tasks",
1440 .disableInfo= NULL,
1441 .printEnable= PRINT_DISABLE,
1442 .prfEnable = PRF_ENABLE,
1443 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
1444 .dcEnable = DATA_CHECK_DISABLE,
1445 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
1446 .numTasks = UDMA_TEST_MAX_DRU_CH,
1447 .testType = {UDMA_TT_DRU_INDIRECT, UDMA_TT_DRU_INDIRECT, UDMA_TT_DRU_INDIRECT, UDMA_TT_DRU_INDIRECT},
1448 .testFxnPtr = {&udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc},
1449 .pacingTime = {PACING_NONE, PACING_NONE, PACING_NONE, PACING_NONE},
1450 .numCh = {1U, 1U, 1U, 1U},
1451 .instId = {UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0},
1452 .chPrmId = {UDMA_TEST_CH_PRMID_DRU_INTR_DEF, UDMA_TEST_CH_PRMID_DRU_INTR_DEF, UDMA_TEST_CH_PRMID_DRU_INTR_DEF, UDMA_TEST_CH_PRMID_DRU_INTR_DEF},
1453 .qdepth = {UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH},
1454 .icnt = {
1455 {1*KB, 1U, 1*KB, 1U},
1456 {1*KB, 1U, 1*KB, 1U},
1457 {1*KB, 1U, 1*KB, 1U},
1458 {1*KB, 1U, 1*KB, 1U},
1459 },
1460 .dicnt = {
1461 {1*KB, 1U, 1*KB, 1U},
1462 {1*KB, 1U, 1*KB, 1U},
1463 {1*KB, 1U, 1*KB, 1U},
1464 {1*KB, 1U, 1*KB, 1U},
1465 },
1466 .dim = {
1467 {0U, 0U, 0U},
1468 {0U, 0U, 0U},
1469 {0U, 0U, 0U},
1470 {0U, 0U, 0U},
1471 },
1472 .ddim = {
1473 {0U, 0U, 0U},
1474 {0U, 0U, 0U},
1475 {0U, 0U, 0U},
1476 {0U, 0U, 0U},
1477 },
1478 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC},
1479 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC},
1480 .srcBufSize = {1*KB, 1*KB, 1*KB, 1*KB},
1481 .destBufSize= {1*KB, 1*KB, 1*KB, 1*KB},
1482 .runFlag = (UDMA_TEST_RF_DRU_MT),
1483 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
1484 },
1485 #endif /* #if defined (UDMA_UTC_ID_MSMC_DRU0) */
1486 {
1487 .enableTest = TEST_ENABLE,
1488 .tcId = 3507U,
1489 .tcName = "Proxy queue and dequeue testcase",
1490 .disableInfo= NULL,
1491 .printEnable= PRINT_ENABLE,
1492 .prfEnable = PRF_DISABLE,
1493 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1494 .dcEnable = DATA_CHECK_ENABLE,
1495 .loopCnt = 5U,
1496 .numTasks = 1U,
1497 .testType = {UDMA_TT_MISC},
1498 .testFxnPtr = {&udmaTestRingProxyTc},
1499 /* All other below parameters not used in this testcase except ring params */
1500 .pacingTime = {PACING_NONE},
1501 .numCh = {1U},
1502 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1503 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1504 .qdepth = {USE_DEF_QDEPTH},
1505 .icnt = {
1506 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1507 },
1508 .dicnt = {
1509 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1510 },
1511 .dim = {
1512 {0U, 0U, 0U}
1513 },
1514 .ddim = {
1515 {0U, 0U, 0U}
1516 },
1517 .heapIdSrc = {DEF_HEAP_ID},
1518 .heapIdDest = {DEF_HEAP_ID},
1519 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1520 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1521 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1522 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
1523 },
1524 {
1525 .enableTest = TEST_ENABLE,
1526 .tcId = 3508U,
1527 .tcName = "Ring flush API testcase",
1528 .disableInfo= NULL,
1529 .printEnable= PRINT_ENABLE,
1530 .prfEnable = PRF_DISABLE,
1531 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1532 .dcEnable = DATA_CHECK_ENABLE,
1533 .loopCnt = 1U,
1534 .numTasks = 1U,
1535 .testType = {UDMA_TT_MISC},
1536 .testFxnPtr = {&udmaTestRingFlushTc},
1537 /* All other below parameters not used in this testcase except ring params */
1538 .pacingTime = {PACING_NONE},
1539 .numCh = {1U},
1540 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1541 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1542 .qdepth = {USE_DEF_QDEPTH},
1543 .icnt = {
1544 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1545 },
1546 .dicnt = {
1547 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1548 },
1549 .dim = {
1550 {0U, 0U, 0U}
1551 },
1552 .ddim = {
1553 {0U, 0U, 0U}
1554 },
1555 .heapIdSrc = {DEF_HEAP_ID},
1556 .heapIdDest = {DEF_HEAP_ID},
1557 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1558 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1559 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1560 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
1561 },
1562 {
1563 .enableTest = TEST_ENABLE,
1564 .tcId = 3509U,
1565 .tcName = "Ring event testcase in interrupt mode",
1566 .disableInfo= NULL,
1567 .printEnable= PRINT_ENABLE,
1568 .prfEnable = PRF_DISABLE,
1569 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1570 .dcEnable = DATA_CHECK_ENABLE,
1571 .loopCnt = 10U,
1572 .numTasks = 1U,
1573 .testType = {UDMA_TT_MISC},
1574 .testFxnPtr = {&udmaTestRingEventTc},
1575 /* All other below parameters not used in this testcase except ring params */
1576 .pacingTime = {PACING_NONE},
1577 .numCh = {1U},
1578 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1579 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1580 .qdepth = {USE_DEF_QDEPTH},
1581 .icnt = {
1582 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1583 },
1584 .dicnt = {
1585 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1586 },
1587 .dim = {
1588 {0U, 0U, 0U}
1589 },
1590 .ddim = {
1591 {0U, 0U, 0U}
1592 },
1593 .heapIdSrc = {DEF_HEAP_ID},
1594 .heapIdDest = {DEF_HEAP_ID},
1595 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1596 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1597 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1598 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_INTR,
1599 },
1600 {
1601 .enableTest = TEST_ENABLE,
1602 .tcId = 3510U,
1603 .tcName = "Ring event testcase in event polled mode",
1604 .disableInfo= NULL,
1605 .printEnable= PRINT_ENABLE,
1606 .prfEnable = PRF_DISABLE,
1607 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1608 .dcEnable = DATA_CHECK_ENABLE,
1609 .loopCnt = 10U,
1610 .numTasks = 1U,
1611 .testType = {UDMA_TT_MISC},
1612 .testFxnPtr = {&udmaTestRingEventTc},
1613 /* All other below parameters not used in this testcase except ring params */
1614 .pacingTime = {PACING_NONE},
1615 .numCh = {1U},
1616 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1617 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1618 .qdepth = {USE_DEF_QDEPTH},
1619 .icnt = {
1620 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1621 },
1622 .dicnt = {
1623 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1624 },
1625 .dim = {
1626 {0U, 0U, 0U}
1627 },
1628 .ddim = {
1629 {0U, 0U, 0U}
1630 },
1631 .heapIdSrc = {DEF_HEAP_ID},
1632 .heapIdDest = {DEF_HEAP_ID},
1633 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1634 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1635 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1636 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_POLLED,
1637 },
1638 {
1639 .enableTest = TEST_ENABLE,
1640 .tcId = 3511U,
1641 .tcName = "Ring parameter check test",
1642 .disableInfo= NULL,
1643 .printEnable= PRINT_ENABLE,
1644 .prfEnable = PRF_DISABLE,
1645 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_NEGATIVE),
1646 .dcEnable = DATA_CHECK_ENABLE,
1647 .loopCnt = 1U,
1648 .numTasks = 1U,
1649 .testType = {UDMA_TT_MISC},
1650 .testFxnPtr = {&udmaTestRingParamCheckTc},
1651 /* All other below parameters not used in this testcase except ring params */
1652 .pacingTime = {PACING_NONE},
1653 .numCh = {1U},
1654 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1655 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1656 .qdepth = {USE_DEF_QDEPTH},
1657 .icnt = {
1658 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1659 },
1660 .dicnt = {
1661 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1662 },
1663 .dim = {
1664 {0U, 0U, 0U}
1665 },
1666 .ddim = {
1667 {0U, 0U, 0U}
1668 },
1669 .heapIdSrc = {DEF_HEAP_ID},
1670 .heapIdDest = {DEF_HEAP_ID},
1671 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1672 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1673 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1674 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_POLLED,
1675 },
1676 {
1677 .enableTest = TEST_ENABLE,
1678 .tcId = 3512U,
1679 .tcName = "Ring Utils Mem Size test",
1680 .disableInfo= NULL,
1681 .printEnable= PRINT_ENABLE,
1682 .prfEnable = PRF_DISABLE,
1683 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1684 .dcEnable = DATA_CHECK_ENABLE,
1685 .loopCnt = 1U,
1686 .numTasks = 1U,
1687 .testType = {UDMA_TT_MISC},
1688 .testFxnPtr = {&udmaTestRingUtilsMemSizeTc},
1689 /* All other below parameters not used in this testcase except ring params */
1690 .pacingTime = {PACING_NONE},
1691 .numCh = {1U},
1692 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1693 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1694 .qdepth = {USE_DEF_QDEPTH},
1695 .icnt = {
1696 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1697 },
1698 .dicnt = {
1699 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1700 },
1701 .dim = {
1702 {0U, 0U, 0U}
1703 },
1704 .ddim = {
1705 {0U, 0U, 0U}
1706 },
1707 .heapIdSrc = {DEF_HEAP_ID},
1708 .heapIdDest = {DEF_HEAP_ID},
1709 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1710 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1711 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1712 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_POLLED,
1713 },
1714 {
1715 .enableTest = TEST_ENABLE,
1716 .tcId = 3682U,
1717 .tcName = "Ring Mem Pointer test",
1718 .disableInfo= NULL,
1719 .printEnable= PRINT_ENABLE,
1720 .prfEnable = PRF_DISABLE,
1721 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1722 .dcEnable = DATA_CHECK_ENABLE,
1723 .loopCnt = 1U,
1724 .numTasks = 1U,
1725 .testType = {UDMA_TT_MISC},
1726 .testFxnPtr = {&udmaTestRingMemPtrTc},
1727 /* All other below parameters not used in this testcase except ring params */
1728 .pacingTime = {PACING_NONE},
1729 .numCh = {1U},
1730 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1731 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1732 .qdepth = {USE_DEF_QDEPTH},
1733 .icnt = {
1734 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1735 },
1736 .dicnt = {
1737 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1738 },
1739 .dim = {
1740 {0U, 0U, 0U}
1741 },
1742 .ddim = {
1743 {0U, 0U, 0U}
1744 },
1745 .heapIdSrc = {DEF_HEAP_ID},
1746 .heapIdDest = {DEF_HEAP_ID},
1747 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1748 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1749 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1750 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_POLLED,
1751 },
1752 {
1753 .enableTest = TEST_ENABLE,
1754 .tcId = 3726U,
1755 .tcName = "Ring attach and detach testcase",
1756 .disableInfo= NULL,
1757 .printEnable= PRINT_ENABLE,
1758 .prfEnable = PRF_DISABLE,
1759 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1760 .dcEnable = DATA_CHECK_ENABLE,
1761 .loopCnt = 5U,
1762 .numTasks = 1U,
1763 .testType = {UDMA_TT_MISC},
1764 .testFxnPtr = {&udmaTestRingAttachTc},
1765 /* All other below parameters not used in this testcase except ring params */
1766 .pacingTime = {PACING_NONE},
1767 .numCh = {1U},
1768 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1769 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1770 .qdepth = {USE_DEF_QDEPTH},
1771 .icnt = {
1772 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1773 },
1774 .dicnt = {
1775 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1776 },
1777 .dim = {
1778 {0U, 0U, 0U}
1779 },
1780 .ddim = {
1781 {0U, 0U, 0U}
1782 },
1783 .heapIdSrc = {DEF_HEAP_ID},
1784 .heapIdDest = {DEF_HEAP_ID},
1785 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1786 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1787 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1788 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
1789 },
1790 {
1791 .enableTest = TEST_ENABLE,
1792 .tcId = 4644U,
1793 .tcName = "Ring reset workaround test",
1794 .disableInfo= NULL,
1795 .printEnable= PRINT_ENABLE,
1796 .prfEnable = PRF_DISABLE,
1797 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1798 .dcEnable = DATA_CHECK_ENABLE,
1799 .loopCnt = 1U,
1800 .numTasks = 1U,
1801 .testType = {UDMA_TT_MISC},
1802 .testFxnPtr = {&udmaTestRingResetTc},
1803 /* All other below parameters not used in this testcase except ring params */
1804 .pacingTime = {PACING_NONE},
1805 .numCh = {1U},
1806 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1807 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1808 .qdepth = {USE_DEF_QDEPTH},
1809 .icnt = {
1810 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1811 },
1812 .dicnt = {
1813 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1814 },
1815 .dim = {
1816 {0U, 0U, 0U}
1817 },
1818 .ddim = {
1819 {0U, 0U, 0U}
1820 },
1821 .heapIdSrc = {DEF_HEAP_ID},
1822 .heapIdDest = {DEF_HEAP_ID},
1823 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1824 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1825 .runFlag = (UDMA_TEST_RF_SOC_AM65XX | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1826 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
1827 },
1828 {
1829 .enableTest = TEST_ENABLE,
1830 .tcId = 4693U,
1831 .tcName = "Ring prime test",
1832 .disableInfo= NULL,
1833 .printEnable= PRINT_ENABLE,
1834 .prfEnable = PRF_DISABLE,
1835 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1836 .dcEnable = DATA_CHECK_ENABLE,
1837 .loopCnt = 1U,
1838 .numTasks = 1U,
1839 .testType = {UDMA_TT_MISC},
1840 .testFxnPtr = {&udmaTestRingPrimeTc},
1841 /* All other below parameters not used in this testcase except ring params */
1842 .pacingTime = {PACING_NONE},
1843 .numCh = {1U},
1844 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1845 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1846 .qdepth = {USE_DEF_QDEPTH},
1847 .icnt = {
1848 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1849 },
1850 .dicnt = {
1851 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1852 },
1853 .dim = {
1854 {0U, 0U, 0U}
1855 },
1856 .ddim = {
1857 {0U, 0U, 0U}
1858 },
1859 .heapIdSrc = {DEF_HEAP_ID},
1860 .heapIdDest = {DEF_HEAP_ID},
1861 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1862 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1863 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1864 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
1865 },
1866 {
1867 .enableTest = TEST_DISABLE,
1868 .tcId = 4636U,
1869 .tcName = "Ring Monitor Push and Pop Mode test",
1870 .disableInfo= "Blocked on SYSFW-2824",
1871 .printEnable= PRINT_ENABLE,
1872 .prfEnable = PRF_DISABLE,
1873 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1874 .dcEnable = DATA_CHECK_ENABLE,
1875 .loopCnt = 1U,
1876 .numTasks = 1U,
1877 .testType = {UDMA_TT_MISC},
1878 .testFxnPtr = {&udmaTestRingMonPushPopTc},
1879 /* All other below parameters not used in this testcase except ring params */
1880 .pacingTime = {PACING_NONE},
1881 .numCh = {1U},
1882 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1883 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1884 .qdepth = {USE_DEF_QDEPTH},
1885 .icnt = {
1886 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1887 },
1888 .dicnt = {
1889 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1890 },
1891 .dim = {
1892 {0U, 0U, 0U}
1893 },
1894 .ddim = {
1895 {0U, 0U, 0U}
1896 },
1897 .heapIdSrc = {DEF_HEAP_ID},
1898 .heapIdDest = {DEF_HEAP_ID},
1899 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1900 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1901 .runFlag = (UDMA_TEST_RF_SOC_J721E | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1902 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
1903 },
1904 {
1905 .enableTest = TEST_DISABLE,
1906 .tcId = 4637U,
1907 .tcName = "Ring Monitor Low Threshold Mode test",
1908 .disableInfo= "Blocked on SYSFW-2824",
1909 .printEnable= PRINT_ENABLE,
1910 .prfEnable = PRF_DISABLE,
1911 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1912 .dcEnable = DATA_CHECK_ENABLE,
1913 .loopCnt = 1U,
1914 .numTasks = 1U,
1915 .testType = {UDMA_TT_MISC},
1916 .testFxnPtr = {&udmaTestRingMonLowThresholdTc},
1917 /* All other below parameters not used in this testcase except ring params */
1918 .pacingTime = {PACING_NONE},
1919 .numCh = {1U},
1920 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1921 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1922 .qdepth = {USE_DEF_QDEPTH},
1923 .icnt = {
1924 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1925 },
1926 .dicnt = {
1927 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1928 },
1929 .dim = {
1930 {0U, 0U, 0U}
1931 },
1932 .ddim = {
1933 {0U, 0U, 0U}
1934 },
1935 .heapIdSrc = {DEF_HEAP_ID},
1936 .heapIdDest = {DEF_HEAP_ID},
1937 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1938 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1939 .runFlag = (UDMA_TEST_RF_SOC_J721E | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1940 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
1941 },
1942 {
1943 .enableTest = TEST_DISABLE,
1944 .tcId = 4638U,
1945 .tcName = "Ring Monitor High Threshold Mode test",
1946 .disableInfo= "Blocked on SYSFW-2824",
1947 .printEnable= PRINT_ENABLE,
1948 .prfEnable = PRF_DISABLE,
1949 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
1950 .dcEnable = DATA_CHECK_ENABLE,
1951 .loopCnt = 1U,
1952 .numTasks = 1U,
1953 .testType = {UDMA_TT_MISC},
1954 .testFxnPtr = {&udmaTestRingMonHighThresholdTc},
1955 /* All other below parameters not used in this testcase except ring params */
1956 .pacingTime = {PACING_NONE},
1957 .numCh = {1U},
1958 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1959 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1960 .qdepth = {USE_DEF_QDEPTH},
1961 .icnt = {
1962 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
1963 },
1964 .dicnt = {
1965 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
1966 },
1967 .dim = {
1968 {0U, 0U, 0U}
1969 },
1970 .ddim = {
1971 {0U, 0U, 0U}
1972 },
1973 .heapIdSrc = {DEF_HEAP_ID},
1974 .heapIdDest = {DEF_HEAP_ID},
1975 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
1976 .destBufSize= {UDMA_TEST_DEF_DICNT0},
1977 .runFlag = (UDMA_TEST_RF_SOC_J721E | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
1978 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
1979 },
1980 {
1981 .enableTest = TEST_ENABLE,
1982 .tcId = 4238U,
1983 .tcName = "Proxy queue and dequeue testcase with allocated proxy",
1984 .disableInfo= NULL,
1985 .printEnable= PRINT_ENABLE,
1986 .prfEnable = PRF_ENABLE,
1987 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
1988 .dcEnable = DATA_CHECK_ENABLE,
1989 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
1990 .numTasks = 1U,
1991 .testType = {UDMA_TT_MISC},
1992 .testFxnPtr = {&udmaTestProxyPerformanceTc},
1993 /* All other below parameters not used in this testcase except ring params */
1994 .pacingTime = {PACING_NONE},
1995 .numCh = {1U},
1996 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
1997 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
1998 .qdepth = {USE_DEF_QDEPTH},
1999 .icnt = {
2000 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
2001 },
2002 .dicnt = {
2003 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
2004 },
2005 .dim = {
2006 {0U, 0U, 0U}
2007 },
2008 .ddim = {
2009 {0U, 0U, 0U}
2010 },
2011 .heapIdSrc = {DEF_HEAP_ID},
2012 .heapIdDest = {DEF_HEAP_ID},
2013 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
2014 .destBufSize= {UDMA_TEST_DEF_DICNT0},
2015 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
2016 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
2017 },
2018 {
2019 .enableTest = TEST_ENABLE,
2020 .tcId = 3729U,
2021 .tcName = "Flow attach and detach testcase",
2022 .disableInfo= NULL,
2023 .printEnable= PRINT_ENABLE,
2024 .prfEnable = PRF_DISABLE,
2025 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
2026 .dcEnable = DATA_CHECK_ENABLE,
2027 .loopCnt = 5U,
2028 .numTasks = 1U,
2029 .testType = {UDMA_TT_MISC},
2030 .testFxnPtr = {&udmaTestFlowAttachTc},
2031 /* All other below parameters not used in this testcase except ring params */
2032 .pacingTime = {PACING_NONE},
2033 .numCh = {1U},
2034 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
2035 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
2036 .qdepth = {USE_DEF_QDEPTH},
2037 .icnt = {
2038 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
2039 },
2040 .dicnt = {
2041 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
2042 },
2043 .dim = {
2044 {0U, 0U, 0U}
2045 },
2046 .ddim = {
2047 {0U, 0U, 0U}
2048 },
2049 .heapIdSrc = {DEF_HEAP_ID},
2050 .heapIdDest = {DEF_HEAP_ID},
2051 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
2052 .destBufSize= {UDMA_TEST_DEF_DICNT0},
2053 .runFlag = (UDMA_TEST_RF_FLOW | UDMA_TEST_RF_CFG_DYN),
2054 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
2055 },
2056 {
2057 .enableTest = TEST_ENABLE,
2058 .tcId = 4154U,
2059 .tcName = "Flow alloc and free testcase",
2060 .disableInfo= NULL,
2061 .printEnable= PRINT_ENABLE,
2062 .prfEnable = PRF_DISABLE,
2063 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
2064 .dcEnable = DATA_CHECK_ENABLE,
2065 .loopCnt = 1U,
2066 .numTasks = 1U,
2067 .testType = {UDMA_TT_MISC},
2068 .testFxnPtr = {&udmaTestFlowAllocTc},
2069 /* All other below parameters not used in this testcase except ring params */
2070 .pacingTime = {PACING_NONE},
2071 .numCh = {1U},
2072 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
2073 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
2074 .qdepth = {USE_DEF_QDEPTH},
2075 .icnt = {
2076 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
2077 },
2078 .dicnt = {
2079 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
2080 },
2081 .dim = {
2082 {0U, 0U, 0U}
2083 },
2084 .ddim = {
2085 {0U, 0U, 0U}
2086 },
2087 .heapIdSrc = {DEF_HEAP_ID},
2088 .heapIdDest = {DEF_HEAP_ID},
2089 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
2090 .destBufSize= {UDMA_TEST_DEF_DICNT0},
2091 .runFlag = (UDMA_TEST_RF_FLOW | UDMA_TEST_RF_CFG_DYN),
2092 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
2093 },
2094 {
2095 .enableTest = TEST_ENABLE,
2096 .tcId = 3513U,
2097 .tcName = "PSIL and PDMA macro verification testcase",
2098 .disableInfo= NULL,
2099 .printEnable= PRINT_ENABLE,
2100 .prfEnable = PRF_DISABLE,
2101 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
2102 .dcEnable = DATA_CHECK_ENABLE,
2103 .loopCnt = USE_DEF_LP_CNT,
2104 .numTasks = 1U,
2105 .testType = {UDMA_TT_MISC},
2106 .testFxnPtr = {&udmaTestPsilMacroTc},
2107 /* All other below parameters not used in this testcase */
2108 .pacingTime = {PACING_NONE},
2109 .numCh = {1U},
2110 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
2111 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
2112 .qdepth = {USE_DEF_QDEPTH},
2113 .icnt = {
2114 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
2115 },
2116 .dicnt = {
2117 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
2118 },
2119 .dim = {
2120 {0U, 0U, 0U}
2121 },
2122 .ddim = {
2123 {0U, 0U, 0U}
2124 },
2125 .heapIdSrc = {DEF_HEAP_ID},
2126 .heapIdDest = {DEF_HEAP_ID},
2127 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
2128 .destBufSize= {UDMA_TEST_DEF_DICNT0},
2129 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF),
2130 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2131 },
2132 {
2133 .enableTest = TEST_ENABLE,
2134 .tcId = 3514U,
2135 .tcName = "OSAL params testcase",
2136 .disableInfo= NULL,
2137 .printEnable= PRINT_ENABLE,
2138 .prfEnable = PRF_DISABLE,
2139 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
2140 .dcEnable = DATA_CHECK_ENABLE,
2141 .loopCnt = USE_DEF_LP_CNT,
2142 .numTasks = 1U,
2143 .testType = {UDMA_TT_MISC},
2144 .testFxnPtr = {&udmaTestOsalPrmsTc},
2145 .pacingTime = {PACING_NONE},
2146 .numCh = {1U},
2147 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
2148 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
2149 .qdepth = {USE_DEF_QDEPTH},
2150 .icnt = {
2151 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
2152 },
2153 .dicnt = {
2154 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
2155 },
2156 .dim = {
2157 {0U, 0U, 0U}
2158 },
2159 .ddim = {
2160 {0U, 0U, 0U}
2161 },
2162 .heapIdSrc = {DEF_HEAP_ID},
2163 .heapIdDest = {DEF_HEAP_ID},
2164 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
2165 .destBufSize= {UDMA_TEST_DEF_DICNT0},
2166 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
2167 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2168 },
2169 {
2170 .enableTest = TEST_ENABLE,
2171 .tcId = 3515U,
2172 .tcName = "TR make utility testcase",
2173 .disableInfo= NULL,
2174 .printEnable= PRINT_ENABLE,
2175 .prfEnable = PRF_DISABLE,
2176 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
2177 .dcEnable = DATA_CHECK_ENABLE,
2178 .loopCnt = USE_DEF_LP_CNT,
2179 .numTasks = 1U,
2180 .testType = {UDMA_TT_MISC},
2181 .testFxnPtr = {&udmaTestTrMakeTc},
2182 /* All other below parameters not used in this testcase */
2183 .pacingTime = {PACING_NONE},
2184 .numCh = {1U},
2185 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
2186 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
2187 .qdepth = {USE_DEF_QDEPTH},
2188 .icnt = {
2189 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
2190 },
2191 .dicnt = {
2192 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
2193 },
2194 .dim = {
2195 {0U, 0U, 0U}
2196 },
2197 .ddim = {
2198 {0U, 0U, 0U}
2199 },
2200 .heapIdSrc = {DEF_HEAP_ID},
2201 .heapIdDest = {DEF_HEAP_ID},
2202 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
2203 .destBufSize= {UDMA_TEST_DEF_DICNT0},
2204 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
2205 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2206 },
2207 {
2208 .enableTest = TEST_ENABLE,
2209 .tcId = 3733U,
2210 .tcName = "UDMA structure size print testcase",
2211 .disableInfo= NULL,
2212 .printEnable= PRINT_ENABLE,
2213 .prfEnable = PRF_DISABLE,
2214 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
2215 .dcEnable = DATA_CHECK_ENABLE,
2216 .loopCnt = USE_DEF_LP_CNT,
2217 .numTasks = 1U,
2218 .testType = {UDMA_TT_MISC},
2219 .testFxnPtr = {&udmaTestStructSizeTc},
2220 /* All other below parameters not used in this testcase */
2221 .pacingTime = {PACING_NONE},
2222 .numCh = {1U},
2223 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
2224 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
2225 .qdepth = {USE_DEF_QDEPTH},
2226 .icnt = {
2227 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
2228 },
2229 .dicnt = {
2230 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
2231 },
2232 .dim = {
2233 {0U, 0U, 0U}
2234 },
2235 .ddim = {
2236 {0U, 0U, 0U}
2237 },
2238 .heapIdSrc = {DEF_HEAP_ID},
2239 .heapIdDest = {DEF_HEAP_ID},
2240 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
2241 .destBufSize= {UDMA_TEST_DEF_DICNT0},
2242 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF),
2243 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2244 },
2245 {
2246 .enableTest = TEST_ENABLE,
2247 .tcId = 3707U,
2248 .tcName = "Out of range flow ID Event testcase",
2249 .disableInfo= NULL,
2250 .printEnable= PRINT_ENABLE,
2251 .prfEnable = PRF_DISABLE,
2252 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
2253 .dcEnable = DATA_CHECK_ENABLE,
2254 .loopCnt = 100U,
2255 .numTasks = 1U,
2256 .testType = {UDMA_TT_MISC},
2257 .testFxnPtr = {&udmaTestEventOutOfRangeFlow},
2258 /* All other below parameters not used in this testcase */
2259 .pacingTime = {PACING_NONE},
2260 .numCh = {1U},
2261 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
2262 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
2263 .qdepth = {USE_DEF_QDEPTH},
2264 .icnt = {
2265 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
2266 },
2267 .dicnt = {
2268 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
2269 },
2270 .dim = {
2271 {0U, 0U, 0U}
2272 },
2273 .ddim = {
2274 {0U, 0U, 0U}
2275 },
2276 .heapIdSrc = {DEF_HEAP_ID},
2277 .heapIdDest = {DEF_HEAP_ID},
2278 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
2279 .destBufSize= {UDMA_TEST_DEF_DICNT0},
2280 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
2281 .ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
2282 },
2283 {
2284 .enableTest = TEST_ENABLE,
2285 .tcId = 3905,
2286 .tcName = "PDK-3863 bug testcase: Udma_chDequeueTdResponse NULL check",
2287 .disableInfo= NULL,
2288 .printEnable= PRINT_ENABLE,
2289 .prfEnable = PRF_DISABLE,
2290 .tcType = (UDMA_TCT_FULL | UDMA_TCT_NEGATIVE),
2291 .dcEnable = DATA_CHECK_ENABLE,
2292 .loopCnt = USE_DEF_LP_CNT,
2293 .numTasks = 1U,
2294 .testType = {UDMA_TT_BLK_CPY},
2295 .testFxnPtr = {&udmaTestBugTcPDK_3863},
2296 .pacingTime = {PACING_NONE},
2297 .numCh = {1U},
2298 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
2299 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
2300 .qdepth = {USE_DEF_QDEPTH},
2301 .icnt = {
2302 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
2303 },
2304 .dicnt = {
2305 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
2306 },
2307 .dim = {
2308 {0U, 0U, 0U}
2309 },
2310 .ddim = {
2311 {0U, 0U, 0U}
2312 },
2313 .heapIdSrc = {DEF_HEAP_ID},
2314 .heapIdDest = {DEF_HEAP_ID},
2315 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
2316 .destBufSize= {UDMA_TEST_DEF_DICNT0},
2317 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
2318 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2319 },
2320 {
2321 .enableTest = TEST_ENABLE,
2322 .tcId = 3965,
2323 .tcName = "Channel pause and resume testcase",
2324 .disableInfo= NULL,
2325 .printEnable= PRINT_ENABLE,
2326 .prfEnable = PRF_DISABLE,
2327 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
2328 .dcEnable = DATA_CHECK_ENABLE,
2329 .loopCnt = 1U,
2330 .numTasks = 1U,
2331 .testType = {UDMA_TT_BLK_CPY},
2332 .testFxnPtr = {&udmaTestBlkcpyPauseResumeTc},
2333 .pacingTime = {PACING_NONE},
2334 .numCh = {1U},
2335 .instId = {UDMA_INST_ID_MAIN_0},
2336 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF},
2337 .qdepth = {USE_DEF_QDEPTH},
2338 .icnt = {
2339 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
2340 },
2341 .dicnt = {
2342 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
2343 },
2344 .dim = {
2345 {0U, 0U, 0U}
2346 },
2347 .ddim = {
2348 {0U, 0U, 0U}
2349 },
2350 .heapIdSrc = {DEF_HEAP_ID},
2351 .heapIdDest = {DEF_HEAP_ID},
2352 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
2353 .destBufSize= {UDMA_TEST_DEF_DICNT0},
2354 .runFlag = (UDMA_TEST_RF_MAIN_BC_PAUSE | UDMA_TEST_RF_CFG_DYN),
2355 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2356 },
2357 {
2358 .enableTest = TEST_ENABLE,
2359 .tcId = 4100U,
2360 .tcName = "Main NAVSS HC Blockcpy DDR 1MB to DDR 1MB performance test",
2361 .disableInfo= NULL,
2362 .printEnable= PRINT_ENABLE,
2363 .prfEnable = PRF_ENABLE,
2364 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
2365 .dcEnable = DATA_CHECK_DISABLE,
2366 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
2367 .numTasks = 1U,
2368 .testType = {UDMA_TT_BLK_CPY},
2369 .testFxnPtr = {&udmaTestBlkcpyTc},
2370 .pacingTime = {PACING_NONE},
2371 .numCh = {1U},
2372 .instId = {UDMA_INST_ID_MAIN_0},
2373 .chPrmId = {UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF},
2374 .qdepth = {UDMA_TEST_PERF_QDEPTH},
2375 .icnt = {
2376 {1*KB, 1U, 1*KB, 1U},
2377 },
2378 .dicnt = {
2379 {1*KB, 1U, 1*KB, 1U},
2380 },
2381 .dim = {
2382 {1*KB, 1*KB, 0U},
2383 },
2384 .ddim = {
2385 {1*KB, 1*KB, 0U},
2386 },
2387 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR},
2388 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR},
2389 .srcBufSize = {1*MB},
2390 .destBufSize= {1*MB},
2391 .runFlag = (UDMA_TEST_RF_MAIN_BC_HC),
2392 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2393 },
2394 {
2395 .enableTest = TEST_ENABLE,
2396 .tcId = 4101U,
2397 .tcName = "Main NAVSS 2D HC Blockcpy MSMC circular 1KB to DDR 1MB performance test",
2398 .disableInfo= NULL,
2399 .printEnable= PRINT_ENABLE,
2400 .prfEnable = PRF_ENABLE,
2401 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
2402 .dcEnable = DATA_CHECK_DISABLE,
2403 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
2404 .numTasks = 1U,
2405 .testType = {UDMA_TT_BLK_CPY},
2406 .testFxnPtr = {&udmaTestBlkcpyTc},
2407 .pacingTime = {PACING_NONE},
2408 .numCh = {1U},
2409 .instId = {UDMA_INST_ID_MAIN_0},
2410 .chPrmId = {UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF},
2411 .qdepth = {UDMA_TEST_DEF_QDEPTH},
2412 .icnt = {
2413 {1*KB, 1U, 1*KB, 1U}
2414 },
2415 .dicnt = {
2416 {1*KB, 1U, 1*KB, 1U}
2417 },
2418 .dim = {
2419 {0U, 0U, 0U}
2420 },
2421 .ddim = {
2422 {1*KB, 1*KB, 0U}
2423 },
2424 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC},
2425 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR},
2426 .srcBufSize = {1*KB},
2427 .destBufSize= {1*MB},
2428 .runFlag = (UDMA_TEST_RF_MAIN_BC_HC),
2429 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2430 },
2431 {
2432 .enableTest = TEST_ENABLE,
2433 .tcId = 4102U,
2434 .tcName = "Main NAVSS 2D HC Blockcpy DDR 1MB to MSMC circular 1KB performance test",
2435 .disableInfo= NULL,
2436 .printEnable= PRINT_ENABLE,
2437 .prfEnable = PRF_ENABLE,
2438 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
2439 .dcEnable = DATA_CHECK_DISABLE,
2440 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
2441 .numTasks = 1U,
2442 .testType = {UDMA_TT_BLK_CPY},
2443 .testFxnPtr = {&udmaTestBlkcpyTc},
2444 .pacingTime = {PACING_NONE},
2445 .numCh = {1U},
2446 .instId = {UDMA_INST_ID_MAIN_0},
2447 .chPrmId = {UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF},
2448 .qdepth = {UDMA_TEST_DEF_QDEPTH},
2449 .icnt = {
2450 {1*KB, 1U, 1*KB, 1U}
2451 },
2452 .dicnt = {
2453 {1*KB, 1U, 1*KB, 1U}
2454 },
2455 .dim = {
2456 {1*KB, 1*KB, 0U}
2457 },
2458 .ddim = {
2459 {0U, 0U, 0U}
2460 },
2461 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR},
2462 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
2463 .srcBufSize = {1*MB},
2464 .destBufSize= {1*KB},
2465 .runFlag = (UDMA_TEST_RF_MAIN_BC_HC),
2466 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2467 },
2468 {
2469 .enableTest = TEST_ENABLE,
2470 .tcId = 4103U,
2471 .tcName = "Main NAVSS 2D HC Blockcpy MSMC circular 1KB to MSMC circular 1KB performance test",
2472 .disableInfo= NULL,
2473 .printEnable= PRINT_ENABLE,
2474 .prfEnable = PRF_ENABLE,
2475 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
2476 .dcEnable = DATA_CHECK_DISABLE,
2477 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
2478 .numTasks = 1U,
2479 .testType = {UDMA_TT_BLK_CPY},
2480 .testFxnPtr = {&udmaTestBlkcpyTc},
2481 .pacingTime = {PACING_NONE},
2482 .numCh = {1U},
2483 .instId = {UDMA_INST_ID_MAIN_0},
2484 .chPrmId = {UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF},
2485 .qdepth = {UDMA_TEST_DEF_QDEPTH},
2486 .icnt = {
2487 {1*KB, 1U, 1*KB, 1U}
2488 },
2489 .dicnt = {
2490 {1*KB, 1U, 1*KB, 1U}
2491 },
2492 .dim = {
2493 {0U, 0U, 0U}
2494 },
2495 .ddim = {
2496 {0U, 0U, 0U}
2497 },
2498 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC},
2499 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
2500 .srcBufSize = {1*KB},
2501 .destBufSize= {1*KB},
2502 .runFlag = (UDMA_TEST_RF_MAIN_BC_HC),
2503 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2504 },
2505 {
2506 .enableTest = TEST_ENABLE,
2507 .tcId = 4104U,
2508 .tcName = "Main NAVSS HC Blockcpy DDR 1MB to DDR 1MB from multiple tasks",
2509 .disableInfo= NULL,
2510 .printEnable= PRINT_DISABLE,
2511 .prfEnable = PRF_ENABLE,
2512 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
2513 .dcEnable = DATA_CHECK_DISABLE,
2514 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
2515 .numTasks = UDMA_TEST_MAX_MAIN_BC_HC_CH,
2516 .testType = {UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY},
2517 .testFxnPtr = {&udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc},
2518 .pacingTime = {PACING_NONE, PACING_NONE, PACING_NONE, PACING_NONE},
2519 .numCh = {1U, 1U, 1U, 1U},
2520 .instId = {UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0},
2521 .chPrmId = {UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF, UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF, UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF, UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF},
2522 .qdepth = {UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH},
2523 .icnt = {
2524 {1*KB, 1U, 1*KB, 1U},
2525 {1*KB, 1U, 1*KB, 1U},
2526 {1*KB, 1U, 1*KB, 1U},
2527 {1*KB, 1U, 1*KB, 1U},
2528 },
2529 .dicnt = {
2530 {1*KB, 1U, 1*KB, 1U},
2531 {1*KB, 1U, 1*KB, 1U},
2532 {1*KB, 1U, 1*KB, 1U},
2533 {1*KB, 1U, 1*KB, 1U},
2534 },
2535 .dim = {
2536 {1*KB, 1*KB, 0U},
2537 {1*KB, 1*KB, 0U},
2538 {1*KB, 1*KB, 0U},
2539 {1*KB, 1*KB, 0U},
2540 },
2541 .ddim = {
2542 {1*KB, 1*KB, 0U},
2543 {1*KB, 1*KB, 0U},
2544 {1*KB, 1*KB, 0U},
2545 {1*KB, 1*KB, 0U},
2546 },
2547 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR},
2548 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR},
2549 .srcBufSize = {1*MB, 1*MB, 1*MB, 1*MB},
2550 .destBufSize= {1*MB, 1*MB, 1*MB, 1*MB},
2551 .runFlag = (UDMA_TEST_RF_MAIN_BC_HC_MT),
2552 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2553 },
2554 {
2555 .enableTest = TEST_ENABLE,
2556 .tcId = 4105U,
2557 .tcName = "Main NAVSS HC Blockcpy MSMC to MSMC 1KBx1K (1MB) circular from multiple tasks",
2558 .disableInfo= NULL,
2559 .printEnable= PRINT_DISABLE,
2560 .prfEnable = PRF_ENABLE,
2561 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
2562 .dcEnable = DATA_CHECK_DISABLE,
2563 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
2564 .numTasks = UDMA_TEST_MAX_MAIN_BC_HC_CH,
2565 .testType = {UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY},
2566 .testFxnPtr = {&udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc, &udmaTestBlkcpyTc},
2567 .pacingTime = {PACING_NONE, PACING_NONE, PACING_NONE, PACING_NONE},
2568 .numCh = {1U, 1U, 1U, 1U},
2569 .instId = {UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0},
2570 .chPrmId = {UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF, UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF, UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF, UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF},
2571 .qdepth = {UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH},
2572 .icnt = {
2573 {1*KB, 1U, 1*KB, 1U},
2574 {1*KB, 1U, 1*KB, 1U},
2575 {1*KB, 1U, 1*KB, 1U},
2576 {1*KB, 1U, 1*KB, 1U},
2577 },
2578 .dicnt = {
2579 {1*KB, 1U, 1*KB, 1U},
2580 {1*KB, 1U, 1*KB, 1U},
2581 {1*KB, 1U, 1*KB, 1U},
2582 {1*KB, 1U, 1*KB, 1U},
2583 },
2584 .dim = {
2585 {0U, 0U, 0U},
2586 {0U, 0U, 0U},
2587 {0U, 0U, 0U},
2588 {0U, 0U, 0U},
2589 },
2590 .ddim = {
2591 {0U, 0U, 0U},
2592 {0U, 0U, 0U},
2593 {0U, 0U, 0U},
2594 {0U, 0U, 0U},
2595 },
2596 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC},
2597 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC},
2598 .srcBufSize = {1*KB, 1*KB, 1*KB, 1*KB},
2599 .destBufSize= {1*KB, 1*KB, 1*KB, 1*KB},
2600 .runFlag = (UDMA_TEST_RF_MAIN_BC_HC_MT),
2601 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2602 },
2603 {
2604 .enableTest = TEST_ENABLE,
2605 .tcId = 4106U,
2606 .tcName = "MCU NAVSS HC Blockcpy DDR 1MB to DDR 1MB performance test",
2607 .disableInfo= NULL,
2608 .printEnable= PRINT_ENABLE,
2609 .prfEnable = PRF_ENABLE,
2610 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
2611 .dcEnable = DATA_CHECK_DISABLE,
2612 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
2613 .numTasks = 1U,
2614 .testType = {UDMA_TT_BLK_CPY},
2615 .testFxnPtr = {&udmaTestBlkcpyTc},
2616 .pacingTime = {PACING_NONE},
2617 .numCh = {1U},
2618 .instId = {UDMA_INST_ID_MCU_0},
2619 .chPrmId = {UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF},
2620 .qdepth = {UDMA_TEST_PERF_QDEPTH},
2621 .icnt = {
2622 {1*KB, 1U, 1*KB, 1U},
2623 },
2624 .dicnt = {
2625 {1*KB, 1U, 1*KB, 1U},
2626 },
2627 .dim = {
2628 {1*KB, 1*KB, 0U},
2629 },
2630 .ddim = {
2631 {1*KB, 1*KB, 0U},
2632 },
2633 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR},
2634 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR},
2635 .srcBufSize = {1*MB},
2636 .destBufSize= {1*MB},
2637 .runFlag = (UDMA_TEST_RF_MCU_BC_HC),
2638 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2639 },
2640 {
2641 .enableTest = TEST_ENABLE,
2642 .tcId = 4107U,
2643 .tcName = "MCU NAVSS 2D HC Blockcpy MSMC circular 1KB to DDR 1MB performance test",
2644 .disableInfo= NULL,
2645 .printEnable= PRINT_ENABLE,
2646 .prfEnable = PRF_ENABLE,
2647 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
2648 .dcEnable = DATA_CHECK_DISABLE,
2649 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
2650 .numTasks = 1U,
2651 .testType = {UDMA_TT_BLK_CPY},
2652 .testFxnPtr = {&udmaTestBlkcpyTc},
2653 .pacingTime = {PACING_NONE},
2654 .numCh = {1U},
2655 .instId = {UDMA_INST_ID_MCU_0},
2656 .chPrmId = {UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF},
2657 .qdepth = {UDMA_TEST_DEF_QDEPTH},
2658 .icnt = {
2659 {1*KB, 1U, 1*KB, 1U}
2660 },
2661 .dicnt = {
2662 {1*KB, 1U, 1*KB, 1U}
2663 },
2664 .dim = {
2665 {0U, 0U, 0U}
2666 },
2667 .ddim = {
2668 {1*KB, 1*KB, 0U}
2669 },
2670 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC},
2671 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR},
2672 .srcBufSize = {1*KB},
2673 .destBufSize= {1*MB},
2674 .runFlag = (UDMA_TEST_RF_MCU_BC_HC),
2675 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2676 },
2677 {
2678 .enableTest = TEST_ENABLE,
2679 .tcId = 4108U,
2680 .tcName = "MCU NAVSS 2D HC Blockcpy DDR 1MB to MSMC circular 1KB performance test",
2681 .disableInfo= NULL,
2682 .printEnable= PRINT_ENABLE,
2683 .prfEnable = PRF_ENABLE,
2684 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
2685 .dcEnable = DATA_CHECK_DISABLE,
2686 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
2687 .numTasks = 1U,
2688 .testType = {UDMA_TT_BLK_CPY},
2689 .testFxnPtr = {&udmaTestBlkcpyTc},
2690 .pacingTime = {PACING_NONE},
2691 .numCh = {1U},
2692 .instId = {UDMA_INST_ID_MCU_0},
2693 .chPrmId = {UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF},
2694 .qdepth = {UDMA_TEST_DEF_QDEPTH},
2695 .icnt = {
2696 {1*KB, 1U, 1*KB, 1U}
2697 },
2698 .dicnt = {
2699 {1*KB, 1U, 1*KB, 1U}
2700 },
2701 .dim = {
2702 {1*KB, 1*KB, 0U}
2703 },
2704 .ddim = {
2705 {0U, 0U, 0U}
2706 },
2707 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR},
2708 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
2709 .srcBufSize = {1*MB},
2710 .destBufSize= {1*KB},
2711 .runFlag = (UDMA_TEST_RF_MCU_BC_HC),
2712 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2713 },
2714 {
2715 .enableTest = TEST_ENABLE,
2716 .tcId = 4109U,
2717 .tcName = "MCU NAVSS 2D HC Blockcpy MSMC circular 1KB to MSMC circular 1KB performance test",
2718 .disableInfo= NULL,
2719 .printEnable= PRINT_ENABLE,
2720 .prfEnable = PRF_ENABLE,
2721 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
2722 .dcEnable = DATA_CHECK_DISABLE,
2723 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
2724 .numTasks = 1U,
2725 .testType = {UDMA_TT_BLK_CPY},
2726 .testFxnPtr = {&udmaTestBlkcpyTc},
2727 .pacingTime = {PACING_NONE},
2728 .numCh = {1U},
2729 .instId = {UDMA_INST_ID_MCU_0},
2730 .chPrmId = {UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF},
2731 .qdepth = {UDMA_TEST_DEF_QDEPTH},
2732 .icnt = {
2733 {1*KB, 1U, 1*KB, 1U}
2734 },
2735 .dicnt = {
2736 {1*KB, 1U, 1*KB, 1U}
2737 },
2738 .dim = {
2739 {0U, 0U, 0U}
2740 },
2741 .ddim = {
2742 {0U, 0U, 0U}
2743 },
2744 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC},
2745 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC},
2746 .srcBufSize = {1*KB},
2747 .destBufSize= {1*KB},
2748 .runFlag = (UDMA_TEST_RF_MCU_BC_HC),
2749 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2750 },
2751 {
2752 .enableTest = TEST_ENABLE,
2753 .tcId = 4110U,
2754 .tcName = "MCU NAVSS HC Blockcpy DDR 1MB to DDR 1MB from multiple tasks",
2755 .disableInfo= NULL,
2756 .printEnable= PRINT_DISABLE,
2757 .prfEnable = PRF_ENABLE,
2758 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
2759 .dcEnable = DATA_CHECK_DISABLE,
2760 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
2761 .numTasks = UDMA_TEST_MAX_MCU_BC_HC_CH,
2762 .testType = {UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY},
2763 .testFxnPtr = {&udmaTestBlkcpyTc, &udmaTestBlkcpyTc},
2764 .pacingTime = {PACING_NONE, PACING_NONE},
2765 .numCh = {1U, 1U},
2766 .instId = {UDMA_INST_ID_MCU_0, UDMA_INST_ID_MCU_0},
2767 .chPrmId = {UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF, UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF},
2768 .qdepth = {UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH},
2769 .icnt = {
2770 {1*KB, 1U, 1*KB, 1U},
2771 {1*KB, 1U, 1*KB, 1U},
2772 },
2773 .dicnt = {
2774 {1*KB, 1U, 1*KB, 1U},
2775 {1*KB, 1U, 1*KB, 1U},
2776 },
2777 .dim = {
2778 {1*KB, 1*KB, 0U},
2779 {1*KB, 1*KB, 0U},
2780 },
2781 .ddim = {
2782 {1*KB, 1*KB, 0U},
2783 {1*KB, 1*KB, 0U},
2784 },
2785 .heapIdSrc = {UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR},
2786 .heapIdDest = {UTILS_MEM_HEAP_ID_DDR, UTILS_MEM_HEAP_ID_DDR},
2787 .srcBufSize = {1*MB, 1*MB},
2788 .destBufSize= {1*MB, 1*MB},
2789 .runFlag = (UDMA_TEST_RF_MCU_BC_HC_MT),
2790 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2791 },
2792 {
2793 .enableTest = TEST_ENABLE,
2794 .tcId = 4111U,
2795 .tcName = "MCU NAVSS HC Blockcpy MSMC to MSMC 1KBx1K (1MB) circular from multiple tasks",
2796 .disableInfo= NULL,
2797 .printEnable= PRINT_DISABLE,
2798 .prfEnable = PRF_ENABLE,
2799 .tcType = (UDMA_TCT_FULL | UDMA_TCT_FUNCTIONAL | UDMA_TCT_PERFORMANCE),
2800 .dcEnable = DATA_CHECK_DISABLE,
2801 .loopCnt = UDMA_TEST_PERF_LOOP_CNT,
2802 .numTasks = UDMA_TEST_MAX_MCU_BC_HC_CH,
2803 .testType = {UDMA_TT_BLK_CPY, UDMA_TT_BLK_CPY},
2804 .testFxnPtr = {&udmaTestBlkcpyTc, &udmaTestBlkcpyTc},
2805 .pacingTime = {PACING_NONE, PACING_NONE},
2806 .numCh = {1U, 1U},
2807 .instId = {UDMA_INST_ID_MCU_0, UDMA_INST_ID_MCU_0},
2808 .chPrmId = {UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF, UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF},
2809 .qdepth = {UDMA_TEST_PERF_QDEPTH, UDMA_TEST_PERF_QDEPTH},
2810 .icnt = {
2811 {1*KB, 1U, 1*KB, 1U},
2812 {1*KB, 1U, 1*KB, 1U},
2813 },
2814 .dicnt = {
2815 {1*KB, 1U, 1*KB, 1U},
2816 {1*KB, 1U, 1*KB, 1U},
2817 },
2818 .dim = {
2819 {0U, 0U, 0U},
2820 {0U, 0U, 0U},
2821 },
2822 .ddim = {
2823 {0U, 0U, 0U},
2824 {0U, 0U, 0U},
2825 },
2826 .heapIdSrc = {UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC},
2827 .heapIdDest = {UTILS_MEM_HEAP_ID_MSMC, UTILS_MEM_HEAP_ID_MSMC},
2828 .srcBufSize = {1*KB, 1*KB},
2829 .destBufSize= {1*KB, 1*KB},
2830 .runFlag = (UDMA_TEST_RF_MCU_BC_HC_MT),
2831 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2832 },
2833 {
2834 .enableTest = TEST_ENABLE,
2835 .tcId = 4656U,
2836 .tcName = "PDK-4654 bug testcase: UDMA deinit resource check",
2837 .disableInfo= NULL,
2838 .printEnable= PRINT_ENABLE,
2839 .prfEnable = PRF_DISABLE,
2840 .tcType = (UDMA_TCT_FULL | UDMA_TCT_NEGATIVE),
2841 .dcEnable = DATA_CHECK_ENABLE,
2842 .loopCnt = USE_DEF_LP_CNT,
2843 .numTasks = 1U,
2844 .testType = {UDMA_TT_BLK_CPY},
2845 .testFxnPtr = {&udmaTestBugTcPDK_4654},
2846 .pacingTime = {PACING_NONE},
2847 .numCh = {1U},
2848 .instId = {UDMA_TEST_DEFAULT_UDMA_INST},
2849 .chPrmId = {UDMA_TEST_CH_PRMID_DEF},
2850 .qdepth = {USE_DEF_QDEPTH},
2851 .icnt = {
2852 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
2853 },
2854 .dicnt = {
2855 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
2856 },
2857 .dim = {
2858 {0U, 0U, 0U}
2859 },
2860 .ddim = {
2861 {0U, 0U, 0U}
2862 },
2863 .heapIdSrc = {DEF_HEAP_ID},
2864 .heapIdDest = {DEF_HEAP_ID},
2865 .srcBufSize = {UDMA_TEST_DEF_ICNT0},
2866 .destBufSize= {UDMA_TEST_DEF_DICNT0},
2867 .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
2868 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2869 },
2870 {
2871 .enableTest = TEST_ENABLE,
2872 .tcId = 4841U,
2873 .tcName = "Main NAVSS Blockcpy DDR to DDR in interrupt mode chaining test",
2874 .disableInfo= NULL,
2875 .printEnable= PRINT_ENABLE,
2876 .prfEnable = PRF_DISABLE,
2877 .tcType = (UDMA_TCT_SANITY | UDMA_TCT_FUNCTIONAL),
2878 .dcEnable = DATA_CHECK_ENABLE,
2879 .loopCnt = USE_DEF_LP_CNT,
2880 .numTasks = 1U,
2881 .testType = {UDMA_TT_BLK_CPY},
2882 .testFxnPtr = {&udmaTestBlkcpyChainingTc},
2883 .pacingTime = {PACING_NONE},
2884 .numCh = {2U},
2885 .instId = {UDMA_INST_ID_MAIN_0, UDMA_INST_ID_MAIN_0},
2886 .chPrmId = {UDMA_TEST_CH_PRMID_INTR_DEF, UDMA_TEST_CH_PRMID_INTR_DEF},
2887 .qdepth = {USE_DEF_QDEPTH, USE_DEF_QDEPTH},
2888 .icnt = {
2889 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U},
2890 {UDMA_TEST_DEF_ICNT0, 1U, 1U, 1U}
2891 },
2892 .dicnt = {
2893 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U},
2894 {UDMA_TEST_DEF_DICNT0, 1U, 1U, 1U}
2895 },
2896 .dim = {
2897 {0U, 0U, 0U},
2898 {0U, 0U, 0U}
2899 },
2900 .ddim = {
2901 {0U, 0U, 0U},
2902 {0U, 0U, 0U}
2903 },
2904 .heapIdSrc = {DEF_HEAP_ID, DEF_HEAP_ID},
2905 .heapIdDest = {DEF_HEAP_ID, DEF_HEAP_ID},
2906 .srcBufSize = {UDMA_TEST_DEF_ICNT0, UDMA_TEST_DEF_ICNT0},
2907 .destBufSize= {UDMA_TEST_DEF_DICNT0, UDMA_TEST_DEF_DICNT0},
2908 .runFlag = (UDMA_TEST_RF_MAIN_BC | UDMA_TEST_RF_CFG_DYN),
2909 .ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
2910 },
2912 };
2914 #ifdef __cplusplus
2915 }
2916 #endif
2918 #endif /* UDMA_TEST_CASES_H_ */