Added DRU trigger and event testcases
[processor-sdk/pdk.git] / packages / ti / drv / udma / unit_test / udma_ut / src / udma_testconfig.h
1 /*
2  *  Copyright (c) Texas Instruments Incorporated 2018
3  *
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5  *  modification, are permitted provided that the following conditions
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9  *    notice, this list of conditions and the following disclaimer.
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13  *    documentation and/or other materials provided with the
14  *    distribution.
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17  *    its contributors may be used to endorse or promote products derived
18  *    from this software without specific prior written permission.
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33 /**
34  *  \file udma_testconfig.h
35  *
36  *  \brief This file defines the common configurations like driver config etc...
37  */
39 #ifndef UDMA_TEST_CONFIG_H_
40 #define UDMA_TEST_CONFIG_H_
42 /* ========================================================================== */
43 /*                             Include Files                                  */
44 /* ========================================================================== */
46 #include <udma_test.h>
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
52 /* ========================================================================== */
53 /*                           Macros & Typedefs                                */
54 /* ========================================================================== */
56 /* None */
58 /* ========================================================================== */
59 /*                            Global Variables                                */
60 /* ========================================================================== */
62 /** \brief Defines the various TX channel parameters. */
63 static const UdmaTestTxChPrm gUdmaTestTxChPrm[] =
64 {
65     {
66         .txChPrmId      = UDMA_TEST_TXCH_PRMID_DEF,
67         .txPrms         =
68         {
69             .pauseOnError   = TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED,
70             .filterEinfo    = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_DISABLED,
71             .filterPsWords  = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_DISABLED,
72             .addrType       = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS,
73             .chanType       = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF,
74             .fetchWordSize  = 16U,
75             .busPriority    = UDMA_DEFAULT_TX_CH_BUS_PRIORITY,
76             .busQos         = UDMA_DEFAULT_TX_CH_BUS_QOS,
77             .busOrderId     = UDMA_DEFAULT_TX_CH_BUS_ORDERID,
78             .dmaPriority    = UDMA_DEFAULT_TX_CH_DMA_PRIORITY,
79             .txCredit       = 0U,
80             .fifoDepth      = 128U,
81             .burstSize      = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES,
82             .supressTdCqPkt = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED,
83         }
84     },
85     {
86         .txChPrmId      = UDMA_TEST_TXCH_PRMID_DMA_PRIORITY_HIGH,
87         .txPrms         =
88         {
89             .pauseOnError   = TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED,
90             .filterEinfo    = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_DISABLED,
91             .filterPsWords  = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_DISABLED,
92             .addrType       = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS,
93             .chanType       = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF,
94             .fetchWordSize  = 16U,
95             .busPriority    = UDMA_DEFAULT_TX_CH_BUS_PRIORITY,
96             .busQos         = UDMA_DEFAULT_TX_CH_BUS_QOS,
97             .busOrderId     = UDMA_DEFAULT_TX_CH_BUS_ORDERID,
98             .dmaPriority    = TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_HIGH,
99             .txCredit       = 0U,
100             .fifoDepth      = 128U,
101             .burstSize      = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES,
102             .supressTdCqPkt = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED,
103         }
104     },
105 };
106 #define UDMA_TEST_NUM_TX_CH_PRM         (sizeof(gUdmaTestTxChPrm) / \
107                                          sizeof(gUdmaTestTxChPrm[0U]))
109 /** \brief Defines the various RX channel parameters. */
110 static const UdmaTestRxChPrm gUdmaTestRxChPrm[] =
112     {
114         .rxChPrmId      = UDMA_TEST_RXCH_PRMID_DEF,
115         .rxPrms         =
116         {
117             .pauseOnError       = TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED,
118             .addrType           = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS,
119             .chanType           = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF,
120             .fetchWordSize      = 16U,
121             .busPriority        = UDMA_DEFAULT_RX_CH_BUS_PRIORITY,
122             .busQos             = UDMA_DEFAULT_RX_CH_BUS_QOS,
123             .busOrderId         = UDMA_DEFAULT_RX_CH_BUS_ORDERID,
124             .dmaPriority        = UDMA_DEFAULT_RX_CH_DMA_PRIORITY,
125             .flowIdFwRangeStart = 0U,  /* Flow ID not used */
126             .flowIdFwRangeCnt   = 0U,  /* Flow ID not used */
127             .ignoreShortPkts    = TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION,
128             .ignoreLongPkts     = TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION,
129             .configDefaultFlow  = TRUE,
130             .burstSize          = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES,
131         }
132     },
133     {
135         .rxChPrmId      = UDMA_TEST_RXCH_PRMID_DMA_PRIORITY_HIGH,
136         .rxPrms         =
137         {
138             .pauseOnError       = TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED,
139             .addrType           = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS,
140             .chanType           = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF,
141             .fetchWordSize      = 16U,
142             .busPriority        = UDMA_DEFAULT_RX_CH_BUS_PRIORITY,
143             .busQos             = UDMA_DEFAULT_RX_CH_BUS_QOS,
144             .busOrderId         = UDMA_DEFAULT_RX_CH_BUS_ORDERID,
145             .dmaPriority        = TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_HIGH,
146             .flowIdFwRangeStart = 0U,  /* Flow ID not used */
147             .flowIdFwRangeCnt   = 0U,  /* Flow ID not used */
148             .ignoreShortPkts    = TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION,
149             .ignoreLongPkts     = TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION,
150             .configDefaultFlow  = TRUE,
151             .burstSize          = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES,
152         }
153     },
154 };
155 #define UDMA_TEST_NUM_RX_CH_PRM         (sizeof(gUdmaTestRxChPrm) / \
156                                          sizeof(gUdmaTestRxChPrm[0U]))
158 /** \brief Defines the various UTC channel parameters. */
159 static const UdmaTestUtcChPrm gUdmaTestUtcChPrm[] =
161     {
162         .utcChPrmId      = UDMA_TEST_UTCCH_PRMID_DEF,
163         .utcPrms         =
164         {
165             .pauseOnError   = FALSE,
166             .addrType       = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS,
167             .chanType       = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_REF,
168             .fetchWordSize  = 16U,
169             .busPriority    = UDMA_DEFAULT_UTC_CH_BUS_PRIORITY,
170             .busQos         = UDMA_DEFAULT_UTC_CH_BUS_QOS,
171             .busOrderId     = UDMA_DEFAULT_UTC_CH_BUS_ORDERID,
172             .dmaPriority    = UDMA_DEFAULT_UTC_CH_DMA_PRIORITY,
173             .burstSize      = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_128_BYTES,
174             .supressTdCqPkt = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED,
175 #if (UDMA_NUM_UTC_INSTANCE > 0)
176             .druOwner       = CSL_DRU_OWNER_UDMAC_TR,
177             .druQueueId     = CSL_DRU_QUEUE_ID_3,
178 #endif
179         }
180     },
181     {
182         .utcChPrmId      = UDMA_TEST_UTCCH_PRMID_DMA_PRIORITY_HIGH,
183         .utcPrms         =
184         {
185             .pauseOnError   = FALSE,
186             .addrType       = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS,
187             .chanType       = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_REF,
188             .fetchWordSize  = 16U,
189             .busPriority    = UDMA_DEFAULT_UTC_CH_BUS_PRIORITY,
190             .busQos         = UDMA_DEFAULT_UTC_CH_BUS_QOS,
191             .busOrderId     = UDMA_DEFAULT_UTC_CH_BUS_ORDERID,
192             .dmaPriority    = TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_HIGH,
193             .burstSize      = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_128_BYTES,
194             .supressTdCqPkt = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED,
195 #if (UDMA_NUM_UTC_INSTANCE > 0)
196             .druOwner       = CSL_DRU_OWNER_UDMAC_TR,
197             .druQueueId     = CSL_DRU_QUEUE_ID_3,
198 #endif
199         }
200     },
201 };
202 #define UDMA_TEST_NUM_UTC_CH_PRM        (sizeof(gUdmaTestUtcChPrm) / \
203                                          sizeof(gUdmaTestUtcChPrm[0U]))
205 /** \brief Defines the various PDMA channel parameters. */
206 static const UdmaTestPdmaChPrm gUdmaTestPdmaChPrm[] =
208     {
209         .pdmaChPrmId    = UDMA_TEST_PDMACH_PRMID_DEF,
210         .pdmaPrms       =
211         {
212             .elemSize  = UDMA_PDMA_ES_8BITS,
213             .elemCnt   = 0U,
214             .fifoCnt   = 0U,
215         }
216     },
217     {
218         .pdmaChPrmId    = UDMA_TEST_PDMACH_PRMID_ES_16BITS,
219         .pdmaPrms       =
220         {
221             .elemSize  = UDMA_PDMA_ES_16BITS,
222             .elemCnt   = 0U,
223             .fifoCnt   = 0U,
224         }
225     },
226 };
227 #define UDMA_TEST_NUM_PDMA_CH_PRM       (sizeof(gUdmaTestPdmaChPrm) / \
228                                          sizeof(gUdmaTestPdmaChPrm[0U]))
230 /** \brief Defines the various channel parameters. */
231 static const UdmaTestChPrm gUdmaTestChPrm[] =
233     {
234         .chPrmId        = UDMA_TEST_CH_PRMID_DEF,
235         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
236         .utcId          = UDMA_UTC_ID_INVALID,
237         .eventMode      = UDMA_TEST_EVENT_NONE,
238         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
239         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
240         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
241         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
242         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
243         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
244         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
245     },
246     {
247         .chPrmId        = UDMA_TEST_CH_PRMID_INTR_DEF,
248         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
249         .utcId          = UDMA_UTC_ID_INVALID,
250         .eventMode      = UDMA_TEST_EVENT_INTR,
251         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
252         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
253         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
254         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
255         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
256         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
257         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
258     },
259     {
260         .chPrmId        = UDMA_TEST_CH_PRMID_TRIGGER_GLOBAL0,
261         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
262         .utcId          = UDMA_UTC_ID_INVALID,
263         .eventMode      = UDMA_TEST_EVENT_NONE,
264         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
265         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
266         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
267         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
268         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
269         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
270         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
271     },
272     {
273         .chPrmId        = UDMA_TEST_CH_PRMID_TRIGGER_GLOBAL0_INTR,
274         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
275         .utcId          = UDMA_UTC_ID_INVALID,
276         .eventMode      = UDMA_TEST_EVENT_INTR,
277         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
278         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
279         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
280         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
281         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
282         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
283         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
284     },
285     {
286         .chPrmId        = UDMA_TEST_CH_PRMID_EVENTSIZE_ICNT1,
287         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
288         .utcId          = UDMA_UTC_ID_INVALID,
289         .eventMode      = UDMA_TEST_EVENT_NONE,
290         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
291         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT1_DEC,
292         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT1_DEC,
293         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
294         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
295         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
296         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
297     },
298     {
299         .chPrmId        = UDMA_TEST_CH_PRMID_EVENTSIZE_ICNT2,
300         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
301         .utcId          = UDMA_UTC_ID_INVALID,
302         .eventMode      = UDMA_TEST_EVENT_NONE,
303         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
304         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT2_DEC,
305         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT2_DEC,
306         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
307         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
308         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
309         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
310     },
311     {
312         .chPrmId        = UDMA_TEST_CH_PRMID_EVENTSIZE_ICNT3,
313         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
314         .utcId          = UDMA_UTC_ID_INVALID,
315         .eventMode      = UDMA_TEST_EVENT_NONE,
316         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
317         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT3_DEC,
318         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT3_DEC,
319         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
320         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
321         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
322         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
323     },
324 #if defined (UDMA_UTC_ID_MSMC_DRU0)
325     {
326         .chPrmId        = UDMA_TEST_CH_PRMID_DRU_DEF,
327         .chType         = UDMA_CH_TYPE_UTC,
328         .utcId          = UDMA_UTC_ID_MSMC_DRU0,
329         .eventMode      = UDMA_TEST_EVENT_NONE,
330         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
331         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
332         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
333         .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
334         .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
335         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
336         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
337     },
338     {
339         .chPrmId        = UDMA_TEST_CH_PRMID_DRU_INTR_DEF,
340         .chType         = UDMA_CH_TYPE_UTC,
341         .utcId          = UDMA_UTC_ID_MSMC_DRU0,
342         .eventMode      = UDMA_TEST_EVENT_INTR,
343         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
344         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
345         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
346         .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
347         .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
348         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
349         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
350     },
351     {
352         .chPrmId        = UDMA_TEST_CH_PRMID_DRU_TRIGGER_GLOBAL0,
353         .chType         = UDMA_CH_TYPE_UTC,
354         .utcId          = UDMA_UTC_ID_MSMC_DRU0,
355         .eventMode      = UDMA_TEST_EVENT_NONE,
356         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
357         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
358         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
359         .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
360         .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
361         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
362         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
363     },
364     {
365         .chPrmId        = UDMA_TEST_CH_PRMID_DRU_TRIGGER_GLOBAL0_INTR,
366         .chType         = UDMA_CH_TYPE_UTC,
367         .utcId          = UDMA_UTC_ID_MSMC_DRU0,
368         .eventMode      = UDMA_TEST_EVENT_INTR,
369         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
370         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
371         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
372         .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
373         .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
374         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
375         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
376     },
377     {
378         .chPrmId        = UDMA_TEST_CH_PRMID_DRU_EVENTSIZE_ICNT1,
379         .chType         = UDMA_CH_TYPE_UTC,
380         .utcId          = UDMA_UTC_ID_MSMC_DRU0,
381         .eventMode      = UDMA_TEST_EVENT_NONE,
382         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
383         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT1_DEC,
384         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT1_DEC,
385         .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
386         .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
387         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
388         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
389     },
390     {
391         .chPrmId        = UDMA_TEST_CH_PRMID_DRU_EVENTSIZE_ICNT2,
392         .chType         = UDMA_CH_TYPE_UTC,
393         .utcId          = UDMA_UTC_ID_MSMC_DRU0,
394         .eventMode      = UDMA_TEST_EVENT_NONE,
395         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
396         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT2_DEC,
397         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT2_DEC,
398         .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
399         .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
400         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
401         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
402     },
403     {
404         .chPrmId        = UDMA_TEST_CH_PRMID_DRU_EVENTSIZE_ICNT3,
405         .chType         = UDMA_CH_TYPE_UTC,
406         .utcId          = UDMA_UTC_ID_MSMC_DRU0,
407         .eventMode      = UDMA_TEST_EVENT_NONE,
408         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
409         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT3_DEC,
410         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT3_DEC,
411         .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
412         .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
413         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
414         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
415     },
416 #endif
417     {
418         .chPrmId        = UDMA_TEST_CH_PRMID_BLKCPY_HC_DEF,
419         .chType         = UDMA_CH_TYPE_TR_BLK_COPY_HC,
420         .utcId          = UDMA_UTC_ID_INVALID,
421         .eventMode      = UDMA_TEST_EVENT_NONE,
422         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
423         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
424         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
425         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
426         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
427         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
428         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
429     },
430     {
431         .chPrmId        = UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF,
432         .chType         = UDMA_CH_TYPE_TR_BLK_COPY_HC,
433         .utcId          = UDMA_UTC_ID_INVALID,
434         .eventMode      = UDMA_TEST_EVENT_INTR,
435         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
436         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
437         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
438         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
439         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
440         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
441         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
442     },
443     {
444         .chPrmId        = UDMA_TEST_CH_PRMID_BLKCPY_UHC_DEF,
445         .chType         = UDMA_CH_TYPE_TR_BLK_COPY_UHC,
446         .utcId          = UDMA_UTC_ID_INVALID,
447         .eventMode      = UDMA_TEST_EVENT_NONE,
448         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
449         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
450         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
451         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
452         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
453         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
454         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
455     },
456     {
457         .chPrmId        = UDMA_TEST_CH_PRMID_BLKCPY_UHC_INTR_DEF,
458         .chType         = UDMA_CH_TYPE_TR_BLK_COPY_UHC,
459         .utcId          = UDMA_UTC_ID_INVALID,
460         .eventMode      = UDMA_TEST_EVENT_INTR,
461         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
462         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
463         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
464         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
465         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
466         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
467         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
468     },
469 };
470 #define UDMA_TEST_NUM_CH_PRM            (sizeof(gUdmaTestChPrm) / \
471                                          sizeof(gUdmaTestChPrm[0U]))
473 /** \brief Defines the various ring parameters. */
474 static const UdmaTestRingPrm gUdmaTestRingPrm[] =
476     {
477         .ringPrmId      = UDMA_TEST_RING_PRMID_EVENT_NONE,
478         .eventMode      = UDMA_TEST_EVENT_NONE,
479     },
480     {
481         .ringPrmId      = UDMA_TEST_RING_PRMID_EVENT_INTR,
482         .eventMode      = UDMA_TEST_EVENT_INTR,
483     },
484     {
485         .ringPrmId      = UDMA_TEST_RING_PRMID_EVENT_POLLED,
486         .eventMode      = UDMA_TEST_EVENT_POLLED,
487     },
488 };
489 #define UDMA_TEST_NUM_RING_PRM          (sizeof(gUdmaTestRingPrm) / \
490                                          sizeof(gUdmaTestRingPrm[0U]))
492 #ifdef __cplusplus
494 #endif
496 #endif /* #ifndef UDMA_TEST_CONFIG_H_ */