udma-lld: add to PDK
[processor-sdk/pdk.git] / packages / ti / drv / udma / unit_test / udma_ut / src / udma_testconfig.h
1 /*
2  *  Copyright (c) Texas Instruments Incorporated 2018
3  *
4  *  Redistribution and use in source and binary forms, with or without
5  *  modification, are permitted provided that the following conditions
6  *  are met:
7  *
8  *    Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  *
11  *    Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the
14  *    distribution.
15  *
16  *    Neither the name of Texas Instruments Incorporated nor the names of
17  *    its contributors may be used to endorse or promote products derived
18  *    from this software without specific prior written permission.
19  *
20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
33 /**
34  *  \file udma_testconfig.h
35  *
36  *  \brief This file defines the common configurations like driver config etc...
37  */
39 #ifndef UDMA_TEST_CONFIG_H_
40 #define UDMA_TEST_CONFIG_H_
42 /* ========================================================================== */
43 /*                             Include Files                                  */
44 /* ========================================================================== */
46 #include <udma_test.h>
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
52 /* ========================================================================== */
53 /*                           Macros & Typedefs                                */
54 /* ========================================================================== */
56 /* None */
58 /* ========================================================================== */
59 /*                            Global Variables                                */
60 /* ========================================================================== */
62 /** \brief Defines the various TX channel parameters. */
63 static const UdmaTestTxChPrm gUdmaTestTxChPrm[] =
64 {
65     {
66         .txChPrmId      = UDMA_TEST_TXCH_PRMID_DEF,
67         .txPrms         =
68         {
69             .pauseOnError   = TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED,
70             .filterEinfo    = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_DISABLED,
71             .filterPsWords  = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_DISABLED,
72             .addrType       = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS,
73             .chanType       = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF,
74             .fetchWordSize  = 16U,
75             .busPriority    = UDMA_DEFAULT_TX_CH_BUS_PRIORITY,
76             .busQos         = UDMA_DEFAULT_TX_CH_BUS_QOS,
77             .busOrderId     = UDMA_DEFAULT_TX_CH_BUS_ORDERID,
78             .dmaPriority    = UDMA_DEFAULT_TX_CH_DMA_PRIORITY,
79             .txCredit       = 0U,
80             .fifoDepth      = 128U,
81             .burstSize      = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES,
82             .supressTdCqPkt = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED,
83         }
84     },
85     {
86         .txChPrmId      = UDMA_TEST_TXCH_PRMID_DMA_PRIORITY_HIGH,
87         .txPrms         =
88         {
89             .pauseOnError   = TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED,
90             .filterEinfo    = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_DISABLED,
91             .filterPsWords  = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_DISABLED,
92             .addrType       = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS,
93             .chanType       = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF,
94             .fetchWordSize  = 16U,
95             .busPriority    = UDMA_DEFAULT_TX_CH_BUS_PRIORITY,
96             .busQos         = UDMA_DEFAULT_TX_CH_BUS_QOS,
97             .busOrderId     = UDMA_DEFAULT_TX_CH_BUS_ORDERID,
98             .dmaPriority    = TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_HIGH,
99             .txCredit       = 0U,
100             .fifoDepth      = 128U,
101             .burstSize      = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES,
102             .supressTdCqPkt = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED,
103         }
104     },
105 };
106 #define UDMA_TEST_NUM_TX_CH_PRM         (sizeof(gUdmaTestTxChPrm) / \
107                                          sizeof(gUdmaTestTxChPrm[0U]))
109 /** \brief Defines the various RX channel parameters. */
110 static const UdmaTestRxChPrm gUdmaTestRxChPrm[] =
112     {
114         .rxChPrmId      = UDMA_TEST_RXCH_PRMID_DEF,
115         .rxPrms         =
116         {
117             .pauseOnError       = TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED,
118             .addrType           = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS,
119             .chanType           = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF,
120             .fetchWordSize      = 16U,
121             .busPriority        = UDMA_DEFAULT_RX_CH_BUS_PRIORITY,
122             .busQos             = UDMA_DEFAULT_RX_CH_BUS_QOS,
123             .busOrderId         = UDMA_DEFAULT_RX_CH_BUS_ORDERID,
124             .dmaPriority        = UDMA_DEFAULT_RX_CH_DMA_PRIORITY,
125             .flowIdFwRangeStart = 0U,  /* Flow ID not used */
126             .flowIdFwRangeCnt   = 0x4000U,
127             .ignoreShortPkts    = TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION,
128             .ignoreLongPkts     = TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION,
129             .configDefaultFlow  = TRUE,
130             .burstSize          = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES,
131         }
132     },
133     {
135         .rxChPrmId      = UDMA_TEST_RXCH_PRMID_DMA_PRIORITY_HIGH,
136         .rxPrms         =
137         {
138             .pauseOnError       = TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED,
139             .addrType           = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS,
140             .chanType           = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF,
141             .fetchWordSize      = 16U,
142             .busPriority        = UDMA_DEFAULT_RX_CH_BUS_PRIORITY,
143             .busQos             = UDMA_DEFAULT_RX_CH_BUS_QOS,
144             .busOrderId         = UDMA_DEFAULT_RX_CH_BUS_ORDERID,
145             .dmaPriority        = TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_HIGH,
146             .flowIdFwRangeStart = 0U,  /* Flow ID not used */
147             .flowIdFwRangeCnt   = 0x4000U,
148             .ignoreShortPkts    = TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION,
149             .ignoreLongPkts     = TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION,
150             .configDefaultFlow  = TRUE,
151             .burstSize          = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES,
152         }
153     },
154 };
155 #define UDMA_TEST_NUM_RX_CH_PRM         (sizeof(gUdmaTestRxChPrm) / \
156                                          sizeof(gUdmaTestRxChPrm[0U]))
158 /** \brief Defines the various UTC channel parameters. */
159 static const UdmaTestUtcChPrm gUdmaTestUtcChPrm[] =
161     {
162         .utcChPrmId      = UDMA_TEST_UTCCH_PRMID_DEF,
163         .utcPrms         =
164         {
165             .pauseOnError   = FALSE,
166             .addrType       = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS,
167             .chanType       = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_REF,
168             .fetchWordSize  = 16U,
169             .busPriority    = UDMA_DEFAULT_UTC_CH_BUS_PRIORITY,
170             .busQos         = UDMA_DEFAULT_UTC_CH_BUS_QOS,
171             .busOrderId     = UDMA_DEFAULT_UTC_CH_BUS_ORDERID,
172             .dmaPriority    = UDMA_DEFAULT_UTC_CH_DMA_PRIORITY,
173             .burstSize      = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_128_BYTES,
174             .supressTdCqPkt = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED,
175             .druOwner       = CSL_DRU_OWNER_UDMAC_TR,
176             .druQueueId     = CSL_DRU_QUEUE_ID_3,
177         }
178     },
179     {
180         .utcChPrmId      = UDMA_TEST_UTCCH_PRMID_DMA_PRIORITY_HIGH,
181         .utcPrms         =
182         {
183             .pauseOnError   = FALSE,
184             .addrType       = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS,
185             .chanType       = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_REF,
186             .fetchWordSize  = 16U,
187             .busPriority    = UDMA_DEFAULT_UTC_CH_BUS_PRIORITY,
188             .busQos         = UDMA_DEFAULT_UTC_CH_BUS_QOS,
189             .busOrderId     = UDMA_DEFAULT_UTC_CH_BUS_ORDERID,
190             .dmaPriority    = TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_HIGH,
191             .burstSize      = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_128_BYTES,
192             .supressTdCqPkt = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED,
193             .druOwner       = CSL_DRU_OWNER_UDMAC_TR,
194             .druQueueId     = CSL_DRU_QUEUE_ID_3,
195         }
196     },
197 };
198 #define UDMA_TEST_NUM_UTC_CH_PRM        (sizeof(gUdmaTestUtcChPrm) / \
199                                          sizeof(gUdmaTestUtcChPrm[0U]))
201 /** \brief Defines the various PDMA channel parameters. */
202 static const UdmaTestPdmaChPrm gUdmaTestPdmaChPrm[] =
204     {
205         .pdmaChPrmId    = UDMA_TEST_PDMACH_PRMID_DEF,
206         .pdmaPrms       =
207         {
208             .elemSize  = UDMA_PDMA_ES_8BITS,
209             .elemCnt   = 0U,
210             .fifoCnt   = 0U,
211         }
212     },
213     {
214         .pdmaChPrmId    = UDMA_TEST_PDMACH_PRMID_ES_16BITS,
215         .pdmaPrms       =
216         {
217             .elemSize  = UDMA_PDMA_ES_16BITS,
218             .elemCnt   = 0U,
219             .fifoCnt   = 0U,
220         }
221     },
222 };
223 #define UDMA_TEST_NUM_PDMA_CH_PRM       (sizeof(gUdmaTestPdmaChPrm) / \
224                                          sizeof(gUdmaTestPdmaChPrm[0U]))
226 /** \brief Defines the various channel parameters. */
227 static const UdmaTestChPrm gUdmaTestChPrm[] =
229     {
230         .chPrmId        = UDMA_TEST_CH_PRMID_DEF,
231         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
232         .utcId          = UDMA_UTC_ID_INVALID,
233         .eventMode      = UDMA_TEST_EVENT_NONE,
234         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
235         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
236         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
237         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
238         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
239         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
240         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
241     },
242     {
243         .chPrmId        = UDMA_TEST_CH_PRMID_INTR_DEF,
244         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
245         .utcId          = UDMA_UTC_ID_INVALID,
246         .eventMode      = UDMA_TEST_EVENT_INTR,
247         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
248         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
249         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
250         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
251         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
252         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
253         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
254     },
255     {
256         .chPrmId        = UDMA_TEST_CH_PRMID_TRIGGER_GLOBAL0,
257         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
258         .utcId          = UDMA_UTC_ID_INVALID,
259         .eventMode      = UDMA_TEST_EVENT_NONE,
260         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
261         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
262         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
263         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
264         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
265         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
266         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
267     },
268     {
269         .chPrmId        = UDMA_TEST_CH_PRMID_TRIGGER_GLOBAL0_INTR,
270         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
271         .utcId          = UDMA_UTC_ID_INVALID,
272         .eventMode      = UDMA_TEST_EVENT_INTR,
273         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
274         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
275         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
276         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
277         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
278         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
279         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
280     },
281     {
282         .chPrmId        = UDMA_TEST_CH_PRMID_EVENTSIZE_ICNT1,
283         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
284         .utcId          = UDMA_UTC_ID_INVALID,
285         .eventMode      = UDMA_TEST_EVENT_NONE,
286         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
287         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT1_DEC,
288         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT1_DEC,
289         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
290         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
291         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
292         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
293     },
294     {
295         .chPrmId        = UDMA_TEST_CH_PRMID_EVENTSIZE_ICNT2,
296         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
297         .utcId          = UDMA_UTC_ID_INVALID,
298         .eventMode      = UDMA_TEST_EVENT_NONE,
299         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
300         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT2_DEC,
301         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT2_DEC,
302         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
303         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
304         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
305         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
306     },
307     {
308         .chPrmId        = UDMA_TEST_CH_PRMID_EVENTSIZE_ICNT3,
309         .chType         = UDMA_CH_TYPE_TR_BLK_COPY,
310         .utcId          = UDMA_UTC_ID_INVALID,
311         .eventMode      = UDMA_TEST_EVENT_NONE,
312         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0,
313         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT3_DEC,
314         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT3_DEC,
315         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
316         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
317         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
318         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
319     },
320     {
321         .chPrmId        = UDMA_TEST_CH_PRMID_DRU_DEF,
322         .chType         = UDMA_CH_TYPE_UTC,
323         .utcId          = UDMA_UTC_ID_MSMC_DRU0,
324         .eventMode      = UDMA_TEST_EVENT_NONE,
325         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
326         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
327         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
328         .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
329         .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
330         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
331         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
332     },
333     {
334         .chPrmId        = UDMA_TEST_CH_PRMID_DRU_INTR_DEF,
335         .chType         = UDMA_CH_TYPE_UTC,
336         .utcId          = UDMA_UTC_ID_MSMC_DRU0,
337         .eventMode      = UDMA_TEST_EVENT_INTR,
338         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
339         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
340         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
341         .txPrmId        = UDMA_TEST_TXCH_PRMID_INVALID,
342         .rxPrmId        = UDMA_TEST_RXCH_PRMID_INVALID,
343         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
344         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
345     },
346     {
347         .chPrmId        = UDMA_TEST_CH_PRMID_BLKCPY_HC_DEF,
348         .chType         = UDMA_CH_TYPE_TR_BLK_COPY_HC,
349         .utcId          = UDMA_UTC_ID_INVALID,
350         .eventMode      = UDMA_TEST_EVENT_NONE,
351         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
352         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
353         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
354         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
355         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
356         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
357         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
358     },
359     {
360         .chPrmId        = UDMA_TEST_CH_PRMID_BLKCPY_HC_INTR_DEF,
361         .chType         = UDMA_CH_TYPE_TR_BLK_COPY_HC,
362         .utcId          = UDMA_UTC_ID_INVALID,
363         .eventMode      = UDMA_TEST_EVENT_INTR,
364         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
365         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
366         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
367         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
368         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
369         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
370         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
371     },
372     {
373         .chPrmId        = UDMA_TEST_CH_PRMID_BLKCPY_UHC_DEF,
374         .chType         = UDMA_CH_TYPE_TR_BLK_COPY_UHC,
375         .utcId          = UDMA_UTC_ID_INVALID,
376         .eventMode      = UDMA_TEST_EVENT_NONE,
377         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
378         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
379         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
380         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
381         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
382         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
383         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
384     },
385     {
386         .chPrmId        = UDMA_TEST_CH_PRMID_BLKCPY_UHC_INTR_DEF,
387         .chType         = UDMA_CH_TYPE_TR_BLK_COPY_UHC,
388         .utcId          = UDMA_UTC_ID_INVALID,
389         .eventMode      = UDMA_TEST_EVENT_INTR,
390         .trigger        = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE,
391         .eventSize      = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION,
392         .triggerType    = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL,
393         .txPrmId        = UDMA_TEST_TXCH_PRMID_DEF,
394         .rxPrmId        = UDMA_TEST_RXCH_PRMID_DEF,
395         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
396         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
397     },
398 };
399 #define UDMA_TEST_NUM_CH_PRM            (sizeof(gUdmaTestChPrm) / \
400                                          sizeof(gUdmaTestChPrm[0U]))
402 /** \brief Defines the various ring parameters. */
403 static const UdmaTestRingPrm gUdmaTestRingPrm[] =
405     {
406         .ringPrmId      = UDMA_TEST_RING_PRMID_EVENT_NONE,
407         .eventMode      = UDMA_TEST_EVENT_NONE,
408     },
409     {
410         .ringPrmId      = UDMA_TEST_RING_PRMID_EVENT_INTR,
411         .eventMode      = UDMA_TEST_EVENT_INTR,
412     },
413     {
414         .ringPrmId      = UDMA_TEST_RING_PRMID_EVENT_POLLED,
415         .eventMode      = UDMA_TEST_EVENT_POLLED,
416     },
417 };
418 #define UDMA_TEST_NUM_RING_PRM          (sizeof(gUdmaTestRingPrm) / \
419                                          sizeof(gUdmaTestRingPrm[0U]))
421 #ifdef __cplusplus
423 #endif
425 #endif /* #ifndef UDMA_TEST_CONFIG_H_ */