1 @******************************************************************************
2 @
3 @ \file cp15.S
4 @
5 @ \brief CP15 coprocessor configuration APIs are defined in this file.
6 @
7 @******************************************************************************
8 @ Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/
9 @
10 @
11 @ Redistribution and use in source and binary forms, with or without
12 @ modification, are permitted provided that the following conditions
13 @ are met:
14 @
15 @ Redistributions of source code must retain the above copyright
16 @ notice, this list of conditions and the following disclaimer.
17 @
18 @ Redistributions in binary form must reproduce the above copyright
19 @ notice, this list of conditions and the following disclaimer in the
20 @ documentation and/or other materials provided with the
21 @ distribution.
22 @
23 @ Neither the name of Texas Instruments Incorporated nor the names of
24 @ its contributors may be used to endorse or promote products derived
25 @ from this software without specific prior written permission.
26 @
27 @ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 @ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 @ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 @ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 @ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 @ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 @ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 @ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 @ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 @ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 @ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 @
39 @******************************************************************************
41 @******************************************************************************
42 @* INCLUDE FILES
43 @******************************************************************************
45 @******************************************************************************
46 @* SYMBOLS
47 @******************************************************************************
49 .global CP15ICacheDisable
50 .global CP15DCacheDisable
51 .global CP15ICacheEnable
52 .global CP15DCacheEnable
53 .global CP15ICacheFlush
54 .global CP15DCacheCleanFlush
55 .global CP15DCacheClean
56 .global CP15DCacheFlush
57 .global CP15DCacheCleanBuff
58 .global CP15DCacheCleanFlushBuff
59 .global CP15DCacheFlushBuff
60 .global CP15ICacheFlushBuff
61 .global CP15Ttb0Set
62 .global CP15TlbInvalidate
63 .global CP15MMUDisable
64 .global CP15MMUEnable
65 .global CP15VectorBaseAddrSet
66 .global CP15BranchPredictorInvalidate
67 .global CP15BranchPredictionEnable
68 .global CP15BranchPredictionDisable
69 .global CP15DomainAccessClientSet
70 .global CP15ControlFeatureDisable
71 .global CP15ControlFeatureEnable
72 .global CP15TtbCtlTtb0Config
73 .global CP15AuxControlFeatureEnable
74 .global CP15AuxControlFeatureDisable
75 .global CP15MainIdPrimPartNumGet
77 @******************************************************************************
78 @* CODE SECTION
79 @******************************************************************************
80 .text
82 @ This code is assembled for ARM instructions
83 .code 32
85 @******************************************************************************
86 @* ASSEMBLY ROUTINES
87 @******************************************************************************
89 @*****************************************************************************
90 @ This API disables the Instruction cache.
91 @*****************************************************************************
92 CP15ICacheDisable:
93 PUSH {lr}
94 MRC p15, #0, r0, c1, c0, #0
95 BIC r0, r0, #0x00001000
96 MCR p15, #0, r0, c1, c0, #0
97 BL CP15ICacheFlush
98 POP {lr}
99 BX lr
101 @*****************************************************************************
102 @ This API disables the Data cache.
103 @*****************************************************************************
104 CP15DCacheDisable:
105 PUSH {r4-r11, lr}
106 MRC p15, #0, r0, c1, c0, #0
107 BIC r0, r0, #0x00000004
108 MCR p15, #0, r0, c1, c0, #0
109 BL CP15DCacheCleanFlush
110 POP {r4-r11, lr}
111 BX lr
113 @*****************************************************************************
114 @ This API enables I-cache
115 @*****************************************************************************
116 CP15ICacheEnable:
117 MRC p15, #0, r0, c1, c0, #0
118 ORR r0, r0, #0x00001000
119 MCR p15, #0, r0, c1, c0, #0
120 BX lr
122 @*****************************************************************************
123 @ This API enables the Data cache.
124 @*****************************************************************************
125 CP15DCacheEnable:
126 MRC p15, #0, r0, c1, c0, #0
127 ORR r0, r0, #0x00000004
128 MCR p15, #0, r0, c1, c0, #0
129 BX lr
131 @*****************************************************************************
132 @ This API Invalidates the entire Data/Unified Cache
133 @*****************************************************************************
134 CP15DCacheFlush:
135 PUSH {r4-r11}
136 DMB
137 MRC p15, #1, r0, c0, c0, #1 @ Read CLID register
138 ANDS r3, r0, #0x7000000 @ Get Level of Coherency
139 MOV r3, r3, lsr #23
140 BEQ ffinished
141 MOV r10, #0
142 floop1:
143 ADD r2, r10, r10, lsr #1
144 MOV r1, r0, lsr r2
145 AND r1, r1, #7
146 CMP r1, #2
147 BLT fskip
148 MCR p15, #2, r10, c0, c0, #0
149 ISB
150 MRC p15, #1, r1, c0, c0, #0
151 AND r2, r1, #7
152 ADD r2, r2, #4
153 LDR r4, _FLD_MAX_WAY
154 ANDS r4, r4, r1, lsr #3
155 CLZ r5, r4
156 LDR r7, _FLD_MAX_IDX
157 ANDS r7, r7, r1, lsr #13
158 floop2:
159 MOV r9, r4
160 floop3:
161 ORR r11, r10, r9, lsl r5
162 ORR r11, r11, r7, lsl r2
163 MCR p15, #0, r11, c7, c6, #2
164 SUBS r9, r9, #1
165 BGE floop3
166 SUBS r7, r7, #1
167 BGE floop2
168 fskip:
169 ADD r10, r10, #2
170 CMP r3, r10
171 BGT floop1
173 ffinished:
174 DSB
175 ISB
176 POP {r4-r11}
177 BX lr
179 @*****************************************************************************
180 @ This API cleans the entire D Cache to PoC
181 @*****************************************************************************
182 CP15DCacheClean:
183 PUSH {r4-r11}
184 DMB
185 MRC p15, #1, r0, c0, c0, #1 @ Read CLID register
186 ANDS r3, r0, #0x7000000 @ Get Level of Coherency
187 MOV r3, r3, lsr #23
188 BEQ cfinished
189 MOV r10, #0
190 cloop1:
191 ADD r2, r10, r10, lsr #1
192 MOV r1, r0, lsr r2
193 AND r1, r1, #7
194 CMP r1, #2
195 BLT cskip
196 MCR p15, #2, r10, c0, c0, #0
197 ISB
198 MRC p15, #1, r1, c0, c0, #0
199 AND r2, r1, #7
200 ADD r2, r2, #4
201 LDR r4, _FLD_MAX_WAY
202 ANDS r4, r4, r1, lsr #3
203 CLZ r5, r4
204 LDR r7, _FLD_MAX_IDX
205 ANDS r7, r7, r1, lsr #13
206 cloop2:
207 MOV r9, r4
208 cloop3:
209 ORR r11, r10, r9, lsl r5
210 ORR r11, r11, r7, lsl r2
211 MCR p15, #0, r11, c7, c10, #2
212 SUBS r9, r9, #1
213 BGE cloop3
214 SUBS r7, r7, #1
215 BGE cloop2
216 cskip:
217 ADD r10, r10, #2
218 CMP r3, r10
219 BGT cloop1
221 cfinished:
222 DSB
223 ISB
224 POP {r4-r11}
225 BX lr
227 @*****************************************************************************
228 @ This API cleans and invalidates the entire D Cache to PoC
229 @*****************************************************************************
230 CP15DCacheCleanFlush:
231 PUSH {r4-r11}
232 DMB
233 MRC p15, #1, r0, c0, c0, #1 @ Read CLID register
234 ANDS r3, r0, #0x7000000 @ Get Level of Coherency
235 MOV r3, r3, lsr #23
236 BEQ finished
237 MOV r10, #0
238 loop1:
239 ADD r2, r10, r10, lsr #1
240 MOV r1, r0, lsr r2
241 AND r1, r1, #7
242 CMP r1, #2
243 BLT skip
244 MCR p15, #2, r10, c0, c0, #0
245 ISB
246 MRC p15, #1, r1, c0, c0, #0
247 AND r2, r1, #7
248 ADD r2, r2, #4
249 LDR r4, _FLD_MAX_WAY
250 ANDS r4, r4, r1, lsr #3
251 CLZ r5, r4
252 LDR r7, _FLD_MAX_IDX
253 ANDS r7, r7, r1, lsr #13
254 loop2:
255 MOV r9, r4
256 loop3:
257 ORR r11, r10, r9, lsl r5
258 ORR r11, r11, r7, lsl r2
259 MCR p15, #0, r11, c7, c14, #2
260 SUBS r9, r9, #1
261 BGE loop3
262 SUBS r7, r7, #1
263 BGE loop2
264 skip:
265 ADD r10, r10, #2
266 CMP r3, r10
267 BGT loop1
269 finished:
270 DSB
271 ISB
272 POP {r4-r11}
273 BX lr
275 @*****************************************************************************
276 @ This API invalidates entire I Cache
277 @*****************************************************************************
278 CP15ICacheFlush:
279 MOV r0, #0
280 MCR p15, #0, r0, c7, c5, #0
281 DSB
282 BX lr
284 @*****************************************************************************
285 @ This API cleans the D-cache/Unified lines corresponding to the buffer
286 @ pointer upto the specified length to PoC.
287 @ r0 - Start Address
288 @ r1 - Number of bytes to be cleaned
289 @*****************************************************************************
290 CP15DCacheCleanBuff:
291 PUSH {r14}
292 ADD r14, r0, r1 @ Calculate the end address
293 DMB
294 MRC p15, #0, r2, c0, c0, #1 @ Read Cache Type Register
295 UBFX r2, r2, #16, #4 @ Extract the DMinLine
296 MOV r3, #2
297 ADD r3, r3, r2
298 MOV r2, #1
299 LSL r2, r2, r3 @ Calculate the line size
301 SUB r3, r2, #1 @ Calculate the mask
302 BIC r0, r0, r3 @ Align to cache line boundary
303 TST r3, r14
304 BIC r14, r14, r3
305 MCRNE p15, #0, r14, c7, c10, #1 @ Clean D/Unified to PoC by MVA
307 cleanloop:
308 MCR p15, #0, r0 , c7, c10, #1 @ Clean D/Unified to PoC by MVA
309 ADDS r0, r0, r2 @ Go to next line
310 CMP r0, r14
311 BLT cleanloop
313 POP {r14}
314 DSB
315 BX lr
317 @*****************************************************************************
318 @ This API cleans and invalidates the D-cache/Unified lines corresponding to
319 @ the buffer pointer upto the specified length to PoC.
320 @ r0 - Start Address
321 @ r1 - Number of bytes to be cleaned and flushed
322 @*****************************************************************************
323 CP15DCacheCleanFlushBuff:
324 PUSH {r14}
325 ADD r14, r0, r1 @ Calculate the end address
326 DMB
327 MRC p15, #0, r2, c0, c0, #1 @ Read Cache Type Register
328 UBFX r2, r2, #16, #4 @ Extract the DMinLine
329 MOV r3, #2
330 ADD r3, r3, r2
331 MOV r2, #1
332 LSL r2, r2, r3 @ Calculate the line size
334 SUB r3, r2, #1 @ Calculate the mask
335 BIC r0, r0, r3 @ Align to cache line boundary
336 TST r3, r14
337 BIC r14, r14, r3
338 MCRNE p15, #0, r14, c7, c14, #1 @ Clean and Flush D/U line to PoC
340 cleanflushloop:
341 MCR p15, #0, r0 , c7, c14, #1 @ Clean and Flush D/U line to PoC
342 ADDS r0, r0, r2 @ Go to next line
343 CMP r0, r14
344 BLT cleanflushloop
346 POP {r14}
347 DSB
348 BX lr
350 @*****************************************************************************
351 @ This API invalidates the D-cache/Unified lines corresponding to
352 @ the buffer pointer up to the specified length to PoC.
353 @ r0 - Start Address
354 @ r1 - Number of bytes to be flushed
355 @*****************************************************************************
356 CP15DCacheFlushBuff:
357 PUSH {r14}
358 ADD r14, r0, r1 @ Calculate the end address
359 DMB
360 MRC p15, #0, r2, c0, c0, #1 @ Read Cache Type Register
361 UBFX r2, r2, #16, #4 @ Extract the DMinLine
362 MOV r3, #2
363 ADD r3, r3, r2
364 MOV r2, #1
365 LSL r2, r2, r3 @ Calculate the line size
367 SUB r3, r2, #1 @ Calculate the mask
368 TST r3, r0
369 BIC r0, r0, r3 @ Align to cache line boundary
370 MCRNE p15, #0, r0, c7, c14, #1 @ Clean and Flush D/U line to PoC
371 ADDNE r0, r0, r2
372 TST r3, r14
373 BIC r14, r14, r3
374 MCRNE p15, #0, r14, c7, c14, #1 @ Clean and Flush D/U line to PoC
375 B dflushcmp
377 dflushloop:
378 MCR p15, #0, r0 , c7, c6, #1 @ Flush D/U line to PoC
379 ADDS r0, r0, r2 @ Go to next line
381 dflushcmp:
382 CMP r0, r14
383 BLT dflushloop
384 POP {r14}
385 DSB
386 BX lr
388 @*****************************************************************************
389 @ This API invalidates I-cache lines from the star address till the length
390 @ specified to PoU.
391 @ r0 - Start Address
392 @ r1 - Number of bytes to be cleaned
393 @*****************************************************************************
394 CP15ICacheFlushBuff:
395 PUSH {r14}
396 ADD r14, r0, r1 @ Calculate the end address
397 DMB
398 MRC p15, #0, r2, c0, c0, #1 @ Read Cache Type Register
399 UBFX r2, r2, #0, #4 @ Extract the DMinLine
400 MOV r3, #2
401 ADD r3, r3, r2
402 MOV r2, #1
403 LSL r2, r2, r3 @ Calculate the line size
405 SUB r3, r2, #1 @ Calculate the mask
406 BIC r0, r0, r3 @ Align to cache line boundary
407 TST r3, r14
408 BIC r14, r14, r3
409 MCRNE p15, #0, r14, c7, c5, #1 @ Invalidate by MVA to PoU
411 iflushloop:
412 MCR p15, #0, r0, c7, c5, #1 @ Invalidate by MVA to PoU
413 ADDS r0, r0, r2 @ Go to next line
414 CMP r0, r14
415 BLT iflushloop
417 POP {r14}
418 DSB
419 BX lr
421 @*****************************************************************************
422 @ Sets TTB0 Register
423 @ r0 - Translation Table Base Address
424 @*****************************************************************************
425 CP15Ttb0Set:
426 MCR p15, #0, r0, c2, c0, #0
427 DMB
428 BX lr
430 @*****************************************************************************
431 @ This API Invalidates the TLB
432 @*****************************************************************************
433 CP15TlbInvalidate:
434 MCR p15, #0, r0, c8, c7, #0 @ r0 value will be ignored
435 DSB
436 BX lr
438 @*****************************************************************************
439 @ This API Disables MMU.
440 @*****************************************************************************
441 CP15MMUDisable:
442 MCR p15, #0, r0, c8, c7, #0 @ Invalidate TLB
443 MRC p15, #0, r0, c1, c0, #0
444 BIC r0, r0, #1
445 MCR p15, #0, r0, c1, c0, #0 @ Clear MMU bit
446 DSB
447 BX lr
449 @*****************************************************************************
450 @ This API Enables MMU.
451 @*****************************************************************************
452 CP15MMUEnable:
453 MRC p15, #0, r0, c1, c0, #0
454 ORR r0, r0, #0x001
455 MCR p15, #0, r0, c1, c0, #0 @ Set MMU Enable bit
456 DSB
457 BX lr
459 @*****************************************************************************
460 @ This API sets the interrupt vector table base address
461 @ r0 - Interrupt Vector Base Address
462 @*****************************************************************************
463 CP15VectorBaseAddrSet:
464 MCR p15, #0, r0, c12, c0, #0
465 DSB
466 BX lr
468 @*****************************************************************************
469 @ This API invalidates the branch predictor
470 @*****************************************************************************
471 CP15BranchPredictorInvalidate:
472 MCR p15, #0, r0, c7, c5, #6
473 ISB
474 BX lr
476 @*****************************************************************************
477 @ This API enables the branch predictor
478 @*****************************************************************************
479 CP15BranchPredictionEnable:
480 MRC p15, #0, r0, c1, c0, #0
481 ORR r0, r0, #0x00000800
482 MCR p15, #0, r0, c1, c0, #0
483 BX lr
485 @*****************************************************************************
486 @ This API disables the branch predictor
487 @*****************************************************************************
488 CP15BranchPredictionDisable:
489 MRC p15, #0, r0, c1, c0, #0
490 BIC r0, r0, #0x00000800
491 MCR p15, #0, r0, c1, c0, #0
492 BX lr
494 @*****************************************************************************
495 @ This API sets the domain access to 'client'
496 @*****************************************************************************
497 CP15DomainAccessClientSet:
498 LDR r0, _CLIENTD
499 MCR p15, #0, r0, c3, c0, #0
500 DSB
501 BX lr
504 @*****************************************************************************
505 @ This API Disables specified features in CP15 control register
506 @ r0 - features Features to disable in Coprocessor 15 control
507 @ register.
508 @ 'features' can take any OR a combination of the
509 @ below values.
510 @ CP15_CONTROL_TEXREMAP - TEX remap flag
511 @ CP15_CONTROL_ACCESSFLAG - Access flag Control
512 @ CP15_CONTROL_ALIGN_CHCK - Alignment Fault Checking
513 @ CP15_CONTROL_MMU - To enable MMU
514 @
515 @ Note: Other fields of the CP15 c1 control register are not given here
516 @ as they are not of importance for StarterWare. However, optionally
517 @ they can also be ADDed.
518 @
519 @*****************************************************************************
520 CP15ControlFeatureDisable:
521 MRC p15, #0, r1, c1, c0, #0
522 BIC r0, r1, r0
523 MCR p15, #0, r0, c1, c0, #0
524 DSB
525 BX lr
527 @*****************************************************************************
528 @ This API Enables specified features in CP15 control register
529 @ r0 - features Features to disable in Coprocessor 15 control
530 @ register.
531 @ 'features' can take any OR a combination of the
532 @ below values.
533 @ CP15_CONTROL_TEXREMAP - TEX remap flag
534 @ CP15_CONTROL_ACCESSFLAG - Access flag Control
535 @ CP15_CONTROL_ALIGN_CHCK - Alignment Fault Checking
536 @ CP15_CONTROL_MMU - To enable MMU
537 @
538 @ Note: Other fields of the CP15 c1 control register are not given here
539 @ as they are not of importance for StarterWare. However, optionally
540 @ they can also be ADDed.
541 @
542 @*****************************************************************************
543 CP15ControlFeatureEnable:
544 MRC p15, #0, r1, c1, c0, #0
545 ORR r0, r1, r0
546 MCR p15, #0, r0, c1, c0, #0
547 DSB
548 BX lr
550 @*****************************************************************************
551 @ This API Configures the TTB control register to use only TTB0
552 @*****************************************************************************
553 CP15TtbCtlTtb0Config:
554 MOV r0, #0x0
555 MCR p15, #0, r0, c2, c0, #2
556 DSB
557 BX lr
559 @*****************************************************************************
560 @ This API Sets the specified fields in Auxiliary Control Register
561 @ r0 - Bit Mask for the bits to be set in Auxiliary Control Register
562 @*****************************************************************************
563 CP15AuxControlFeatureEnable:
564 MRC p15, #0, r1, c1, c0, #1
565 ORR r0, r0, r1
566 MCR p15, #0, r0, c1, c0, #1
567 DSB
568 BX lr
570 @*****************************************************************************
571 @ This API Clears the specified fields in Auxiliary Control Register
572 @ r0 - Bit Mask for the bits to be cleared in Auxiliary Control Register
573 @*****************************************************************************
574 CP15AuxControlFeatureDisable:
575 MRC p15, #0, r1, c1, c0, #1
576 BIC r0, r1, r0
577 MCR p15, #0, r0, c1, c0, #1
578 DSB
579 BX lr
581 @*****************************************************************************
582 @ This API returns the main ID register in r0
583 @*****************************************************************************
584 CP15MainIdPrimPartNumGet:
585 MRC p15, #0, r0, c0, c0, #0
586 UBFX r0, r0, #4, #12
587 BX lr
589 @******************************************************************************
590 @* LABELS
591 @******************************************************************************
592 _CLIENTD:
593 .word 0x55555555
594 _FLD_MAX_WAY:
595 .word 0x3ff
596 _FLD_MAX_IDX:
597 .word 0x7ff
599 .end