1 /*
2 * Copyright (c) 2015-2018, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /*
33 * ======== HwiP_tirtos.c ========
34 */
36 #include <stdint.h>
37 #include <stdbool.h>
38 #include <stdlib.h>
39 #include <string.h>
40 #include <ti/osal/src/nonos/Nonos_config.h>
41 #include <ti/osal/TaskP.h>
43 #include <FreeRTOS.h>
45 /* External Clock should be defined under osal_soc.h
46 * if SOC is not supporting it, set to -1
47 */
48 #ifndef EXTERNAL_CLOCK_KHZ_DEFAULT
49 #define EXTERNAL_CLOCK_KHZ_DEFAULT (-1)
50 #endif
52 #ifndef OSAL_DELAY_TIMER_ADDR_DEFAULT
53 #define OSAL_DELAY_TIMER_ADDR_DEFAULT ((uintptr_t)(0U))
54 #endif
56 #ifndef OSAL_TARGET_PROC_MASK_DEFAULT
57 #define OSAL_TARGET_PROC_MASK_DEFAULT (0xFFFFU)
58 #endif
60 /* Global Osal static memory status variables */
61 uint32_t gOsalSemAllocCnt = 0U, gOsalSemPeak = 0U;
62 uint32_t gOsalTimerAllocCnt = 0U, gOsalTimerPeak = 0U;
63 uint32_t gOsalHwiAllocCnt = 0U, gOsalHwiPeak = 0U;
64 #ifndef OSAL_CPU_FREQ_KHZ_DEFAULT
65 #define OSAL_CPU_FREQ_KHZ_DEFAULT (400000)
66 #endif
68 volatile bool Osal_DebugP_Assert_Val=(bool)true;
70 /* Global Osal_HwAttr structure */
71 Osal_HwAttrs gOsal_HwAttrs = {
72 OSAL_CPU_FREQ_KHZ_DEFAULT,
73 EXTERNAL_CLOCK_KHZ_DEFAULT,
74 #if defined(gnu_targets_arm_A15F)
75 OSAL_TARGET_PROC_MASK_DEFAULT,
76 #endif
77 #ifdef _TMS320C6X
78 /* ECM_intNum[]: Event combiner interrupts */
79 { OSAL_ECM_GROUP0_INT, /* Interrupt[4-15] to use for Event Combiner Group 0 */
80 OSAL_ECM_GROUP1_INT, /* Interrupt[4-15] to use for Event Combiner Group 1 */
81 OSAL_ECM_GROUP2_INT, /* Interrupt[4-15] to use for Event Combiner Group 2 */
82 OSAL_ECM_GROUP3_INT /* Interrupt[4-15] to use for Event Combiner Group 3 */
83 },
84 #endif
85 OSAL_HWACCESS_UNRESTRICTED, /* Unrestricted access to hardware resources */
86 /* Below timer base configuration is applicable for only AM335x/AM437x SoCs
87 * It is not applicable and should not be set for other SoCs
88 * Osal setHwAttrs API would return failure (osal_FAILURE) if attempted to
89 * be set for SoCs other than AM335x and AM437x.
90 */
91 (uintptr_t) OSAL_DELAY_TIMER_ADDR_DEFAULT, /* Timer Base address for osal delay implementation for AM3/AM4 parts */
92 /* Default external Semaphore Memory Block */
93 {
94 (uintptr_t) 0U,
95 0U
96 },
97 /* Default external HwiP Memory Block */
98 {
99 (uintptr_t) 0U,
100 0U
101 }
102 };
104 /*
105 * ======== Osal_DebugP_assert ========
106 */
107 void Osal_DebugP_assert(int32_t expression, const char *file, int32_t line)
108 {
109 (void)file;
110 (void)line;
112 if (expression != 0) {
113 while (Osal_DebugP_Assert_Val == (bool)true) {}
114 }
115 }
117 Osal_ThreadType Osal_getThreadType(void)
118 {
119 Osal_ThreadType osalThreadType;
120 if( xPortInIsrContext())
121 {
122 osalThreadType = Osal_ThreadType_Hwi;
123 }
124 else
125 {
126 osalThreadType = Osal_ThreadType_Task;
127 }
128 return (osalThreadType);
129 }
131 /* Osal delay */
132 int32_t Osal_delay(uint32_t nTicks)
133 {
134 Osal_ThreadType type;
135 int32_t ret;
137 type = Osal_getThreadType();
138 if (type == Osal_ThreadType_Task) {
139 TaskP_sleep(nTicks);
140 ret = osal_OK;
141 }
142 else {
143 ret = osal_FAILURE;
144 }
145 return(ret);
146 }
148 /*
149 * set Osal_HwAttrs structure
150 */
151 int32_t Osal_setHwAttrs(uint32_t ctrlBitMap, const Osal_HwAttrs *hwAttrs)
152 {
153 int32_t ret = osal_FAILURE;
154 if (hwAttrs != NULL_PTR) {
155 if ((ctrlBitMap & OSAL_HWATTR_SET_EXT_CLK) !=0U) {
156 gOsal_HwAttrs.extClkKHz= hwAttrs->extClkKHz;
157 ret = osal_OK;
158 }
159 #ifdef _TMS320C6X
160 /* Set the Event Combiner Interrupts */
161 if ((ctrlBitMap & OSAL_HWATTR_SET_ECM_INT) !=0U) {
162 (void)memcpy(gOsal_HwAttrs.ECM_intNum,hwAttrs->ECM_intNum,4U*sizeof(gOsal_HwAttrs.ECM_intNum[0]));
163 ret = osal_OK;
164 }
165 #endif
166 /* Set the Hw Access type */
167 if ((ctrlBitMap & OSAL_HWATTR_SET_HWACCESS_TYPE) != 0U) {
168 gOsal_HwAttrs.hwAccessType = hwAttrs->hwAccessType;
169 ret = osal_OK;
170 }
172 /* Set the Hw Access type */
173 if ((ctrlBitMap & OSAL_HWATTR_SET_OSALDELAY_TIMER_BASE) !=0U) {
174 #if defined(SOC_AM437x)|| defined (SOC_AM335x)
175 gOsal_HwAttrs.osalDelayTimerBaseAddr = hwAttrs->osalDelayTimerBaseAddr;
176 ret = osal_OK;
177 #else
178 ret = osal_UNSUPPORTED;
179 #endif
180 }
182 /* Set the extended memmory block for semaphore operations */
183 if ((ctrlBitMap & OSAL_HWATTR_SET_SEMP_EXT_BASE) !=0U)
184 {
185 gOsal_HwAttrs.extSemaphorePBlock = hwAttrs->extSemaphorePBlock;
186 /* Zero out the given memory block */
187 (void)memset((void*)gOsal_HwAttrs.extSemaphorePBlock.base, 0, gOsal_HwAttrs.extSemaphorePBlock.size);
188 ret = osal_OK;
189 }
191 /* Set the extended memmory block for semaphore operations */
192 if ((ctrlBitMap & OSAL_HWATTR_SET_HWIP_EXT_BASE)!=0U)
193 {
194 gOsal_HwAttrs.extHwiPBlock = hwAttrs->extHwiPBlock;
195 /* Zero out the given memory block */
196 (void)memset((void*)gOsal_HwAttrs.extHwiPBlock.base, 0, gOsal_HwAttrs.extHwiPBlock.size);
197 ret = osal_OK;
198 }
199 /* Set the CPU frequency */
200 if ((ctrlBitMap & OSAL_HWATTR_SET_CPU_FREQ)!=0U)
201 {
202 gOsal_HwAttrs.cpuFreqKHz = hwAttrs->cpuFreqKHz;
203 ret = osal_OK;
204 }
205 }
206 return(ret);
207 }
209 /*
210 * set Osal_HwAttrs structure
211 */
212 int32_t Osal_getHwAttrs( Osal_HwAttrs *hwAttrs)
213 {
214 int32_t ret = osal_FAILURE;
215 if (hwAttrs != NULL_PTR) {
216 (void)memcpy(hwAttrs, &gOsal_HwAttrs, sizeof(Osal_HwAttrs));
217 ret = osal_OK;
218 }
219 return(ret);
220 }
222 int32_t Osal_getStaticMemStatus(Osal_StaticMemStatus *pMemStat)
223 {
224 int32_t retVal = osal_OK;
225 uintptr_t cookie;
227 if (NULL_PTR != pMemStat)
228 {
229 cookie = HwiP_disable();
231 pMemStat->peakSemObjs = gOsalSemPeak;
232 pMemStat->numMaxSemObjs = OSAL_TIRTOS_CONFIGNUM_SEMAPHORE;
233 pMemStat->numFreeSemObjs =
234 pMemStat->numMaxSemObjs - gOsalSemAllocCnt;
236 pMemStat->peakTimerObjs = gOsalTimerPeak;
237 pMemStat->numMaxTimerObjs = OSAL_TIRTOS_CONFIGNUM_TIMER;
238 pMemStat->numFreeTimerObjs =
239 pMemStat->numMaxTimerObjs - gOsalTimerAllocCnt;
241 pMemStat->peakHwiObjs = gOsalHwiPeak;
242 pMemStat->numMaxHwiObjs = OSAL_TIRTOS_CONFIGNUM_HWI;
243 pMemStat->numFreeHwiObjs =
244 pMemStat->numMaxHwiObjs - gOsalHwiAllocCnt;
246 HwiP_restore(cookie);
247 }
248 else
249 {
250 retVal = osal_FAILURE;
251 }
253 return (retVal);
254 }
256 /* Nothing past this point */