1 /*
2 * Copyright (c) 2015-2018, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /*
33 * ======== HwiP_tirtos.c ========
34 */
36 #include <stdint.h>
37 #include <stdbool.h>
38 #include <stdlib.h>
39 #include <string.h>
40 #include <ti/osal/src/nonos/Nonos_config.h>
41 #include <ti/osal/TaskP.h>
43 #include <FreeRTOS.h>
44 #include <task.h>
46 /* External Clock should be defined under osal_soc.h
47 * if SOC is not supporting it, set to -1
48 */
49 #ifndef EXTERNAL_CLOCK_KHZ_DEFAULT
50 #define EXTERNAL_CLOCK_KHZ_DEFAULT (-1)
51 #endif
53 #ifndef OSAL_DELAY_TIMER_ADDR_DEFAULT
54 #define OSAL_DELAY_TIMER_ADDR_DEFAULT ((uintptr_t)(0U))
55 #endif
57 #ifndef OSAL_TARGET_PROC_MASK_DEFAULT
58 #define OSAL_TARGET_PROC_MASK_DEFAULT (0xFFFFU)
59 #endif
61 /* Global Osal static memory status variables */
62 uint32_t gOsalSemAllocCnt = 0U, gOsalSemPeak = 0U;
63 uint32_t gOsalTimerAllocCnt = 0U, gOsalTimerPeak = 0U;
64 uint32_t gOsalHwiAllocCnt = 0U, gOsalHwiPeak = 0U;
65 #ifndef OSAL_CPU_FREQ_KHZ_DEFAULT
66 #define OSAL_CPU_FREQ_KHZ_DEFAULT (400000)
67 #endif
69 volatile bool Osal_DebugP_Assert_Val=(bool)true;
71 /* Global Osal_HwAttr structure */
72 Osal_HwAttrs gOsal_HwAttrs = {
73 OSAL_CPU_FREQ_KHZ_DEFAULT,
74 EXTERNAL_CLOCK_KHZ_DEFAULT,
75 #if defined(gnu_targets_arm_A15F)
76 OSAL_TARGET_PROC_MASK_DEFAULT,
77 #endif
78 #ifdef _TMS320C6X
79 /* ECM_intNum[]: Event combiner interrupts */
80 { OSAL_ECM_GROUP0_INT, /* Interrupt[4-15] to use for Event Combiner Group 0 */
81 OSAL_ECM_GROUP1_INT, /* Interrupt[4-15] to use for Event Combiner Group 1 */
82 OSAL_ECM_GROUP2_INT, /* Interrupt[4-15] to use for Event Combiner Group 2 */
83 OSAL_ECM_GROUP3_INT /* Interrupt[4-15] to use for Event Combiner Group 3 */
84 },
85 #endif
86 OSAL_HWACCESS_UNRESTRICTED, /* Unrestricted access to hardware resources */
87 /* Below timer base configuration is applicable for only AM335x/AM437x SoCs
88 * It is not applicable and should not be set for other SoCs
89 * Osal setHwAttrs API would return failure (osal_FAILURE) if attempted to
90 * be set for SoCs other than AM335x and AM437x.
91 */
92 (uintptr_t) OSAL_DELAY_TIMER_ADDR_DEFAULT, /* Timer Base address for osal delay implementation for AM3/AM4 parts */
93 /* Default external Semaphore Memory Block */
94 {
95 (uintptr_t) 0U,
96 0U
97 },
98 /* Default external HwiP Memory Block */
99 {
100 (uintptr_t) 0U,
101 0U
102 }
103 };
105 /*
106 * ======== Osal_DebugP_assert ========
107 */
108 void Osal_DebugP_assert(int32_t expression, const char *file, int32_t line)
109 {
110 (void)file;
111 (void)line;
113 if (expression != 0) {
114 while (Osal_DebugP_Assert_Val == (bool)true) {}
115 }
116 }
118 Osal_ThreadType Osal_getThreadType(void)
119 {
120 Osal_ThreadType osalThreadType;
121 if( xPortInIsrContext())
122 {
123 osalThreadType = Osal_ThreadType_Hwi;
124 }
125 else if(taskSCHEDULER_NOT_STARTED == xTaskGetSchedulerState())
126 {
127 osalThreadType = Osal_ThreadType_Main;
128 }
129 else
130 {
131 osalThreadType = Osal_ThreadType_Task;
132 }
133 return (osalThreadType);
134 }
136 /* Osal delay */
137 int32_t Osal_delay(uint32_t nTicks)
138 {
139 Osal_ThreadType type;
140 int32_t ret;
142 type = Osal_getThreadType();
143 if (type == Osal_ThreadType_Task) {
144 TaskP_sleep(nTicks);
145 ret = osal_OK;
146 }
147 else {
148 ret = osal_FAILURE;
149 }
150 return(ret);
151 }
153 /*
154 * set Osal_HwAttrs structure
155 */
156 int32_t Osal_setHwAttrs(uint32_t ctrlBitMap, const Osal_HwAttrs *hwAttrs)
157 {
158 int32_t ret = osal_FAILURE;
159 if (hwAttrs != NULL_PTR) {
160 if ((ctrlBitMap & OSAL_HWATTR_SET_EXT_CLK) !=0U) {
161 gOsal_HwAttrs.extClkKHz= hwAttrs->extClkKHz;
162 ret = osal_OK;
163 }
164 #ifdef _TMS320C6X
165 /* Set the Event Combiner Interrupts */
166 if ((ctrlBitMap & OSAL_HWATTR_SET_ECM_INT) !=0U) {
167 (void)memcpy(gOsal_HwAttrs.ECM_intNum,hwAttrs->ECM_intNum,4U*sizeof(gOsal_HwAttrs.ECM_intNum[0]));
168 ret = osal_OK;
169 }
170 #endif
171 /* Set the Hw Access type */
172 if ((ctrlBitMap & OSAL_HWATTR_SET_HWACCESS_TYPE) != 0U) {
173 gOsal_HwAttrs.hwAccessType = hwAttrs->hwAccessType;
174 ret = osal_OK;
175 }
177 /* Set the Hw Access type */
178 if ((ctrlBitMap & OSAL_HWATTR_SET_OSALDELAY_TIMER_BASE) !=0U) {
179 #if defined(SOC_AM437x)|| defined (SOC_AM335x)
180 gOsal_HwAttrs.osalDelayTimerBaseAddr = hwAttrs->osalDelayTimerBaseAddr;
181 ret = osal_OK;
182 #else
183 ret = osal_UNSUPPORTED;
184 #endif
185 }
187 /* Set the extended memmory block for semaphore operations */
188 if ((ctrlBitMap & OSAL_HWATTR_SET_SEMP_EXT_BASE) !=0U)
189 {
190 gOsal_HwAttrs.extSemaphorePBlock = hwAttrs->extSemaphorePBlock;
191 /* Zero out the given memory block */
192 (void)memset((void*)gOsal_HwAttrs.extSemaphorePBlock.base, 0, gOsal_HwAttrs.extSemaphorePBlock.size);
193 ret = osal_OK;
194 }
196 /* Set the extended memmory block for semaphore operations */
197 if ((ctrlBitMap & OSAL_HWATTR_SET_HWIP_EXT_BASE)!=0U)
198 {
199 gOsal_HwAttrs.extHwiPBlock = hwAttrs->extHwiPBlock;
200 /* Zero out the given memory block */
201 (void)memset((void*)gOsal_HwAttrs.extHwiPBlock.base, 0, gOsal_HwAttrs.extHwiPBlock.size);
202 ret = osal_OK;
203 }
204 /* Set the CPU frequency */
205 if ((ctrlBitMap & OSAL_HWATTR_SET_CPU_FREQ)!=0U)
206 {
207 gOsal_HwAttrs.cpuFreqKHz = hwAttrs->cpuFreqKHz;
208 ret = osal_OK;
209 }
210 }
211 return(ret);
212 }
214 /*
215 * set Osal_HwAttrs structure
216 */
217 int32_t Osal_getHwAttrs( Osal_HwAttrs *hwAttrs)
218 {
219 int32_t ret = osal_FAILURE;
220 if (hwAttrs != NULL_PTR) {
221 (void)memcpy(hwAttrs, &gOsal_HwAttrs, sizeof(Osal_HwAttrs));
222 ret = osal_OK;
223 }
224 return(ret);
225 }
227 int32_t Osal_getStaticMemStatus(Osal_StaticMemStatus *pMemStat)
228 {
229 int32_t retVal = osal_OK;
230 uintptr_t cookie;
232 if (NULL_PTR != pMemStat)
233 {
234 cookie = HwiP_disable();
236 pMemStat->peakSemObjs = gOsalSemPeak;
237 pMemStat->numMaxSemObjs = OSAL_TIRTOS_CONFIGNUM_SEMAPHORE;
238 pMemStat->numFreeSemObjs =
239 pMemStat->numMaxSemObjs - gOsalSemAllocCnt;
241 pMemStat->peakTimerObjs = gOsalTimerPeak;
242 pMemStat->numMaxTimerObjs = OSAL_TIRTOS_CONFIGNUM_TIMER;
243 pMemStat->numFreeTimerObjs =
244 pMemStat->numMaxTimerObjs - gOsalTimerAllocCnt;
246 pMemStat->peakHwiObjs = gOsalHwiPeak;
247 pMemStat->numMaxHwiObjs = OSAL_TIRTOS_CONFIGNUM_HWI;
248 pMemStat->numFreeHwiObjs =
249 pMemStat->numMaxHwiObjs - gOsalHwiAllocCnt;
251 HwiP_restore(cookie);
252 }
253 else
254 {
255 retVal = osal_FAILURE;
256 }
258 return (retVal);
259 }
261 /* Nothing past this point */