1 /*
2 * Copyright (c) 2016-2018, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /*
33 * ======== HwiP_nonos.c ========
34 */
36 #include <stdint.h>
37 #include <stdbool.h>
38 #include <stdlib.h>
40 #include <ti/osal/src/nonos/Nonos_config.h>
42 extern uint32_t gOsalHwiAllocCnt, gOsalHwiPeak;
44 /*
45 * ======== HwiP_clearInterrupt ========
46 */
47 void HwiP_clearInterrupt(int32_t interruptNum)
48 {
49 OsalArch_clearInterrupt((uint32_t)interruptNum);
50 }
52 /*
53 * ======== HwiP_create ========
54 */
55 HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn,
56 const HwiP_Params *params)
57 {
58 HwiP_Handle handle;
59 handle = OsalArch_HwiPCreate(interruptNum,hwiFxn,params);
61 /* Update statistics for successful allocation */
62 if (handle != NULL_PTR)
63 {
64 gOsalHwiAllocCnt++;
65 if (gOsalHwiAllocCnt > gOsalHwiPeak)
66 {
67 gOsalHwiPeak = gOsalHwiAllocCnt;
68 }
69 }
70 return (handle);
71 }
73 /*
74 * ======== HwiP_delete ========
75 */
76 HwiP_Status HwiP_delete(HwiP_Handle handle)
77 {
78 HwiP_Status status;
80 OSAL_Assert((handle == NULL_PTR));
82 if(handle!=NULL_PTR) {
83 status = OsalArch_HwiPDelete(handle);
85 if (status == HwiP_OK)
86 {
87 if (gOsalHwiAllocCnt > 0U)
88 {
89 gOsalHwiAllocCnt--;
90 }
91 }
92 }
93 else
94 {
95 status = HwiP_FAILURE;
96 }
98 return (status);
99 }
101 /*
102 * ======== HwiP_disable ========
103 */
104 uintptr_t HwiP_disable(void)
105 {
106 return (OsalArch_globalDisableInterrupt());
107 }
109 /*
110 * ======== HwiP_disableInterrupt ========
111 */
112 void HwiP_disableInterrupt(int32_t interruptNum)
113 {
114 OsalArch_disableInterrupt((uint32_t)interruptNum);
115 return;
116 }
118 /*
119 * ======== HwiP_enableInterrupt ========
120 */
121 void HwiP_enableInterrupt(int32_t interruptNum)
122 {
123 OsalArch_enableInterrupt((uint32_t)interruptNum);
124 return;
125 }
127 int32_t HwiP_post(uint32_t interruptNum)
128 {
129 #if defined (SOC_AM65XX) || defined (SOC_AM572x) || defined (SOC_AM64X) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_TPR12)
130 return(OsalArch_postInterrupt(interruptNum));
131 #else
132 return (osal_UNSUPPORTED);
133 #endif
134 }
137 /*
138 * ======== HwiP_Params_init ========
139 */
140 void HwiP_Params_init(HwiP_Params *params)
141 {
142 params->name = (char *) NULL_PTR;
143 params->arg = 0;
144 params->priority = HWIP_USE_DEFAULT_PRIORITY;
145 params->evtId = 0;
146 params->enableIntr = TRUE;
147 #if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__)
148 params->triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LEVEL;
149 #if !defined (SOC_AM437x) && !defined(SOC_AM335x) && !defined (__TI_ARM_V7R4__)
150 {
151 Osal_HwAttrs hwAttrs;
152 (void)Osal_getHwAttrs(&hwAttrs);
153 if(hwAttrs.hwAccessType==OSAL_HWACCESS_UNRESTRICTED)
154 {
155 /* Do GIC init only in the case of unrestricted hw access */
156 OsalArch_gicInit();
157 }
158 }
159 #endif
160 #endif
161 }
163 /*
164 * ======== HwiP_restore ========
165 */
166 void HwiP_restore(uintptr_t key)
167 {
168 OsalArch_globalRestoreInterrupt(key);
169 return;
170 }
172 #ifdef _TMS320C6X
173 /*
174 * ======== HwiP_getHandle ========
175 * Returns the HwiP handle associated with an interrupt number
176 */
177 HwiP_Handle HwiP_getHandle(int32_t interruptNum)
178 {
179 return(OsalArch_getHandle(interruptNum));
180 }
182 /*
183 * ======== HwiP_getEventId ========
184 * Returns the Event ID associated with an interrupt
185 */
186 int32_t HwiP_getEventId(int32_t interruptNum)
187 {
188 return(OsalArch_getEventId(interruptNum));
189 }
190 #endif