1 /*
2 * Copyright (C) 2021-2022 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /**
34 * \file SafeRTOS_mpu_r5f.c
35 *
36 * \brief The file implements the safertos R5F MPU configuration.
37 *
38 **/
40 /* ========================================================================== */
41 /* Include Files */
42 /* ========================================================================== */
44 /* Generic headers */
45 #include <stdlib.h>
46 #include <stdint.h>
47 #include <string.h>
49 #include <ti/osal/SafeRTOS_MPU.h>
51 /* SafeRTOS includes */
52 #include "SafeRTOS_API.h"
53 #include "mpuARM.h"
55 /* ========================================================================== */
56 /* Macros & Typedefs */
57 /* ========================================================================== */
59 /* None */
61 /* ========================================================================== */
62 /* Function Declarations */
63 /* ========================================================================== */
65 __attribute__((section(".startupCode"))) \
66 static portUInt32Type xConfigureMPUAccessCtrl(xMPU_CONFIG_ACCESS *xMPUconfigAccess);
68 /* ========================================================================== */
69 /* Global Variables */
70 /* ========================================================================== */
72 /**
73 * \brief TEX[2:0], C and B values.
74 * CSL_ArmR5MemAttr is used as intex here.
75 * gMemAttr[x][0]: TEX[2:0] values
76 * gMemAttr[x][1]: C bit value
77 * gMemAttr[x][2]: B bit value
78 */
79 __attribute__((section(".startupData"))) \
80 static uint32_t gMemAttr[CSL_ARM_R5_MEM_ATTR_MAX][3U] =
81 {
82 /* TEX[2:0], C, B bits */
83 { 0x0U, 0x0U, 0x0U,}, /* Strongly-ordered.*/
84 { 0x0U, 0x0U, 0x1U,}, /* Shareable Device.*/
85 { 0x0U, 0x1U, 0x0U,}, /* Outer and Inner write-through, no write-allocate. */
86 { 0x0U, 0x1U, 0x1U,}, /* Outer and Inner write-back, no write-allocate. */
87 { 0x1U, 0x0U, 0x0U,}, /* Outer and Inner Non-cacheable. */
88 { 0x1U, 0x1U, 0x1U,}, /* Outer and Inner write-back, write-allocate.*/
89 { 0x2U, 0x0U, 0x0U,}, /* Non-shareable Device.*/
90 };
92 __attribute__((section(".startupData"))) __attribute__((weak)) \
93 xMPU_CONFIG_PARAMETERS gMPUConfigParms[CSL_ARM_R5F_MPU_REGIONS_MAX] =
94 {
95 {
96 /* Region 0 configuration: complete 32 bit address space = 4Gbits add one more 2gb */
97 /* ulRegionNumber */
98 .ulRegionNumber = 1U,
99 /* Starting address */
100 .ulRegionBeginAddress = 0x0U,
101 /* Access permission */
102 {
103 .ulexeNeverControl = 1U,
104 .ulaccessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
105 .ulshareable = 0U,
106 .ulcacheable = 0U,
107 .ulcachePolicy = 0U,
108 .ulmemAttr = 0U,
109 },
110 /* TODO region size is 4GB, but 2GB is largest supported */
111 .ulRegionSize = portmpuLARGEST_REGION_SIZE_ACTUAL,
112 /* ulSubRegionDisable */
113 .ulSubRegionDisable = mpuREGION_ALL_SUB_REGIONS_ENABLED,
114 },
115 {
116 /* Region 0 configuration: second half of 2 GB */
117 /* ulRegionNumber */
118 .ulRegionNumber = 2U,
119 /* Starting address */
120 .ulRegionBeginAddress = portmpuLARGEST_REGION_SIZE_ACTUAL,
121 /* Access permission */
122 {
123 .ulexeNeverControl = 1U,
124 .ulaccessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
125 .ulshareable = 0U,
126 .ulcacheable = 0U,
127 .ulcachePolicy = 0U,
128 .ulmemAttr = 0U,
129 },
130 /* TODO region size is 4GB, but 2GB is largest supported */
131 .ulRegionSize = portmpuLARGEST_REGION_SIZE_ACTUAL,
132 /* ulSubRegionDisable */
133 .ulSubRegionDisable = mpuREGION_ALL_SUB_REGIONS_ENABLED,
134 },
135 {
136 /* Region 1 configuration: 128 bytes memory for exception vector execution */
137 /* ulRegionNumber */
138 .ulRegionNumber = 3U,
139 /* Starting address */
140 .ulRegionBeginAddress = 0x0U,
141 /* Access permission */
142 {
143 .ulexeNeverControl = 0U,
144 .ulaccessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
145 .ulshareable = 0U,
146 .ulcacheable = 1U,
147 .ulcachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
148 .ulmemAttr = 0U,
149 },
150 /* ulRegionSize */
151 .ulRegionSize = 128U,
152 /* ulSubRegionDisable */
153 .ulSubRegionDisable = mpuREGION_ALL_SUB_REGIONS_ENABLED,
154 },
155 {
156 /* Region 2 configuration: 1MB KB MCU MSRAM */
157 /* ulRegionNumber */
158 .ulRegionNumber = 4U,
159 /* Starting address */
160 .ulRegionBeginAddress = 0x41C00000,
161 /* Access permission */
162 {
163 .ulexeNeverControl = 0U,
164 .ulaccessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
165 .ulshareable = 0U,
166 .ulcacheable = 1U,
167 .ulcachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
168 .ulmemAttr = 0U,
169 },
170 /* Size is 512KB */
171 .ulRegionSize = (512U * 1024U),
172 #if defined (SOC_J721E) || defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4)
173 /* Size is 1MB */
174 .ulRegionSize = (1024U * 1024U),
175 #endif
176 /* ulSubRegionDisable */
177 .ulSubRegionDisable = mpuREGION_ALL_SUB_REGIONS_ENABLED,
178 },
179 {
180 /* Region 3 configuration: 2 MB MCMS3 RAM */
181 /* ulRegionNumber */
182 .ulRegionNumber = 5U,
183 /* Starting address */
184 .ulRegionBeginAddress = 0x70000000,
185 /* Access permission */
186 {
187 .ulexeNeverControl = 0U,
188 .ulaccessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
189 .ulshareable = 0U,
190 .ulcacheable = 1U,
191 .ulcachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
192 .ulmemAttr = 0U,
193 },
194 /* Size is 2MB */
195 .ulRegionSize = (2U * 1024U * 1024U),
196 #if defined (SOC_J721E)
197 /* Size is 8MB */
198 .ulRegionSize = (8U * 1024U * 1024U),
199 #endif
201 #if defined (SOC_J7200)
202 /* Size is 1MB */
203 .ulRegionSize = (1U * 1024U * 1024U),
204 #endif
206 #if defined (SOC_J721S2) || defined (SOC_J784S4)
207 /* Size is 4MB */
208 .ulRegionSize = (4U * 1024U * 1024U),
209 #endif
210 /* ulSubRegionDisable */
211 .ulSubRegionDisable = mpuREGION_ALL_SUB_REGIONS_ENABLED,
212 },
213 {
214 /* Region 4 configuration: 2 GB DDR RAM */
215 /* ulRegionNumber */
216 .ulRegionNumber = 6U,
217 /* Starting address */
218 .ulRegionBeginAddress = 0x80000000,
219 /* Access permission */
220 {
221 .ulexeNeverControl = 0U,
222 .ulaccessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
223 .ulshareable = 0U,
224 .ulcacheable = 1U,
225 .ulcachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
226 .ulmemAttr = 0U,
227 },
228 /* size is 2GB */
229 .ulRegionSize = portmpuLARGEST_REGION_SIZE_ACTUAL,
230 /* ulSubRegionDisable */
231 .ulSubRegionDisable = mpuREGION_ALL_SUB_REGIONS_ENABLED,
232 },
233 {
234 /* Region 5 configuration: 32 KB BTCM */
235 /* Address of ATCM/BTCM are configured via MCU_SEC_MMR registers
236 It can either be '0x0' or '0x41010000'. Application/Boot-loader shall
237 take care this configurations and linker command file shall be
238 in sync with this. For either of the above configurations,
239 MPU configurations will not changes as both regions will have same
240 set of permissions in almost all scenarios.
241 Application can chose to overwrite this MPU configuration if needed.
242 The same is true for the region corresponding to ATCM. */
243 /* ulRegionNumber */
244 .ulRegionNumber = 7U,
245 /* Starting address */
246 .ulRegionBeginAddress = 0x41010000,
247 /* Access permission */
248 {
249 .ulexeNeverControl = 0U,
250 .ulaccessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
251 .ulshareable = 0U,
252 .ulcacheable = 1U,
253 .ulcachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
254 .ulmemAttr = 0U,
255 },
256 /* size is 32KB */
257 .ulRegionSize = (32U * 1024U),
258 /* ulSubRegionDisable */
259 .ulSubRegionDisable = mpuREGION_ALL_SUB_REGIONS_ENABLED,
260 },
261 {
262 /* Region 6 configuration: 32 KB ATCM */
263 /* ulRegionNumber */
264 .ulRegionNumber = 8U,
265 /* Starting address */
266 .ulRegionBeginAddress = 0x0,
267 /* Access permission */
268 {
269 .ulexeNeverControl = 0U,
270 .ulaccessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
271 .ulshareable = 0U,
272 .ulcacheable = 1U,
273 .ulcachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
274 .ulmemAttr = 0U,
275 },
276 /* size is 32KB */
277 .ulRegionSize = (32U * 1024U),
278 /* ulSubRegionDisable */
279 .ulSubRegionDisable = mpuREGION_ALL_SUB_REGIONS_ENABLED,
280 },
281 };
283 /* ========================================================================== */
284 /* Function Defintions */
285 /* ========================================================================== */
287 __attribute__((section(".startupCode"))) portBaseType xConfigureMPU()
288 {
289 portBaseType xInitMpuResult = pdPASS;
290 xMPU_CONFIG_PARAMETERS *xMPUconfig;
291 xMPU_CONFIG_ACCESS *xMPUconfigAccess;
292 portUInt32Type ulRegionAccess;
293 uint32_t loopCnt;
295 /* Configure MPU regions only for provided configuration */
296 for(loopCnt = 0; loopCnt < CSL_ARM_R5F_MPU_REGIONS_MAX; loopCnt++)
297 {
298 /* Check if the region is enabled */
299 if (CSL_ARM_R5_MPU_REGION_SIZE_32BYTE <= gMPUConfigParms[loopCnt].ulRegionSize)
300 {
301 ulRegionAccess = 0;
302 xMPUconfig = &gMPUConfigParms[loopCnt];
304 /* Update access control */
305 xMPUconfigAccess = &xMPUconfig->xRegionAccess;
307 ulRegionAccess = xConfigureMPUAccessCtrl(xMPUconfigAccess);
309 xInitMpuResult = xMPUConfigureGlobalRegion(
310 xMPUconfig->ulRegionNumber,
311 xMPUconfig->ulRegionBeginAddress,
312 ulRegionAccess,
313 xMPUconfig->ulRegionSize,
314 xMPUconfig->ulSubRegionDisable
315 );
316 if(pdPASS != xInitMpuResult)
317 {
318 break;
319 }
320 }
321 }
323 return xInitMpuResult;
324 }
326 /*---------------------------------------------------------------------------*/
328 /* ========================================================================== */
329 /* Static Function Definitions */
330 /* ========================================================================== */
332 __attribute__((section(".startupCode"))) \
333 static portUInt32Type xConfigureMPUAccessCtrl(xMPU_CONFIG_ACCESS *xMPUconfigAccess)
334 {
335 portUInt32Type accessCtrlRegVal = 0, tex;
337 accessCtrlRegVal |= ( xMPUconfigAccess->ulexeNeverControl <<
338 CSL_ARM_R5_MPU_REGION_AC_XN_SHIFT);
339 accessCtrlRegVal |= ( xMPUconfigAccess->ulaccessPermission <<
340 CSL_ARM_R5_MPU_REGION_AC_AP_SHIFT);
341 accessCtrlRegVal |= ( xMPUconfigAccess->ulshareable <<
342 CSL_ARM_R5_MPU_REGION_AC_S_SHIFT);
343 if (xMPUconfigAccess->ulcacheable == 1U)
344 {
345 tex = (1U << 2U);
346 tex |= (xMPUconfigAccess->ulcachePolicy);
347 accessCtrlRegVal |=
348 ( tex << CSL_ARM_R5_MPU_REGION_AC_TEX_SHIFT);
349 accessCtrlRegVal |= ( xMPUconfigAccess->ulcachePolicy <<
350 CSL_ARM_R5_MPU_REGION_AC_CB_SHIFT);
351 }
352 else
353 {
354 tex = gMemAttr[xMPUconfigAccess->ulmemAttr][0U];
355 accessCtrlRegVal |=
356 ( tex << CSL_ARM_R5_MPU_REGION_AC_TEX_SHIFT);
357 accessCtrlRegVal |=
358 ( gMemAttr[xMPUconfigAccess->ulmemAttr][1U] <<
359 CSL_ARM_R5_MPU_REGION_AC_B_SHIFT);
360 accessCtrlRegVal |=
361 ( gMemAttr[xMPUconfigAccess->ulmemAttr][2U] <<
362 CSL_ARM_R5_MPU_REGION_AC_C_SHIFT);
363 }
364 return accessCtrlRegVal;
365 }
367 /*---------------------------------------------------------------------------*/