23b4126bd5f509e0404fc9cd8d5df3f72998a550
1 /**
2 * \file main_osal_test.c
3 *
4 * \brief OSAL driver test application main file.
5 *
6 */
8 /*
9 * Copyright (C) 2016-2020 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #if !(defined(BARE_METAL) || defined(FREERTOS))
42 /* XDCtools Header files */
43 #include <xdc/std.h>
44 #if defined (SOC_J721E) || defined(SOC_J7200)
45 // workaround for A72 does not supported in SYS/BIOS yet
46 #if defined (BUILD_C7X_1)
47 #ifndef BARE_METAL
48 #include <ti/sysbios/family/c7x/Hwi.h>
49 #endif //BARE_METAL
50 #endif //BUILD_C7X_1
51 #else
52 #include <xdc/cfg/global.h>
53 #endif
54 #include <xdc/runtime/System.h>
55 #include <xdc/runtime/Error.h>
57 /* BIOS Header files */
58 #include <ti/sysbios/BIOS.h>
59 #include <ti/osal/SwiP.h>
60 #endif
62 #if !defined(BARE_METAL)
63 /* include for both tirtos and freertos. */
64 #include <ti/osal/TaskP.h>
65 #endif
67 #if defined (FREERTOS)
68 #include "FreeRTOS.h"
69 #include "task.h"
70 #include <ti/osal/MemoryP.h>
71 #endif
73 #include <stdio.h>
74 #include <string.h>
75 #include <math.h>
77 /* TI-RTOS Header files */
78 #include <ti/osal/osal.h>
79 #include <ti/osal/soc/osal_soc.h>
80 #include "OSAL_log.h"
82 #include "OSAL_board.h"
84 #if defined (SOC_J721E) || defined(SOC_J7200)
85 #include <ti/drv/sciclient/sciclient.h>
86 #endif
87 /**********************************************************************
88 ************************** Internal functions ************************
89 **********************************************************************/
90 #define TWO_TIMER_INTERRUPT_TEST 0
91 #if defined(SOC_TPR12) || defined (SOC_AWR294X)
92 #define ENABLE_DEBUG_LOG_TEST 1
93 #endif
95 #include <ti/csl/soc.h>
97 #if defined (__C7100__)
98 #include <ti/csl/csl_clec.h>
99 #include <ti/csl/arch/csl_arch.h>
100 #endif
101 #include <ti/csl/tistdtypes.h>
102 #if defined (BARE_METAL)
103 #if !defined(SOC_TPR12) && !defined (SOC_AWR294X)
104 #include <ti/csl/csl_timer.h>
105 #endif
106 #include <ti/csl/arch/csl_arch.h>
108 #if defined (SOC_AM571x) || defined (SOC_AM572x) || defined (SOC_AM574x)
109 #undef TWO_TIMER_INTERRUPT_TEST
110 #define TWO_TIMER_INTERRUPT_TEST 1
111 #endif
112 #elif defined (FREERTOS)
114 #else
115 void ErrorHandler(Error_Block *eb)
116 {
117 OSAL_log("ErrorHandler: ");
118 Error_print(eb);
119 }
120 #endif
122 #if defined(BUILD_C66X_1) || defined(BUILD_C66X_2)
123 /* To set C66 timer interrupts on J7ES VLAB */
124 void C66xTimerInterruptInit(void);
125 #endif
127 #ifdef BUILD_C7X_1
128 void Osal_appC7xPreInit(void);
129 void C7x_ConfigureTimerOutput(void);
130 #endif
132 #undef ENABLE_GET_TIME_TEST
133 #if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_AM572x) || defined(SOC_K2G) || defined(SOC_AM335x) || defined(SOC_AM437x) || defined(SOC_J7200)|| defined(SOC_TPR12) || defined (SOC_AWR294X)
134 #define ENABLE_GET_TIME_TEST 1
135 #endif
137 #ifndef NULL_PTR
138 #define NULL_PTR ((void *)0x0)
139 #endif
141 /**********************************************************************
142 ************************** Global Variables **************************
143 **********************************************************************/
144 #if defined (__TI_ARM_V5__)
145 TimerP_Handle handle;
146 #endif
148 /* Test application stack size */
149 #if defined (__C7100__)
150 /* Temp workaround to avoid assertion failure: A_stackSizeTooSmall : Task stack size must be >= 16KB.
151 * until the Bug PDK-7605 is resolved */
152 #define APP_TSK_STACK_MAIN (32U * 1024U)
153 #else
154 #define APP_TSK_STACK_MAIN (16U * 1024U)
155 #endif
157 #ifdef BARE_METAL
158 /* No task support for Bare metal */
159 #else
160 /* Test application stack */
161 static uint8_t gAppTskStackMain[APP_TSK_STACK_MAIN] __attribute__((aligned(32)));
162 #endif
164 /*
165 * ======== Board_initOSAL ========
166 */
167 void Board_initOSAL(void)
168 {
169 Board_initCfg boardCfg;
170 Board_STATUS status;
171 #if defined(evmK2E) || defined(evmC6678)
172 boardCfg = BOARD_INIT_MODULE_CLOCK |
173 BOARD_INIT_UART_STDIO;
174 #else
175 boardCfg = BOARD_INIT_PINMUX_CONFIG;
176 /* For TPR12 AWR294X we dont do module clock init from app. This is done by
177 * GEL file or SBL. Doing Module Clock init causes OSAL RTI interrupts
178 * to stop if another core also runs OSAL test
179 */
180 #if !defined(SOC_TPR12) && !defined (SOC_AWR294X)
181 #if !defined(_TMS320C6X)
182 boardCfg |= BOARD_INIT_MODULE_CLOCK;
183 #endif
184 #endif /* !defined(SOC_TPR12) */
186 #if defined (UART_CONSOLE)
187 boardCfg |= BOARD_INIT_UART_STDIO;
188 #endif
189 #endif
190 status = Board_init(boardCfg);
192 if (status != BOARD_SOK)
193 {
194 OSAL_log(" Board_init() is not successful...unexpected results may happen \n");
195 }
197 return;
198 }
201 /*
202 * ======== HWI test function ========
203 */
204 volatile uint64_t gTestlocalTimeout = 0x300000U;
206 #if (defined (SOC_AM65XX) || defined (SOC_AM64X) || defined(SOC_J721E) || defined(SOC_J7200) || defined (SOC_TPR12) || defined (SOC_AWR294X)) && (!defined(BUILD_C66X_1))&&(!defined(BUILD_C66X_2))&&(!defined(BUILD_C7X_1))
207 #define INT_NUM_IRQ 32
208 #define LOOP_CNT 100
209 volatile uint64_t gFlagIRQ = 0;
211 void myIsrIRQ(uintptr_t arg)
212 {
213 gFlagIRQ = 1;
214 gTestlocalTimeout = 0x300000;
215 }
216 bool OSAL_core_hwi_test()
217 {
219 HwiP_Params hwiParams;
220 HwiP_Handle handle;
221 volatile int intCount = 0;
222 int32_t ret;
223 bool test_pass=true;
225 HwiP_Params_init(&hwiParams);
227 OSAL_log("Creating Hwi myIsr \n");
228 handle = HwiP_create(INT_NUM_IRQ, myIsrIRQ, &hwiParams);
229 if (handle == NULL_PTR) {
230 OSAL_log("Failed to create the HwiP handle \n");
231 test_pass = false;
232 }
234 if (test_pass == true)
235 {
236 while (intCount != LOOP_CNT)
237 {
238 ret=HwiP_post(INT_NUM_IRQ);
240 if(ret==osal_UNSUPPORTED)
241 { /* In case of unsupported SOC/error */
242 OSAL_log("HwiP_post unsupported/failed!\n");
243 test_pass=false;
244 break;
245 }
247 /* Wait for software timeout, ISR should hit
248 * otherwise return the test as failed */
249 while (gTestlocalTimeout != 0U)
250 {
251 gTestlocalTimeout--;
252 if (gFlagIRQ)
253 {
254 gFlagIRQ = 0;
255 intCount++;
256 break;
257 }
258 }
259 /* Wait is over - did not get any interrupts posted/received
260 * declare the test as fail
261 */
262 if (gTestlocalTimeout == 0)
263 {
264 OSAL_log("Failed to get interrupts \n");
265 test_pass = false;
266 break;
267 }
268 }
270 OSAL_log("%d IRQs received. Test over !\n",intCount);
271 ret = HwiP_delete(handle);
272 if (ret != HwiP_OK)
273 {
274 OSAL_log(" Failed to delete HwiP handle \n");
275 test_pass= false;
276 }
277 }
279 return test_pass;
280 }
281 #endif
283 bool OSAL_hwi_test()
284 {
285 bool pass = true;
286 #if (defined (SOC_AM65XX) || defined (SOC_AM64X) || defined(SOC_J721E) || defined(SOC_J7200) || defined (SOC_TPR12) || defined (SOC_AWR294X)) && (!defined(BUILD_C66X_1))&&(!defined(BUILD_C66X_2))&&(!defined(BUILD_C7X_1))
287 pass = OSAL_core_hwi_test();
288 #endif
289 return pass;
290 }
292 typedef enum UT_Timer_Type_s {
293 UT_Timer_DMTIMER = 0,
294 UT_Timer_TIMER64 = 1,
295 UT_Timer_RTITIMER = 2
296 } UT_Timer_Type_t;
299 #if defined(SOC_AM335x)
300 #define CM_PER_TIMER3_CLKCTRL (0x44e00084)
301 #define CM_DPLL_CLKSEL_TIMER3_CLK (0x44e0050c)
302 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
303 #define OSAL_TEST_TIMER_ID (1U)
304 #define OSAL_TEST_TIMER_PERIOD (5000U)
305 #elif defined(SOC_AM437x)
306 #define CM_PER_TIMER3_CLKCTRL (0x44DF8800 + 0x538)
307 #define CM_DPLL_CLKSEL_TIMER3_CLK (0x44DF4200 + 0x8)
308 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
309 #define OSAL_TEST_TIMER_ID (3U)
310 #define OSAL_TEST_TIMER_PERIOD (5000U)
312 #elif defined(SOC_K2E) || defined(SOC_K2L)
313 UT_Timer_Type_t timer_type = UT_Timer_TIMER64;
314 #define OSAL_TEST_TIMER_ID (TimerP_ANY)
315 #define OSAL_TEST_TIMER_PERIOD (5000U)
316 #elif defined(SOC_K2H) || defined(SOC_K2K)
317 UT_Timer_Type_t timer_type = UT_Timer_TIMER64;
318 #define OSAL_TEST_TIMER_ID (8U)
319 #define OSAL_TEST_TIMER_PERIOD (5000U)
320 #elif defined(SOC_K2G)
321 UT_Timer_Type_t timer_type = UT_Timer_TIMER64;
322 #define OSAL_TEST_TIMER_ID (1U)
323 #define OSAL_TEST_TIMER_ID2 (2U)
324 #define OSAL_TEST_TIMER_PERIOD (5000U)
325 #elif defined(SOC_AM572x) || defined (SOC_AM574x)
326 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
327 #if defined (__ARM_ARCH_7A__)
328 #define OSAL_TEST_TIMER_ID (1U)
329 #define OSAL_TEST_TIMER_ID2 (9U)
330 #define OSAL_TEST_TIMER_PERIOD (5000U)
331 #elif defined (_TMS320C6X)
332 #define OSAL_TEST_TIMER_ID (4U)
333 #define OSAL_TEST_TIMER_ID2 (5U)
334 #define OSAL_TEST_TIMER_PERIOD (5000U)
335 #else
336 #define OSAL_TEST_TIMER_ID (8U)
337 #define OSAL_TEST_TIMER_ID2 (10U)
338 #define OSAL_TEST_TIMER_PERIOD (5000U)
339 #endif
340 #elif defined(SOC_AM571x)
341 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
342 #if defined (__ARM_ARCH_7A__)
343 #define OSAL_TEST_TIMER_ID (1U)
344 #define OSAL_TEST_TIMER_ID2 (9U)
345 #define OSAL_TEST_TIMER_PERIOD (5000U)
346 #elif defined (_TMS320C6X)
347 #define OSAL_TEST_TIMER_ID (4U)
348 #define OSAL_TEST_TIMER_ID2 (5U)
349 #define OSAL_TEST_TIMER_PERIOD (5000U)
350 #else
351 #define OSAL_TEST_TIMER_ID (8U)
352 #define OSAL_TEST_TIMER_ID2 (10U)
353 #define OSAL_TEST_TIMER_PERIOD (5000U)
354 #endif
355 #elif defined(SOC_OMAPL137) || defined (SOC_OMAPL138)
356 UT_Timer_Type_t timer_type = UT_Timer_TIMER64;
357 #define OSAL_TEST_TIMER_ID (1U)
358 #define OSAL_TEST_TIMER_PERIOD (5000U)
360 #elif defined(SOC_AM65XX)
361 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
362 #if defined (__TI_ARM_V7R4__)
363 #define OSAL_TEST_TIMER_ID (1U)
364 #define OSAL_TEST_TIMER_ID2 (2U)
365 #define OSAL_TEST_TIMER_PERIOD (5000U)
366 #else
367 #define OSAL_TEST_TIMER_ID (4U)
368 #define OSAL_TEST_TIMER_ID2 (5U)
369 #define OSAL_TEST_TIMER_PERIOD (5000U)
370 #endif
371 #elif defined(SOC_J721E)
372 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
373 #if defined (BUILD_MCU1_0)
374 #define OSAL_TEST_TIMER_ID (2U)
375 #define OSAL_TEST_TIMER_ID2 (3U)
376 #define OSAL_TEST_TIMER_PERIOD (5000U)
377 #elif defined (__TI_ARM_V7R4__)
378 #define OSAL_TEST_TIMER_ID (1U)
379 #define OSAL_TEST_TIMER_ID2 (2U)
380 #define OSAL_TEST_TIMER_PERIOD (5000U)
381 #elif defined (BUILD_C66X_1)
382 #define OSAL_TEST_TIMER_ID (2U)
383 #define OSAL_TEST_TIMER_ID2 (3U)
384 #define OSAL_TEST_TIMER_PERIOD (5000U)
385 #elif defined (BUILD_C66X_2)
386 #define OSAL_TEST_TIMER_ID (2U)
387 #define OSAL_TEST_TIMER_ID2 (3U)
388 #define OSAL_TEST_TIMER_PERIOD (5000U)
389 #elif defined (BUILD_C7X_1)
390 #define OSAL_TEST_TIMER_ID (1U)
391 #define OSAL_TEST_TIMER_ID2 (2U)
392 #define OSAL_TEST_TIMER_PERIOD (5000U)
393 #else
394 #define OSAL_TEST_TIMER_ID (2U)
395 #define OSAL_TEST_TIMER_ID2 (5U)
396 #define OSAL_TEST_TIMER_PERIOD (5000U)
397 #endif
398 #elif defined(SOC_J7200)
399 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
400 #if defined (__TI_ARM_V7R4__)
401 #define OSAL_TEST_TIMER_ID (1U)
402 #define OSAL_TEST_TIMER_ID2 (2U)
403 #define OSAL_TEST_TIMER_PERIOD (5000U)
404 #else
405 #define OSAL_TEST_TIMER_ID (2U)
406 #define OSAL_TEST_TIMER_ID2 (5U)
407 #define OSAL_TEST_TIMER_PERIOD (5000U)
408 #endif
409 #elif defined(SOC_AM64X)
410 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
411 #if defined(BUILD_MCU)
412 #define OSAL_TEST_TIMER_ID (1U)
413 #define OSAL_TEST_TIMER_ID2 (2U)
414 #define OSAL_TEST_TIMER_PERIOD (5000U)
415 #endif
416 #if defined(BUILD_MPU)
417 #define OSAL_TEST_TIMER_ID (4U)
418 #define OSAL_TEST_TIMER_ID2 (2U)
419 #define OSAL_TEST_TIMER_PERIOD (5000U)
420 #endif
421 #if defined(BUILD_M4F)
422 #define OSAL_TEST_TIMER_ID (1U)
423 #define OSAL_TEST_TIMER_ID2 (2U)
424 #define OSAL_TEST_TIMER_PERIOD (5000U)
425 #endif
426 #elif (defined(SOC_TPR12) || defined (SOC_AWR294X))
427 UT_Timer_Type_t timer_type = UT_Timer_RTITIMER;
428 #define OSAL_TEST_TIMER_ID (TimerP_ANY)
429 #if defined(SIM_BUILD)
430 #define OSAL_TEST_TIMER_PERIOD (500U)
431 #else
432 #define OSAL_TEST_TIMER_PERIOD (5000U)
433 #endif
434 #else
435 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
436 #if defined (__ARM_ARCH_7A__)
437 #define OSAL_TEST_TIMER_ID (1U)
438 #define OSAL_TEST_TIMER_PERIOD (5000U)
439 #elif defined (_TMS320C6X)
440 #define OSAL_TEST_TIMER_ID (4U)
441 #define OSAL_TEST_TIMER_PERIOD (5000U)
442 #else
443 #define OSAL_TEST_TIMER_ID (8U)
444 #define OSAL_TEST_TIMER_PERIOD (5000U)
445 #endif
446 #endif
448 #if defined(SIM_BUILD)
449 #define OSAL_GET_TIME_MAX_SAMPLES (10U)
450 #else
451 #define OSAL_GET_TIME_MAX_SAMPLES (20U)
452 #endif
453 volatile uint32_t timerIsrCount = 0;
454 volatile uint32_t timerIsr2Count = 0;
456 #if defined(SIM_BUILD)
457 #define OSAL_TIMER_TEST_MAX_INTERRUPTS (10U)
458 #else
459 #define OSAL_TIMER_TEST_MAX_INTERRUPTS (100U)
460 #endif
463 #if defined (ENABLE_GET_TIME_TEST)
464 uint64_t gTestTimeRd[OSAL_GET_TIME_MAX_SAMPLES];
465 #endif
467 void timerIsr(void *arg)
468 {
469 #if defined(BARE_METAL) && defined(__TI_ARM_V5__)
470 TimerP_ClearInterrupt(handle);
471 #endif
473 #if defined (ENABLE_GET_TIME_TEST)
474 if (timerIsrCount < OSAL_GET_TIME_MAX_SAMPLES)
475 {
476 gTestTimeRd[timerIsrCount] = TimerP_getTimeInUsecs();
477 }
478 #endif
479 timerIsrCount++;
480 }
483 #if TWO_TIMER_INTERRUPT_TEST
484 void timerIsr2(void *arg)
485 {
486 timerIsr2Count++;
487 }
488 #endif
490 /*
491 * ========= Osal Delay Test function =========
492 */
493 #if defined(SIM_BUILD)
494 #define OSAL_DELAY_TIME 1
495 #else
496 #define OSAL_DELAY_TIME 10
497 #endif
498 bool Osal_delay_test(void)
499 {
500 #if !defined(SOC_AM64X)
501 int32_t i;
502 /* This test assumes that Board init has been already
503 * called outside this function
504 */
505 /* Notice a '.' on terminal for every 1 second */
507 for (i=0; i<10;i++) {
508 #endif
509 Osal_delay(OSAL_DELAY_TIME);
510 OSAL_log(".");
511 #if !defined(SOC_AM64X)
512 }
513 #endif
514 OSAL_log("\n");
516 return(true);
517 }
519 #if defined (ENABLE_GET_TIME_TEST)
520 /*
521 * ========= Osal getTime Test function =========
522 */
523 bool Osal_getTime_test(void)
524 {
525 int32_t i;
526 bool retVal = true;
528 OSAL_log(" \n time read in micro seconds is \n ");
529 for (i = 0; i < OSAL_GET_TIME_MAX_SAMPLES; i++)
530 {
531 OSAL_log(" %d \n ", (uint32_t) gTestTimeRd[i]);
532 }
534 return(retVal);
535 }
536 #endif
538 /*
539 * ======== Timer test function ========
540 */
541 bool OSAL_timer_test()
542 {
543 TimerP_Params timerParams;
544 #if !defined (__TI_ARM_V5__)
545 /* Timer handle is defined as global for OMAPL13x ARM9 core since
546 it is required for clearing the interrupt from ISR */
547 TimerP_Handle handle;
548 #endif
550 #if TWO_TIMER_INTERRUPT_TEST
551 TimerP_Handle handle2;
552 #endif
553 TimerP_Status timerStatus;
554 Osal_HwAttrs hwAttrs;
556 #if defined(BARE_METAL) || defined(FREERTOS)
557 int32_t id = OSAL_TEST_TIMER_ID;
558 #else
559 int32_t id = TimerP_ANY;
560 #endif
562 #if defined(SOC_AM437x)
563 /* We can't use Timer_ANY for Sys BIOS as it allocates Timer0 which is
564 * firewalled on HS device and hence changing the Test Timer ID = 3 for
565 * both HS and GP parts
566 */
567 id = OSAL_TEST_TIMER_ID;
568 #endif
570 #if defined(SOC_J721E)
571 #if !defined(BARE_METAL)
572 #if defined(BUILD_C66X_1) || defined(BUILD_C66X_2) || defined(BUILD_C7X_1) || defined(BUILD_MCU1_0)
573 id = OSAL_TEST_TIMER_ID;
574 #endif
575 #endif
576 #endif
577 volatile int32_t i;
578 uint32_t prevCount, ctrlBitmap = OSAL_HWATTR_SET_OSALDELAY_TIMER_BASE ;
579 bool ret = true;
580 int32_t osal_ret;
582 #if (defined (SOC_AM437x) || defined (SOC_AM335x))
583 *(unsigned int*)CM_DPLL_CLKSEL_TIMER3_CLK = 0x1; /* high frequency input clock */
585 // enable the TIMER
586 *(unsigned int*)CM_PER_TIMER3_CLKCTRL = 0x2; /* Module is explicitly enabled */
587 #endif
589 /* Set the timer base for the osal delay */
590 Osal_getHwAttrs(&hwAttrs);
592 #if defined (SOC_AM437x)
593 hwAttrs.osalDelayTimerBaseAddr = (uintptr_t) 0x48040000U; /* DMTIMER2 */
594 #endif
596 #if defined (OSAL_TEST_CPU_FREQ_KHZ)
597 hwAttrs.cpuFreqKHz = OSAL_TEST_CPU_FREQ_KHZ;
598 ctrlBitmap |= OSAL_HWATTR_SET_CPU_FREQ;
599 #endif
601 /* This API should return osal_OK for AM3/AM4 and return unsupported for other Socs */
602 osal_ret = Osal_setHwAttrs(ctrlBitmap, &hwAttrs);
604 #if defined (SOC_AM437x) || defined (SOC_AM335x)
605 if (osal_ret == osal_OK) {
606 ret = true;
607 }
608 else {
609 ret = false;
610 }
611 #else
612 if ((osal_ret == osal_UNSUPPORTED) ||
613 (osal_ret == osal_OK)) {
614 ret = true;
615 }
616 else {
617 ret = false;
618 }
619 #endif /* (SOC_AM437x) || defined (SOC_AM335x) */
621 TimerP_Params_init(&timerParams);
622 timerParams.runMode = TimerP_RunMode_CONTINUOUS;
623 timerParams.startMode = TimerP_StartMode_USER;
624 timerParams.periodType = TimerP_PeriodType_MICROSECS;
625 timerParams.period = OSAL_TEST_TIMER_PERIOD;
627 #if defined(SOC_J721E) || defined(SOC_J7200)
628 #if defined(BUILD_C66X_1)
629 /* the Eevnt 21 is used for DMTimer0 by SYS/BIOS by default, so we need to use a different one here for DMTimer2 */
630 timerParams.eventId = 22;
631 /* the Interrupt 14 is used for DMTimer0 by SYS/BIOS by default, so we need to use a different one here for DMTimer2 */
632 timerParams.intNum = 15;
633 OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id);
634 #endif
635 #if defined(BUILD_C66X_2)
636 /* the Eevnt 20 is used for DMTimer0 by SYS/BIOS by default, so we need to use a different one here for DMTimer2 */
637 timerParams.eventId = 22;
638 /* the Interrupt 14 is used for DMTimer0 by SYS/BIOS by default, so we need to use a different one here for DMTimer2 */
639 timerParams.intNum = 15;
640 #endif
642 #if defined(BUILD_C7X_1)
643 timerParams.intNum = 15;
644 OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id);
645 #endif
646 #endif
648 #if !defined(SOC_J721E) || !defined(SOC_J7200)
649 #if defined(_TMS320C6X)
650 #if defined(SOC_TPR12)
651 timerParams.intNum = 16;
652 #else
653 timerParams.intNum = 15;
654 #endif
655 OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id);
656 #endif
657 #endif
659 if (timer_type == UT_Timer_TIMER64)
660 {
661 timerParams.timerMode = TimerP_Timer64Mode_UNCHAINED;
662 timerParams.timerHalf = TimerP_Timer64Half_LOWER;
663 }
664 handle = TimerP_create(id, (TimerP_Fxn)&timerIsr, &timerParams);
666 /* don't expect the handle to be null */
667 if (handle == NULL_PTR)
668 {
669 OSAL_log("\n Timer Create error \n");
670 ret = false;
671 }
673 #if defined(ENABLE_GET_TIME_TEST)
674 TimerP_getTimeInUsecs();
675 #endif
677 #if TWO_TIMER_INTERRUPT_TEST
679 #if (defined(_TMS320C6X) && (!defined(SOC_J721E) ))
680 timerParams.intNum = 14;
681 #endif
683 if (ret == true) {
684 handle2 = TimerP_create(OSAL_TEST_TIMER_ID2, (TimerP_Fxn)&timerIsr2, &timerParams);
685 /* don't expect the handle to be null */
686 if (handle2 == NULL_PTR)
687 {
688 OSAL_log("\n Timer Create error for handle2 \n");
689 ret = false;
690 }
691 }
692 #endif
694 if (ret == true)
695 {
696 timerIsrCount = 0U;
697 timerStatus = TimerP_start(handle);
699 if (timerStatus != TimerP_OK) {
700 OSAL_log("Err: Coult not start the timer %d \n", id);
701 ret = false;
702 }
704 #if TWO_TIMER_INTERRUPT_TEST
705 timerIsr2Count = 0U;
706 timerStatus = TimerP_start(handle2);
708 if (timerStatus != TimerP_OK) {
709 OSAL_log("Err: Coult not start the timer %d \n", id + 1);
710 ret = false;
711 }
713 while (1)
714 {
715 if (timerIsr2Count >= OSAL_TIMER_TEST_MAX_INTERRUPTS) {
716 timerStatus = TimerP_stop(handle2);
717 if (timerStatus != TimerP_OK) {
718 OSAL_log("Err: Coult not stop the timer %d \n", id);
719 ret = false;
720 }
721 break;
722 }
723 }
724 #endif
726 while (1)
727 {
728 if (timerIsrCount >= OSAL_TIMER_TEST_MAX_INTERRUPTS) {
729 timerStatus = TimerP_stop(handle);
730 if (timerStatus != TimerP_OK) {
731 OSAL_log("Err: Coult not stop the timer %d \n", id);
732 ret = false;
733 }
735 break;
736 }
737 }
739 /* Latch the ISR count after the timer stops */
740 prevCount = (timerIsrCount);
742 /* Give some time for all pending interrupts to be processed */
743 for(i = 0; i < 1000; i++)
744 {
745 asm (" nop ");
746 }
748 /* Now check if timer ISR gets kicked in
749 * timer ISR should not be kicked in */
750 if (ret == true)
751 {
752 for (i = 0; i < 50000; i++);
754 if (prevCount != timerIsrCount)
755 {
756 OSAL_log(" Error: Timer appears to be not stopped via OSAL calls, val1 = %u and val2 = %u \n ", prevCount, timerIsrCount);
757 ret = false;
758 }
759 else
760 {
761 OSAL_log(" TimerTestLog: got %u ticks from timer id = %d \n", timerIsrCount, id);
762 #if TWO_TIMER_INTERRUPT_TEST
763 OSAL_log(" TimerTestLog: got %u ticks from timer id = %d \n", timerIsr2Count, id+1);
764 #endif
765 }
766 }
767 }
769 if (handle != NULL_PTR)
770 {
771 if (TimerP_delete(handle) != TimerP_OK)
772 {
773 ret = false;
774 }
775 }
777 for (i = 0; i < (log2(TIMERP_AVAILABLE_MASK+1U)+1U); i++)
778 {
779 TimerP_Params_init(&timerParams);
780 timerParams.runMode = TimerP_RunMode_CONTINUOUS;
781 timerParams.startMode = TimerP_StartMode_USER;
782 timerParams.periodType = TimerP_PeriodType_MICROSECS;
783 timerParams.period = OSAL_TEST_TIMER_PERIOD;
784 handle = TimerP_create(TimerP_ANY, NULL, &timerParams);
785 /* don't expect the handle to be null */
786 if (handle == NULL_PTR)
787 {
788 OSAL_log("\n Error: Timer Create failed for %d th time \n", i);
789 ret = false;
790 }
791 if (TimerP_delete(handle) != TimerP_OK)
792 {
793 OSAL_log("\n Error: Timer Delete failed for %d th time \n", i);
794 ret = false;
795 }
796 }
797 return (ret);
798 }
800 /*
801 * ======== Clock test function ========
802 */
803 bool OSAL_clock_test()
804 {
805 return true;
806 }
808 #ifdef MANUAL_CACHE_TEST
810 #if defined (__ARM_ARCH_7A__)
811 #include <ti/csl/csl_a15.h>
812 #include <ti/csl/csl_armGicAux.h>
813 #elif defined (_TMS320C6X)
814 #include <ti/csl/csl_cacheAux.h>
815 #endif
817 #if defined (SOC_AM437x) || defined(SOC_AM335x)
818 #include <ti/starterware/include/chipdb.h>
819 #include <ti/starterware/include/armv7a/pl310.h>
820 #include <ti/starterware/include/armv7a/pl310_config.h>
821 #endif
823 #define BUF_LEN 256
824 #define LOCAL_CPU_WRITE_PATTERN_1 0xA1A1A1A1
825 #define LOCAL_CPU_WRITE_PATTERN_2 0xA2A2A2A2
826 #define LOCAL_CPU_WRITE_PATTERN_3 0xA3A3A3A3
828 #define ALTERNATE_CPU_WRITE_PATTERN_1 0xB1B1B1B1
829 #define ALTERNATE_CPU_WRITE_PATTERN_2 0xB2B2B2B2
830 #define ALTERNATE_CPU_WRITE_PATTERN_3 0xB3B3B3B3
832 #if defined (__ARM_ARCH_7A__)
833 uint32_t ddr_buf[BUF_LEN] __attribute__((aligned(256))); // GCC way of aligning
834 #elif defined (_TMS320C6X)
835 #pragma DATA_SECTION(ddr_buf,".cachetest_ddrbuf")
836 #pragma DATA_ALIGN(ddr_buf,256)
837 uint32_t ddr_buf[BUF_LEN];
838 #elif defined(__TI_ARM_V7M4__)
839 uint32_t ddr_buf[BUF_LEN];
840 #endif
841 void OSAL_cache_test_fill_buf(uint32_t *buf, int len,uint32_t pattern) {
842 int i;
843 for(i=0;i<len;i++) {
844 buf[i]=pattern;
845 }
846 }
847 /* Returns FALSE if all the buffer is not 'pattern'. This will read the contents though */
848 bool OSAL_cache_test_check_buf(uint32_t *buf, int len,uint32_t pattern) {
849 int i;
850 bool match=TRUE;
851 for(i=0;i<len;i++) {
852 if(buf[i]!=pattern) {
853 match=FALSE;
854 }
855 }
856 return(match);
857 }
859 #if defined (SOC_AM572x) || defined (SOC_AM574x)
860 bool OSAL_cache_test()
861 {
863 bool match,res=TRUE;
864 #if defined (__ARM_ARCH_7A__)
865 CSL_a15EnableCache();
866 #elif defined(_TMS320C6X)
867 /* Enable for most of the DDR3 memory , especially the first two MAR regions where ddr_buf will reside */
868 CACHE_enableCaching(128);
869 CACHE_enableCaching(129);
870 CACHE_setL1DSize(CACHE_L1_4KCACHE);
871 CACHE_setL2Size(CACHE_1024KCACHE);
872 #endif
873 OSAL_log("This manual cache test is a CCS based test. Please do the following\n");
874 OSAL_log("1) On the local CPU open two memory windows for the address 0x%x\n: One CPU view and One Physical memory view\n",&ddr_buf[0]);
875 OSAL_log("2) Connect an alternate CPU (for example if local cpu is A15, open a c66/m4 as the alternate CPU\n");
876 OSAL_log("3) On the alternate CPU ( preferably a different window through (CCS->New Window)) Open the address 0x%x\n with a physical memory view\n",&ddr_buf[0]);
878 OSAL_log("\n**** Forcing a read to get the buffer cached() ******\n");
879 OSAL_cache_test_check_buf(ddr_buf,BUF_LEN,0); /* Checking for dummy pattern, just to force the cache read */
881 OSAL_log("\n**** Testing Cache_Invalidate() ******\n");
883 OSAL_log("\nWriting 0x%x local ddr memory\n",LOCAL_CPU_WRITE_PATTERN_1);
884 /************************ TEST for CacheP_Inv() *********************/
885 /* A15- Write LOCAL_CPU_WRITE_PATTERN_1 in to ddr_buf[0] */
886 OSAL_cache_test_fill_buf(ddr_buf,BUF_LEN,LOCAL_CPU_WRITE_PATTERN_1);
888 /* Check in the alternate cpu window (m4/c66x/a15) if it can see it (Physical memory). It shouldnt if cache is enabled. */
889 OSAL_log("\nCheck in the alternate cpu window (m4/c66x/a15) if it can see it (Physical memory). It shouldn't appear as it is still in cache\n");
891 OSAL_log("\nInvalidating cache.\n");
892 /* Now OSAL_CacheInv() - Invalidates and writes back cache() */
893 CacheP_Inv(ddr_buf,BUF_LEN*sizeof(uint32_t));
895 OSAL_log("\nCheck in alternate cpu window (m4/c66x/a15) if it can see it (Physical memory). For A15 it should (Invalidate also writes back for A15), for others it should not \n");
897 OSAL_log("\nNow write(%d 32-bit words) of pattern 0x%x on the alternate CPU physical memory window (a15/m4/c66x) \n",BUF_LEN,ALTERNATE_CPU_WRITE_PATTERN_1);
898 OSAL_log("\nCheck if this pattern 0x%x has made it to the physical memory view of this cpu.It should. \n",ALTERNATE_CPU_WRITE_PATTERN_1);
900 #if defined(__ARM_ARCH_7A__)
901 /* The below invalidate test is to account for ARM prefetching. On A15 Cache Inv writes back too. To see any changes AFTER the DDR was
902 externally modified, a Cache Invalidate is required */
903 CacheP_Inv(ddr_buf,BUF_LEN*sizeof(uint32_t));
904 #endif
905 OSAL_log("\nChecking if local CPU read fetches the 0x%x value updated by the alternate cpu core\n",ALTERNATE_CPU_WRITE_PATTERN_1);
906 /* Now read the value on A15 now */
907 match=OSAL_cache_test_check_buf(ddr_buf,BUF_LEN,ALTERNATE_CPU_WRITE_PATTERN_1);
908 if(match==TRUE) {
909 OSAL_log("\nPattern matched. OSAL_CacheInv() Test passed\n");
910 } else {
911 OSAL_log("\n OSAL_CacheInv() Test failed\n");
912 }
914 /************************ TEST for CacheP_wb() *********************/
915 OSAL_log("\n**** Testing Cache_WriteBack() ******\n");
917 OSAL_log("\nWriting 0x%x local ddr memory\n",LOCAL_CPU_WRITE_PATTERN_2);
918 /* local cpu- Write LOCAL_CPU_WRITE_PATTERN_2 in to ddr_buf[0] */
919 OSAL_cache_test_fill_buf(ddr_buf,BUF_LEN,LOCAL_CPU_WRITE_PATTERN_2);
921 OSAL_log("\nCheck in the alternate cpu window (m4/c66x/a15) if the pattern 0x%x can be seen it (Physical memory). It shouldn't appear as it is still in cache\n",LOCAL_CPU_WRITE_PATTERN_2);
923 OSAL_log("\nWriting back cache.\n");
924 /* Now OSAL_CacheWb() - Writes back cache() */
925 CacheP_wb(ddr_buf,BUF_LEN*sizeof(uint32_t));
927 /* Check in DSP window if it can see it (Physical memory). It should now. */
928 OSAL_log("\nCheck in alternate cpu window (m4/c66x/a15) and verify that the 0x%x is seen in Physical memory\n",LOCAL_CPU_WRITE_PATTERN_2);
930 /* If so, write back portion is tested. */
931 OSAL_log("\nNow write the pattern 0x%x on the alternate CPU physical memory window (a15/m4/c66x) \n",ALTERNATE_CPU_WRITE_PATTERN_2);
932 /* Since, on this local cpu, we just wrote back cache() only, and not invalidated, the ALTERNATE_CPU_WRITE_PATTERN_2 wont be seen in the local cpu's cached memory
933 Read Variable on A15 to ensure CPU Read(). The value should be the old LOCAL_CPU_WRITE_PATTERN_2.. and NOT the ALTERNATE_CPU_WRITE_PATTERN_2.. which the alternate CPU wrote. */
934 match=OSAL_cache_test_check_buf(ddr_buf,BUF_LEN,LOCAL_CPU_WRITE_PATTERN_2);
935 if(match==TRUE) {
936 OSAL_log("\nPattern matched. OSAL_Cache_Writeback() Test passed\n");
937 } else {
938 OSAL_log("\n OSAL_Cache_Writeback() Test failed\n");
939 }
941 /************************ TEST for CacheP_wbInv() *********************/
942 OSAL_log("\n**** Testing Cache_WriteBack_Invalidate() ******\n");
944 OSAL_log("\nWriting 0x%x local ddr memory\n",LOCAL_CPU_WRITE_PATTERN_3);
946 /* local cpu- Write LOCAL_CPU_WRITE_PATTERN_3 in to ddr_buf[0] */
947 OSAL_cache_test_fill_buf(ddr_buf,BUF_LEN,LOCAL_CPU_WRITE_PATTERN_3);
949 OSAL_log("\nCheck in the alternate cpu window (m4/c66x/a15) if the pattern 0x%x can be seen it (Physical memory). It shouldn't appear as it is still in cache\n",LOCAL_CPU_WRITE_PATTERN_3);
951 OSAL_log("\nWriting back cache and invalidating it.\n");
953 /* Now OSAL_CacheWbInv() - Writes back cache and invalidate() */
954 CacheP_wbInv(ddr_buf,BUF_LEN*sizeof(uint32_t));
956 /* Check in DSP window if it can see it (Physical memory). It should now. */
957 OSAL_log("\nCheck in alternate cpu window (m4/c66x/a15) and verify that the 0x%x is seen in Physical memory. If not it is a failure \n",LOCAL_CPU_WRITE_PATTERN_3);
960 OSAL_log("\nNow write the pattern 0x%x on the alternate CPU physical memory window (a15/m4/c66x) \n",ALTERNATE_CPU_WRITE_PATTERN_3);
962 #if defined(__ARM_ARCH_7A__)
963 /* This is due to ARM prefetching */
964 CacheP_Inv(ddr_buf,BUF_LEN*sizeof(uint32_t));
965 #endif
967 /* Since, on local cpu, we not only wrote back cache but also invalidated it,the local cpu should be able the alternate pattern now */
968 match=OSAL_cache_test_check_buf(ddr_buf,BUF_LEN,ALTERNATE_CPU_WRITE_PATTERN_3);
969 if(match==TRUE) {
970 OSAL_log("\nPattern matched. OSAL_Cache_WritebackInvalidate() Test passed\n");
971 } else {
972 OSAL_log("\nOSAL_Cache_WritebackInvalidate() Test failed\n");
973 }
975 return(res);
976 }
977 #endif /* SOC_AM572x || SOC_AM574x */
978 #endif /* MANUAL_CACHE_TEST */
980 /*
981 * ======== Extended memory block test function ========
982 * This test aims at testing the create and delete functions that
983 * are enhanced to support extended memory blocks for SemaphoreP and HwiP
984 */
985 #define OSAL_TEST_NUM_EXT_SEMAPHORES (1U)
986 #define OSAL_TEST_NUM_EXT_HWIPS (1U)
988 #if defined (BARE_METAL)
989 #define SEMP_BLOCK_SIZE (OSAL_TEST_NUM_EXT_SEMAPHORES * OSAL_NONOS_SEMAPHOREP_SIZE_BYTES)
990 #define HWIP_BLOCK_SIZE (OSAL_TEST_NUM_EXT_HWIPS * OSAL_NONOS_HWIP_SIZE_BYTES)
991 uint8_t semPMemBlock[SEMP_BLOCK_SIZE];
992 uint8_t hwiPMemBlock[HWIP_BLOCK_SIZE];
993 #else
994 #define SEMP_BLOCK_SIZE (OSAL_TEST_NUM_EXT_SEMAPHORES * OSAL_TIRTOS_SEMAPHOREP_SIZE_BYTES)
995 #define HWIP_BLOCK_SIZE (OSAL_TEST_NUM_EXT_HWIPS * OSAL_TIRTOS_HWIP_SIZE_BYTES)
996 uint8_t semPMemBlock[SEMP_BLOCK_SIZE];
997 uint8_t hwiPMemBlock[HWIP_BLOCK_SIZE];
998 #endif
1000 static void myIsr(void)
1001 {
1002 }
1004 bool OSAL_ExtBlock_test(void)
1005 {
1006 SemaphoreP_Params semParams;
1007 HwiP_Params hwiParams;
1008 Osal_HwAttrs hwAttrs;
1009 int32_t osal_ret;
1010 uint32_t ctrlBitMap = ( OSAL_HWATTR_SET_SEMP_EXT_BASE |
1011 OSAL_HWATTR_SET_HWIP_EXT_BASE);
1012 SemaphoreP_Handle semHandle;
1013 HwiP_Handle hwiHandle;
1015 /* Set the timer base for the osal delay */
1016 osal_ret = Osal_getHwAttrs(&hwAttrs);
1017 if (osal_ret != osal_OK)
1018 {
1019 return (false);
1020 }
1022 /* This API should return osal_OK for AM3/AM4 and return unsupported for other Socs */
1023 hwAttrs.extSemaphorePBlock.base = (uintptr_t) &semPMemBlock[0];
1024 hwAttrs.extSemaphorePBlock.size = SEMP_BLOCK_SIZE;
1025 hwAttrs.extHwiPBlock.size = HWIP_BLOCK_SIZE;
1026 hwAttrs.extHwiPBlock.base = (uintptr_t) &hwiPMemBlock[0];
1027 osal_ret = Osal_setHwAttrs(ctrlBitMap, &hwAttrs);
1028 if (osal_ret != osal_OK)
1029 {
1030 return (false);
1031 }
1033 /* Default parameter initialization */
1034 SemaphoreP_Params_init(&semParams);
1036 /* create the semaphore block */
1037 semHandle = SemaphoreP_create(0, &semParams);
1038 if (semHandle == (SemaphoreP_Handle) NULL_PTR)
1039 {
1040 return (false);
1041 }
1043 /* Verify the block created is in the extended memory block range */
1044 if (semHandle != (SemaphoreP_Handle) &semPMemBlock[0])
1045 {
1046 return(false);
1047 }
1049 /* delete the semaphore block */
1050 osal_ret = SemaphoreP_delete(semHandle);
1051 if (osal_ret != (SemaphoreP_Status) SemaphoreP_OK)
1052 {
1053 return (false);
1054 }
1057 /* Default parameter initialization */
1058 HwiP_Params_init(&hwiParams);
1060 /* create the hwi block */
1061 hwiHandle = HwiP_create(8, (HwiP_Fxn)myIsr, &hwiParams);
1062 if (hwiHandle == (HwiP_Handle) NULL_PTR)
1063 {
1064 return (false);
1065 }
1067 /* Verify the block created is in the extended memory block range */
1068 if (hwiHandle != (HwiP_Handle) &hwiPMemBlock[0])
1069 {
1070 return(false);
1071 }
1073 /* delete the hwi block */
1074 osal_ret = HwiP_delete(hwiHandle);
1075 if (osal_ret != (HwiP_Status) HwiP_OK)
1076 {
1077 return (false);
1078 }
1080 /* Clear the extended block base for next tests */
1081 /* This API should return osal_OK for AM3/AM4 and return unsupported for other Socs */
1082 hwAttrs.extSemaphorePBlock.base = (uintptr_t) NULL_PTR;
1083 hwAttrs.extSemaphorePBlock.size = 0;
1084 hwAttrs.extHwiPBlock.size = 0;
1085 hwAttrs.extHwiPBlock.base = (uintptr_t) NULL_PTR;
1086 osal_ret = Osal_setHwAttrs(ctrlBitMap, &hwAttrs);
1087 if (osal_ret != osal_OK)
1088 {
1089 return (false);
1090 }
1091 return(true);
1093 }
1096 /*
1097 * ======== Semaphore test function ========
1098 */
1099 bool OSAL_semaphore_test()
1100 {
1101 SemaphoreP_Params semParams;
1102 SemaphoreP_Handle handle1, handle2;
1104 SemaphoreP_Params_init(&semParams);
1106 /* Test 1: counting mode, no timeout */
1107 semParams.mode = SemaphoreP_Mode_COUNTING;
1108 handle1 = SemaphoreP_create(0, &semParams);
1109 if (handle1 == NULL_PTR)
1110 {
1111 return false;
1112 }
1113 if (SemaphoreP_post(handle1) != SemaphoreP_OK)
1114 {
1115 return false;
1116 }
1117 if (SemaphoreP_pend(handle1, 0) != SemaphoreP_OK)
1118 {
1119 return false;
1120 }
1122 /* Test 2: binary mode, with timeout */
1123 semParams.mode = SemaphoreP_Mode_BINARY;
1124 handle2 = SemaphoreP_create(1, &semParams);
1125 if (handle2 == NULL_PTR)
1126 {
1127 return false;
1128 }
1129 if (SemaphoreP_pend(handle2, 0) != SemaphoreP_OK)
1130 {
1131 return false;
1132 }
1133 if (SemaphoreP_pend(handle2, 10) != SemaphoreP_TIMEOUT)
1134 {
1135 return false;
1136 }
1138 if (SemaphoreP_delete(handle1) != SemaphoreP_OK)
1139 {
1140 return false;
1141 }
1143 if (SemaphoreP_delete(handle2) != SemaphoreP_OK)
1144 {
1145 return false;
1146 }
1148 return true;
1149 }
1151 #if !(defined(BARE_METAL) || defined(FREERTOS))
1153 /*
1154 * ======== Queue test function ========
1155 */
1156 typedef struct Test_Queue_Buf_s
1157 {
1158 Osal_Queue_Elem lnk;
1159 uint32_t index;
1160 uint8_t* pkt;
1162 } Test_Queue_Buf;
1164 bool OSAL_queue_test()
1165 {
1166 Osal_Queue_Elem queueList;
1167 Osal_Queue_Handle handle;
1168 Test_Queue_Buf buf[10], *pBuf;
1169 int i;
1171 Osal_Queue_construct((void *)&queueList, (void *)NULL);
1172 handle = Osal_Queue_handle((void *)&queueList);
1174 if (handle == NULL_PTR)
1175 {
1176 OSAL_log("Failed to create queue \n");
1177 return false;
1178 }
1180 for (i = 0; i < 10; i++)
1181 {
1182 buf[i].index = (uint32_t)i;
1183 buf[i].pkt = NULL;
1184 }
1186 /* Test 1: queue push/pop test */
1187 for (i = 0; i < 10; i++)
1188 {
1189 Osal_Queue_put(handle, (Osal_Queue_Elem *)&buf[i]);
1190 }
1192 for (i = 0; i < 10; i++)
1193 {
1194 pBuf = (Test_Queue_Buf *)Osal_Queue_get(handle);
1196 if (pBuf == NULL_PTR)
1197 {
1198 OSAL_log("Failed to pop queue element %d \n", i);
1199 return false;
1200 }
1202 if (pBuf->index != i)
1203 {
1204 OSAL_log("Pop element %d, but expect %d \n", pBuf->index, i);
1205 return false;
1207 }
1208 }
1210 /* Test 2: queue empty test */
1211 if (!Osal_Queue_empty(handle))
1212 {
1213 OSAL_log("Empty queue check failed\n");
1214 return false;
1215 }
1217 pBuf = (Test_Queue_Buf *)Osal_Queue_get(handle);
1219 if (pBuf != (Test_Queue_Buf *)&queueList)
1220 {
1221 OSAL_log("Queue is still not empry with element %p handle %p queue struct %p\n", pBuf, handle, &queueList);
1222 return false;
1223 }
1225 return true;
1226 }
1228 volatile bool gFlagSwi;
1229 void mySwiFxn(uintptr_t arg0, uintptr_t arg1)
1230 {
1231 gFlagSwi = 1U;
1232 }
1234 bool OSAL_swi_test()
1235 {
1236 SwiP_Handle handle;
1237 SwiP_Params swiParams;
1238 SwiP_Status status;
1239 bool retVal = true;
1241 SwiP_Params_init(&swiParams);
1242 handle = SwiP_create((SwiP_Fxn)&mySwiFxn, &swiParams);
1243 if (handle == NULL_PTR)
1244 {
1245 OSAL_log("Failed to create software interrupt \n");
1246 retVal = false;
1247 }
1249 if (retVal == true)
1250 {
1251 gFlagSwi = 0;
1252 status = SwiP_post(handle);
1253 if (status != SwiP_OK)
1254 {
1255 OSAL_log("Failed to post software interrupt \n");
1256 retVal = false;
1257 }
1258 }
1260 if (retVal == true)
1261 {
1262 gTestlocalTimeout = 0x300000U;
1263 while (gTestlocalTimeout != 0U)
1264 {
1265 gTestlocalTimeout--;
1266 if (gFlagSwi)
1267 {
1268 gFlagSwi = 0;
1269 retVal = true;
1270 break;
1271 }
1272 }
1274 if (gTestlocalTimeout == 0)
1275 {
1276 OSAL_log("Failed to get software interrupt \n");
1277 retVal = false;
1278 }
1279 }
1281 if (retVal == true)
1282 {
1283 status = SwiP_delete(&handle);
1284 if (status != SwiP_OK)
1285 {
1286 OSAL_log("Failed to delete software interrupt \n");
1287 retVal = false;
1288 }
1289 }
1291 return (retVal);
1292 }
1293 #endif
1295 #if ENABLE_DEBUG_LOG_TEST
1296 bool OSAL_log_test()
1297 {
1298 bool retVal = true;
1300 OSAL_log("BegugP Log test starts!\n");
1302 DebugP_log0 ("debugP_log0 run successfully\n");
1303 DebugP_log1 ("debugP_log1 run with %u argument uccessfully\n", 1U);
1304 DebugP_log2 ("debugP_log2 run with %u arguments (2, %d) successfully\n", 2U, 2);
1305 DebugP_log3 ("debugP_log3 run with %u arguments (3, %d, %d) successfully\n", 3U, 3, 3);
1306 DebugP_log4 ("debugP_log4 run with %u arguments (4, %d, %d, 0x%x) successfully\n", 4U, 4, 4, 64);
1308 return (retVal);
1309 }
1310 #endif
1312 #ifndef BARE_METAL
1313 #if defined(FREERTOS)
1315 #else
1316 #include <ti/sysbios/knl/Clock.h>
1317 #endif
1318 #ifndef SIM_BUILD
1319 #define OSAL_TASKP_TEST_ITERATION (10U)
1320 #if defined(FREERTOS)
1321 #define OSAL_TASKP_TEST_1MS (1U)
1322 #else
1323 #define OSAL_TASKP_TEST_1MS (1000U)
1324 #endif
1325 #define OSAL_TASKP_TEST_TICKS (1000U)
1326 #else
1327 #define OSAL_TASKP_TEST_ITERATION (2U)
1328 #define OSAL_TASKP_TEST_1MS (10U)
1329 #define OSAL_TASKP_TEST_TICKS (10U)
1330 #endif
1332 uint64_t OSAL_get_ticks()
1333 {
1334 uint64_t ticks;
1335 #if defined(FREERTOS)
1336 ticks = (uint64_t)uiPortGetRunTimeCounterValue();
1337 #else
1338 ticks = (uint64_t)Clock_getTicks();
1339 #endif
1340 return ticks;
1341 }
1343 bool OSAL_task_sleep_test(void)
1344 {
1345 int32_t i;
1346 uint64_t start_time_nticks, end_time_nticks;
1347 uint32_t diff_nticks, diff_tout;
1349 /* nTicks in OSAL is 1000 ticks per milli seconds
1350 * hence the task sleep = 1000 milliseconds should
1351 * provide the same sleep time as in TaskP_sleep(nTicks = 1000)
1352 */
1353 start_time_nticks = OSAL_get_ticks();
1355 for (i=0; i < OSAL_TASKP_TEST_ITERATION; i++)
1356 {
1357 TaskP_sleep(OSAL_TASKP_TEST_TICKS);
1358 }
1359 end_time_nticks = OSAL_get_ticks();
1360 diff_nticks = (uint32_t)(end_time_nticks - start_time_nticks);
1362 start_time_nticks = OSAL_get_ticks();
1364 for (i=0; i < OSAL_TASKP_TEST_ITERATION; i++)
1365 {
1366 TaskP_sleepInMsecs(OSAL_TASKP_TEST_1MS);
1367 }
1368 end_time_nticks = OSAL_get_ticks();
1369 diff_tout = (uint32_t)(end_time_nticks - start_time_nticks);
1371 OSAL_log(" \n \
1372 diff_nticks = %d \n \
1373 diff_tout = %d \n ", diff_nticks, diff_tout);
1374 #if !defined(FREERTOS)
1375 OSAL_log(" Clock_tickPeriod = %d \n \
1376 Clock_tickSource = %d ", Clock_tickPeriod, Clock_tickSource);
1377 #endif
1379 return (true);
1381 }
1382 #endif
1384 #if defined(FREERTOS)
1385 bool OSAL_mempry_test()
1386 {
1387 void *memPtr1, *memPtr2, *memPtr[5];
1388 uint32_t align;
1389 bool retVal = true;
1390 uint32_t i;
1392 /* Test1: Allocate 16 bytes aligned memory. */
1393 align = 16;
1394 memPtr1 = MemoryP_ctrlAlloc(100, align);
1395 if (memPtr1 != NULL)
1396 {
1397 /* Check if teh allocated mempry is 16 bytes aligned. */
1398 if ((uintptr_t)memPtr1 & (align - 1)!= 0)
1399 {
1400 retVal = false;
1401 }
1402 }
1403 else
1404 {
1405 retVal = false;
1406 }
1408 /* Test2: Allocate 64 bytes aligned memory. */
1409 align = 64;
1410 memPtr2 = MemoryP_ctrlAlloc(200, align);
1411 if (memPtr2 != NULL)
1412 {
1413 /* Check if teh allocated mempry is 16 bytes aligned. */
1414 if ((uintptr_t)memPtr2 & (align - 1)!= 0)
1415 {
1416 retVal = false;
1417 }
1418 }
1419 else
1420 {
1421 retVal = false;
1422 }
1424 if (memPtr1 != NULL)
1425 {
1426 MemoryP_ctrlFree(memPtr1, 100);
1427 }
1428 if (memPtr2 != NULL)
1429 {
1430 MemoryP_ctrlFree(memPtr2, 200);
1431 }
1433 /* Test2: check memory leak
1434 * multiple iteration of alloc and free to give same mem pointer.
1435 */
1436 for (i=0; i<5; i++)
1437 {
1438 align = 64;
1439 memPtr[i] = MemoryP_ctrlAlloc(200, align);
1440 MemoryP_ctrlFree(memPtr[i], 200);
1441 }
1442 for (i=1; i<5; i++)
1443 {
1444 if (memPtr[i] != memPtr[i-1])
1445 {
1446 retVal = false;
1447 break;
1448 }
1449 }
1450 return retVal;
1451 }
1452 #endif
1454 /*
1455 * ======== main test function ========
1456 */
1457 #if defined(BARE_METAL)
1458 void osal_test()
1459 #elif defined(FREERTOS)
1460 void osal_test(void *arg0, void *arg1)
1461 #else
1462 void osal_test(UArg arg0, UArg arg1)
1463 #endif
1464 {
1465 bool testFail = false;
1466 Osal_StaticMemStatus pMemStats;
1468 Board_initOSAL();
1470 #ifdef BUILD_C7X_1
1471 Osal_appC7xPreInit();
1472 C7x_ConfigureTimerOutput();
1473 #endif
1475 #ifdef BUILD_M4F
1476 OSAL_log("\n M4 test \n");
1477 #endif
1479 #if defined(BUILD_C66X_1) || defined(BUILD_C66X_2)
1480 /* To set C66 timer interrupts on J7ES VLAB */
1481 C66xTimerInterruptInit();
1482 #endif
1484 OSAL_log(" OSAL Test Starting...\n Takes about 30 seconds ...\n");
1486 #if defined(BARE_METAL)
1487 /* No TASKP test for BAREmetal */
1488 #else
1489 /* TASK Sleep APIs test for RTOS */
1490 if (OSAL_task_sleep_test() == true)
1491 {
1492 OSAL_log("\n TaskP tests have passed. \n");
1493 }
1494 else
1495 {
1496 OSAL_log("\n TaskP tests have failed. \n");
1497 }
1498 #endif
1500 if(OSAL_hwi_test() == true)
1501 {
1502 OSAL_log("\n HWI tests have passed. \n");
1503 }
1504 else
1505 {
1506 OSAL_log("\n HWI tests have failed. \n");
1507 testFail = true;
1508 }
1510 #ifdef ENABLE_TIMER_TEST
1511 if(OSAL_timer_test() == true)
1512 {
1513 OSAL_log("\n Timer tests have passed. \n");
1514 }
1515 else
1516 {
1517 OSAL_log("\n Timer tests have failed. \n");
1518 testFail = true;
1519 }
1520 #endif
1522 /* The test does not support below SoCs */
1523 #if !defined(SOC_TDA2XX) && !defined(SOC_TDA2PX) && !defined(SOC_TDA2EX) && !defined(SOC_TDA3XX)
1524 OSAL_log("\n Running Osal_Delay test:");
1526 if(Osal_delay_test() == true)
1527 {
1528 OSAL_log("\n Osal_Delay tests have passed. \n");
1529 }
1530 else
1531 {
1532 OSAL_log("\n Osal_Delay tests have failed. \n");
1533 testFail = true;
1534 }
1535 #endif
1537 #ifdef ENABLE_GET_TIME_TEST
1538 OSAL_log("\n Running Osal_getTime test:");
1540 if(Osal_getTime_test() == true)
1541 {
1542 OSAL_log("\n Osal_getTime tests have passed. \n");
1543 }
1544 else
1545 {
1546 OSAL_log("\n Osal_getTime tests have failed. \n");
1547 testFail = true;
1548 }
1549 #endif
1551 if(OSAL_clock_test() == true)
1552 {
1553 OSAL_log("\n Clock tests have passed. \n");
1554 }
1555 else
1556 {
1557 OSAL_log("\n Clock tests have failed. \n");
1558 testFail = true;
1559 }
1561 if(OSAL_semaphore_test() == true)
1562 {
1563 OSAL_log("\n Semaphore tests have passed. \n");
1564 }
1565 else
1566 {
1567 OSAL_log("\n Semaphore tests have failed. \n");
1568 testFail = true;
1569 }
1571 #ifdef ENABLE_EXT_BLOCK_TEST
1573 if(OSAL_ExtBlock_test() == true)
1574 {
1575 OSAL_log("\n Extended Memory Block tests for HwiP/SwiP have passed. \n");
1576 }
1577 else
1578 {
1579 OSAL_log("\n Extended Memory Block tests for HwiP/SwiP have failed. \n");
1580 testFail = true;
1581 }
1582 #endif
1584 #ifdef MANUAL_CACHE_TEST
1585 /* This test is valid only for MANUAL testing */
1586 OSAL_cache_test();
1587 #endif
1589 /* Now print the static memory statistics */
1590 if(Osal_getStaticMemStatus(&pMemStats) == osal_OK)
1591 {
1592 OSAL_log("\n Semaphore Statistics: \
1593 \n PeakSemObjs = %u, \
1594 \n numMaxSemObjs = %u, \
1595 \n numFreeSemObjs = %u \n", \
1596 pMemStats.peakSemObjs, \
1597 pMemStats.numMaxSemObjs, \
1598 pMemStats.numFreeSemObjs);
1600 OSAL_log("\n Hwi Statistics: \
1601 \n PeakHwiObjs = %u, \
1602 \n numMaxHwiObjs = %u, \
1603 \n numFreeHwiObjs = %u \n", \
1604 pMemStats.peakHwiObjs, \
1605 pMemStats.numMaxHwiObjs, \
1606 pMemStats.numFreeHwiObjs);
1608 OSAL_log("\n Timer Statistics: \
1609 \n PeakTimerObjs = %u, \
1610 \n numMaxTimerObjs = %u, \
1611 \n numFreeTimerObjs = %u \n", \
1612 pMemStats.peakTimerObjs, \
1613 pMemStats.numMaxTimerObjs, \
1614 pMemStats.numFreeTimerObjs);
1616 }
1617 else
1618 {
1619 testFail = true;
1620 OSAL_log("\n Memory Statistics query failed \n");
1621 }
1623 #if !(defined(BARE_METAL) || defined(FREERTOS))
1624 if(OSAL_swi_test() == true)
1625 {
1626 OSAL_log("\n SWI tests have passed. \n");
1627 }
1628 else
1629 {
1630 OSAL_log("\n SWI tests have failed. \n");
1631 testFail = true;
1632 }
1634 if(OSAL_queue_test() == true)
1635 {
1636 OSAL_log("\n Queue tests have passed. \n");
1637 }
1638 else
1639 {
1640 OSAL_log("\n Queue tests have failed. \n");
1641 testFail = true;
1642 }
1643 #endif
1645 #if ENABLE_DEBUG_LOG_TEST
1646 if(OSAL_log_test() == true)
1647 {
1648 OSAL_log("\n DebugP Log tests have passed. \n");
1649 }
1650 else
1651 {
1652 OSAL_log("\n DebugP Log tests have failed. \n");
1653 testFail = true;
1654 }
1655 #endif
1657 #if defined(FREERTOS)
1658 if(OSAL_mempry_test() == true)
1659 {
1660 OSAL_log("\n MemoryP Log tests have passed. \n");
1661 }
1662 else
1663 {
1664 OSAL_log("\n MemoryP Log tests have failed. \n");
1665 testFail = true;
1666 }
1667 #endif
1669 if(testFail == true)
1670 {
1671 OSAL_log("\n Some tests have failed. \n");
1672 }
1673 else
1674 {
1675 OSAL_log("\n All tests have passed. \n");
1676 }
1678 #ifdef BARE_METAL
1679 while (1)
1680 {
1681 }
1682 #endif
1684 }
1686 #ifdef BUILD_C7X_1
1687 void sysIdleLoop(void)
1688 {
1689 __asm(" IDLE");
1690 }
1692 #include <ti/sysbios/family/c7x/Hwi.h>
1693 #include <ti/csl/csl_clec.h>
1694 void C7x_ConfigureTimerOutput()
1695 {
1696 CSL_ClecEventConfig cfgClec;
1697 CSL_CLEC_EVTRegs *clecBaseAddr = (CSL_CLEC_EVTRegs*)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE;
1699 uint32_t input = CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER0_INTR_PEND_0 + 992; /* Used for Timer Interrupt */
1700 uint32_t corepackEvent = 14;
1702 /* Configure CLEC */
1703 cfgClec.secureClaimEnable = FALSE;
1704 cfgClec.evtSendEnable = TRUE;
1705 cfgClec.rtMap = CSL_CLEC_RTMAP_CPU_ALL;
1706 cfgClec.extEvtNum = 0;
1707 cfgClec.c7xEvtNum = corepackEvent;
1708 CSL_clecConfigEvent(clecBaseAddr, input, &cfgClec);
1710 input = CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER1_INTR_PEND_0 + 992; /* Used for Timer Interrupt */
1711 corepackEvent = 15;
1713 /* Configure CLEC */
1714 cfgClec.secureClaimEnable = FALSE;
1715 cfgClec.evtSendEnable = TRUE;
1716 cfgClec.rtMap = CSL_CLEC_RTMAP_CPU_ALL;
1717 cfgClec.extEvtNum = 0;
1718 cfgClec.c7xEvtNum = corepackEvent;
1719 CSL_clecConfigEvent(clecBaseAddr, input, &cfgClec);
1720 }
1722 #endif
1724 #if defined(BUILD_C66X_1) || defined(BUILD_C66X_2)
1725 /* To set C66 timer interrupts on J7ES VLAB */
1726 void C66xTimerInterruptInit(void)
1727 {
1728 #if defined (_TMS320C6X) && !defined(SOC_TPR12) && !defined (SOC_AWR294X)
1729 struct tisci_msg_rm_irq_set_req rmIrqReq;
1730 struct tisci_msg_rm_irq_set_resp rmIrqResp;
1732 /* On C66x builds we define OS timer tick in the configuration file to
1733 * trigger event #21 for C66x_1 and #20 for C66x_2. Map
1734 * DMTimer 0 interrupt to these events through DMSC RM API.
1735 */
1736 rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
1737 TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
1738 rmIrqReq.src_id = TISCI_DEV_TIMER0;
1739 rmIrqReq.src_index = 0U;
1740 #if defined (BUILD_C66X_1)
1741 rmIrqReq.dst_id = TISCI_DEV_C66SS0_CORE0;
1742 rmIrqReq.dst_host_irq = 21U;
1743 #endif
1744 #if defined (BUILD_C66X_2)
1745 rmIrqReq.dst_id = TISCI_DEV_C66SS1_CORE0;
1746 rmIrqReq.dst_host_irq = 20U;
1747 #endif
1748 /* Unused params */
1749 rmIrqReq.global_event = 0U;
1750 rmIrqReq.ia_id = 0U;
1751 rmIrqReq.vint = 0U;
1752 rmIrqReq.vint_status_bit_index = 0U;
1753 rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
1755 Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
1757 /* On C66x builds we define OS timer tick in the configuration file to
1758 * trigger event #22 for C66x_1 and #22 for C66x_2. Map
1759 * DMTimer 0 interrupt to these events through DMSC RM API.
1760 */
1761 rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
1762 TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
1763 rmIrqReq.src_id = TISCI_DEV_TIMER2;
1764 rmIrqReq.src_index = 0U;
1765 #if defined (BUILD_C66X_1)
1766 rmIrqReq.dst_id = TISCI_DEV_C66SS0_CORE0;
1767 rmIrqReq.dst_host_irq = 22U;
1768 #endif
1769 #if defined (BUILD_C66X_2)
1770 rmIrqReq.dst_id = TISCI_DEV_C66SS1_CORE0;
1771 rmIrqReq.dst_host_irq = 22U;
1772 #endif
1774 /* Unused params */
1775 rmIrqReq.global_event = 0U;
1776 rmIrqReq.ia_id = 0U;
1777 rmIrqReq.vint = 0U;
1778 rmIrqReq.vint_status_bit_index = 0U;
1779 rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
1781 Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
1783 #endif
1784 }
1786 void sysIdleLoop(void)
1787 {
1788 __asm(" IDLE");
1789 }
1791 #endif
1793 /*
1794 * ======== main ========
1795 */
1796 int main(void)
1797 {
1799 #ifdef BARE_METAL
1800 osal_test();
1801 #else
1802 /* All other platforms have the task created under RTSC cfg file
1803 * hence not needed to be created again as below
1804 * For AM65XX TPR12 and J7 the common RTSC cfg file is used and hence there is
1805 * no test application specific task is created in teh RTSC cfg file
1806 */
1807 #if defined (SOC_AM65XX) || defined (SOC_J721E) || defined(SOC_J7200) || defined(SOC_TPR12) || defined (SOC_AWR294X)|| defined(SOC_AM64X)
1808 TaskP_Params taskParams;
1809 #if !defined(FREERTOS)
1810 Error_Block eb;
1811 #endif
1812 TaskP_Params_init(&taskParams);
1813 taskParams.priority =2;
1814 taskParams.stack = gAppTskStackMain;
1815 taskParams.stacksize = sizeof (gAppTskStackMain);
1816 #if !defined(FREERTOS)
1817 taskParams.pErrBlk = &eb;
1818 #endif
1819 TaskP_create(osal_test, &taskParams);
1820 #endif
1821 #if defined (FREERTOS)
1822 /* Start the scheduler to start the tasks executing. */
1823 vTaskStartScheduler();
1824 #else
1825 /* Start BIOS */
1826 BIOS_start();
1827 #endif
1828 #endif
1829 return (0);
1830 }
1832 #if defined(BUILD_MPU) || defined (__C7100__)
1833 extern void Osal_initMmuDefault(void);
1834 void InitMmu(void)
1835 {
1836 Osal_initMmuDefault();
1837 }
1838 #endif
1840 void Osal_appC7xPreInit(void)
1841 {
1842 #if defined (__C7100__)
1843 CSL_ClecEventConfig cfgClec;
1844 CSL_CLEC_EVTRegs *clecBaseAddr = (CSL_CLEC_EVTRegs*) CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE;
1845 uint32_t i, maxInputs = 2048U;
1847 /* make secure claim bit to FALSE so that after we switch to non-secure mode
1848 * we can program the CLEC MMRs
1849 */
1850 cfgClec.secureClaimEnable = FALSE;
1851 cfgClec.evtSendEnable = FALSE;
1852 cfgClec.rtMap = CSL_CLEC_RTMAP_DISABLE;
1853 cfgClec.extEvtNum = 0U;
1854 cfgClec.c7xEvtNum = 0U;
1855 for(i = 0U; i < maxInputs; i++)
1856 {
1857 CSL_clecConfigEvent(clecBaseAddr, i, &cfgClec);
1858 }
1859 #endif
1861 return;
1862 }