1 /**
2 * \file main_osal_test.c
3 *
4 * \brief OSAL driver test application main file.
5 *
6 */
8 /*
9 * Copyright (C) 2016-2022 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #if defined(USE_BIOS)
42 /* XDCtools Header files */
43 #include <xdc/std.h>
44 #if defined (SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
45 // workaround for A72 does not supported in SYS/BIOS yet
46 #if defined (BUILD_C7X)
47 #ifndef BARE_METAL
48 #include <ti/sysbios/family/c7x/Hwi.h>
49 #endif //BARE_METAL
50 #endif //BUILD_C7X
51 #else
52 #include <xdc/cfg/global.h>
53 #endif
54 #include <xdc/runtime/System.h>
55 #include <xdc/runtime/Error.h>
57 /* BIOS Header files */
58 #include <ti/sysbios/BIOS.h>
59 #include <ti/osal/SwiP.h>
60 #endif
62 #if !defined(BARE_METAL)
63 /* include for both safertos and freertos. */
64 #include <ti/osal/TaskP.h>
65 #include <ti/osal/EventP.h>
66 #endif
68 #if defined (FREERTOS)
69 #include "FreeRTOS.h"
70 #include <ti/osal/MemoryP.h>
71 #include <ti/osal/LoadP.h>
72 #endif
74 #if defined (SAFERTOS)
75 #include "SafeRTOS.h"
76 #endif
78 #include <stdio.h>
79 #include <string.h>
80 #include <math.h>
82 /* TI-RTOS Header files */
83 #include <ti/osal/osal.h>
84 #include <ti/osal/soc/osal_soc.h>
85 #include "OSAL_log.h"
87 #include "OSAL_board.h"
89 #if defined (SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
90 #include <ti/drv/sciclient/sciclient.h>
91 #endif
92 /**********************************************************************
93 ************************** Internal functions ************************
94 **********************************************************************/
95 #define TWO_TIMER_INTERRUPT_TEST 0
96 #if defined(SOC_TPR12) || defined (SOC_AWR294X)
97 #define ENABLE_DEBUG_LOG_TEST 1
98 #endif
100 #include <ti/csl/soc.h>
102 #if defined (BUILD_C7X)
103 #include <ti/csl/csl_clec.h>
104 #include <ti/csl/arch/csl_arch.h>
105 #endif
106 #include <ti/csl/tistdtypes.h>
107 #if defined (BARE_METAL)
108 #if !defined(SOC_TPR12) && !defined (SOC_AWR294X)
109 #include <ti/csl/csl_timer.h>
110 #endif
111 #include <ti/csl/arch/csl_arch.h>
113 #if defined (SOC_AM571x) || defined (SOC_AM572x) || defined (SOC_AM574x)
114 #undef TWO_TIMER_INTERRUPT_TEST
115 #define TWO_TIMER_INTERRUPT_TEST 1
116 #endif
117 #elif defined (USE_BIOS)
118 void ErrorHandler(Error_Block *eb)
119 {
120 OSAL_log("ErrorHandler: ");
121 Error_print(eb);
122 }
123 #endif
125 #if defined(BUILD_C66X)
127 /* To set C66 timer interrupts on J7ES */
128 void C66xTimerInterruptInit(void);
130 #if defined(SOC_J721E)
131 /* To set C66 timer interrupts on J7ES */
132 #if defined (BUILD_C66X_1)
133 #define OSAL_TEST_CORE_TISCI_ID (TISCI_DEV_C66SS0_CORE0)
134 #define OSAL_TEST_OS_TIMER_TISCI_ID (TISCI_DEV_TIMER0)
135 #endif
136 #if defined (BUILD_C66X_2)
137 #define OSAL_TEST_CORE_TISCI_ID (TISCI_DEV_C66SS1_CORE0)
138 #define OSAL_TEST_OS_TIMER_TISCI_ID (TISCI_DEV_TIMER1)
139 #endif
140 /* DMTimers used by OS */
141 #if defined(USE_BIOS)
142 /* On C66x builds we define OS timer tick in the configuration file to
143 * trigger event #21 for C66x_1 and #20 for C66x_2.
144 * Map DMTimer 0 interrupt to these events.
145 */
146 #define OSAL_TEST_OS_TIMER_INT_NUM (14U)
147 #if defined (BUILD_C66X_1)
148 #define OSAL_TEST_OS_TIMER_EVENT_NUM (21U)
149 #endif
150 #if defined (BUILD_C66X_2)
151 #define OSAL_TEST_OS_TIMER_EVENT_NUM (20U)
152 #endif
153 #endif
154 #if defined(FREERTOS)
155 #define OSAL_TEST_OS_TIMER_INT_NUM ((uint32_t)configTIMER_INT_NUM) /* 14 for C66x_1; 15 for C66x_2 */
156 #define OSAL_TEST_OS_TIMER_EVENT_NUM ((uint32_t)configTIMER_EVENT_ID) /* 21 for C66x_1; 20 for C66x_2 */
157 #endif
158 #if defined(SAFERTOS)
159 #define OSAL_TEST_OS_TIMER_INT_NUM ((uint32_t)configTIMER_INT_NUM) /* 14 for C66x_1; 15 for C66x_2 */
160 #define OSAL_TEST_OS_TIMER_EVENT_NUM ((uint32_t)configTIMER_EVENT_ID) /* 21 for C66x_1; 20 for C66x_2 */
161 #endif
162 /* DMTimers used for OSAL Timer Test */
163 /* The Event 20/21 is used for DMTimer0/1 by SysBIOS/FreeRTOS by default,
164 * so we need to use a different one here */
165 #define OSAL_TEST_TIMER_TISCI_ID (TISCI_DEV_TIMER2)
166 #define OSAL_TEST_TIMER_EVENT_NUM (22U)
167 #define OSAL_TEST_TIMER_INT_NUM (OSAL_TEST_OS_TIMER_INT_NUM + 1U)
168 #endif
170 #endif
172 #ifdef BUILD_C7X
174 /* To set C7x interrupts of DMTimers used for OSAL Timer Test on J721E/J721S2/J784S4 */
175 void C7x_ConfigureTimerOutput(void);
177 /* DMTimers used for OSAL Timer Test */
178 #if defined(SOC_J721E)
179 #define OSAL_TEST_CLEC_BASE_ADDRESS (CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE)
180 /* DMTimer 2 and Interrupt num 16 is used by SysBIOS/FreeRTOS by default,
181 * so we need to use a different one here */
182 #define OSAL_TEST_TIMER_INT_NUM (14U)
183 #define OSAL_TEST_TIMER_EVENT_NUM (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_TIMER0_INTR_PEND_0 + 992)
184 #endif
185 #if defined(SOC_J721S2)
186 #if defined(FREERTOS)
187 #define OSAL_TEST_CLEC_BASE_ADDRESS (CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE)
188 /* DMTimer 0/1 and Interrupt num 14(configTIMER_INT_NUM)
189 * is used by FreeRTOS by default for C7x_1/C7x_2 respectively,
190 * so we need to use a different one here */
191 /* 15 for C7x_1 - DMTimer 1; 15 for C7x_2 - DMTimer 2 */
192 #define OSAL_TEST_TIMER_INT_NUM (configTIMER_INT_NUM + 1U)
193 #define OSAL_TEST_TIMER_EVENT_NUM (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_TIMER0_INTR_PEND_0 + 992U + configTIMER_ID + 1U)
194 #elif defined(SAFERTOS)
195 #define OSAL_TEST_CLEC_BASE_ADDRESS (CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE)
196 /* DMTimer 0/1 and Interrupt num 14 is used by SafeRTOS by default for C7x_1/C7x_2 respectively,
197 * So we need to use a different one here */
198 #if defined (BUILD_C7X_1)
199 #define OSAL_TEST_TIMER_INT_NUM (OSAL_SAFERTOS_OS_TIMER_INT_NUM_C7X_1+1U)
200 #define OSAL_TEST_TIMER_EVENT_NUM (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_TIMER0_INTR_PEND_0 + 992U + OSAL_SAFERTOS_OS_TIMER_ID_C7X_1 + 1U)
201 #elif defined (BUILD_C7X_2)
202 #define OSAL_TEST_TIMER_INT_NUM (OSAL_SAFERTOS_OS_TIMER_INT_NUM_C7X_2+1U)
203 #define OSAL_TEST_TIMER_EVENT_NUM (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_TIMER0_INTR_PEND_0 + 992U + OSAL_SAFERTOS_OS_TIMER_ID_C7X_2 + 1U)
204 #endif
205 #endif
206 #endif
207 #if defined(SOC_J784S4)
208 #if defined(FREERTOS)
209 #define OSAL_TEST_CLEC_BASE_ADDRESS (CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE)
210 /* DMTimer 0/1/2/3 and Interrupt num 14(configTIMER_INT_NUM)
211 * is used by FreeRTOS by default for C7x_1/C7x_2/C7x_3/C7x_4 respectively,
212 * so we need to use a different one here */
213 /* 15 for C7x_1 - DMTimer 1; 15 for C7x_2 - DMTimer 2 */
214 /* 15 for C7x_3 - DMTimer 3; 15 for C7x_4 - DMTimer 4 */
215 #define OSAL_TEST_TIMER_INT_NUM (configTIMER_INT_NUM + 1U)
216 #define OSAL_TEST_TIMER_EVENT_NUM (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_TIMER0_INTR_PEND_0 + 992U + configTIMER_ID + 1U)
217 #elif defined(SAFERTOS)
218 #define OSAL_TEST_CLEC_BASE_ADDRESS (CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE)
219 /* DMTimer 0/1/2/3 and Interrupt num 14 is used by SafeRTOS
220 * by default for C7x_1/C7x_2/C7x_3/C7x_4 respectively,
221 * So we need to use a different one here */
222 /* 15 for C7x_1 - DMTimer 1; 15 for C7x_2 - DMTimer 2 */
223 /* 15 for C7x_3 - DMTimer 3; 15 for C7x_4 - DMTimer 4 */
224 #if defined (BUILD_C7X_1)
225 #define OSAL_TEST_TIMER_INT_NUM (OSAL_SAFERTOS_OS_TIMER_INT_NUM_C7X_1+1U)
226 #define OSAL_TEST_TIMER_EVENT_NUM (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_TIMER0_INTR_PEND_0 + 992U + OSAL_SAFERTOS_OS_TIMER_ID_C7X_1 + 1U)
227 #elif defined (BUILD_C7X_2)
228 #define OSAL_TEST_TIMER_INT_NUM (OSAL_SAFERTOS_OS_TIMER_INT_NUM_C7X_2+1U)
229 #define OSAL_TEST_TIMER_EVENT_NUM (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_TIMER0_INTR_PEND_0 + 992U + OSAL_SAFERTOS_OS_TIMER_ID_C7X_2 + 1U)
230 #elif defined (BUILD_C7X_3)
231 #define OSAL_TEST_TIMER_INT_NUM (OSAL_SAFERTOS_OS_TIMER_INT_NUM_C7X_3+1U)
232 #define OSAL_TEST_TIMER_EVENT_NUM (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_TIMER0_INTR_PEND_0 + 992U + OSAL_SAFERTOS_OS_TIMER_ID_C7X_3 + 1U)
233 #elif defined (BUILD_C7X_4)
234 #define OSAL_TEST_TIMER_INT_NUM (OSAL_SAFERTOS_OS_TIMER_INT_NUM_C7X_4+1U)
235 #define OSAL_TEST_TIMER_EVENT_NUM (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_TIMER0_INTR_PEND_0 + 992U + OSAL_SAFERTOS_OS_TIMER_ID_C7X_4 + 1U)
236 #endif
237 #endif
238 #endif
240 #endif
242 #undef ENABLE_GET_TIME_TEST
243 #if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_AM572x) || defined(SOC_K2G) || defined(SOC_AM335x) || defined(SOC_AM437x) || defined(SOC_J7200)|| defined(SOC_TPR12) || defined (SOC_AWR294X) || defined (SOC_J721S2) || defined(SOC_J784S4)
244 #define ENABLE_GET_TIME_TEST 1
245 #endif
247 #ifndef NULL_PTR
248 #define NULL_PTR ((void *)0x0)
249 #endif
251 /**********************************************************************
252 ************************** Global Variables **************************
253 **********************************************************************/
254 #if ( __ARM_ARCH == 5)
255 TimerP_Handle handle;
256 #endif
258 /* Test application stack size */
259 #if defined (BUILD_C7X)
260 /* Temp workaround to avoid assertion failure: A_stackSizeTooSmall : Task stack size must be >= 16KB.
261 * until the Bug PDK-7605 is resolved */
262 #define APP_TSK_STACK_MAIN (64U * 1024U)
263 #else
264 #define APP_TSK_STACK_MAIN (16U * 1024U)
265 #endif
267 #ifdef BARE_METAL
268 /* No task support for Bare metal */
269 #else
270 /* Test application stack */
271 /* For SafeRTOS on R5F with FFI Support, task stack should be aligned to the stack size */
272 #if defined(SAFERTOS) && defined (BUILD_MCU)
273 static uint8_t gAppTskStackMain[APP_TSK_STACK_MAIN] __attribute__(( aligned( APP_TSK_STACK_MAIN ))) = { 0 };
274 #else
275 static uint8_t gAppTskStackMain[APP_TSK_STACK_MAIN] __attribute__(( aligned( 32 )));
276 #endif
277 #endif
279 /*
280 * ======== Board_initOSAL ========
281 */
282 void Board_initOSAL(void)
283 {
284 Board_initCfg boardCfg;
285 Board_STATUS status;
286 #if defined(evmK2E) || defined(evmC6678)
287 boardCfg = BOARD_INIT_MODULE_CLOCK |
288 BOARD_INIT_UART_STDIO;
289 #else
290 boardCfg = BOARD_INIT_PINMUX_CONFIG;
291 /* For TPR12 AWR294X we dont do module clock init from app. This is done by
292 * GEL file or SBL. Doing Module Clock init causes OSAL RTI interrupts
293 * to stop if another core also runs OSAL test
294 */
295 #if !defined(SOC_TPR12) && !defined (SOC_AWR294X)
296 #if !defined(_TMS320C6X)
297 boardCfg |= BOARD_INIT_MODULE_CLOCK;
298 #endif
299 #endif /* !defined(SOC_TPR12) */
301 #if defined (UART_CONSOLE)
302 boardCfg |= BOARD_INIT_UART_STDIO;
303 #endif
304 #endif
305 status = Board_init(boardCfg);
307 if (status != BOARD_SOK)
308 {
309 OSAL_log(" Board_init() is not successful...unexpected results may happen \n");
310 }
312 return;
313 }
315 #if !defined (BARE_METAL)
316 /*
317 * ======== Floating point test function ========
318 */
319 #define FLOAT_CALC_ITER 100
320 #if defined (BUILD_MCU) && defined (SAFERTOS)
321 uint8_t gFloatingNoiseTaskStack[4*1024] __attribute__((aligned(4*1024)));
322 #else
323 uint8_t gFloatingNoiseTaskStack[32*1024] __attribute__(( aligned( 128 )));
324 #endif
325 SemaphoreP_Handle noiseSem, floatSem;
327 /* Aim of this task is to do some floating point operations in between operations carried by OSAL_floating_point_test */
328 void floatingNoiseTaskFxn( void *arg1, void *arg2 )
329 {
330 /* Below variable values are randomly picked. No special significance. */
331 volatile double floating_noise = 1.09, val_2p0 = 2.0;
332 uint8_t count = FLOAT_CALC_ITER;
333 /* FreeRTOS task needs to call portTASK_USES_FLOATING_POINT if configFLOATING_POINT_CONTEXT is 0.
334 * SafeRTOS enables FPU by default.
335 */
336 #if defined (FREERTOS) && (configFLOATING_POINT_CONTEXT==0)
337 portTASK_USES_FLOATING_POINT();
338 #endif
340 while(count--)
341 {
342 SemaphoreP_pend(noiseSem, SemaphoreP_WAIT_FOREVER);
343 floating_noise = floating_noise + 0.1;
344 floating_noise = floating_noise * val_2p0;
345 floating_noise = floating_noise / val_2p0;
346 SemaphoreP_post(floatSem);
347 }
348 }
350 bool OSAL_floating_point_test()
351 {
352 /* FreeRTOS task needs to call portTASK_USES_FLOATING_POINT if configFLOATING_POINT_CONTEXT is 0.
353 * SafeRTOS enables FPU by default.
354 */
355 #if defined (FREERTOS) && (configFLOATING_POINT_CONTEXT==0)
356 portTASK_USES_FLOATING_POINT();
357 #endif
358 /* Below variable values are randomly picked. No special significance. */
359 volatile double expected_float = 1.07, calculated_float = 1.07, val_1p02 = 1.02;
360 uint8_t count = FLOAT_CALC_ITER;
361 TaskP_Params taskParams;
362 SemaphoreP_Params semParams;
363 TaskP_Handle taskHandle;
364 bool retval = false;
366 /* Initialize and create Noise task and task faculties. */
367 TaskP_Params_init(&taskParams);
368 taskParams.priority = 2;
369 taskParams.stack = gFloatingNoiseTaskStack;
370 taskParams.stacksize = sizeof(gFloatingNoiseTaskStack);
371 SemaphoreP_Params_init(&semParams);
372 noiseSem = SemaphoreP_create(1U, &semParams);
373 SemaphoreP_Params_init(&semParams);
374 floatSem = SemaphoreP_create(0U, &semParams);
376 taskHandle = TaskP_create(&floatingNoiseTaskFxn, &taskParams);
377 if (taskHandle == NULL)
378 {
379 OSAL_log("\n Floating Noise Task could not be created!!\n");
380 }
382 /* Floating point calculations under test here, while exchanging CPU time with the noisy floating point task. */
383 while (count--)
384 {
385 SemaphoreP_pend(floatSem, SemaphoreP_WAIT_FOREVER);
386 calculated_float = pow(calculated_float, val_1p02);
387 SemaphoreP_post(noiseSem);
388 }
389 /* Calculate the expected value. */
390 count = FLOAT_CALC_ITER;
391 while( count-- )
392 {
393 expected_float = pow(expected_float, 1.02);
394 }
396 OSAL_log("\n Calculated float is %u.%u, and expected float is %u.%u ...\n", (uint32_t)calculated_float, (uint32_t)((calculated_float-(uint32_t)calculated_float)*1000000), (uint32_t)expected_float, (uint32_t)((expected_float-(uint32_t)expected_float)*1000000));
398 /* Match the expected and the calculated value. if same return true, else return false. */
399 if (calculated_float == expected_float)
400 {
401 retval = true;
402 }
404 return retval;
405 }
406 #endif
408 /*
409 * ======== HWI test function ========
410 */
411 volatile uint64_t gTestlocalTimeout = 0x300000U;
413 #if (defined (SOC_AM65XX) || defined (SOC_AM64X) || defined(SOC_J721E) || defined(SOC_J7200) || defined (SOC_TPR12) || defined (SOC_AWR294X) || defined (SOC_J721S2) || defined(SOC_J784S4)) && (!defined(BUILD_C66X))&&(!defined(BUILD_C7X))
414 #define INT_NUM_IRQ 32U
415 #define LOOP_CNT 100
416 volatile uint64_t gFlagIRQ = 0;
418 void myIsrIRQ(uintptr_t arg)
419 {
420 gFlagIRQ = 1;
421 gTestlocalTimeout = 0x300000;
422 }
423 bool OSAL_core_hwi_test()
424 {
426 HwiP_Params hwiParams;
427 HwiP_Handle handle;
428 volatile int intCount = 0;
429 int32_t ret;
430 bool test_pass=true;
432 HwiP_Params_init(&hwiParams);
434 OSAL_log("Creating Hwi myIsr \n");
435 handle = HwiP_create(INT_NUM_IRQ, myIsrIRQ, &hwiParams);
436 if (handle == NULL_PTR) {
437 OSAL_log("Failed to create the HwiP handle \n");
438 test_pass = false;
439 }
441 if (test_pass == true)
442 {
443 while (intCount != LOOP_CNT)
444 {
445 ret=HwiP_post(INT_NUM_IRQ);
447 if(ret==osal_UNSUPPORTED)
448 { /* In case of unsupported SOC/error */
449 OSAL_log("HwiP_post unsupported/failed!\n");
450 test_pass=false;
451 break;
452 }
454 /* Wait for software timeout, ISR should hit
455 * otherwise return the test as failed */
456 while (gTestlocalTimeout != 0U)
457 {
458 gTestlocalTimeout--;
459 if (gFlagIRQ)
460 {
461 gFlagIRQ = 0;
462 intCount++;
463 break;
464 }
465 }
466 /* Wait is over - did not get any interrupts posted/received
467 * declare the test as fail
468 */
469 if (gTestlocalTimeout == 0)
470 {
471 OSAL_log("Failed to get interrupts \n");
472 test_pass = false;
473 break;
474 }
475 }
477 OSAL_log("%d IRQs received. Test over !\n",intCount);
478 ret = HwiP_delete(handle);
479 if (ret != HwiP_OK)
480 {
481 OSAL_log(" Failed to delete HwiP handle \n");
482 test_pass= false;
483 }
484 }
486 return test_pass;
487 }
488 #endif
490 bool OSAL_hwi_test()
491 {
492 bool pass = true;
493 #if (defined (SOC_AM65XX) || defined (SOC_AM64X) || defined(SOC_J721E) || defined(SOC_J7200) || defined (SOC_TPR12) || defined (SOC_AWR294X) || defined (SOC_J721S2) || defined(SOC_J784S4)) && (!defined(BUILD_C66X))&&(!defined(BUILD_C7X))
494 pass = OSAL_core_hwi_test();
495 #endif
496 return pass;
497 }
499 typedef enum UT_Timer_Type_s {
500 UT_Timer_DMTIMER = 0,
501 UT_Timer_TIMER64 = 1,
502 UT_Timer_RTITIMER = 2
503 } UT_Timer_Type_t;
506 #if defined(SOC_AM335x)
507 #define CM_PER_TIMER3_CLKCTRL (0x44e00084)
508 #define CM_DPLL_CLKSEL_TIMER3_CLK (0x44e0050c)
509 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
510 #define OSAL_TEST_TIMER_ID (1U)
511 #define OSAL_TEST_TIMER_PERIOD (5000U)
512 #elif defined(SOC_AM437x)
513 #define CM_PER_TIMER3_CLKCTRL (0x44DF8800 + 0x538)
514 #define CM_DPLL_CLKSEL_TIMER3_CLK (0x44DF4200 + 0x8)
515 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
516 #define OSAL_TEST_TIMER_ID (3U)
517 #define OSAL_TEST_TIMER_PERIOD (5000U)
519 #elif defined(SOC_K2E) || defined(SOC_K2L)
520 UT_Timer_Type_t timer_type = UT_Timer_TIMER64;
521 #define OSAL_TEST_TIMER_ID (TimerP_ANY)
522 #define OSAL_TEST_TIMER_PERIOD (5000U)
523 #elif defined(SOC_K2H) || defined(SOC_K2K)
524 UT_Timer_Type_t timer_type = UT_Timer_TIMER64;
525 #define OSAL_TEST_TIMER_ID (8U)
526 #define OSAL_TEST_TIMER_PERIOD (5000U)
527 #elif defined(SOC_K2G)
528 UT_Timer_Type_t timer_type = UT_Timer_TIMER64;
529 #define OSAL_TEST_TIMER_ID (1U)
530 #define OSAL_TEST_TIMER_ID2 (2U)
531 #define OSAL_TEST_TIMER_PERIOD (5000U)
532 #elif defined(SOC_AM572x) || defined (SOC_AM574x)
533 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
534 #if defined (__ARM_ARCH_7A__)
535 #define OSAL_TEST_TIMER_ID (1U)
536 #define OSAL_TEST_TIMER_ID2 (9U)
537 #define OSAL_TEST_TIMER_PERIOD (5000U)
538 #elif defined (_TMS320C6X)
539 #define OSAL_TEST_TIMER_ID (4U)
540 #define OSAL_TEST_TIMER_ID2 (5U)
541 #define OSAL_TEST_TIMER_PERIOD (5000U)
542 #else
543 #define OSAL_TEST_TIMER_ID (8U)
544 #define OSAL_TEST_TIMER_ID2 (10U)
545 #define OSAL_TEST_TIMER_PERIOD (5000U)
546 #endif
547 #elif defined(SOC_AM571x)
548 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
549 #if defined (__ARM_ARCH_7A__)
550 #define OSAL_TEST_TIMER_ID (1U)
551 #define OSAL_TEST_TIMER_ID2 (9U)
552 #define OSAL_TEST_TIMER_PERIOD (5000U)
553 #elif defined (_TMS320C6X)
554 #define OSAL_TEST_TIMER_ID (4U)
555 #define OSAL_TEST_TIMER_ID2 (5U)
556 #define OSAL_TEST_TIMER_PERIOD (5000U)
557 #else
558 #define OSAL_TEST_TIMER_ID (8U)
559 #define OSAL_TEST_TIMER_ID2 (10U)
560 #define OSAL_TEST_TIMER_PERIOD (5000U)
561 #endif
562 #elif defined(SOC_OMAPL137) || defined (SOC_OMAPL138)
563 UT_Timer_Type_t timer_type = UT_Timer_TIMER64;
564 #define OSAL_TEST_TIMER_ID (1U)
565 #define OSAL_TEST_TIMER_PERIOD (5000U)
567 #elif defined(SOC_AM65XX)
568 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
569 #if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
570 #define OSAL_TEST_TIMER_ID (1U)
571 #define OSAL_TEST_TIMER_PERIOD (5000U)
572 #else
573 #define OSAL_TEST_TIMER_ID (4U)
574 #define OSAL_TEST_TIMER_PERIOD (5000U)
575 #endif
576 #elif defined(SOC_J721E)
577 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
578 #if defined (BUILD_MCU1_0)
579 #define OSAL_TEST_TIMER_ID (2U)
580 #define OSAL_TEST_TIMER_PERIOD (5000U)
581 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
582 #define OSAL_TEST_TIMER_ID (1U)
583 #define OSAL_TEST_TIMER_PERIOD (5000U)
584 #elif defined (BUILD_C66X_1)
585 #define OSAL_TEST_TIMER_ID (2U)
586 #define OSAL_TEST_TIMER_PERIOD (5000U)
587 #elif defined (BUILD_C66X_2)
588 #define OSAL_TEST_TIMER_ID (2U)
589 #define OSAL_TEST_TIMER_PERIOD (5000U)
590 #elif defined (BUILD_C7X_1)
591 #define OSAL_TEST_TIMER_ID (0U)
592 #define OSAL_TEST_TIMER_PERIOD (5000U)
593 #else
594 #define OSAL_TEST_TIMER_ID (2U)
595 #define OSAL_TEST_TIMER_PERIOD (5000U)
596 #endif
597 #elif defined(SOC_J721S2)
598 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
599 #if defined (BUILD_MCU1_0)
600 #define OSAL_TEST_TIMER_ID (2U)
601 #define OSAL_TEST_TIMER_PERIOD (5000U)
602 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
603 #define OSAL_TEST_TIMER_ID (1U)
604 #define OSAL_TEST_TIMER_PERIOD (5000U)
605 #elif defined (BUILD_C7X_1)
606 #define OSAL_TEST_TIMER_ID (1U)
607 #define OSAL_TEST_TIMER_PERIOD (5000U)
608 #elif defined (BUILD_C7X_2)
609 #define OSAL_TEST_TIMER_ID (2U)
610 #define OSAL_TEST_TIMER_PERIOD (5000U)
611 #else
612 #define OSAL_TEST_TIMER_ID (6U)
613 #define OSAL_TEST_TIMER_PERIOD (5000U)
614 #endif
615 #elif defined(SOC_J784S4)
616 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
617 #if defined (BUILD_MCU1_0)
618 #define OSAL_TEST_TIMER_ID (2U)
619 #define OSAL_TEST_TIMER_PERIOD (5000U)
620 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
621 #define OSAL_TEST_TIMER_ID (1U)
622 #define OSAL_TEST_TIMER_PERIOD (5000U)
623 #elif defined (BUILD_C7X_1)
624 #define OSAL_TEST_TIMER_ID (1U)
625 #define OSAL_TEST_TIMER_PERIOD (5000U)
626 #elif defined (BUILD_C7X_2)
627 #define OSAL_TEST_TIMER_ID (2U)
628 #define OSAL_TEST_TIMER_PERIOD (5000U)
629 #elif defined (BUILD_C7X_3)
630 #define OSAL_TEST_TIMER_ID (3U)
631 #define OSAL_TEST_TIMER_PERIOD (5000U)
632 #elif defined (BUILD_C7X_4)
633 #define OSAL_TEST_TIMER_ID (4U)
634 #define OSAL_TEST_TIMER_PERIOD (5000U)
635 #else
636 #define OSAL_TEST_TIMER_ID (6U)
637 #define OSAL_TEST_TIMER_PERIOD (5000U)
638 #endif
639 #elif defined(SOC_J7200)
640 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
641 #if defined (BUILD_MCU1_0)
642 #define OSAL_TEST_TIMER_ID (2U)
643 #define OSAL_TEST_TIMER_PERIOD (5000U)
644 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
645 #define OSAL_TEST_TIMER_ID (1U)
646 #define OSAL_TEST_TIMER_PERIOD (5000U)
647 #else
648 #define OSAL_TEST_TIMER_ID (2U)
649 #define OSAL_TEST_TIMER_PERIOD (5000U)
650 #endif
651 #elif defined(SOC_AM64X)
652 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
653 #if defined(BUILD_MCU)
654 #define OSAL_TEST_TIMER_ID (1U)
655 #define OSAL_TEST_TIMER_PERIOD (5000U)
656 #endif
657 #if defined(BUILD_MPU)
658 #define OSAL_TEST_TIMER_ID (4U)
659 #define OSAL_TEST_TIMER_PERIOD (5000U)
660 #endif
661 #if defined(BUILD_M4F)
662 #define OSAL_TEST_TIMER_ID (1U)
663 #define OSAL_TEST_TIMER_PERIOD (5000U)
664 #endif
665 #elif (defined(SOC_TPR12) || defined (SOC_AWR294X))
666 UT_Timer_Type_t timer_type = UT_Timer_RTITIMER;
667 #define OSAL_TEST_TIMER_ID (TimerP_ANY)
668 #if defined(SIM_BUILD)
669 #define OSAL_TEST_TIMER_PERIOD (500U)
670 #else
671 #define OSAL_TEST_TIMER_PERIOD (5000U)
672 #endif
673 #else
674 UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
675 #if defined (__ARM_ARCH_7A__)
676 #define OSAL_TEST_TIMER_ID (1U)
677 #define OSAL_TEST_TIMER_PERIOD (5000U)
678 #elif defined (_TMS320C6X)
679 #define OSAL_TEST_TIMER_ID (4U)
680 #define OSAL_TEST_TIMER_PERIOD (5000U)
681 #else
682 #define OSAL_TEST_TIMER_ID (8U)
683 #define OSAL_TEST_TIMER_PERIOD (5000U)
684 #endif
685 #endif
687 #if defined(SIM_BUILD)
688 #define OSAL_GET_TIME_MAX_SAMPLES (10U)
689 #else
690 #define OSAL_GET_TIME_MAX_SAMPLES (20U)
691 #endif
692 volatile uint32_t timerIsrCount = 0;
693 volatile uint32_t timerIsr2Count = 0;
695 #if defined(SIM_BUILD)
696 #define OSAL_TIMER_TEST_MAX_INTERRUPTS (10U)
697 #else
698 #define OSAL_TIMER_TEST_MAX_INTERRUPTS (100U)
699 #endif
702 #if defined (ENABLE_GET_TIME_TEST)
703 uint64_t gTestTimeRd[OSAL_GET_TIME_MAX_SAMPLES];
704 #endif
706 void timerIsr(void *arg)
707 {
708 #if (defined(BARE_METAL) && ( __ARM_ARCH == 5))
709 TimerP_ClearInterrupt(handle);
710 #endif
712 #if defined (ENABLE_GET_TIME_TEST)
713 if (timerIsrCount < OSAL_GET_TIME_MAX_SAMPLES)
714 {
715 gTestTimeRd[timerIsrCount] = TimerP_getTimeInUsecs();
716 }
717 #endif
718 timerIsrCount++;
719 }
722 #if TWO_TIMER_INTERRUPT_TEST
723 void timerIsr2(void *arg)
724 {
725 timerIsr2Count++;
726 }
727 #endif
729 /*
730 * ========= Osal Delay Test function =========
731 */
732 #if defined(SIM_BUILD)
733 #define OSAL_DELAY_TIME 1
734 #else
735 #define OSAL_DELAY_TIME 10
736 #endif
737 bool Osal_delay_test(void)
738 {
739 #if !defined(SOC_AM64X)
740 int32_t i;
741 /* This test assumes that Board init has been already
742 * called outside this function
743 */
744 /* Notice a '.' on terminal for every 1 second */
746 for (i=0; i<10;i++) {
747 #endif
748 Osal_delay(OSAL_DELAY_TIME);
749 OSAL_log(".");
750 #if !defined(SOC_AM64X)
751 }
752 #endif
753 OSAL_log("\n");
755 return(true);
756 }
758 #if defined (ENABLE_GET_TIME_TEST)
759 /*
760 * ========= Osal getTime Test function =========
761 */
762 bool Osal_getTime_test(void)
763 {
764 int32_t i;
765 bool retVal = true;
767 OSAL_log(" \n time read in micro seconds is \n ");
768 for (i = 0; i < OSAL_GET_TIME_MAX_SAMPLES; i++)
769 {
770 OSAL_log(" %d \n ", (uint32_t) gTestTimeRd[i]);
771 }
773 return(retVal);
774 }
775 #endif
777 /*
778 * ======== Timer test function ========
779 */
780 bool OSAL_timer_test()
781 {
782 TimerP_Params timerParams;
783 #if ( __ARM_ARCH != 5)
784 /* Timer handle is defined as global for OMAPL13x ARM9 core since
785 it is required for clearing the interrupt from ISR */
786 TimerP_Handle handle;
787 #endif
789 #if TWO_TIMER_INTERRUPT_TEST
790 TimerP_Handle handle2;
791 #endif
792 TimerP_Status timerStatus;
793 Osal_HwAttrs hwAttrs;
795 #if defined(BARE_METAL)
796 int32_t id = OSAL_TEST_TIMER_ID;
797 #else
798 /* Pass TimerP_ANY for FreeRTOS, since FreeRTOS kernel running on each core
799 * will use one timer per core. So if there is a conflict in the id passed
800 * TimerP_create will fail. See FreeRTOS_config_<core>.h for details about
801 * the timer instance used by each core */
802 int32_t id = TimerP_ANY;
803 #endif
805 #if defined(SOC_AM437x)
806 /* We can't use Timer_ANY for Sys BIOS as it allocates Timer0 which is
807 * firewalled on HS device and hence changing the Test Timer ID = 3 for
808 * both HS and GP parts
809 */
810 id = OSAL_TEST_TIMER_ID;
811 #endif
813 #if defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
814 #if !(defined(BARE_METAL) || defined(FREERTOS))
815 #if defined(BUILD_C66X) || defined(BUILD_C7X) || defined(BUILD_MCU1_0)
816 id = OSAL_TEST_TIMER_ID;
817 #endif
818 #endif
819 #endif
820 #if defined(SOC_J721E)
821 #if defined(FREERTOS)
822 #if defined(BUILD_C66X)
823 id = OSAL_TEST_TIMER_ID;
824 #endif
825 #endif
826 #endif
827 #if defined(SOC_J721E) || defined(SOC_J721S2) || defined(SOC_J784S4)
828 #if defined(BUILD_C7X)
829 id = OSAL_TEST_TIMER_ID;
830 #endif
831 #endif
833 volatile int32_t i;
834 uint32_t prevCount, ctrlBitmap = OSAL_HWATTR_SET_OSALDELAY_TIMER_BASE ;
835 bool ret = true;
836 int32_t osal_ret;
838 #if (defined (SOC_AM437x) || defined (SOC_AM335x))
839 *(unsigned int*)CM_DPLL_CLKSEL_TIMER3_CLK = 0x1; /* high frequency input clock */
841 // enable the TIMER
842 *(unsigned int*)CM_PER_TIMER3_CLKCTRL = 0x2; /* Module is explicitly enabled */
843 #endif
845 /* Set the timer base for the osal delay */
846 Osal_getHwAttrs(&hwAttrs);
848 #if defined (SOC_AM437x)
849 hwAttrs.osalDelayTimerBaseAddr = (uintptr_t) 0x48040000U; /* DMTIMER2 */
850 #endif
852 #if defined (OSAL_TEST_CPU_FREQ_KHZ)
853 hwAttrs.cpuFreqKHz = OSAL_TEST_CPU_FREQ_KHZ;
854 ctrlBitmap |= OSAL_HWATTR_SET_CPU_FREQ;
855 #endif
857 /* This API should return osal_OK for AM3/AM4 and return unsupported for other Socs */
858 osal_ret = Osal_setHwAttrs(ctrlBitmap, &hwAttrs);
860 #if defined (SOC_AM437x) || defined (SOC_AM335x)
861 if (osal_ret == osal_OK) {
862 ret = true;
863 }
864 else {
865 ret = false;
866 }
867 #else
868 if ((osal_ret == osal_UNSUPPORTED) ||
869 (osal_ret == osal_OK)) {
870 ret = true;
871 }
872 else {
873 ret = false;
874 }
875 #endif /* (SOC_AM437x) || defined (SOC_AM335x) */
877 TimerP_Params_init(&timerParams);
878 timerParams.runMode = TimerP_RunMode_CONTINUOUS;
879 timerParams.startMode = TimerP_StartMode_USER;
880 timerParams.periodType = TimerP_PeriodType_MICROSECS;
881 timerParams.period = OSAL_TEST_TIMER_PERIOD;
883 #if defined(SOC_J721E) || defined(SOC_J721S2) || defined(SOC_J784S4)
884 #if defined(_TMS320C6X)
885 timerParams.eventId = OSAL_TEST_TIMER_EVENT_NUM;
886 timerParams.intNum = OSAL_TEST_TIMER_INT_NUM;
887 OSAL_log("\n set intNum=%d, eventId=%d, id=%d, \n", timerParams.intNum, timerParams.eventId, id);
888 #endif
889 #endif
891 #if defined(SOC_J721E) || defined(SOC_J721S2) || defined(SOC_J784S4)
892 #if defined(BUILD_C7X)
893 timerParams.intNum = OSAL_TEST_TIMER_INT_NUM;
894 OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id);
895 #endif
896 #endif
898 #if defined(_TMS320C6X)
899 #if defined(SOC_TPR12) || defined(SOC_AWR294X)
900 timerParams.intNum = 16;
901 OSAL_log("\n set intNum=%d, id=%d, \n", timerParams.intNum, id);
902 #endif
903 #endif
905 if (timer_type == UT_Timer_TIMER64)
906 {
907 timerParams.timerMode = TimerP_Timer64Mode_UNCHAINED;
908 timerParams.timerHalf = TimerP_Timer64Half_LOWER;
909 }
910 handle = TimerP_create(id, (TimerP_Fxn)&timerIsr, &timerParams);
912 /* don't expect the handle to be null */
913 if (handle == NULL_PTR)
914 {
915 OSAL_log("\n Timer Create error \n");
916 ret = false;
917 }
919 #if defined(ENABLE_GET_TIME_TEST)
920 TimerP_getTimeInUsecs();
921 #endif
923 #if TWO_TIMER_INTERRUPT_TEST
925 #if (defined(_TMS320C6X) && (!defined(SOC_J721E)))
926 timerParams.intNum = 14;
927 #endif
929 if (ret == true) {
930 handle2 = TimerP_create(OSAL_TEST_TIMER_ID2, (TimerP_Fxn)&timerIsr2, &timerParams);
931 /* don't expect the handle to be null */
932 if (handle2 == NULL_PTR)
933 {
934 OSAL_log("\n Timer Create error for handle2 \n");
935 ret = false;
936 }
937 }
938 #endif
940 if (ret == true)
941 {
942 timerIsrCount = 0U;
943 timerStatus = TimerP_start(handle);
945 if (timerStatus != TimerP_OK) {
946 OSAL_log("Err: Coult not start the timer %d \n", id);
947 ret = false;
948 }
950 #if TWO_TIMER_INTERRUPT_TEST
951 timerIsr2Count = 0U;
952 timerStatus = TimerP_start(handle2);
954 if (timerStatus != TimerP_OK) {
955 OSAL_log("Err: Coult not start the timer %d \n", id + 1);
956 ret = false;
957 }
959 while (1)
960 {
961 if (timerIsr2Count >= OSAL_TIMER_TEST_MAX_INTERRUPTS) {
962 timerStatus = TimerP_stop(handle2);
963 if (timerStatus != TimerP_OK) {
964 OSAL_log("Err: Coult not stop the timer %d \n", id);
965 ret = false;
966 }
967 break;
968 }
969 }
970 #endif
972 while (1)
973 {
974 if (timerIsrCount >= OSAL_TIMER_TEST_MAX_INTERRUPTS) {
975 timerStatus = TimerP_stop(handle);
976 if (timerStatus != TimerP_OK) {
977 OSAL_log("Err: Coult not stop the timer %d \n", id);
978 ret = false;
979 }
981 break;
982 }
983 }
985 /* Latch the ISR count after the timer stops */
986 prevCount = (timerIsrCount);
988 /* Give some time for all pending interrupts to be processed */
989 for(i = 0; i < 1000; i++)
990 {
991 asm (" nop ");
992 }
994 /* Now check if timer ISR gets kicked in
995 * timer ISR should not be kicked in */
996 if (ret == true)
997 {
998 for (i = 0; i < 50000; i++);
1000 if (prevCount != timerIsrCount)
1001 {
1002 OSAL_log(" Error: Timer appears to be not stopped via OSAL calls, val1 = %u and val2 = %u \n ", prevCount, timerIsrCount);
1003 ret = false;
1004 }
1005 else
1006 {
1007 OSAL_log(" TimerTestLog: got %u ticks from timer id = %d \n", timerIsrCount, id);
1008 #if TWO_TIMER_INTERRUPT_TEST
1009 OSAL_log(" TimerTestLog: got %u ticks from timer id = %d \n", timerIsr2Count, id+1);
1010 #endif
1011 }
1012 }
1013 }
1015 if (handle != NULL_PTR)
1016 {
1017 if (TimerP_delete(handle) != TimerP_OK)
1018 {
1019 ret = false;
1020 }
1021 }
1023 for (i = 0; i < (log2(TIMERP_AVAILABLE_MASK+1U)+1U); i++)
1024 {
1025 TimerP_Params_init(&timerParams);
1026 timerParams.runMode = TimerP_RunMode_CONTINUOUS;
1027 timerParams.startMode = TimerP_StartMode_USER;
1028 timerParams.periodType = TimerP_PeriodType_MICROSECS;
1029 timerParams.period = OSAL_TEST_TIMER_PERIOD;
1030 handle = TimerP_create(TimerP_ANY, NULL, &timerParams);
1031 /* don't expect the handle to be null */
1032 if (handle == NULL_PTR)
1033 {
1034 OSAL_log("\n Error: Timer Create failed for %d th time \n", i);
1035 ret = false;
1036 }
1037 if (TimerP_delete(handle) != TimerP_OK)
1038 {
1039 OSAL_log("\n Error: Timer Delete failed for %d th time \n", i);
1040 ret = false;
1041 }
1042 }
1043 return (ret);
1044 }
1046 /*
1047 * ======== Clock test function ========
1048 */
1049 bool OSAL_clock_test()
1050 {
1051 return true;
1052 }
1054 #ifdef MANUAL_CACHE_TEST
1056 #if defined (__ARM_ARCH_7A__)
1057 #include <ti/csl/csl_a15.h>
1058 #include <ti/csl/csl_armGicAux.h>
1059 #elif defined (_TMS320C6X)
1060 #include <ti/csl/csl_cacheAux.h>
1061 #endif
1063 #if defined (SOC_AM437x) || defined(SOC_AM335x)
1064 #include <ti/starterware/include/chipdb.h>
1065 #include <ti/starterware/include/armv7a/pl310.h>
1066 #include <ti/starterware/include/armv7a/pl310_config.h>
1067 #endif
1069 #define BUF_LEN 256
1070 #define LOCAL_CPU_WRITE_PATTERN_1 0xA1A1A1A1
1071 #define LOCAL_CPU_WRITE_PATTERN_2 0xA2A2A2A2
1072 #define LOCAL_CPU_WRITE_PATTERN_3 0xA3A3A3A3
1074 #define ALTERNATE_CPU_WRITE_PATTERN_1 0xB1B1B1B1
1075 #define ALTERNATE_CPU_WRITE_PATTERN_2 0xB2B2B2B2
1076 #define ALTERNATE_CPU_WRITE_PATTERN_3 0xB3B3B3B3
1078 #if defined (__ARM_ARCH_7A__)
1079 uint32_t ddr_buf[BUF_LEN] __attribute__((aligned(256))); // GCC way of aligning
1080 #elif defined (_TMS320C6X)
1081 #pragma DATA_SECTION(ddr_buf,".cachetest_ddrbuf")
1082 #pragma DATA_ALIGN(ddr_buf,256)
1083 uint32_t ddr_buf[BUF_LEN];
1084 #elif defined(__TI_ARM_V7M4__)
1085 uint32_t ddr_buf[BUF_LEN];
1086 #endif
1087 void OSAL_cache_test_fill_buf(uint32_t *buf, uint32_t len,uint32_t pattern) {
1088 uint32_t i;
1089 for(i=0;i<len;i++) {
1090 buf[i]=pattern;
1091 }
1092 }
1093 /* Returns FALSE if all the buffer is not 'pattern'. This will read the contents though */
1094 bool OSAL_cache_test_check_buf(uint32_t *buf, uint32_t len,uint32_t pattern) {
1095 uint32_t i;
1096 bool match=TRUE;
1097 for(i=0;i<len;i++) {
1098 if(buf[i]!=pattern) {
1099 match=FALSE;
1100 }
1101 }
1102 return(match);
1103 }
1105 #if defined (SOC_AM572x) || defined (SOC_AM574x)
1106 bool OSAL_cache_test()
1107 {
1109 bool match,res=TRUE;
1110 #if defined (__ARM_ARCH_7A__)
1111 CSL_a15EnableCache();
1112 #elif defined(_TMS320C6X)
1113 /* Enable for most of the DDR3 memory , especially the first two MAR regions where ddr_buf will reside */
1114 CACHE_enableCaching(128);
1115 CACHE_enableCaching(129);
1116 CACHE_setL1DSize(CACHE_L1_4KCACHE);
1117 CACHE_setL2Size(CACHE_1024KCACHE);
1118 #endif
1119 OSAL_log("This manual cache test is a CCS based test. Please do the following\n");
1120 OSAL_log("1) On the local CPU open two memory windows for the address 0x%x\n: One CPU view and One Physical memory view\n",&ddr_buf[0]);
1121 OSAL_log("2) Connect an alternate CPU (for example if local cpu is A15, open a c66/m4 as the alternate CPU\n");
1122 OSAL_log("3) On the alternate CPU ( preferably a different window through (CCS->New Window)) Open the address 0x%x\n with a physical memory view\n",&ddr_buf[0]);
1124 OSAL_log("\n**** Forcing a read to get the buffer cached() ******\n");
1125 OSAL_cache_test_check_buf(ddr_buf,BUF_LEN,0); /* Checking for dummy pattern, just to force the cache read */
1127 OSAL_log("\n**** Testing Cache_Invalidate() ******\n");
1129 OSAL_log("\nWriting 0x%x local ddr memory\n",LOCAL_CPU_WRITE_PATTERN_1);
1130 /************************ TEST for CacheP_Inv() *********************/
1131 /* A15- Write LOCAL_CPU_WRITE_PATTERN_1 in to ddr_buf[0] */
1132 OSAL_cache_test_fill_buf(ddr_buf,BUF_LEN,LOCAL_CPU_WRITE_PATTERN_1);
1134 /* Check in the alternate cpu window (m4/c66x/a15) if it can see it (Physical memory). It shouldnt if cache is enabled. */
1135 OSAL_log("\nCheck in the alternate cpu window (m4/c66x/a15) if it can see it (Physical memory). It shouldn't appear as it is still in cache\n");
1137 OSAL_log("\nInvalidating cache.\n");
1138 /* Now OSAL_CacheInv() - Invalidates and writes back cache() */
1139 CacheP_Inv(ddr_buf,BUF_LEN*sizeof(uint32_t));
1141 OSAL_log("\nCheck in alternate cpu window (m4/c66x/a15) if it can see it (Physical memory). For A15 it should (Invalidate also writes back for A15), for others it should not \n");
1143 OSAL_log("\nNow write(%d 32-bit words) of pattern 0x%x on the alternate CPU physical memory window (a15/m4/c66x) \n",BUF_LEN,ALTERNATE_CPU_WRITE_PATTERN_1);
1144 OSAL_log("\nCheck if this pattern 0x%x has made it to the physical memory view of this cpu.It should. \n",ALTERNATE_CPU_WRITE_PATTERN_1);
1146 #if defined(__ARM_ARCH_7A__)
1147 /* The below invalidate test is to account for ARM prefetching. On A15 Cache Inv writes back too. To see any changes AFTER the DDR was
1148 externally modified, a Cache Invalidate is required */
1149 CacheP_Inv(ddr_buf,BUF_LEN*sizeof(uint32_t));
1150 #endif
1151 OSAL_log("\nChecking if local CPU read fetches the 0x%x value updated by the alternate cpu core\n",ALTERNATE_CPU_WRITE_PATTERN_1);
1152 /* Now read the value on A15 now */
1153 match=OSAL_cache_test_check_buf(ddr_buf,BUF_LEN,ALTERNATE_CPU_WRITE_PATTERN_1);
1154 if(match==TRUE) {
1155 OSAL_log("\nPattern matched. OSAL_CacheInv() Test passed\n");
1156 } else {
1157 OSAL_log("\n OSAL_CacheInv() Test failed\n");
1158 }
1160 /************************ TEST for CacheP_wb() *********************/
1161 OSAL_log("\n**** Testing Cache_WriteBack() ******\n");
1163 OSAL_log("\nWriting 0x%x local ddr memory\n",LOCAL_CPU_WRITE_PATTERN_2);
1164 /* local cpu- Write LOCAL_CPU_WRITE_PATTERN_2 in to ddr_buf[0] */
1165 OSAL_cache_test_fill_buf(ddr_buf,BUF_LEN,LOCAL_CPU_WRITE_PATTERN_2);
1167 OSAL_log("\nCheck in the alternate cpu window (m4/c66x/a15) if the pattern 0x%x can be seen it (Physical memory). It shouldn't appear as it is still in cache\n",LOCAL_CPU_WRITE_PATTERN_2);
1169 OSAL_log("\nWriting back cache.\n");
1170 /* Now OSAL_CacheWb() - Writes back cache() */
1171 CacheP_wb(ddr_buf,BUF_LEN*sizeof(uint32_t));
1173 /* Check in DSP window if it can see it (Physical memory). It should now. */
1174 OSAL_log("\nCheck in alternate cpu window (m4/c66x/a15) and verify that the 0x%x is seen in Physical memory\n",LOCAL_CPU_WRITE_PATTERN_2);
1176 /* If so, write back portion is tested. */
1177 OSAL_log("\nNow write the pattern 0x%x on the alternate CPU physical memory window (a15/m4/c66x) \n",ALTERNATE_CPU_WRITE_PATTERN_2);
1178 /* Since, on this local cpu, we just wrote back cache() only, and not invalidated, the ALTERNATE_CPU_WRITE_PATTERN_2 wont be seen in the local cpu's cached memory
1179 Read Variable on A15 to ensure CPU Read(). The value should be the old LOCAL_CPU_WRITE_PATTERN_2.. and NOT the ALTERNATE_CPU_WRITE_PATTERN_2.. which the alternate CPU wrote. */
1180 match=OSAL_cache_test_check_buf(ddr_buf,BUF_LEN,LOCAL_CPU_WRITE_PATTERN_2);
1181 if(match==TRUE) {
1182 OSAL_log("\nPattern matched. OSAL_Cache_Writeback() Test passed\n");
1183 } else {
1184 OSAL_log("\n OSAL_Cache_Writeback() Test failed\n");
1185 }
1187 /************************ TEST for CacheP_wbInv() *********************/
1188 OSAL_log("\n**** Testing Cache_WriteBack_Invalidate() ******\n");
1190 OSAL_log("\nWriting 0x%x local ddr memory\n",LOCAL_CPU_WRITE_PATTERN_3);
1192 /* local cpu- Write LOCAL_CPU_WRITE_PATTERN_3 in to ddr_buf[0] */
1193 OSAL_cache_test_fill_buf(ddr_buf,BUF_LEN,LOCAL_CPU_WRITE_PATTERN_3);
1195 OSAL_log("\nCheck in the alternate cpu window (m4/c66x/a15) if the pattern 0x%x can be seen it (Physical memory). It shouldn't appear as it is still in cache\n",LOCAL_CPU_WRITE_PATTERN_3);
1197 OSAL_log("\nWriting back cache and invalidating it.\n");
1199 /* Now OSAL_CacheWbInv() - Writes back cache and invalidate() */
1200 CacheP_wbInv(ddr_buf,BUF_LEN*sizeof(uint32_t));
1202 /* Check in DSP window if it can see it (Physical memory). It should now. */
1203 OSAL_log("\nCheck in alternate cpu window (m4/c66x/a15) and verify that the 0x%x is seen in Physical memory. If not it is a failure \n",LOCAL_CPU_WRITE_PATTERN_3);
1206 OSAL_log("\nNow write the pattern 0x%x on the alternate CPU physical memory window (a15/m4/c66x) \n",ALTERNATE_CPU_WRITE_PATTERN_3);
1208 #if defined(__ARM_ARCH_7A__)
1209 /* This is due to ARM prefetching */
1210 CacheP_Inv(ddr_buf,BUF_LEN*sizeof(uint32_t));
1211 #endif
1213 /* Since, on local cpu, we not only wrote back cache but also invalidated it,the local cpu should be able the alternate pattern now */
1214 match=OSAL_cache_test_check_buf(ddr_buf,BUF_LEN,ALTERNATE_CPU_WRITE_PATTERN_3);
1215 if(match==TRUE) {
1216 OSAL_log("\nPattern matched. OSAL_Cache_WritebackInvalidate() Test passed\n");
1217 } else {
1218 OSAL_log("\nOSAL_Cache_WritebackInvalidate() Test failed\n");
1219 }
1221 return(res);
1222 }
1223 #endif /* SOC_AM572x || SOC_AM574x */
1224 #endif /* MANUAL_CACHE_TEST */
1226 /*
1227 * ======== Extended memory block test function ========
1228 * This test aims at testing the create and delete functions that
1229 * are enhanced to support extended memory blocks for SemaphoreP and HwiP
1230 */
1231 #define OSAL_TEST_NUM_EXT_SEMAPHORES (1U)
1232 #define OSAL_TEST_NUM_EXT_HWIPS (1U)
1234 #if defined (BARE_METAL)
1235 #define SEMP_BLOCK_SIZE (OSAL_TEST_NUM_EXT_SEMAPHORES * OSAL_NONOS_SEMAPHOREP_SIZE_BYTES)
1236 #define HWIP_BLOCK_SIZE (OSAL_TEST_NUM_EXT_HWIPS * OSAL_NONOS_HWIP_SIZE_BYTES)
1237 uint8_t semPMemBlock[SEMP_BLOCK_SIZE];
1238 uint8_t hwiPMemBlock[HWIP_BLOCK_SIZE];
1239 #elif defined (FREERTOS)
1240 #define SEMP_BLOCK_SIZE (OSAL_TEST_NUM_EXT_SEMAPHORES * OSAL_FREERTOS_SEMAPHOREP_SIZE_BYTES)
1241 #if defined (BUILD_C7X)
1242 #define HWIP_BLOCK_SIZE (OSAL_TEST_NUM_EXT_HWIPS * OSAL_FREERTOS_HWIP_C7X_SIZE_BYTES)
1243 #else
1244 #define HWIP_BLOCK_SIZE (OSAL_TEST_NUM_EXT_HWIPS * OSAL_NONOS_HWIP_SIZE_BYTES)
1245 #endif
1246 uint8_t semPMemBlock[SEMP_BLOCK_SIZE]
1247 __attribute__ ((aligned(64)));
1248 uint8_t hwiPMemBlock[HWIP_BLOCK_SIZE]
1249 __attribute__ ((aligned(64)));
1250 #elif defined (SAFERTOS)
1251 #define SEMP_BLOCK_SIZE (OSAL_TEST_NUM_EXT_SEMAPHORES * OSAL_SAFERTOS_SEMAPHOREP_SIZE_BYTES)
1252 #if defined (BUILD_C7X)
1253 #define HWIP_BLOCK_SIZE (OSAL_TEST_NUM_EXT_HWIPS * OSAL_SAFERTOS_HWIP_C7X_SIZE_BYTES)
1254 #else
1255 #define HWIP_BLOCK_SIZE (OSAL_TEST_NUM_EXT_HWIPS * OSAL_NONOS_HWIP_SIZE_BYTES)
1256 #endif
1257 uint8_t semPMemBlock[SEMP_BLOCK_SIZE]
1258 __attribute__ ((aligned(64)));
1259 uint8_t hwiPMemBlock[HWIP_BLOCK_SIZE]
1260 __attribute__ ((aligned(64)));
1261 #endif
1264 static void myIsr(void)
1265 {
1266 }
1268 bool OSAL_ExtBlock_test(void)
1269 {
1270 SemaphoreP_Params semParams;
1271 HwiP_Params hwiParams;
1272 Osal_HwAttrs hwAttrs;
1273 int32_t osal_ret;
1274 uint32_t ctrlBitMap = ( OSAL_HWATTR_SET_SEMP_EXT_BASE |
1275 OSAL_HWATTR_SET_HWIP_EXT_BASE);
1276 SemaphoreP_Handle semHandle;
1277 HwiP_Handle hwiHandle;
1279 /* Set the timer base for the osal delay */
1280 osal_ret = Osal_getHwAttrs(&hwAttrs);
1281 if (osal_ret != osal_OK)
1282 {
1283 return (false);
1284 }
1286 /* This API should return osal_OK for AM3/AM4 and return unsupported for other Socs */
1287 hwAttrs.extSemaphorePBlock.base = (uintptr_t) &semPMemBlock[0];
1288 hwAttrs.extSemaphorePBlock.size = SEMP_BLOCK_SIZE;
1289 hwAttrs.extHwiPBlock.size = HWIP_BLOCK_SIZE;
1290 hwAttrs.extHwiPBlock.base = (uintptr_t) &hwiPMemBlock[0];
1291 osal_ret = Osal_setHwAttrs(ctrlBitMap, &hwAttrs);
1292 if (osal_ret != osal_OK)
1293 {
1294 return (false);
1295 }
1297 /* Default parameter initialization */
1298 SemaphoreP_Params_init(&semParams);
1300 /* create the semaphore block */
1301 semHandle = SemaphoreP_create(0, &semParams);
1302 if (semHandle == (SemaphoreP_Handle) NULL_PTR)
1303 {
1304 return (false);
1305 }
1307 /* Verify the block created is in the extended memory block range */
1308 if (semHandle != (SemaphoreP_Handle) &semPMemBlock[0])
1309 {
1310 return(false);
1311 }
1313 /* delete the semaphore block */
1314 osal_ret = SemaphoreP_delete(semHandle);
1315 if (osal_ret != (SemaphoreP_Status) SemaphoreP_OK)
1316 {
1317 return (false);
1318 }
1321 /* Default parameter initialization */
1322 HwiP_Params_init(&hwiParams);
1324 /* create the hwi block */
1325 hwiHandle = HwiP_create(8U, (HwiP_Fxn)myIsr, &hwiParams);
1326 if (hwiHandle == (HwiP_Handle) NULL_PTR)
1327 {
1328 return (false);
1329 }
1331 /* Verify the block created is in the extended memory block range */
1332 if (hwiHandle != (HwiP_Handle) &hwiPMemBlock[0])
1333 {
1334 return(false);
1335 }
1337 /* delete the hwi block */
1338 osal_ret = HwiP_delete(hwiHandle);
1339 if (osal_ret != (HwiP_Status) HwiP_OK)
1340 {
1341 return (false);
1342 }
1344 /* Clear the extended block base for next tests */
1345 /* This API should return osal_OK for AM3/AM4 and return unsupported for other Socs */
1346 hwAttrs.extSemaphorePBlock.base = (uintptr_t) NULL_PTR;
1347 hwAttrs.extSemaphorePBlock.size = 0;
1348 hwAttrs.extHwiPBlock.size = 0;
1349 hwAttrs.extHwiPBlock.base = (uintptr_t) NULL_PTR;
1350 osal_ret = Osal_setHwAttrs(ctrlBitMap, &hwAttrs);
1351 if (osal_ret != osal_OK)
1352 {
1353 return (false);
1354 }
1355 return(true);
1357 }
1360 /*
1361 * ======== Semaphore test function ========
1362 */
1363 bool OSAL_semaphore_test()
1364 {
1365 SemaphoreP_Params semParams;
1366 SemaphoreP_Handle handle1, handle2;
1368 SemaphoreP_Params_init(&semParams);
1370 /* Test 1: counting mode, no timeout */
1371 semParams.mode = SemaphoreP_Mode_COUNTING;
1372 handle1 = SemaphoreP_create(0, &semParams);
1373 if (handle1 == NULL_PTR)
1374 {
1375 return false;
1376 }
1377 if (SemaphoreP_post(handle1) != SemaphoreP_OK)
1378 {
1379 return false;
1380 }
1381 if (SemaphoreP_pend(handle1, 0) != SemaphoreP_OK)
1382 {
1383 return false;
1384 }
1386 /* Test 2: binary mode, with timeout */
1387 semParams.mode = SemaphoreP_Mode_BINARY;
1388 handle2 = SemaphoreP_create(1, &semParams);
1389 if (handle2 == NULL_PTR)
1390 {
1391 return false;
1392 }
1393 if (SemaphoreP_pend(handle2, 0) != SemaphoreP_OK)
1394 {
1395 return false;
1396 }
1397 if (SemaphoreP_pend(handle2, 10) != SemaphoreP_TIMEOUT)
1398 {
1399 return false;
1400 }
1402 /* SemaphoreP_delete is not available in Safertos */
1403 if (SemaphoreP_delete(handle1) != SemaphoreP_OK)
1404 {
1405 return false;
1406 }
1408 if (SemaphoreP_delete(handle2) != SemaphoreP_OK)
1409 {
1410 return false;
1411 }
1413 return true;
1414 }
1416 #if !defined(BARE_METAL)
1418 /*
1419 * ======== Queue test function ========
1420 */
1421 typedef struct Test_Queue_Buf_s
1422 {
1423 QueueP_Elem lnk;
1424 uint32_t index;
1425 uint8_t* pkt;
1427 } Test_Queue_Buf;
1429 bool OSAL_queue_test()
1430 {
1431 QueueP_Params params;
1432 QueueP_Handle handle;
1433 Test_Queue_Buf buf[10], *pBuf;
1434 QueueP_Status status;
1435 uint32_t i;
1437 QueueP_Params_init(¶ms);
1439 handle = QueueP_create(¶ms);
1441 if (handle == NULL_PTR)
1442 {
1443 OSAL_log("Failed to create queue \n");
1444 return false;
1445 }
1447 for (i = 0; i < 10; i++)
1448 {
1449 buf[i].index = i;
1450 buf[i].pkt = NULL;
1451 }
1453 /* Test 1: queue push/pop test */
1454 for (i = 0; i < 10; i++)
1455 {
1456 status = QueueP_put(handle, (QueueP_Elem *)&buf[i]);
1457 if(QueueP_OK != status)
1458 {
1459 OSAL_log("Failed to push to queue \n");
1460 return false;
1461 }
1462 }
1464 for (i = 0; i < 10; i++)
1465 {
1466 pBuf = (Test_Queue_Buf *)QueueP_get(handle);
1468 if (pBuf == NULL_PTR)
1469 {
1470 OSAL_log("Failed to pop queue element %d \n", i);
1471 return false;
1472 }
1474 if (pBuf->index != i)
1475 {
1476 OSAL_log("Pop element %d, but expect %d \n", pBuf->index, i);
1477 return false;
1479 }
1480 }
1482 /* Test 2: queue empty test */
1483 /* After poping all the pushed elements, queue should be empty */
1484 if (QueueP_EMPTY != QueueP_isEmpty(handle))
1485 {
1486 OSAL_log("Empty queue check failed\n");
1487 return false;
1488 }
1490 /* When called with an empty queue, QueueP_get should return a pointer to the queue itself */
1491 pBuf = QueueP_get(handle);
1493 if (pBuf != NULL)
1494 {
1495 OSAL_log("Queue is still not empty with element %p, handle %p \n", pBuf, handle);
1496 return false;
1497 }
1499 status = QueueP_delete(handle);
1500 if(QueueP_OK != status)
1501 {
1502 OSAL_log("Failed to delete queue \n");
1503 return false;
1504 }
1506 return true;
1507 }
1509 /*
1510 * ======== Event test function ========
1511 */
1512 bool OSAL_event_test()
1513 {
1514 EventP_Params params;
1515 EventP_Handle handle;
1516 EventP_Status status;
1517 uint32_t eventMask;
1518 uint32_t retEventMask;
1520 EventP_Params_init(¶ms);
1522 handle = EventP_create(¶ms);
1524 if (handle == NULL_PTR)
1525 {
1526 OSAL_log("Failed to create event \n");
1527 return false;
1528 }
1530 /* Test 1: event post test */
1531 eventMask = EventP_ID_00 + EventP_ID_02 + EventP_ID_04 + EventP_ID_05;
1532 status = EventP_post(handle, eventMask);
1533 if(EventP_OK != status)
1534 {
1535 OSAL_log("Failed to post an event \n");
1536 return false;
1537 }
1539 /* Test 2: event wait with AND logic test */
1540 eventMask = EventP_ID_00 + EventP_ID_02;
1541 retEventMask = EventP_wait(handle, eventMask, EventP_WaitMode_ALL, EventP_WAIT_FOREVER);
1542 if((retEventMask & eventMask) != eventMask)
1543 {
1544 OSAL_log("EventP_wait returned %d, but expect %d \n", retEventMask, eventMask);
1545 return false;
1546 }
1548 /* Test 3: EventP_wait Timeout test */
1549 /* Event 0 should be cleared since its already consumed */
1550 eventMask = EventP_ID_00 + EventP_ID_04;
1551 retEventMask = EventP_wait(handle, eventMask, EventP_WaitMode_ALL, EventP_NO_WAIT);
1552 if((retEventMask & eventMask) == eventMask)
1553 {
1554 OSAL_log("EventP_wait Timeout test failed \n");
1555 OSAL_log("EventP_wait returned %d, but expect %d \n", retEventMask, 0);
1556 return false;
1557 }
1559 /* Test 4: event wait with OR logic test */
1560 eventMask = EventP_ID_00 + EventP_ID_04;
1561 retEventMask = EventP_wait(handle, eventMask, EventP_WaitMode_ANY, EventP_WAIT_FOREVER);
1562 if((retEventMask & eventMask) != EventP_ID_04)
1563 {
1564 OSAL_log("EventP_wait returned %d, but expect %d \n", retEventMask, EventP_ID_04);
1565 return false;
1566 }
1568 /* Test 5: event get posted events test */
1569 retEventMask = EventP_getPostedEvents(handle);
1570 if((retEventMask & EventP_ID_05) != EventP_ID_05)
1571 {
1572 OSAL_log("EventP_getPostedEvents returned %d, but expect %d \n", retEventMask, EventP_ID_05);
1573 return false;
1574 }
1576 status = EventP_delete(&handle);
1577 if(EventP_OK != status)
1578 {
1579 OSAL_log("Failed to delete event \n");
1580 return false;
1581 }
1583 return true;
1584 }
1586 /*
1587 * ======== Mutex test function ========
1588 */
1589 #define OSAL_MUTEX_TEST_ITERATIONS (10U)
1590 #define OSAL_MUTEX_TEST_TASK_PRIO (1U)
1591 #if defined(SOC_TPR12) || defined (SOC_AWR294X)
1592 #define OSAL_MUTEX_TEST_NUM_TASKS (2U)
1593 #else
1594 #define OSAL_MUTEX_TEST_NUM_TASKS (5U)
1595 #endif
1597 #if defined(SAFERTOS)
1598 static uint8_t gAppTskStackMutexTask[OSAL_MUTEX_TEST_NUM_TASKS][APP_TSK_STACK_MAIN] __attribute__((aligned(APP_TSK_STACK_MAIN)));
1599 #else
1600 static uint8_t gAppTskStackMutexTask[OSAL_MUTEX_TEST_NUM_TASKS][APP_TSK_STACK_MAIN] __attribute__((aligned(32)));
1601 #endif
1603 uint32_t gCnt = 0U;
1604 bool gMutexTestStatus = TRUE;
1606 void mutexTestFxn(MutexP_Handle mutexHandle, SemaphoreP_Handle hDoneSem)
1607 {
1608 uint32_t idx;
1609 uint32_t temp;
1610 MutexP_Status status = MutexP_OK;
1612 for(idx = 0U; idx < OSAL_MUTEX_TEST_ITERATIONS; idx++)
1613 {
1614 status = MutexP_lock(mutexHandle, MutexP_WAIT_FOREVER);
1615 if(MutexP_OK != status)
1616 {
1617 OSAL_log("Failed to lock mutex \n");
1618 gMutexTestStatus = FALSE;
1619 }
1621 temp = ++gCnt;
1622 {
1623 /* Force a task switch to verify mutex lock effect */
1624 TaskP_yield();
1625 }
1626 gCnt = temp;
1628 status = MutexP_unlock(mutexHandle);
1629 if(MutexP_OK != status)
1630 {
1631 OSAL_log("Failed to unlock mutex \n");
1632 gMutexTestStatus = FALSE;
1633 }
1634 }
1636 SemaphoreP_post(hDoneSem);
1637 }
1639 bool OSAL_mutex_test()
1640 {
1641 TaskP_Params taskParams;
1642 TaskP_Handle hMutexTestTask[OSAL_MUTEX_TEST_ITERATIONS];
1643 SemaphoreP_Params semPrms;
1644 SemaphoreP_Handle hDoneSem;
1645 MutexP_Status status = MutexP_OK;
1646 uint32_t i;
1648 MutexP_Object mutexObj;
1649 MutexP_Handle mutexHandle;
1651 mutexHandle = MutexP_create(&mutexObj);
1652 if (mutexHandle == NULL_PTR)
1653 {
1654 OSAL_log("Failed to create mutex \n");
1655 return false;
1656 }
1658 /* Create semaphore to signal completion of mutex tasks */
1659 SemaphoreP_Params_init(&semPrms);
1660 semPrms.mode = SemaphoreP_Mode_COUNTING;
1661 hDoneSem = SemaphoreP_create(0U, &semPrms);
1663 /* Create tasks */
1664 for(i = 0U; i < OSAL_MUTEX_TEST_NUM_TASKS; i++)
1665 {
1666 TaskP_Params_init(&taskParams);
1667 memset( &gAppTskStackMutexTask[i], 0xFF, sizeof( gAppTskStackMutexTask[i] ) );
1668 taskParams.priority = OSAL_MUTEX_TEST_TASK_PRIO;
1669 taskParams.stack = &gAppTskStackMutexTask[i];
1670 taskParams.stacksize = APP_TSK_STACK_MAIN;
1671 taskParams.arg0 = mutexHandle;
1672 taskParams.arg1 = hDoneSem;
1673 hMutexTestTask[i] = TaskP_create(&mutexTestFxn, &taskParams);
1674 }
1676 /* Wait for tasks completion */
1677 for(i = 0U; i < OSAL_MUTEX_TEST_NUM_TASKS; i++)
1678 {
1679 SemaphoreP_pend(hDoneSem, SemaphoreP_WAIT_FOREVER);
1680 }
1682 if(gCnt != (OSAL_MUTEX_TEST_NUM_TASKS * OSAL_MUTEX_TEST_ITERATIONS))
1683 {
1684 OSAL_log("Mutex Lock Test Failed.\n Expected Count = %d. Actual Count = %d. \n",
1685 (uint32_t)(OSAL_MUTEX_TEST_NUM_TASKS * OSAL_MUTEX_TEST_ITERATIONS),
1686 (uint32_t)gCnt);
1687 gMutexTestStatus = FALSE;
1688 }
1690 Osal_delay(OSAL_DELAY_TIME);
1691 /* Delete tasks */
1692 for(i = 0U; i < OSAL_MUTEX_TEST_NUM_TASKS; i++)
1693 {
1694 TaskP_delete(&hMutexTestTask[i]);
1695 }
1697 /* Delete Semaphore */
1698 SemaphoreP_delete(hDoneSem);
1699 hDoneSem = NULL;
1701 status = MutexP_delete(mutexHandle);
1702 if(MutexP_OK != status)
1703 {
1704 OSAL_log("Failed to delete mutex \n");
1705 gMutexTestStatus = FALSE;
1706 }
1708 return gMutexTestStatus;
1709 }
1711 #endif /* #if !defined(BARE_METAL) && !defined (SAFERTOS) */
1713 #if defined(FREERTOS)
1714 /*
1715 * ======== Load test function ========
1716 */
1717 #define OSAL_LOAD_TEST_TASK_PRIO (1U)
1718 #define OSAL_LOAD_TEST_NUM_TASKS (3U)
1720 static uint8_t gAppTskStackLoadTask[OSAL_LOAD_TEST_NUM_TASKS+1][APP_TSK_STACK_MAIN] __attribute__((aligned(32)));
1722 TaskP_Handle hLoadTestTask[OSAL_LOAD_TEST_NUM_TASKS+1];
1724 static bool loadPrint()
1725 {
1726 uint32_t i;
1727 LoadP_Status status = LoadP_OK;
1728 LoadP_Stats loadStatsTask[OSAL_LOAD_TEST_NUM_TASKS+1];
1729 uint32_t cpuLoad;
1731 /* Query Load stats for each task and print % load */
1732 for(i = 0U; i <= OSAL_LOAD_TEST_NUM_TASKS; i++)
1733 {
1734 status += LoadP_getTaskLoad(hLoadTestTask[i], &loadStatsTask[i]);
1736 if(loadStatsTask[i].percentLoad > 0U)
1737 {
1738 OSAL_log(" %s - Load = %d%% \n", loadStatsTask[i].name, loadStatsTask[i].percentLoad);
1739 }
1740 else
1741 {
1742 /* Load less than 1%, Try to get fractional part */
1743 OSAL_log(" %s - Load = 0.000%d%% \n", loadStatsTask[i].name, loadStatsTask[i].threadTime/(loadStatsTask[i].totalTime/(100*1000)));
1744 }
1745 }
1746 if(LoadP_OK != status)
1747 {
1748 OSAL_log("Failed to get tasks load measurement \n");
1749 return false;
1750 }
1752 /* Query CPU Load */
1753 cpuLoad = LoadP_getCPULoad();
1754 OSAL_log("\n CPU Load = %d%% \n\n", cpuLoad);
1756 return true;
1757 }
1759 static void loadPrintFxn(SemaphoreP_Handle hDoneSem, void *arg1)
1760 {
1761 uint32_t printIntervalInMs = 500;
1763 while(1)
1764 {
1765 TaskP_sleepInMsecs(printIntervalInMs);
1767 /* Check for signal to exit */
1768 if(SemaphoreP_OK == SemaphoreP_pend(hDoneSem, SemaphoreP_NO_WAIT))
1769 {
1770 break;
1771 }
1773 OSAL_log("** Intermediate Load Stats ** \n");
1774 loadPrint();
1775 }
1776 }
1778 void loadTestFxn(SemaphoreP_Handle hSignalSem, void *arg1)
1779 {
1780 /* Wait for signal to start */
1781 SemaphoreP_pend(hSignalSem, SemaphoreP_WAIT_FOREVER);
1783 while(1)
1784 {
1785 /* Check for signal to exit */
1786 if(SemaphoreP_OK == SemaphoreP_pend(hSignalSem, SemaphoreP_NO_WAIT))
1787 {
1788 break;
1789 }
1790 };
1792 }
1794 bool OSAL_load_test()
1795 {
1796 TaskP_Params taskParams;
1797 SemaphoreP_Params semPrms;
1798 SemaphoreP_Handle hDoneSem;
1799 SemaphoreP_Handle hTaskSignalSem[OSAL_LOAD_TEST_NUM_TASKS];
1800 TaskP_Handle hPrintTask;
1801 uint32_t i;
1802 char *taskNameStr[] = { "Task A", "Task B", "Task C"};
1803 bool status = true;
1805 /* Create semaphore to signal completion of load tasks */
1806 SemaphoreP_Params_init(&semPrms);
1807 semPrms.mode = SemaphoreP_Mode_COUNTING;
1808 hDoneSem = SemaphoreP_create(0U, &semPrms);
1810 /* Reset Load measurement */
1811 LoadP_reset();
1813 /* Create tasks and signal semaphores*/
1814 for(i = 0U; i < OSAL_LOAD_TEST_NUM_TASKS; i++)
1815 {
1816 SemaphoreP_Params_init(&semPrms);
1817 semPrms.mode = SemaphoreP_Mode_COUNTING;
1818 hTaskSignalSem[i] = SemaphoreP_create(0U, &semPrms);
1820 TaskP_Params_init(&taskParams);
1821 taskParams.priority = OSAL_LOAD_TEST_TASK_PRIO;
1822 taskParams.name = (const char *)taskNameStr[i];
1823 taskParams.stack = &gAppTskStackLoadTask[i];
1824 taskParams.stacksize = APP_TSK_STACK_MAIN;
1825 taskParams.arg0 = hTaskSignalSem[i];
1826 hLoadTestTask[i] = TaskP_create(&loadTestFxn, &taskParams);
1827 }
1828 hLoadTestTask[OSAL_LOAD_TEST_NUM_TASKS] = TaskP_self();
1830 /* Create print task, to print the load in regular intervals */
1831 TaskP_Params_init(&taskParams);
1832 taskParams.priority = OSAL_LOAD_TEST_TASK_PRIO + 2U;
1833 taskParams.stack = &gAppTskStackLoadTask[i];
1834 taskParams.stacksize = APP_TSK_STACK_MAIN;
1835 taskParams.arg0 = hDoneSem;
1836 hPrintTask = TaskP_create(&loadPrintFxn, &taskParams);
1838 /* ==============================================================================
1839 * Stay in while loop of Task A for ~2s, (Expected Task Load:......2s/7s = ~28%)
1840 * followed by Task B for ~1s, (Expected Task Load:......1s/7s = ~14%)
1841 * followed by Task C for ~0.5s(Expected Task Load:.....0.5/7s = ~7%)
1842 * And finally go to idle mode for ~3.5s(Expected CPU Load :(7-3.5)s/7s = ~50%)
1843 * ------------------------------------------------------------------------------
1844 * Total Time: ~(2s+1s+0.5+3.5s) = ~7s |
1845 * =============================================================================*/
1846 {
1847 uint32_t waitTimeInMsec[OSAL_LOAD_TEST_NUM_TASKS] = {2000, 1000, 500};
1848 uint32_t idleTimeInMsec = 3500;
1850 for(i = 0U; i < OSAL_LOAD_TEST_NUM_TASKS; i++)
1851 {
1852 /* Signal start */
1853 SemaphoreP_post(hTaskSignalSem[i]);
1854 /* Spin in Task 'i' */
1855 TaskP_sleepInMsecs(waitTimeInMsec[i]);
1856 /* Signal exit */
1857 SemaphoreP_post(hTaskSignalSem[i]);
1858 }
1860 TaskP_sleepInMsecs(idleTimeInMsec);
1861 }
1863 SemaphoreP_post(hDoneSem);
1865 OSAL_log("*************** FINAL LOAD STATS ************* \n");
1866 status = loadPrint();
1868 /* Delete tasks and signal semaphores */
1869 for(i = 0U; i < OSAL_LOAD_TEST_NUM_TASKS; i++)
1870 {
1871 TaskP_delete(&hLoadTestTask[i]);
1872 SemaphoreP_delete(hTaskSignalSem[i]);
1873 }
1874 /* Delete Print Task */
1875 TaskP_delete(&hPrintTask);
1877 /* Delete Semaphore */
1878 SemaphoreP_delete(hDoneSem);
1879 hDoneSem = NULL;
1881 return status;
1882 }
1884 #endif /* #if defined(FREERTOS) */
1887 #if defined(USE_BIOS)
1889 /*
1890 * ======== SWI test function ========
1891 */
1892 volatile bool gFlagSwi;
1893 void mySwiFxn(uintptr_t arg0, uintptr_t arg1)
1894 {
1895 gFlagSwi = 1U;
1896 }
1898 bool OSAL_swi_test()
1899 {
1900 SwiP_Handle handle;
1901 SwiP_Params swiParams;
1902 SwiP_Status status;
1903 bool retVal = true;
1905 SwiP_Params_init(&swiParams);
1906 handle = SwiP_create((SwiP_Fxn)&mySwiFxn, &swiParams);
1907 if (handle == NULL_PTR)
1908 {
1909 OSAL_log("Failed to create software interrupt \n");
1910 retVal = false;
1911 }
1913 if (retVal == true)
1914 {
1915 gFlagSwi = 0;
1916 status = SwiP_post(handle);
1917 if (status != SwiP_OK)
1918 {
1919 OSAL_log("Failed to post software interrupt \n");
1920 retVal = false;
1921 }
1922 }
1924 if (retVal == true)
1925 {
1926 gTestlocalTimeout = 0x300000U;
1927 while (gTestlocalTimeout != 0U)
1928 {
1929 gTestlocalTimeout--;
1930 if (gFlagSwi)
1931 {
1932 gFlagSwi = 0;
1933 retVal = true;
1934 break;
1935 }
1936 }
1938 if (gTestlocalTimeout == 0)
1939 {
1940 OSAL_log("Failed to get software interrupt \n");
1941 retVal = false;
1942 }
1943 }
1945 if (retVal == true)
1946 {
1947 status = SwiP_delete(&handle);
1948 if (status != SwiP_OK)
1949 {
1950 OSAL_log("Failed to delete software interrupt \n");
1951 retVal = false;
1952 }
1953 }
1955 return (retVal);
1956 }
1957 #endif
1959 #if ENABLE_DEBUG_LOG_TEST
1960 bool OSAL_log_test()
1961 {
1962 bool retVal = true;
1964 OSAL_log("BegugP Log test starts!\n");
1966 DebugP_log0 ("debugP_log0 run successfully\n");
1967 DebugP_log1 ("debugP_log1 run with %u argument uccessfully\n", 1U);
1968 DebugP_log2 ("debugP_log2 run with %u arguments (2, %d) successfully\n", 2U, 2);
1969 DebugP_log3 ("debugP_log3 run with %u arguments (3, %d, %d) successfully\n", 3U, 3, 3);
1970 DebugP_log4 ("debugP_log4 run with %u arguments (4, %d, %d, 0x%x) successfully\n", 4U, 4, 4, 64);
1972 return (retVal);
1973 }
1974 #endif
1976 #ifndef BARE_METAL
1977 #if defined(USE_BIOS)
1978 #include <ti/sysbios/knl/Clock.h>
1979 #endif
1980 #ifndef SIM_BUILD
1981 #define OSAL_TASKP_TEST_ITERATION (10U)
1982 #define OSAL_TASKP_TEST_1MS (1000U)
1983 #define OSAL_TASKP_TEST_TICKS (1000U)
1984 #else
1985 #define OSAL_TASKP_TEST_ITERATION (2U)
1986 #define OSAL_TASKP_TEST_1MS (10U)
1987 #define OSAL_TASKP_TEST_TICKS (10U)
1988 #endif
1990 uint64_t OSAL_get_ticks()
1991 {
1992 uint64_t ticks;
1993 #if defined(FREERTOS)
1994 ticks = (uint64_t)portGET_RUN_TIME_COUNTER_VALUE();
1995 #elif defined(SAFERTOS)
1996 ticks = (uint64_t)TimerP_getTimeInUsecs();
1997 #else
1998 ticks = (uint64_t)Clock_getTicks();
1999 #endif
2000 return ticks;
2001 }
2003 bool OSAL_task_sleep_test(void)
2004 {
2005 int32_t i;
2006 uint64_t start_time_nticks, end_time_nticks;
2007 uint32_t diff_nticks, diff_tout;
2009 /* nTicks in OSAL is 1000 ticks per milli seconds
2010 * hence the task sleep = 1000 milliseconds should
2011 * provide the same sleep time as in TaskP_sleep(nTicks = 1000)
2012 */
2013 start_time_nticks = OSAL_get_ticks();
2015 for (i=0; i < OSAL_TASKP_TEST_ITERATION; i++)
2016 {
2017 TaskP_sleep(OSAL_TASKP_TEST_TICKS);
2018 }
2019 end_time_nticks = OSAL_get_ticks();
2020 diff_nticks = (uint32_t)(end_time_nticks - start_time_nticks);
2022 start_time_nticks = OSAL_get_ticks();
2024 for (i=0; i < OSAL_TASKP_TEST_ITERATION; i++)
2025 {
2026 TaskP_sleepInMsecs(OSAL_TASKP_TEST_1MS);
2027 }
2028 end_time_nticks = OSAL_get_ticks();
2029 diff_tout = (uint32_t)(end_time_nticks - start_time_nticks);
2031 OSAL_log(" \n \
2032 diff_nticks = %d \n \
2033 diff_tout = %d \n ", diff_nticks, diff_tout);
2034 #if defined(USE_BIOS)
2035 OSAL_log(" Clock_tickPeriod = %d \n \
2036 Clock_tickSource = %d ", Clock_tickPeriod, Clock_tickSource);
2037 #endif
2039 return (true);
2041 }
2042 #endif
2044 #if defined(FREERTOS)
2045 bool OSAL_mempry_test()
2046 {
2047 void *memPtr1, *memPtr2, *memPtr[5];
2048 uint32_t align;
2049 bool retVal = true;
2050 uint32_t i;
2052 /* Test1: Allocate 16 bytes aligned memory. */
2053 align = 16;
2054 memPtr1 = MemoryP_ctrlAlloc(100, align);
2055 if (memPtr1 != NULL)
2056 {
2057 /* Check if teh allocated mempry is 16 bytes aligned. */
2058 if (((uintptr_t)memPtr1 & (align - 1)) != 0)
2059 {
2060 retVal = false;
2061 }
2062 }
2063 else
2064 {
2065 retVal = false;
2066 }
2068 /* Test2: Allocate 64 bytes aligned memory. */
2069 align = 64;
2070 memPtr2 = MemoryP_ctrlAlloc(200, align);
2071 if (memPtr2 != NULL)
2072 {
2073 /* Check if teh allocated mempry is 16 bytes aligned. */
2074 if (((uintptr_t)memPtr2 & (align - 1)) != 0)
2075 {
2076 retVal = false;
2077 }
2078 }
2079 else
2080 {
2081 retVal = false;
2082 }
2084 if (memPtr1 != NULL)
2085 {
2086 MemoryP_ctrlFree(memPtr1, 100);
2087 }
2088 if (memPtr2 != NULL)
2089 {
2090 MemoryP_ctrlFree(memPtr2, 200);
2091 }
2093 /* Test2: check memory leak
2094 * multiple iteration of alloc and free to give same mem pointer.
2095 */
2096 for (i=0; i<5; i++)
2097 {
2098 align = 64;
2099 memPtr[i] = MemoryP_ctrlAlloc(200, align);
2100 MemoryP_ctrlFree(memPtr[i], 200);
2101 }
2102 for (i=1; i<5; i++)
2103 {
2104 if (memPtr[i] != memPtr[i-1])
2105 {
2106 retVal = false;
2107 break;
2108 }
2109 }
2110 return retVal;
2111 }
2112 #endif
2114 /*
2115 * ======== main test function ========
2116 */
2117 #if defined(BARE_METAL)
2118 void osal_test()
2119 #else
2120 void osal_test(void *arg0, void *arg1)
2121 #endif
2122 {
2123 bool testFail = false;
2124 Osal_StaticMemStatus pMemStats;
2126 Board_initOSAL();
2128 #if defined (BUILD_C7X)
2129 C7x_ConfigureTimerOutput();
2130 #endif
2132 #ifdef BUILD_M4F
2133 OSAL_log("\n M4 test \n");
2134 #endif
2136 #if defined(BUILD_C66X)
2137 /* To set C66 timer interrupts on J7ES */
2138 C66xTimerInterruptInit();
2139 #endif
2141 OSAL_log(" OSAL Test Starting...\n Takes about 30 seconds ...\n");
2143 #if defined(BARE_METAL)
2144 /* No TASKP test for BAREmetal */
2145 #else
2146 /* TASK Sleep APIs test for RTOS */
2147 if (OSAL_task_sleep_test() == true)
2148 {
2149 OSAL_log("\n TaskP tests have passed. \n");
2150 }
2151 else
2152 {
2153 OSAL_log("\n TaskP tests have failed. \n");
2154 }
2155 #endif
2157 if(OSAL_hwi_test() == true)
2158 {
2159 OSAL_log("\n HWI tests have passed. \n");
2160 }
2161 else
2162 {
2163 OSAL_log("\n HWI tests have failed. \n");
2164 testFail = true;
2165 }
2167 #ifdef ENABLE_TIMER_TEST
2168 if(OSAL_timer_test() == true)
2169 {
2170 OSAL_log("\n Timer tests have passed. \n");
2171 }
2172 else
2173 {
2174 OSAL_log("\n Timer tests have failed. \n");
2175 testFail = true;
2176 }
2177 #endif
2179 /* The test does not support below SoCs */
2180 #if !defined(SOC_TDA2XX) && !defined(SOC_TDA2PX) && !defined(SOC_TDA2EX) && !defined(SOC_TDA3XX)
2181 OSAL_log("\n Running Osal_Delay test:");
2183 if(Osal_delay_test() == true)
2184 {
2185 OSAL_log("\n Osal_Delay tests have passed. \n");
2186 }
2187 else
2188 {
2189 OSAL_log("\n Osal_Delay tests have failed. \n");
2190 testFail = true;
2191 }
2192 #endif
2194 #ifdef ENABLE_GET_TIME_TEST
2195 OSAL_log("\n Running Osal_getTime test:");
2197 if(Osal_getTime_test() == true)
2198 {
2199 OSAL_log("\n Osal_getTime tests have passed. \n");
2200 }
2201 else
2202 {
2203 OSAL_log("\n Osal_getTime tests have failed. \n");
2204 testFail = true;
2205 }
2206 #endif
2208 if(OSAL_clock_test() == true)
2209 {
2210 OSAL_log("\n Clock tests have passed. \n");
2211 }
2212 else
2213 {
2214 OSAL_log("\n Clock tests have failed. \n");
2215 testFail = true;
2216 }
2218 if(OSAL_semaphore_test() == true)
2219 {
2220 OSAL_log("\n Semaphore tests have passed. \n");
2221 }
2222 else
2223 {
2224 OSAL_log("\n Semaphore tests have failed. \n");
2225 testFail = true;
2226 }
2228 #ifdef ENABLE_EXT_BLOCK_TEST
2230 if(OSAL_ExtBlock_test() == true)
2231 {
2232 OSAL_log("\n Extended Memory Block tests for HwiP/SwiP have passed. \n");
2233 }
2234 else
2235 {
2236 OSAL_log("\n Extended Memory Block tests for HwiP/SwiP have failed. \n");
2237 testFail = true;
2238 }
2239 #endif
2241 #ifdef MANUAL_CACHE_TEST
2242 /* This test is valid only for MANUAL testing */
2243 OSAL_cache_test();
2244 #endif
2246 /* Now print the static memory statistics */
2247 if(Osal_getStaticMemStatus(&pMemStats) == osal_OK)
2248 {
2249 OSAL_log("\n Semaphore Statistics: \
2250 \n PeakSemObjs = %u, \
2251 \n numMaxSemObjs = %u, \
2252 \n numFreeSemObjs = %u \n", \
2253 pMemStats.peakSemObjs, \
2254 pMemStats.numMaxSemObjs, \
2255 pMemStats.numFreeSemObjs);
2257 OSAL_log("\n Hwi Statistics: \
2258 \n PeakHwiObjs = %u, \
2259 \n numMaxHwiObjs = %u, \
2260 \n numFreeHwiObjs = %u \n", \
2261 pMemStats.peakHwiObjs, \
2262 pMemStats.numMaxHwiObjs, \
2263 pMemStats.numFreeHwiObjs);
2265 OSAL_log("\n Timer Statistics: \
2266 \n PeakTimerObjs = %u, \
2267 \n numMaxTimerObjs = %u, \
2268 \n numFreeTimerObjs = %u \n", \
2269 pMemStats.peakTimerObjs, \
2270 pMemStats.numMaxTimerObjs, \
2271 pMemStats.numFreeTimerObjs);
2273 }
2274 else
2275 {
2276 testFail = true;
2277 OSAL_log("\n Memory Statistics query failed \n");
2278 }
2280 #if defined(USE_BIOS)
2281 if(OSAL_swi_test() == true)
2282 {
2283 OSAL_log("\n SWI tests have passed. \n");
2284 }
2285 else
2286 {
2287 OSAL_log("\n SWI tests have failed. \n");
2288 testFail = true;
2289 }
2290 #endif
2292 #if !defined(BARE_METAL)
2293 /* No QueueP,EventP,MutexP tests for Baremetal */
2294 if(OSAL_queue_test() == true)
2295 {
2296 OSAL_log("\n Queue tests have passed. \n");
2297 }
2298 else
2299 {
2300 OSAL_log("\n Queue tests have failed. \n");
2301 testFail = true;
2302 }
2304 if(OSAL_event_test() == true)
2305 {
2306 OSAL_log("\n Event tests have passed. \n");
2307 }
2308 else
2309 {
2310 OSAL_log("\n Event tests have failed. \n");
2311 testFail = true;
2312 }
2314 if(OSAL_mutex_test() == true)
2315 {
2316 OSAL_log("\n Mutex tests have passed. \n");
2317 }
2318 else
2319 {
2320 OSAL_log("\n Mutex tests have failed. \n");
2321 testFail = true;
2322 }
2323 #endif /* #if !defined(BARE_METAL) && !defined (SAFERTOS) */
2325 #if defined(FREERTOS)
2326 OSAL_log(" \n OSAL Load Test Starting...\n Takes about 10 seconds ...\n\n");
2327 if(OSAL_load_test() == true)
2328 {
2329 OSAL_log("\n Load tests have passed. \n");
2330 }
2331 else
2332 {
2333 OSAL_log("\n Load tests have failed. \n");
2334 testFail = true;
2335 }
2336 #endif /* #if defined(FREERTOS) */
2338 #if ENABLE_DEBUG_LOG_TEST
2339 if(OSAL_log_test() == true)
2340 {
2341 OSAL_log("\n DebugP Log tests have passed. \n");
2342 }
2343 else
2344 {
2345 OSAL_log("\n DebugP Log tests have failed. \n");
2346 testFail = true;
2347 }
2348 #endif
2350 #if defined(FREERTOS)
2351 if(OSAL_mempry_test() == true)
2352 {
2353 OSAL_log("\n MemoryP Log tests have passed. \n");
2354 }
2355 else
2356 {
2357 OSAL_log("\n MemoryP Log tests have failed. \n");
2358 testFail = true;
2359 }
2360 #endif
2362 #if !defined (BARE_METAL)
2363 if (OSAL_floating_point_test() == true)
2364 {
2365 OSAL_log("\n Floating point tests have passed. \n");
2366 }
2367 else
2368 {
2369 testFail = true;
2370 }
2371 #endif
2373 if(testFail == true)
2374 {
2375 OSAL_log("\n Some tests have failed. \n");
2376 }
2377 else
2378 {
2379 OSAL_log("\n All tests have passed. \n");
2380 }
2382 #ifdef BARE_METAL
2383 while (1)
2384 {
2385 }
2386 #endif
2388 }
2390 #ifdef BUILD_C7X
2391 void sysIdleLoop(void)
2392 {
2393 __asm(" IDLE");
2394 }
2396 #include <ti/csl/csl_clec.h>
2398 void C7x_ConfigureTimerOutput()
2399 {
2400 CSL_ClecEventConfig cfgClec;
2401 CSL_CLEC_EVTRegs *clecBaseAddr = (CSL_CLEC_EVTRegs*)OSAL_TEST_CLEC_BASE_ADDRESS;
2403 uint32_t input = OSAL_TEST_TIMER_EVENT_NUM; /* Used for Timer Interrupt */
2404 uint32_t corepackEvent = OSAL_TEST_TIMER_INT_NUM;
2406 /* Configure CLEC */
2407 cfgClec.secureClaimEnable = FALSE;
2408 cfgClec.evtSendEnable = TRUE;
2409 cfgClec.rtMap = CSL_CLEC_RTMAP_CPU_ALL;
2410 cfgClec.extEvtNum = 0;
2411 cfgClec.c7xEvtNum = corepackEvent;
2412 CSL_clecClearEvent(clecBaseAddr, input);
2413 CSL_clecConfigEventLevel(clecBaseAddr, input, 0); /* configure interrupt as pulse */
2414 CSL_clecConfigEvent(clecBaseAddr, input, &cfgClec);
2416 }
2418 #endif
2420 #if defined(BUILD_C66X)
2422 /* To set C66 timer interrupts on J7ES */
2423 void C66xTimerInterruptInit(void)
2424 {
2425 /* Map DMTimer interrupt to C6xx events through DMSC RM API. */
2426 #if defined (_TMS320C6X) && !defined(SOC_TPR12) && !defined (SOC_AWR294X)
2427 /* DMTimers used by OS */
2428 struct tisci_msg_rm_irq_set_req rmIrqReq;
2429 struct tisci_msg_rm_irq_set_resp rmIrqResp;
2430 #if !defined(SAFERTOS)
2431 /* SAFERTOS already configured IR for Timer Interrupts as a part of OS_init*/
2432 rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
2433 TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
2434 rmIrqReq.src_id = OSAL_TEST_OS_TIMER_TISCI_ID;
2435 rmIrqReq.src_index = 0U;
2436 rmIrqReq.dst_id = OSAL_TEST_CORE_TISCI_ID;
2437 rmIrqReq.dst_host_irq = OSAL_TEST_OS_TIMER_EVENT_NUM;
2438 /* Unused params */
2439 rmIrqReq.global_event = 0U;
2440 rmIrqReq.ia_id = 0U;
2441 rmIrqReq.vint = 0U;
2442 rmIrqReq.vint_status_bit_index = 0U;
2443 rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
2445 Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
2446 #endif
2447 /* DMTimers used for OSAL Timer Test */
2448 rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
2449 TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
2450 rmIrqReq.src_id = OSAL_TEST_TIMER_TISCI_ID;
2451 rmIrqReq.src_index = 0U;
2452 rmIrqReq.dst_id = OSAL_TEST_CORE_TISCI_ID;
2453 rmIrqReq.dst_host_irq = OSAL_TEST_TIMER_EVENT_NUM;
2454 /* Unused params */
2455 rmIrqReq.global_event = 0U;
2456 rmIrqReq.ia_id = 0U;
2457 rmIrqReq.vint = 0U;
2458 rmIrqReq.vint_status_bit_index = 0U;
2459 rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
2461 Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
2463 #endif
2464 }
2466 void sysIdleLoop(void)
2467 {
2468 __asm(" IDLE");
2469 }
2471 #endif
2473 /*
2474 * ======== main ========
2475 */
2476 int main(void)
2477 {
2479 #ifdef BARE_METAL
2480 osal_test();
2481 #else
2482 /* All other platforms have the task created under RTSC cfg file
2483 * hence not needed to be created again as below
2484 * For AM65XX TPR12 and J7 the common RTSC cfg file is used and hence there is
2485 * no test application specific task is created in teh RTSC cfg file
2486 */
2487 #if defined (SOC_AM65XX) || defined (SOC_J721E) || defined(SOC_J7200) || defined(SOC_TPR12) || defined (SOC_AWR294X)|| defined(SOC_AM64X) || defined(SOC_J721S2) || defined(SOC_J784S4)
2488 TaskP_Params taskParams;
2490 #if defined(USE_BIOS)
2491 Error_Block eb;
2492 #endif
2493 OS_init();
2494 memset( gAppTskStackMain, 0xFF, sizeof( gAppTskStackMain ) );
2495 TaskP_Params_init(&taskParams);
2496 taskParams.priority =2;
2497 taskParams.stack = gAppTskStackMain;
2498 taskParams.stacksize = sizeof (gAppTskStackMain);
2499 #if defined(USE_BIOS)
2500 taskParams.pErrBlk = &eb;
2501 #endif
2502 TaskP_create(&osal_test, &taskParams);
2503 #endif
2504 OS_start();
2505 #endif
2506 return (0);
2507 }
2509 #if defined(BUILD_MPU) || defined (BUILD_C7X)
2510 extern void Osal_initMmuDefault(void);
2511 void InitMmu(void)
2512 {
2513 Osal_initMmuDefault();
2514 }
2515 #endif