[processor-sdk/pdk.git] / packages / ti / transport / ndk / nimu / example / src / main_icev2AM335x.c
1 /*
2 * Copyright (C) 2015 - 2018 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
15 * distribution.
16 *
17 * Neither the name of Texas Instruments Incorporated nor the names of
18 * its contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
35 /* ========================================================================== */
36 /* Include Files */
37 /* ========================================================================== */
39 #include <stdio.h>
40 #include <string.h>
41 #include <stdlib.h>
42 #include <xdc/std.h>
43 #include <xdc/runtime/Error.h>
44 #include <xdc/runtime/System.h>
45 #include <ti/sysbios/BIOS.h>
46 #include <ti/sysbios/knl/Task.h>
47 #include <ti/sysbios/family/arm/a8/Mmu.h>
49 #include <ti/ndk/inc/stkmain.h>
51 #include <ti/drv/emac/emac_drv.h>
52 #include <ti/drv/emac/src/v4/emac_drv_v4.h>
54 #include <ti/starterware/include/types.h>
55 #include <ti/starterware/include/hw/hw_types.h>
56 #include <ti/starterware/include/hw/hw_control_am335x.h>
57 #include <ti/starterware/include/hw/soc_am335x.h>
58 #include <ti/starterware/include/ethernet.h>
59 #include <ti/starterware/include/soc_control.h>
61 #include <ti/board/board.h>
63 /* TI-RTOS Header files */
64 #include <ti/drv/i2c/I2C.h>
65 #include <ti/drv/i2c/soc/I2C_v1.h>
67 /* UART Header files */
68 #include <ti/drv/uart/UART.h>
69 #include <ti/drv/uart/UART_stdio.h>
71 #include <ti/drv/gpio/GPIO.h>
72 #include <ti/drv/gpio/soc/GPIO_v1.h>
74 extern char *LocalIPAddr;
75 extern void app_stats(UArg arg0, UArg arg1);
77 /* Enable the below macro to have prints on the IO Console */
78 //#define IO_CONSOLE
80 #ifndef IO_CONSOLE
81 #define NIMU_log UART_printf
82 #else
83 #define NIMU_log printf
84 #endif
86 /* ========================================================================== */
87 /* Macros */
88 /* ========================================================================== */
90 /**Phy address of the CPSW port 1*/
91 #define EMAC_CPSW_PORT0_PHY_ADDR_ICE2 1
92 /**Phy address of the CPSW port 1*/
93 #define EMAC_CPSW_PORT1_PHY_ADDR_ICE2 3
96 #define MAX_TABLE_ENTRIES 3
98 /* ========================================================================== */
99 /* Global Variables */
100 /* ========================================================================== */
102 /* GPIO pin value definitions */
103 #define GPIO_PIN_VAL_LOW (0U)
104 #define GPIO_PIN_VAL_HIGH (1U)
106 /* Port and pin number mask for GPIO Load pin.
107 Bits 7-0: Pin number and Bits 15-8: (Port number + 1) */
108 #define GPIO_PR1_MII_CTRL_PIN_NUM (0x04)
109 #define GPIO_MUX_MII_CTRL_PIN_NUM (0x0A)
110 #define GPIO_FET_SWITCH_CTRL_PIN_NUM (0x07)
111 #define GPIO_DDR_VTT_EN_PIN_NUM (0x12)
112 #define GPIO_PHY_0_1_RST_PIN_NUM (0x05)
113 #define GPIO_PR1_MII_CTRL_PORT_NUM (0x03)
114 #define GPIO_MUX_MII_CTRL_PORT_NUM (0x03)
115 #define GPIO_FET_SWITCH_CTRL_PORT_NUM (0x00)
116 #define GPIO_DDR_VTT_EN_PORT_NUM (0x00)
117 #define GPIO_PHY_0_1_RST_PORT_NUM (0x02)
119 /* ON Board LED pins which are connected to GPIO pins. */
120 typedef enum GPIO_PIN {
121 GPIO_PIN_PR1_MII_CTRL = 0U,
122 GPIO_PIN_MUX_MII_CTRL = 1U,
123 GPIO_PIN_FET_SWITCH_CTRL = 2U,
124 GPIO_PIN_DDR_VTT_EN = 3U,
125 GPIO_PIN_PHY_0_1_RST = 4U,
126 GPIO_PIN_COUNT
127 }GPIO_PIN;
129 /* GPIO Driver board specific pin configuration structure */
130 GPIO_PinConfig gpioPinConfigs[] = {
131 /* Output pin : AM335X_ICE V2_LD_PIN */
132 GPIO_DEVICE_CONFIG((GPIO_PR1_MII_CTRL_PORT_NUM + 1), GPIO_PR1_MII_CTRL_PIN_NUM) | GPIO_CFG_OUTPUT,
133 GPIO_DEVICE_CONFIG((GPIO_MUX_MII_CTRL_PORT_NUM + 1), GPIO_MUX_MII_CTRL_PIN_NUM) | GPIO_CFG_OUTPUT,
134 GPIO_DEVICE_CONFIG((GPIO_FET_SWITCH_CTRL_PORT_NUM + 1), GPIO_FET_SWITCH_CTRL_PIN_NUM)| GPIO_CFG_OUTPUT,
135 GPIO_DEVICE_CONFIG((GPIO_DDR_VTT_EN_PORT_NUM + 1), GPIO_DDR_VTT_EN_PIN_NUM) | GPIO_CFG_OUTPUT,
136 GPIO_DEVICE_CONFIG((GPIO_PHY_0_1_RST_PORT_NUM + 1), GPIO_PHY_0_1_RST_PIN_NUM) | GPIO_CFG_OUTPUT,
137 };
139 /* GPIO Driver call back functions */
140 GPIO_CallbackFxn gpioCallbackFunctions[] = {
141 NULL,
142 NULL,
143 NULL,
144 NULL,
145 NULL
146 };
148 /* GPIO Driver configuration structure */
149 GPIO_v1_Config GPIO_v1_config = {
150 gpioPinConfigs,
151 gpioCallbackFunctions,
152 sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
153 sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
154 0,
155 };
157 /**Task handle for EIP*/
158 Task_Handle main_task;
160 static int nimu_device_index = 0U;
162 //MAC_CONFIG mac_configuration;
164 NIMU_DEVICE_TABLE_ENTRY NIMUDeviceTable[MAX_TABLE_ENTRIES];
166 void TaskFxn(UArg a0, UArg a1);
167 uint32_t ClockSynthesizerSetup(void);
168 extern int CpswEmacInit (STKEVENT_Handle hEvent);
169 extern const I2C_Config I2C_config[];
170 extern void SOCCtrlGetPortMacAddr(uint32_t portNum, uint8_t *pMacAddr);
172 extern void PhySetupAndReset(void);
175 /**
176 * \name main
177 * \brief Main Function
178 * \param none
179 * \return none
180 *
181 */
182 int main()
183 {
184 /* Call board init functions */
185 Board_initCfg boardCfg;
186 Task_Params taskParams;
187 EMAC_HwAttrs_V4 cfg;
188 nimu_device_index = 0U;
190 boardCfg = BOARD_INIT_PINMUX_CONFIG |
191 BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO;
192 Board_init(boardCfg);
194 ClockSynthesizerSetup();
196 /* Init GPIO driver */
197 GPIO_init();
199 /* Chip configuration MII/RMII selection */
200 PhySetupAndReset();
202 SOCCtrlCpswPortMacModeSelect(1, ETHERNET_MAC_TYPE_RMII);
203 SOCCtrlCpswPortMacModeSelect(2, ETHERNET_MAC_TYPE_RMII);
205 EMAC_socGetInitCfg(0, &cfg);
206 cfg.port[0].phy_addr = EMAC_CPSW_PORT0_PHY_ADDR_ICE2;
207 cfg.port[1].phy_addr = EMAC_CPSW_PORT1_PHY_ADDR_ICE2;
208 cfg.macModeFlags = EMAC_CPSW_CONFIG_MODEFLG_FULLDUPLEX| EMAC_CPSW_CONFIG_MODEFLG_IFCTLA;
209 EMAC_socSetInitCfg(0, &cfg);
212 Task_Params_init(&taskParams);
213 taskParams.priority = 1;
214 taskParams.stackSize = 0x1400;
215 main_task = Task_create (TaskFxn, &taskParams, NULL);
217 Task_Params_init(&taskParams);
218 taskParams.priority = 9;
219 taskParams.instance->name = "EmacStats";
220 Task_create(app_stats, &taskParams, NULL);
222 NIMUDeviceTable[nimu_device_index++].init = &CpswEmacInit ;
223 NIMUDeviceTable[nimu_device_index].init = NULL ;
225 BIOS_start();
227 return -1;
228 }
230 /**
231 * \name TaskFxn
232 * \brief Task which do EIP initialization
233 * \param a0
234 * \param a1
235 * \return none
236 *
237 */
238 void TaskFxn(UArg a0, UArg a1)
239 {
240 NIMU_log("\n\rSYS/BIOS Ethernet/IP (CPSW) Sample application, EVM IP address: %s\n\r", LocalIPAddr);
241 #ifdef NIMU_FTP_APP
242 ftpserver_init();
243 #endif
244 }
246 /** \brief Macro indicating the i2c time out value. */
247 #define I2C_TIMEOUT_VAL (100U)
249 /* Delay function */
250 static void delay(unsigned int delayValue);
253 /*
254 * ======== Delay function ========
255 */
256 void delay(unsigned int delayValue)
257 {
258 volatile uint32_t delay1 = delayValue*10000;
259 while (delay1--) ;
260 }
262 /* I2C Instance Controlling Clock Synthesizer */
263 #define CLOCK_SYNTHESIZER_I2C_INST_NUM 0
265 /* Clock Synthesizer Device Address */
266 #define CLOCK_SYNTHESIZER_I2C_ADDR 0x65
268 #define CLOCK_SYNTHESIZER_ID_REG 0
270 /* Crystal load capacitor selection */
271 #define CLOCK_SYNTHESIZER_XCSEL 0x05
273 /* PLL1 Configuration Register */
274 #define CLOCK_SYNTHESIZER_MUX_REG 0x14
276 /* PDIV2 */
277 #define CLOCK_SYNTHESIZER_PDIV2_REG 0x16
279 /* PDIV3 */
280 #define CLOCK_SYNTHESIZER_PDIV3_REG 0x17
282 #define TX_LENGTH (2U)
283 #define RX_LENGTH (10U)
285 uint32_t ClockSynthesizerSetup(void)
286 {
287 uint32_t status = TRUE;
288 uint32_t regValue = 0U;
289 I2C_Params i2cParams;
290 I2C_Handle handle = NULL;
291 I2C_Transaction i2cTransaction;
292 char txBuf[TX_LENGTH] = {0x00, 0x01};
293 char rxBuf[RX_LENGTH] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
294 0x00, 0x00};
296 I2C_init();
298 I2C_Params_init(&i2cParams);
300 ((I2C_HwAttrs *) I2C_config[CLOCK_SYNTHESIZER_I2C_INST_NUM].hwAttrs)->enableIntr = false;
301 handle = I2C_open(CLOCK_SYNTHESIZER_I2C_INST_NUM, &i2cParams);
303 /* Initializing I2C transaction params to default value */
304 I2C_transactionInit(&i2cTransaction);
306 /* Read - CLOCK_SYNTHESIZER_ID_REG */
308 if (FALSE != status)
309 {
310 txBuf[0] = CLOCK_SYNTHESIZER_ID_REG | 0x80U;
311 i2cTransaction.slaveAddress = CLOCK_SYNTHESIZER_I2C_ADDR;
312 i2cTransaction.writeBuf = (uint8_t *)&txBuf[0];
313 i2cTransaction.writeCount = 1U;
314 i2cTransaction.readBuf = (uint8_t *)&rxBuf[0];
315 i2cTransaction.readCount = 0U;
316 status = I2C_transfer(handle, &i2cTransaction);
318 if(FALSE == status)
319 {
320 NIMU_log("\n CLOCK_SYNTHESIZER_ID_REG: Data Write failed. \n");
321 }
322 }
324 delay(I2C_TIMEOUT_VAL);
326 if (FALSE != status)
327 {
328 i2cTransaction.slaveAddress = CLOCK_SYNTHESIZER_I2C_ADDR;
329 i2cTransaction.writeBuf = (uint8_t *)&txBuf[0];
330 i2cTransaction.writeCount = 0U;
331 i2cTransaction.readBuf = (uint8_t *)&rxBuf[0];
332 i2cTransaction.readCount = 1U;
333 status = I2C_transfer(handle, &i2cTransaction);
335 if(FALSE == status)
336 {
337 NIMU_log("\n CLOCK_SYNTHESIZER_ID_REG: Data Read failed. \n");
338 }
339 else
340 {
341 regValue = rxBuf[0];
342 }
343 }
345 delay(I2C_TIMEOUT_VAL);
347 if((regValue & 0x81U)!= 0x81U)
348 {
349 NIMU_log("\n Clock synthesizer: Read: Failed");
350 status = FALSE;
351 }
353 /** CDCE913 Clock Synthesizer configuration for RMII Clock = 50 MHz
354 * fout = fin/Pdiv x N/M
355 * fout = 50 MHz
356 * fin = 25 MHz
357 * Pdiv = 2
358 * N = 4
359 * M = 1
360 */
362 /* Crystal load Capacitor Selection - 18pF: 0x12h(bits 7:3) */
364 /* Write - CLOCK_SYNTHESIZER_XCSEL */
366 if (FALSE != status)
367 {
368 txBuf[0] = CLOCK_SYNTHESIZER_XCSEL | 0x80U;
369 txBuf[1] = 0x90U;
370 i2cTransaction.slaveAddress = CLOCK_SYNTHESIZER_I2C_ADDR;
371 i2cTransaction.writeBuf = (uint8_t *)&txBuf[0];
372 i2cTransaction.writeCount = 2U;
373 i2cTransaction.readBuf = (uint8_t *)&rxBuf[0];
374 i2cTransaction.readCount = 0U;
375 status = I2C_transfer(handle, &i2cTransaction);
377 if(FALSE == status)
378 {
379 NIMU_log("\n CLOCK_SYNTHESIZER_XCSEL: Data Write failed. \n");
380 }
381 }
383 delay(I2C_TIMEOUT_VAL);
385 if (FALSE == status)
386 {
387 NIMU_log("\n Clock synthesizer: Write: Failed");
388 }
390 /* PLL1 Multiplexer b7:0 (PLL1) */
392 /* Write - CLOCK_SYNTHESIZER_MUX_REG */
394 if (FALSE != status)
395 {
396 txBuf[0] = CLOCK_SYNTHESIZER_MUX_REG | 0x80U;
397 txBuf[1] = 0x6DU;
398 i2cTransaction.slaveAddress = CLOCK_SYNTHESIZER_I2C_ADDR;
399 i2cTransaction.writeBuf = (uint8_t *)&txBuf[0];
400 i2cTransaction.writeCount = 2U;
401 i2cTransaction.readBuf = (uint8_t *)&rxBuf[0];
402 i2cTransaction.readCount = 0U;
403 status = I2C_transfer(handle, &i2cTransaction);
405 if(FALSE == status)
406 {
407 NIMU_log("\n CLOCK_SYNTHESIZER_MUX_REG: Data Write failed. \n");
408 }
409 }
411 delay(I2C_TIMEOUT_VAL);
413 if (FALSE == status)
414 {
415 NIMU_log("\n Clock synthesizer: Write: Failed");
416 }
418 /** b7-0(PLL1 SSC down selection by default),
419 * b6:0-0x02h(7-bit Y2-Output-Divider Pdiv2)
420 */
422 /* Write - CLOCK_SYNTHESIZER_PDIV2_REG */
424 if (FALSE != status)
425 {
426 txBuf[0] = CLOCK_SYNTHESIZER_PDIV2_REG | 0x80U;
427 txBuf[1] = 0x02U;
428 i2cTransaction.slaveAddress = CLOCK_SYNTHESIZER_I2C_ADDR;
429 i2cTransaction.writeBuf = (uint8_t *)&txBuf[0];
430 i2cTransaction.writeCount = 2U;
431 i2cTransaction.readBuf = (uint8_t *)&rxBuf[0];
432 i2cTransaction.readCount = 0U;
433 status = I2C_transfer(handle, &i2cTransaction);
435 if(FALSE == status)
436 {
437 NIMU_log("\n CLOCK_SYNTHESIZER_PDIV2_REG: Data Write failed. \n");
438 }
439 }
441 delay(I2C_TIMEOUT_VAL);
443 if (FALSE == status)
444 {
445 NIMU_log("\n Clock synthesizer: Write: Failed");
446 }
448 /* b6:0-0x02h(7-bit Y3-Output-Divider Pdiv3) */
450 /* Write - CLOCK_SYNTHESIZER_PDIV3_REG */
452 if (FALSE != status)
453 {
454 txBuf[0] = CLOCK_SYNTHESIZER_PDIV3_REG | 0x80U;
455 txBuf[1] = 0x02U;
456 i2cTransaction.slaveAddress = CLOCK_SYNTHESIZER_I2C_ADDR;
457 i2cTransaction.writeBuf = (uint8_t *)&txBuf[0];
458 i2cTransaction.writeCount = 2U;
459 i2cTransaction.readBuf = (uint8_t *)&rxBuf[0];
460 i2cTransaction.readCount = 0U;
461 status = I2C_transfer(handle, &i2cTransaction);
463 if(FALSE == status)
464 {
465 NIMU_log("\n CLOCK_SYNTHESIZER_PDIV3_REG: Data Write failed. \n");
466 }
467 }
469 delay(I2C_TIMEOUT_VAL);
471 if (FALSE == status)
472 {
473 NIMU_log("\n Clock synthesizer: Write: Failed");
474 }
476 I2C_close(handle);
478 return status;
479 }
481 void PhySetupAndReset(void)
482 {
483 /* PR1_MII_CTL */
484 GPIO_write(GPIO_PIN_PR1_MII_CTRL, GPIO_PIN_VAL_HIGH);
486 /* MUX MII CONTROL */
487 GPIO_write(GPIO_PIN_MUX_MII_CTRL, GPIO_PIN_VAL_HIGH);
489 /* FET SWITCH CONTROL */
490 GPIO_write(GPIO_PIN_FET_SWITCH_CTRL, GPIO_PIN_VAL_HIGH);
492 /* DDR VTT ENABLE */
493 GPIO_write(GPIO_PIN_DDR_VTT_EN, GPIO_PIN_VAL_HIGH);
495 /* Phy 0 & 1 reset */
496 GPIO_write(GPIO_PIN_PHY_0_1_RST, GPIO_PIN_VAL_LOW);
497 delay(100);
498 GPIO_write(GPIO_PIN_PHY_0_1_RST, GPIO_PIN_VAL_HIGH);
499 delay(100);
500 }