[PDK-8586] SBL: OSPI: Early CAN response optimization

[processor-sdk/pdk.git] / packages / ti / boot / sbl / board / k3 / sbl_main.c

diff --git a/packages/ti/boot/sbl/board/k3/sbl_main.c b/packages/ti/boot/sbl/board/k3/sbl_main.c
old mode 100644 (file)
new mode 100755 (executable)
index c559fd7..dc1fc6d
--- a/packages/ti/boot/sbl/board/k3/sbl_main.c
+++ b/packages/ti/boot/sbl/board/k3/sbl_main.c
@@ -275,123 +275,30 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
         .memAttr          = 0U,
     },
     {
-        /* Region 6 configuration: Covers first 32MB of EVM Flash (FSS DAT0) */
+        /* Region 6 configuration: Covers first 64MB of EVM Flash (FSS DAT0) */
         .regionId         = 6U,
         .enable           = 1U,
         .baseAddr         = 0x50000000,
-        .size             = CSL_ARM_R5_MPU_REGION_SIZE_32MB,
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_64MB,
         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
         .exeNeverControl  = 0U,
         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
         .shareable        = 0U,
         .cacheable        = (uint32_t)TRUE,
-        .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
-        .memAttr          = 0U,
-    },
-    {
-        /* Region 7 configuration: Covers next 16MB of EVM Flash (FSS DAT0) */
-        .regionId         = 7U,
-        .enable           = 1U,
-        .baseAddr         = 0x52000000,
-        .size             = CSL_ARM_R5_MPU_REGION_SIZE_16MB,
-        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
-        .exeNeverControl  = 0U,
-        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
-        .shareable        = 0U,
-        .cacheable        = (uint32_t)TRUE,
-        .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
-        .memAttr          = 0U,
-    },
-    {
-        /* Region 8 configuration: Covers next 8MB of EVM Flash (FSS DAT0) */
-        .regionId         = 8U,
-        .enable           = 1U,
-        .baseAddr         = 0x53000000,
-        .size             = CSL_ARM_R5_MPU_REGION_SIZE_8MB,
-        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
-        .exeNeverControl  = 0U,
-        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
-        .shareable        = 0U,
-        .cacheable        = (uint32_t)TRUE,
-        .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
-        .memAttr          = 0U,
-    },
-    {
-        /* Region 9 configuration: Covers next 4MB of EVM Flash (FSS DAT0) */
-        .regionId         = 9U,
-        .enable           = 1U,
-        .baseAddr         = 0x53800000,
-        .size             = CSL_ARM_R5_MPU_REGION_SIZE_4MB,
-        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
-        .exeNeverControl  = 0U,
-        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
-        .shareable        = 0U,
-        .cacheable        = (uint32_t)TRUE,
-        .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
-        .memAttr          = 0U,
-    },
-    {
-        /* Region 10 configuration: Covers next 2MB of EVM Flash (FSS DAT0) */
-        .regionId         = 10U,
-        .enable           = 1U,
-        .baseAddr         = 0x53C00000,
-        .size             = CSL_ARM_R5_MPU_REGION_SIZE_2MB,
-        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
-        .exeNeverControl  = 0U,
-        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
-        .shareable        = 0U,
-        .cacheable        = (uint32_t)TRUE,
-        .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
-        .memAttr          = 0U,
-    },
-    {
-        /* Region 11 configuration: Covers next 1MB of EVM Flash (FSS DAT0) */
-        .regionId         = 11U,
-        .enable           = 1U,
-        .baseAddr         = 0x53E00000,
-        .size             = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
-        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
-        .exeNeverControl  = 0U,
-        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
-        .shareable        = 0U,
-        .cacheable        = (uint32_t)TRUE,
-        .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
-        .memAttr          = 0U,
-    },
-    {
-        /* Region 12 configuration: Covers next 512KB of EVM Flash (FSS DAT0) */
-        .regionId         = 12U,
-        .enable           = 1U,
-        .baseAddr         = 0x53F00000,
-        .size             = CSL_ARM_R5_MPU_REGION_SIZE_512KB,
-        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
-        .exeNeverControl  = 0U,
-        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
-        .shareable        = 0U,
-        .cacheable        = (uint32_t)TRUE,
-        .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
-        .memAttr          = 0U,
-    },
-    {
-        /* Region 13 configuration: Covers next 256KB of EVM Flash (FSS DAT0) */
-        .regionId         = 13U,
-        .enable           = 1U,
-        .baseAddr         = 0x53F80000,
-        .size             = CSL_ARM_R5_MPU_REGION_SIZE_256KB,
-        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
-        .exeNeverControl  = 0U,
-        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
-        .shareable        = 0U,
-        .cacheable        = (uint32_t)TRUE,
-        .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
         .memAttr          = 0U,
     },
     {
         /* Region 14 configuration (Non-cached for PHY tuning data): Covers last 256KB of EVM Flash (FSS DAT0) */
-        .regionId         = 14U,
+        .regionId         = 7U,
         .enable           = 1U,
+#if defined(SOC_J7200)
         .baseAddr         = 0x53FC0000,
         .size             = CSL_ARM_R5_MPU_REGION_SIZE_256KB,
+#else
+        .baseAddr         = 0x53FE0000,
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_128KB,
+#endif
         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
         .exeNeverControl  = 0U,
         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
@@ -405,7 +312,7 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
     },
     {
         /* Region 15 configuration: 128 MB FSS DAT1 */
-        .regionId         = 15U,
+        .regionId         = 8U,
         .enable           = 1U,
         .baseAddr         = 0x58000000,
         .size             = CSL_ARM_R5_MPU_REGION_SIZE_128MB,