diff --git a/packages/ti/boot/sbl/soc/k3/sbl_slave_core_boot.c b/packages/ti/boot/sbl/soc/k3/sbl_slave_core_boot.c
index 859d73df3aa793101b5a9f0650d20b79dddfc47a..8199b43c04ae0b4b4a35f98ed89feb875e3d4366 100644 (file)
SBL_DEV_ID_DSP2_C7X,
SBL_CLK_ID_DSP2_C7X,
SBL_DSP2_C7X_FREQ_HZ,
+ },
+ /* M4F Core0 info*/
+ {
+ SBL_PROC_ID_M4F_CPU0,
+ SBL_DEV_ID_M4F_CPU0,
+ SBL_CLK_ID_M4F_CPU0,
+ SBL_M4F_CPU0_FREQ_HZ,
}
};
SBL_MCU3_CPU1_ATCM_BASE_ADDR_SOC
};
+#if !defined(SOC_AM65XX)
static const uint32_t SblBtcmAddr[] =
{
SBL_MCU_BTCM_BASE,
SBL_MCU3_CPU0_BTCM_BASE_ADDR_SOC,
SBL_MCU3_CPU1_BTCM_BASE_ADDR_SOC
};
+#endif
/* ========================================================================== */
/* Internal Functions */
/* ========================================================================== */
-static void SBL_RequestAllCores(void)
+static void SBL_RequestCore(cpu_core_id_t core_id)
{
#if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
- uint32_t i;
+ int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
int32_t status = CSL_EFAIL;
- uint32_t num_cpus = sizeof(sbl_slave_core_info)/ sizeof(sblSlaveCoreInfo_t);
- SBL_ADD_PROFILE_POINT;
+#if defined(SOC_AM64X)
+ /* Do not touch the M4 if reset isolation is enabled */
+ uint32_t mmrMagicRegister;
+ mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
+ if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
+ {
+ return;
+ }
+#endif
- for (i = 0; i < num_cpus; i++)
+ if (proc_id != 0xBAD00000)
{
- if(sbl_slave_core_info[i].tisci_proc_id != 0xBAD00000)
+ SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootRequestProcessor, ProcId 0x%x... \n", proc_id);
+
+ status = Sciclient_procBootRequestProcessor(proc_id, SCICLIENT_SERVICE_WAIT_FOREVER);
+ if (status != CSL_PASS)
{
- SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootRequestProcessor, ProcId 0x%x... \n", sbl_slave_core_info[i].tisci_proc_id);
- status = Sciclient_procBootRequestProcessor(sbl_slave_core_info[i].tisci_proc_id, SCICLIENT_SERVICE_WAIT_FOREVER);
- if (status != CSL_PASS)
- {
- SBL_log(SBL_LOG_ERR, "Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", sbl_slave_core_info[i].tisci_proc_id);
- SblErrLoop(__FILE__, __LINE__);
- }
+ SBL_log(SBL_LOG_ERR, "Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", proc_id);
+ SblErrLoop(__FILE__, __LINE__);
}
}
+#endif
+
+ return;
+}
+
+static void SBL_RequestAllCores(void)
+{
+#if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
+ cpu_core_id_t core_id;
+ uint32_t num_cores = sizeof(sbl_slave_core_info)/ sizeof(sblSlaveCoreInfo_t);
+
+ SBL_ADD_PROFILE_POINT;
+
+ for (core_id = 0; core_id < num_cores; core_id++)
+ {
+ SBL_RequestCore(core_id);
+ }
SBL_ADD_PROFILE_POINT;
#endif
return;
}
-static void SBL_ReleaseAllCores(void)
+static void SBL_ReleaseCore (cpu_core_id_t core_id, uint32_t reqFlag)
{
#if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
- uint32_t i;
+ int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
int32_t status = CSL_EFAIL;
- uint32_t num_cpus = sizeof(sbl_slave_core_info)/sizeof(sblSlaveCoreInfo_t);
- SBL_ADD_PROFILE_POINT;
+#if defined(SOC_AM64X)
+ /* Do not touch the M4 if reset isolation is enabled */
+ uint32_t mmrMagicRegister;
+ mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
+ if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
+ {
+ return;
+ }
+#endif
- for (i = 0; i < num_cpus; i++)
+ if(proc_id != 0xBAD00000)
{
- if(sbl_slave_core_info[i].tisci_proc_id != 0xBAD00000)
+ SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", proc_id);
+ status = Sciclient_procBootReleaseProcessor(proc_id, reqFlag, SCICLIENT_SERVICE_WAIT_FOREVER);
+
+ if (status != CSL_PASS)
{
- SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", sbl_slave_core_info[i].tisci_proc_id);
- status = Sciclient_procBootReleaseProcessor(sbl_slave_core_info[i].tisci_proc_id, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
- if (status != CSL_PASS)
- {
- SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", sbl_slave_core_info[i].tisci_proc_id);
- SblErrLoop(__FILE__, __LINE__);
- }
+ SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", proc_id);
+ SblErrLoop(__FILE__, __LINE__);
}
}
+#endif
+
+ return;
+}
+
+static void SBL_ReleaseAllCores(void)
+{
+#if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
+ cpu_core_id_t core_id;
+ uint32_t num_cores = sizeof(sbl_slave_core_info)/sizeof(sblSlaveCoreInfo_t);
+
+ SBL_ADD_PROFILE_POINT;
+
+ for (core_id = 0; core_id < num_cores; core_id++)
+ {
+ SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
+ }
SBL_ADD_PROFILE_POINT;
#endif
@@ -289,12 +342,12 @@ static void SBL_ConfigMcuLockStep(uint8_t enableLockStep, const sblSlaveCoreInfo
if (enableLockStep)
{
- SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling Lockstep mode...\n");
+ SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling Lockstep mode...\n", cpuStatus.processor_id);
proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
}
else
{
- SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling split mode...\n");
+ SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling split mode...\n", cpuStatus.processor_id);
proc_set_config_req.config_flags_1_clear |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
}
@@ -303,8 +356,7 @@ static void SBL_ConfigMcuLockStep(uint8_t enableLockStep, const sblSlaveCoreInfo
status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
- SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
- SblErrLoop(__FILE__, __LINE__);
+ SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg lockstep...NOT DONE \n");
}
SBL_ADD_PROFILE_POINT;
@@ -312,7 +364,7 @@ static void SBL_ConfigMcuLockStep(uint8_t enableLockStep, const sblSlaveCoreInfo
return;
}
-int32_t SBL_ImageCopy(sblEntryPoint_t *pEntry)
+int32_t SBL_BootImage(sblEntryPoint_t *pEntry)
{
int32_t retval = 0;
cpu_core_id_t core_id;
{
int32_t status = CSL_EFAIL;
uint8_t runLockStep = 0;
+ uint8_t mcuModeConfigured = 0;
struct tisci_msg_proc_get_status_resp cpuStatus;
struct tisci_msg_proc_set_config_req proc_set_config_req;
const sblSlaveCoreInfo_t *sblSlaveCoreInfoPtr;
SBL_ADD_PROFILE_POINT;
+#if defined(SOC_AM64X)
+ /* Do not touch the M4 if reset isolation is enabled */
+ uint32_t mmrMagicRegister;
+ mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
+ if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
+ {
+ return;
+ }
+#endif
+
/* Remap virtual core-ids if needed */
switch (core_id)
{
if(runLockStep)
{
- SBL_log(SBL_LOG_MAX, "Detected locktep for core_id %d, proc_id 0x%x... \n", core_id, sblSlaveCoreInfoPtr->tisci_proc_id);
+ SBL_log(SBL_LOG_MAX, "Detected lockstep for core_id %d, proc_id 0x%x... \n", core_id, sblSlaveCoreInfoPtr->tisci_proc_id);
SBL_ConfigMcuLockStep(SBL_ENABLE_MCU_LOCKSTEP, sblSlaveCoreInfoPtr);
+ mcuModeConfigured = 1;
}
switch (core_id)
case MCU1_CPU1_ID:
case MCU2_CPU1_ID:
case MCU3_CPU1_ID:
- SBL_log(SBL_LOG_MAX, "Switching core id %d, proc_id 0x%x to split mode %d... \n", core_id-1, sbl_slave_core_info[core_id-1].tisci_proc_id);
+ SBL_log(SBL_LOG_MAX, "Switching core id %d, proc_id 0x%x to split mode... \n", core_id-1, sbl_slave_core_info[core_id-1].tisci_proc_id);
/* Image for second MCU core present, disable lock step for the cluster */
SBL_ConfigMcuLockStep(SBL_DISABLE_MCU_LOCKSTEP, &(sbl_slave_core_info[core_id-1]));
+ mcuModeConfigured = 1;
/* DOnt break, fall through for enabling TCMs */
case MCU1_CPU0_ID:
case MCU2_CPU0_ID:
case MCU3_CPU0_ID:
+ if (!mcuModeConfigured)
+ {
+ SBL_log(SBL_LOG_MAX, "Switching core id %d, proc_id 0x%x to split mode... \n", core_id, sbl_slave_core_info[core_id].tisci_proc_id);
+ /* Non-SMP image used, disable lock step for the cluster */
+ SBL_ConfigMcuLockStep(SBL_DISABLE_MCU_LOCKSTEP, &(sbl_slave_core_info[core_id]));
+ }
+
+ /* Ensure Power is OFF for each core before configuring TCMs */
+ /* SBL running on MCU0, don't fool around with its power */
+ if (core_id != MCU1_CPU0_ID)
+ {
+ if (runLockStep)
+ {
+ SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id + 1);
+ Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id + 1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+ SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
+ Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_proc_id);
status = Sciclient_procBootGetProcessorState(sblSlaveCoreInfoPtr->tisci_proc_id, &cpuStatus, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
proc_set_config_req.bootvector_hi = cpuStatus.bootvector_hi;
proc_set_config_req.config_flags_1_set = 0;
proc_set_config_req.config_flags_1_clear = 0;
+#if defined(SOC_AM65XX)
+ SBL_log(SBL_LOG_MAX, "Restore TCM defaults (ATCM disabled), after reset, for core %d\n", core_id);
+ proc_set_config_req.config_flags_1_clear |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
+#else
SBL_log(SBL_LOG_MAX, "Enabling MCU TCMs after reset for core %d\n", core_id);
+ proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
+#endif
proc_set_config_req.config_flags_1_set |= (TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN |
- TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN |
TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE);
- SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling TCMs...\n");
+#if defined(SOC_J7200) || defined(SOC_AM64X)
+ /* Only need to set mem_init disable bit for MCU1_0 or MCU2_0 (for each cluster) */
+ if ((core_id == MCU1_CPU0_ID) || (core_id == MCU2_CPU0_ID))
+ {
+ SBL_log(SBL_LOG_MAX, "Disabling HW-based memory init of MCU TCMs for core %d\n", core_id);
+ proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS;
+ }
+#endif
+
+ SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...\n");
status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
SblErrLoop(__FILE__, __LINE__);
}
- /* SBL running on MCU0, don't fool around with its power */
+
+#if !defined(SOC_AM65XX)
+ /* Only initialize TCMs for Non-AM65xx SoCs. For AM65xx, TCMs must be initialized by the app itself. */
+
+ /* For lockstep R5 pairs, this section will naturally only set HALT bit for MCU2_CPU0_ID or MCU3_CPU0_ID */
if (core_id != MCU1_CPU0_ID)
{
- SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
- Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
- }
- SBL_log(SBL_LOG_MAX, "Setting HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
- status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
- if (status != CSL_PASS)
- {
- SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
- SblErrLoop(__FILE__, __LINE__);
+ SBL_log(SBL_LOG_MAX, "Setting HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
+ status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
+ if (status != CSL_PASS)
+ {
+ SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
+ SblErrLoop(__FILE__, __LINE__);
+ }
}
+
/* SBL running on MCU0, don't fool around with its power & TCMs */
if (core_id != MCU1_CPU0_ID)
{
+ uint32_t atcm_size = sblAtcmSize();
+ uint32_t btcm_size = sblBtcmSize();
+
+ if (runLockStep)
+ {
+ /* If in lock-step mode, need to bring Core 1 out of reset, before Core 0, in order to init TCMs */
+ SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id + 1);
+ Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id + 1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
/* Initialize the TCMs - TCMs of MCU running SBL are already initialized by ROM & SBL */
- SBL_log(SBL_LOG_MAX, "Clearing core_id %d ATCM @ 0x%x ", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
- memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
- SBL_log(SBL_LOG_MAX, "& BTCM @0x%x\n", SblBtcmAddr[core_id - MCU1_CPU0_ID]);
- memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
+ SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
+ memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, atcm_size);
+
+#ifndef VLAB_SIM
+ SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
+ memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, btcm_size);
+#else
+/* BTCM is not recognized in VLAB : ASTC TICKET # TBD */
+ SBL_log(SBL_LOG_MAX, "***Not Clearing*** BTCM @0x%x\n", SblBtcmAddr[core_id - MCU1_CPU0_ID]);
+#endif
}
+#endif /* #if !defined(SOC_AM65XX) */
break;
case MPU1_SMP_ID:
case MPU1_CPU0_ID:
SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER1);
Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
break;
+ case M4F_CPU0_ID:
+ SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
+ status = Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
+ if (status != CSL_PASS)
+ {
+ SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleState Off...FAILED \n");
+ SblErrLoop(__FILE__, __LINE__);
+ }
+ SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, DevId 0x%x with RESET \n", sblSlaveCoreInfoPtr->tisci_dev_id);
+ status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id, 1, SCICLIENT_SERVICE_WAIT_FOREVER);
+ if (status != CSL_PASS)
+ {
+ SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RESET ...FAILED \n");
+ SblErrLoop(__FILE__, __LINE__);
+ }
+
+ SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
+ status = Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
+ if (status != CSL_PASS)
+ {
+ SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleState...FAILED \n");
+ SblErrLoop(__FILE__, __LINE__);
+ }
+ break;
case MPU_SMP_ID:
/* Enable SMP on all MPU clusters. Enable SMP only if cluster is present */
if (SBL_DEV_ID_MPU_CLUSTER0 != 0xBAD00000)
* \param core_id = Selects a core on the SOC, refer to cpu_core_id_t enum
* freqHz = Speed of core at boot up, 0 indicates use SBL default freqs.
* pAppEntry = SBL entry point struct
+ * requestCoresFlag = Specify whether cores should be requested/released
+ * from within SBL_SlaveCoreBoot. Accepts the values SBL_REQUEST_CORE
+ * and SBL_DONT_REQUEST_CORE.
*
**/
-void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *pAppEntry)
+void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *pAppEntry, uint32_t requestCoresFlag)
{
int32_t status = CSL_EFAIL;
struct tisci_msg_proc_set_config_req proc_set_config_req;
@@ -522,13 +667,23 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
SBL_ADD_PROFILE_POINT;
+#if defined(SOC_AM64X)
+ /* Do not touch the M4 if reset isolation is enabled */
+ uint32_t mmrMagicRegister;
+ mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
+ if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
+ {
+ return;
+ }
+#endif
+
#if defined(SBL_SKIP_MCU_RESET) && (defined(SBL_SKIP_BRD_CFG_BOARD) || defined(SBL_SKIP_BRD_CFG_PM) || defined(SBL_SKIP_SYSFW_INIT))
/* Skip copy if R5 app entry point is already 0 */
if ((core_id == MCU1_CPU0_ID) &&
(pAppEntry->CpuEntryPoint[core_id]) &&
(pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR))
{
- SBL_log(SBL_LOG_MAX, "Copying first 128 byptes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
+ SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
return;
}
@@ -546,21 +701,19 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
}
#endif
- SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootRequestProcessor, ProcId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_proc_id);
- status = Sciclient_procBootRequestProcessor(sblSlaveCoreInfoPtr->tisci_proc_id, SCICLIENT_SERVICE_WAIT_FOREVER);
- if (status != CSL_PASS)
+ /* Request core */
+ if (requestCoresFlag == SBL_REQUEST_CORE)
{
- SBL_log(SBL_LOG_ERR, "Sciclient_procBootRequestProcessor...FAILED \n");
- SblErrLoop(__FILE__, __LINE__);
+ SBL_RequestCore(core_id);
}
+ /* Set entry point as boot vector */
proc_set_config_req.processor_id = sblSlaveCoreInfoPtr->tisci_proc_id;
proc_set_config_req.bootvector_lo = pAppEntry->CpuEntryPoint[core_id];
proc_set_config_req.bootvector_hi = 0x0;
proc_set_config_req.config_flags_1_set = 0;
proc_set_config_req.config_flags_1_clear = 0;
-
if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR) /* Set entry point only is valid */
{
SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, EntryPoint 0x%x...\n", proc_set_config_req.processor_id, proc_set_config_req.bootvector_lo);
@@ -592,39 +745,71 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
/* Display profile logs */
SBL_printProfileLog();
+#if !defined(SOC_AM65XX) /* Pre-loading ATCM is not permitted for AM65xx */
if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
{
/* Skip copy if R5 app entry point is already 0 */
if (pAppEntry->CpuEntryPoint[core_id])
{
- SBL_log(SBL_LOG_MAX, "Copying first 128 byptes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
+ SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
}
}
+#endif
#ifdef SBL_SKIP_MCU_RESET
+ if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
+ {
+#if !defined(SOC_AM65XX)
+ /* Un-halt MCU1_1 core */
+ Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+#endif
+ Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
/* Release the CPU and branch to app */
- status = Sciclient_procBootReleaseProcessor(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
- if (status != CSL_PASS)
+ if (requestCoresFlag == SBL_REQUEST_CORE)
{
- SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", sblSlaveCoreInfoPtr->tisci_proc_id);
- SblErrLoop(__FILE__, __LINE__);
+ SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
}
- SBL_log(SBL_LOG_MAX, "Starting app, branching to 0x0 \n");
- /* Branch to start of ATCM */
+ /* Start the App - Branch to start of ATCM (0x0) */
((void(*)(void))0x0)();
#else
- SBL_log(SBL_LOG_MAX, "Sciclient_procBootRequestProcessor, ProcId 0x%x... \n", SBL_PROC_ID_MCU1_CPU0);
- status = Sciclient_procBootRequestProcessor(SBL_PROC_ID_MCU1_CPU0, SCICLIENT_SERVICE_WAIT_FOREVER);
- if (status != CSL_PASS)
+ /* Request MCU1_0 */
+ if (requestCoresFlag == SBL_REQUEST_CORE)
{
- SBL_log(SBL_LOG_ERR, "Sciclient_procBootRequestProcessorProcId 0x%x...FAILED \n", SBL_PROC_ID_MCU1_CPU0);
- SblErrLoop(__FILE__, __LINE__);
+ SBL_RequestCore(core_id - 1);
}
- /* Setting up DMSC to wait for WFI */
- SBL_log(SBL_LOG_MAX, "Sciclient_procBootWaitProcessorState, ProcId 0x%x... \n", SBL_PROC_ID_MCU1_CPU0);
+ /**
+ * Reset sequence for cluster running SBL
+ *
+ * The reset sequence for the cluster running SBL has to be done differently from
+ * that of other clusters. More detail is described in comments below, but a high-
+ * level overview of the reset sequence is as follows:
+ *
+ * 1. Processor Boot Wait (holds the queue)
+ * 2. MCU1_1 Enter Reset - (AM65x case: already powered OFF)
+ * 3. MCU1_0 Enter Reset - (AM65x case: Power OFF)
+ * 4. Un-halt MCU1_1 - (AM65x case: Not necessary)
+ * 5. Release control of MCU1_0
+ * 6. Release control of MCU1_1
+ * 7. MCU1_0 Leave Reset - (AM65x case: Power ON)
+ * 8. MCU1_1 Leave Reset (if an application is requested to run there) - (AM65x case: Power ON)
+ */
+
+ /**
+ * Processor Boot Wait
+ *
+ * DMSC will block until a WFI is issued, thus allowing the following commands
+ * to be queued so this cluster may be reset by DMSC (queue length is defined in
+ * "drv/sciclient/soc/sysfw/include/<soc>/tisci_sec_proxy.h"). If these commands
+ * were to be issued and executed prior to WFI, the cluster would enter reset and
+ * SBL would quite sensibly not be able to tell DMSC to take itself out of reset.
+ */
+ /* SBL_log(SBL_LOG_MAX, "Sciclient_procBootWaitProcessorState, ProcId 0x%x... \n", SBL_PROC_ID_MCU1_CPU0); */
status = Sciclient_procBootWaitProcessorState(SBL_PROC_ID_MCU1_CPU0, 1, 1, 0, 3, 0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
@@ -632,47 +817,80 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
SblErrLoop(__FILE__, __LINE__);
}
- /* Power down core running SBL */
+ /**
+ * Both cores enter reset
+ *
+ * It is necessary to reset MCU1_1 before MCU1_0, so as to maintain the specification that
+ * MCU1_1 may never ben in a higher functional state than MCU1_0.
+ */
+#if !defined(SOC_AM65XX)
+ Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU1, 1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU0, 1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+
+ /**
+ * Un-halt MCU1_1 (MCU1_0 is not halted)
+ */
+ Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+#else
+ /* AM65x case (can't use local reset flags): Power down core running SBL */
Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+#endif
- /* Both cores halted at this point. Now un-halt them as needed */
- Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU0, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ /**
+ * Notify SYSFW that the SBL is relinquishing the MCU cluster running the SBL
+ */
+#if !defined(SOC_J721E) && !defined(SOC_J7200)
+ if (requestCoresFlag == SBL_REQUEST_CORE)
+ {
+ Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+#endif
+ /**
+ * MCU1_0 and (optionally) MCU1_1 leave reset
+ *
+ * Ensuring that MCU1_1 is never in a higher functional state than MCU1_0, both cores
+ * shall leave reset. Only take MCU1_1 out of reset if an application will be running
+ * on it.
+ */
+#if !defined(SOC_AM65XX)
+ Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
{
- Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU1, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
}
-
- /* Notifying SYSFW that the SBL is relinquishing the MCU cluster running the SBL */
- status = Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
- status = Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
-
- /* Power up cores as needed */
+#else
+ /* AM65x case (can't use local reset flags): Power ON CPU0 core, then power ON CPU1 core if necessary */
Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
{
- Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
}
+#endif
+
+#if defined(SOC_J721E) || defined(SOC_J7200)
+ /* Notifying SYSFW that the SBL is relinquishing the MCU cluster running the SBL */
+ /* This is done at the end as the PM set module state relies on the fact the SBL is the owner of MCU1_0 and MCU1_1 */
+ if (requestCoresFlag == SBL_REQUEST_CORE)
+ {
+ Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+#endif
/* Execute a WFI */
asm volatile (" wfi");
-
#endif
break;
case MCU1_CPU0_ID:
/* Skip copy if R5 app entry point is already 0 */
+#if !defined(SOC_AM65XX) || defined(SBL_SKIP_MCU_RESET)
if (pAppEntry->CpuEntryPoint[core_id])
{
- SBL_log(SBL_LOG_MAX, "Copying first 128 byptes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
+ SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
}
- SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
- status = Sciclient_procBootReleaseProcessor(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
- if (status != CSL_PASS)
- {
- SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", sblSlaveCoreInfoPtr->tisci_proc_id);
- SblErrLoop(__FILE__, __LINE__);
- }
+#endif
break;
case MCU2_CPU0_ID:
case MCU2_CPU1_ID:
@@ -683,7 +901,7 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
/* Skip copy if R5 app entry point is already 0 */
if (pAppEntry->CpuEntryPoint[core_id])
{
- SBL_log(SBL_LOG_MAX, "Copying first 128 byptes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
+ SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
}
SBL_log(SBL_LOG_MAX, "Clearing HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
@@ -693,30 +911,45 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
SblErrLoop(__FILE__, __LINE__);
}
- SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
- Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
}
- SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
- status = Sciclient_procBootReleaseProcessor(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
- if (status != CSL_PASS)
+
+ /* Release core */
+ if (requestCoresFlag == SBL_REQUEST_CORE)
{
- SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", sblSlaveCoreInfoPtr->tisci_proc_id);
- SblErrLoop(__FILE__, __LINE__);
+ SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
}
+
SBL_ADD_PROFILE_POINT;
break;
- default:
- SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
- status = Sciclient_procBootReleaseProcessor(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
+ case M4F_CPU0_ID:
+ SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, ProcId 0x%x with RELEASE \n", sblSlaveCoreInfoPtr->tisci_proc_id);
+ status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
- SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", sblSlaveCoreInfoPtr->tisci_proc_id);
+ SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RELEASE...FAILED \n");
SblErrLoop(__FILE__, __LINE__);
}
+
+ /* Release core */
+ if (requestCoresFlag == SBL_REQUEST_CORE)
+ {
+ SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
+ }
+
+ SBL_ADD_PROFILE_POINT;
+ break;
+ default:
SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
+
+ /* Release core */
+ if (requestCoresFlag == SBL_REQUEST_CORE)
+ {
+ SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
+ }
+
SBL_ADD_PROFILE_POINT;
break;
}