diff --git a/packages/ti/boot/sbl/soc/k3/sbl_slave_core_boot.c b/packages/ti/boot/sbl/soc/k3/sbl_slave_core_boot.c
index f9aa3d31fadf6fd59f7c975343979710694a71a3..8199b43c04ae0b4b4a35f98ed89feb875e3d4366 100644 (file)
SBL_MCU3_CPU1_ATCM_BASE_ADDR_SOC
};
+#if !defined(SOC_AM65XX)
static const uint32_t SblBtcmAddr[] =
{
SBL_MCU_BTCM_BASE,
SBL_MCU3_CPU0_BTCM_BASE_ADDR_SOC,
SBL_MCU3_CPU1_BTCM_BASE_ADDR_SOC
};
+#endif
/* ========================================================================== */
/* Internal Functions */
/* ========================================================================== */
int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
int32_t status = CSL_EFAIL;
+#if defined(SOC_AM64X)
+ /* Do not touch the M4 if reset isolation is enabled */
+ uint32_t mmrMagicRegister;
+ mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
+ if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
+ {
+ return;
+ }
+#endif
+
if (proc_id != 0xBAD00000)
{
SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootRequestProcessor, ProcId 0x%x... \n", proc_id);
return;
}
-static void SBL_ReleaseCore(cpu_core_id_t core_id)
+static void SBL_ReleaseCore (cpu_core_id_t core_id, uint32_t reqFlag)
{
#if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
int32_t status = CSL_EFAIL;
+#if defined(SOC_AM64X)
+ /* Do not touch the M4 if reset isolation is enabled */
+ uint32_t mmrMagicRegister;
+ mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
+ if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
+ {
+ return;
+ }
+#endif
+
if(proc_id != 0xBAD00000)
{
SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", proc_id);
- status = Sciclient_procBootReleaseProcessor(proc_id, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
+ status = Sciclient_procBootReleaseProcessor(proc_id, reqFlag, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
for (core_id = 0; core_id < num_cores; core_id++)
{
- SBL_ReleaseCore(core_id);
+ SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
}
SBL_ADD_PROFILE_POINT;
SBL_ADD_PROFILE_POINT;
+#if defined(SOC_AM64X)
+ /* Do not touch the M4 if reset isolation is enabled */
+ uint32_t mmrMagicRegister;
+ mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
+ if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
+ {
+ return;
+ }
+#endif
+
/* Remap virtual core-ids if needed */
switch (core_id)
{
}
SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
-
-#ifdef VLAB_SIM
- /* HALT issue on VLAB causes the core to a immediate halt. ASTC Ticket #*/
- SBL_log(SBL_LOG_MAX, "Setting HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
- status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
- if (status != CSL_PASS)
- {
- SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
- SblErrLoop(__FILE__, __LINE__);
- }
-#endif
}
-#ifndef VLAB_SIM
- /* In case of VLAB_SIM, the below step is done only for all but mcu1_0 shown above */
- SBL_log(SBL_LOG_MAX, "Setting HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
- status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
- if (status != CSL_PASS)
- {
- SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
- SblErrLoop(__FILE__, __LINE__);
- }
-#endif
-
SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_proc_id);
status = Sciclient_procBootGetProcessorState(sblSlaveCoreInfoPtr->tisci_proc_id, &cpuStatus, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
proc_set_config_req.bootvector_hi = cpuStatus.bootvector_hi;
proc_set_config_req.config_flags_1_set = 0;
proc_set_config_req.config_flags_1_clear = 0;
- proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
-
+#if defined(SOC_AM65XX)
+ SBL_log(SBL_LOG_MAX, "Restore TCM defaults (ATCM disabled), after reset, for core %d\n", core_id);
+ proc_set_config_req.config_flags_1_clear |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
+#else
SBL_log(SBL_LOG_MAX, "Enabling MCU TCMs after reset for core %d\n", core_id);
+ proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
+#endif
proc_set_config_req.config_flags_1_set |= (TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN |
TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE);
}
#endif
- SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg enabling TCMs...\n");
+ SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...\n");
status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
SblErrLoop(__FILE__, __LINE__);
}
+#if !defined(SOC_AM65XX)
+ /* Only initialize TCMs for Non-AM65xx SoCs. For AM65xx, TCMs must be initialized by the app itself. */
+
+ /* For lockstep R5 pairs, this section will naturally only set HALT bit for MCU2_CPU0_ID or MCU3_CPU0_ID */
+ if (core_id != MCU1_CPU0_ID)
+ {
+ SBL_log(SBL_LOG_MAX, "Setting HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
+ status = Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
+ if (status != CSL_PASS)
+ {
+ SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
+ SblErrLoop(__FILE__, __LINE__);
+ }
+ }
+
/* SBL running on MCU0, don't fool around with its power & TCMs */
if (core_id != MCU1_CPU0_ID)
{
+ uint32_t atcm_size = sblAtcmSize();
+ uint32_t btcm_size = sblBtcmSize();
+
if (runLockStep)
{
/* If in lock-step mode, need to bring Core 1 out of reset, before Core 0, in order to init TCMs */
Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
/* Initialize the TCMs - TCMs of MCU running SBL are already initialized by ROM & SBL */
-#if defined(SOC_J7200)
- /* J7200: ATCM in lock-step is the combined size of both the split-mode ATCMs */
- if (runLockStep)
- {
- SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
- memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x10000);
- }
- else
- /* Clear the normal size of ATCM for non-lockstep cores */
-#endif
- {
- SBL_log(SBL_LOG_MAX, "Clearing core_id %d ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
- memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
- }
+ SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
+ memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, atcm_size);
#ifndef VLAB_SIM
-#if defined(SOC_J7200)
- /* J7200: BTCM in lock-step is the combined size of both the split-mode BTCMs */
- if (runLockStep)
- {
- SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
- memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x10000);
- }
- else
- /* Clear the normal size of BTCM for non-lockstep cores */
-#endif
- {
- SBL_log(SBL_LOG_MAX, "Clearing core_id %d BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
- memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
- }
+ SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
+ memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, btcm_size);
#else
/* BTCM is not recognized in VLAB : ASTC TICKET # TBD */
SBL_log(SBL_LOG_MAX, "***Not Clearing*** BTCM @0x%x\n", SblBtcmAddr[core_id - MCU1_CPU0_ID]);
#endif
}
+#endif /* #if !defined(SOC_AM65XX) */
break;
case MPU1_SMP_ID:
case MPU1_CPU0_ID:
SblErrLoop(__FILE__, __LINE__);
}
SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, DevId 0x%x with RESET \n", sblSlaveCoreInfoPtr->tisci_dev_id);
- status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id,1,SCICLIENT_SERVICE_WAIT_FOREVER);
+ status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id, 1, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RESET ...FAILED \n");
@@ -658,6 +667,16 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
SBL_ADD_PROFILE_POINT;
+#if defined(SOC_AM64X)
+ /* Do not touch the M4 if reset isolation is enabled */
+ uint32_t mmrMagicRegister;
+ mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
+ if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
+ {
+ return;
+ }
+#endif
+
#if defined(SBL_SKIP_MCU_RESET) && (defined(SBL_SKIP_BRD_CFG_BOARD) || defined(SBL_SKIP_BRD_CFG_PM) || defined(SBL_SKIP_SYSFW_INIT))
/* Skip copy if R5 app entry point is already 0 */
if ((core_id == MCU1_CPU0_ID) &&
@@ -726,6 +745,7 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
/* Display profile logs */
SBL_printProfileLog();
+#if !defined(SOC_AM65XX) /* Pre-loading ATCM is not permitted for AM65xx */
if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
{
/* Skip copy if R5 app entry point is already 0 */
@@ -735,33 +755,61 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
}
}
+#endif
#ifdef SBL_SKIP_MCU_RESET
if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
{
+#if !defined(SOC_AM65XX)
+ /* Un-halt MCU1_1 core */
Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+#endif
Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
}
/* Release the CPU and branch to app */
if (requestCoresFlag == SBL_REQUEST_CORE)
{
- SBL_ReleaseCore(core_id);
+ SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
}
- SBL_log(SBL_LOG_MAX, "Starting app, branching to 0x0 \n");
- /* Branch to start of ATCM */
+ /* Start the App - Branch to start of ATCM (0x0) */
((void(*)(void))0x0)();
#else
- /* Request MCU1_0 */
+ /* Request MCU1_0 */
if (requestCoresFlag == SBL_REQUEST_CORE)
{
SBL_RequestCore(core_id - 1);
}
- /* Setting up DMSC to wait for WFI */
- SBL_log(SBL_LOG_MAX, "Sciclient_procBootWaitProcessorState, ProcId 0x%x... \n", SBL_PROC_ID_MCU1_CPU0);
+ /**
+ * Reset sequence for cluster running SBL
+ *
+ * The reset sequence for the cluster running SBL has to be done differently from
+ * that of other clusters. More detail is described in comments below, but a high-
+ * level overview of the reset sequence is as follows:
+ *
+ * 1. Processor Boot Wait (holds the queue)
+ * 2. MCU1_1 Enter Reset - (AM65x case: already powered OFF)
+ * 3. MCU1_0 Enter Reset - (AM65x case: Power OFF)
+ * 4. Un-halt MCU1_1 - (AM65x case: Not necessary)
+ * 5. Release control of MCU1_0
+ * 6. Release control of MCU1_1
+ * 7. MCU1_0 Leave Reset - (AM65x case: Power ON)
+ * 8. MCU1_1 Leave Reset (if an application is requested to run there) - (AM65x case: Power ON)
+ */
+
+ /**
+ * Processor Boot Wait
+ *
+ * DMSC will block until a WFI is issued, thus allowing the following commands
+ * to be queued so this cluster may be reset by DMSC (queue length is defined in
+ * "drv/sciclient/soc/sysfw/include/<soc>/tisci_sec_proxy.h"). If these commands
+ * were to be issued and executed prior to WFI, the cluster would enter reset and
+ * SBL would quite sensibly not be able to tell DMSC to take itself out of reset.
+ */
+ /* SBL_log(SBL_LOG_MAX, "Sciclient_procBootWaitProcessorState, ProcId 0x%x... \n", SBL_PROC_ID_MCU1_CPU0); */
status = Sciclient_procBootWaitProcessorState(SBL_PROC_ID_MCU1_CPU0, 1, 1, 0, 3, 0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
@@ -769,48 +817,66 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
SblErrLoop(__FILE__, __LINE__);
}
- /* Power down core running SBL */
+ /**
+ * Both cores enter reset
+ *
+ * It is necessary to reset MCU1_1 before MCU1_0, so as to maintain the specification that
+ * MCU1_1 may never ben in a higher functional state than MCU1_0.
+ */
+#if !defined(SOC_AM65XX)
+ Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU1, 1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU0, 1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+
+ /**
+ * Un-halt MCU1_1 (MCU1_0 is not halted)
+ */
+ Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+#else
+ /* AM65x case (can't use local reset flags): Power down core running SBL */
Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+#endif
- /* Both cores halted at this point. Now un-halt them as needed */
- Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU0, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
- if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
- {
- Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
- }
-
- /* Notifying SYSFW that the SBL is relinquishing the MCU cluster running the SBL */
+ /**
+ * Notify SYSFW that the SBL is relinquishing the MCU cluster running the SBL
+ */
+#if !defined(SOC_J721E) && !defined(SOC_J7200)
if (requestCoresFlag == SBL_REQUEST_CORE)
{
- SBL_ReleaseCore(core_id - 1); /* MCU1_0 */
- SBL_ReleaseCore(core_id); /* MCU1_1 */
+ Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
}
-
- /* Power up cores as needed */
-#if defined(SOC_AM64X) || defined(SOC_J7200)
- /* AM64X & J7200 have a different Power on sequence than other K3 SOCs.
- * We must ensure that CPU1 is powered off, first, before turning on CPU0 (and then CPU1) */
+#endif
+ /**
+ * MCU1_0 and (optionally) MCU1_1 leave reset
+ *
+ * Ensuring that MCU1_1 is never in a higher functional state than MCU1_0, both cores
+ * shall leave reset. Only take MCU1_1 out of reset if an application will be running
+ * on it.
+ */
+#if !defined(SOC_AM65XX)
+ Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
{
- /* Multicore image has valid images for both core 0 and core 1 */
- Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
- Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
- Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU1, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
}
- else
- {
- /* Multicore image has valid images for core 0 and no image for core 1 */
- Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
- }
#else
+ /* AM65x case (can't use local reset flags): Power ON CPU0 core, then power ON CPU1 core if necessary */
Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR)
{
- Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
}
#endif
-
+
+#if defined(SOC_J721E) || defined(SOC_J7200)
+ /* Notifying SYSFW that the SBL is relinquishing the MCU cluster running the SBL */
+ /* This is done at the end as the PM set module state relies on the fact the SBL is the owner of MCU1_0 and MCU1_1 */
+ if (requestCoresFlag == SBL_REQUEST_CORE)
+ {
+ Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+#endif
/* Execute a WFI */
asm volatile (" wfi");
#endif
@@ -818,11 +884,13 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
case MCU1_CPU0_ID:
/* Skip copy if R5 app entry point is already 0 */
+#if !defined(SOC_AM65XX) || defined(SBL_SKIP_MCU_RESET)
if (pAppEntry->CpuEntryPoint[core_id])
{
SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
}
+#endif
break;
case MCU2_CPU0_ID:
case MCU2_CPU1_ID:
@@ -843,21 +911,19 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
SblErrLoop(__FILE__, __LINE__);
}
- SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
- Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
}
/* Release core */
if (requestCoresFlag == SBL_REQUEST_CORE)
{
- SBL_ReleaseCore(core_id);
+ SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
}
SBL_ADD_PROFILE_POINT;
break;
case M4F_CPU0_ID:
SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, ProcId 0x%x with RELEASE \n", sblSlaveCoreInfoPtr->tisci_proc_id);
- status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id,0,SCICLIENT_SERVICE_WAIT_FOREVER);
+ status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RELEASE...FAILED \n");
@@ -867,7 +933,7 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
/* Release core */
if (requestCoresFlag == SBL_REQUEST_CORE)
{
- SBL_ReleaseCore(core_id);
+ SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
}
SBL_ADD_PROFILE_POINT;
@@ -881,7 +947,7 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
/* Release core */
if (requestCoresFlag == SBL_REQUEST_CORE)
{
- SBL_ReleaseCore(core_id);
+ SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
}
SBL_ADD_PROFILE_POINT;