PDK-10903: SBL: J7xx: OSPI DMA transfer to MCU TCM to use SoC addr

[processor-sdk/pdk.git] / packages / ti / boot / sbl / soc / k3 / sbl_soc_cfg.h

diff --git a/packages/ti/boot/sbl/soc/k3/sbl_soc_cfg.h b/packages/ti/boot/sbl/soc/k3/sbl_soc_cfg.h
index 0cbc79ed1484a884d8d5192b4307dcfe9429add7..07e14c3e8b5ad4298be0c7b7e5b871abf428732e 100755 (executable)
--- a/packages/ti/boot/sbl/soc/k3/sbl_soc_cfg.h
+++ b/packages/ti/boot/sbl/soc/k3/sbl_soc_cfg.h
@@ -283,12 +283,14 @@ extern uint16_t sblMapOtpVidToMilliVolts[256];
 #define SBL_MCU_BTCM_BASE      (CSL_MCU_ARMSS_BTCM_BASE)
 #define SBL_MCU_BTCM_SIZE      (CSL_MCU_ARMSS_BTCM_SIZE)
 
+#define SBL_MCU1_CPU0_ATCM_BASE_ADDR_SOC    (CSL_MCU_R5FSS0_CORE0_ATCM_BASE)
 #define SBL_MCU1_CPU1_ATCM_BASE_ADDR_SOC    (CSL_MCU_R5FSS0_CORE1_ATCM_BASE)
 #define SBL_MCU2_CPU0_ATCM_BASE_ADDR_SOC    (CSL_R5FSS0_CORE0_ATCM_BASE)
 #define SBL_MCU2_CPU1_ATCM_BASE_ADDR_SOC    (CSL_R5FSS0_CORE1_ATCM_BASE)
 #define SBL_MCU3_CPU0_ATCM_BASE_ADDR_SOC    (CSL_R5FSS1_CORE0_ATCM_BASE)
 #define SBL_MCU3_CPU1_ATCM_BASE_ADDR_SOC    (CSL_R5FSS1_CORE1_ATCM_BASE)
 
+#define SBL_MCU1_CPU0_BTCM_BASE_ADDR_SOC    (CSL_MCU_R5FSS0_CORE0_BTCM_BASE)
 #define SBL_MCU1_CPU1_BTCM_BASE_ADDR_SOC    (CSL_MCU_R5FSS0_CORE1_BTCM_BASE)
 #define SBL_MCU2_CPU0_BTCM_BASE_ADDR_SOC    (CSL_R5FSS0_CORE0_BTCM_BASE)
 #define SBL_MCU2_CPU1_BTCM_BASE_ADDR_SOC    (CSL_R5FSS0_CORE1_BTCM_BASE)
@@ -464,12 +466,14 @@ extern uint16_t sblMapOtpVidToMilliVolts[256];
 #define SBL_MCU_BTCM_BASE      (CSL_MCU_R5FSS0_BTCM_BASE)
 #define SBL_MCU_BTCM_SIZE      (CSL_MCU_R5FSS0_BTCM_SIZE)
 
+#define SBL_MCU1_CPU0_ATCM_BASE_ADDR_SOC    (CSL_MCU_R5FSS0_CORE0_ATCM_BASE)
 #define SBL_MCU1_CPU1_ATCM_BASE_ADDR_SOC    (CSL_MCU_R5FSS0_CORE1_ATCM_BASE)
 #define SBL_MCU2_CPU0_ATCM_BASE_ADDR_SOC    (CSL_R5FSS0_CORE0_ATCM_BASE)
 #define SBL_MCU2_CPU1_ATCM_BASE_ADDR_SOC    (CSL_R5FSS0_CORE1_ATCM_BASE)
 #define SBL_MCU3_CPU0_ATCM_BASE_ADDR_SOC    (0xBAD00000)
 #define SBL_MCU3_CPU1_ATCM_BASE_ADDR_SOC    (0xBAD00000)
 
+#define SBL_MCU1_CPU0_BTCM_BASE_ADDR_SOC    (CSL_MCU_R5FSS0_CORE0_BTCM_BASE)
 #define SBL_MCU1_CPU1_BTCM_BASE_ADDR_SOC    (CSL_MCU_R5FSS0_CORE1_BTCM_BASE)
 #define SBL_MCU2_CPU0_BTCM_BASE_ADDR_SOC    (CSL_R5FSS0_CORE0_BTCM_BASE)
 #define SBL_MCU2_CPU1_BTCM_BASE_ADDR_SOC    (CSL_R5FSS0_CORE1_BTCM_BASE)