index adf750cb8daad6b835d000ad251b89b288ad3cf2..0cbc79ed1484a884d8d5192b4307dcfe9429add7 100755 (executable)
#endif /* if defined (SOC_J7200) */
+#if defined (SOC_J721S2)
+
+#define SBL_MCU_ATCM_BASE (CSL_MCU_R5FSS0_ATCM_BASE)
+#define SBL_MCU_ATCM_SIZE (CSL_MCU_R5FSS0_ATCM_SIZE)
+#define SBL_MCU_BTCM_BASE (CSL_MCU_R5FSS0_BTCM_BASE)
+#define SBL_MCU_BTCM_SIZE (CSL_MCU_R5FSS0_BTCM_SIZE)
+
+#define SBL_MCU1_CPU0_ATCM_BASE_ADDR_SOC (CSL_MCU_R5FSS0_CORE0_ATCM_BASE)
+#define SBL_MCU1_CPU1_ATCM_BASE_ADDR_SOC (CSL_MCU_R5FSS0_CORE1_ATCM_BASE)
+#define SBL_MCU2_CPU0_ATCM_BASE_ADDR_SOC (CSL_R5FSS0_CORE0_ATCM_BASE)
+#define SBL_MCU2_CPU1_ATCM_BASE_ADDR_SOC (CSL_R5FSS0_CORE1_ATCM_BASE)
+#define SBL_MCU3_CPU0_ATCM_BASE_ADDR_SOC (CSL_R5FSS1_CORE0_ATCM_BASE)
+#define SBL_MCU3_CPU1_ATCM_BASE_ADDR_SOC (CSL_R5FSS1_CORE1_ATCM_BASE)
+
+#define SBL_MCU1_CPU0_BTCM_BASE_ADDR_SOC (CSL_MCU_R5FSS0_CORE0_BTCM_BASE)
+#define SBL_MCU1_CPU1_BTCM_BASE_ADDR_SOC (CSL_MCU_R5FSS0_CORE1_BTCM_BASE)
+#define SBL_MCU2_CPU0_BTCM_BASE_ADDR_SOC (CSL_R5FSS0_CORE0_BTCM_BASE)
+#define SBL_MCU2_CPU1_BTCM_BASE_ADDR_SOC (CSL_R5FSS0_CORE1_BTCM_BASE)
+#define SBL_MCU3_CPU0_BTCM_BASE_ADDR_SOC (CSL_R5FSS1_CORE0_BTCM_BASE)
+#define SBL_MCU3_CPU1_BTCM_BASE_ADDR_SOC (CSL_R5FSS1_CORE1_BTCM_BASE)
+
+#define SBL_C66X_L2SRAM_BASE (0xBAD00000)
+#define SBL_C66X_L2SRAM_SIZE (0xBAD00000)
+#define SBL_C66X_L1DMEM_BASE (0xBAD00000)
+#define SBL_C66X_L1DMEM_SIZE (0xBAD00000)
+
+#define SBL_C66X1_L2SRAM_BASE_ADDR_SOC (0xBAD00000)
+#define SBL_C66X2_L2SRAM_BASE_ADDR_SOC (0xBAD00000)
+
+#define SBL_C66X1_L1DMEM_BASE_ADDR_SOC (0xBAD00000)
+#define SBL_C66X2_L1DMEM_BASE_ADDR_SOC (0xBAD00000)
+
+#define SBL_C7X_L2SRAM_BASE (0xBAD00000)
+#define SBL_C7X_L2SRAM_SIZE (0xBAD00000)
+#define SBL_C7X_L1DMEM_BASE (0xBAD00000)
+#define SBL_C7X_L1DMEM_SIZE (0xBAD00000)
+
+#define SBL_C7X1_L2SRAM_BASE_ADDR_SOC (0xBAD00000)
+#define SBL_C7X2_L2SRAM_BASE_ADDR_SOC (0xBAD00000)
+
+#define SBL_C7X1_L1DMEM_BASE_ADDR_SOC (0xBAD00000)
+#define SBL_C7X2_L1DMEM_BASE_ADDR_SOC (0xBAD00000)
+
+#define SBL_M4F_IRAM_BASE (0xBAD00000)
+#define SBL_M4F_IRAM_SIZE (0xBAD00000)
+#define SBL_M4F_DRAM_BASE (0xBAD00000)
+#define SBL_M4F_DRAM_SIZE (0xBAD00000)
+
+#define SBL_M4F_IRAM_BASE_ADDR_SOC (0xBAD00000)
+#define SBL_M4F_DRAM_BASE_ADDR_SOC (0xBAD00000)
+
+#define SBL_UART_PLL_BASE (CSL_MCU_PLL0_CFG_BASE)
+#define SBL_UART_PLL_KICK0_OFFSET (CSL_MCU_PLL_MMR_CFG_PLL1_LOCKKEY0)
+#define SBL_UART_PLL_KICK1_OFFSET (CSL_MCU_PLL_MMR_CFG_PLL1_LOCKKEY1)
+#define SBL_UART_PLL_DIV_OFFSET (CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CTRL3)
+#define SBL_UART_PLL_DIV_VAL (0x00008031)
+#define SBL_UART_PLL_KICK0_UNLOCK_VAL (0x68EF3490)
+#define SBL_UART_PLL_KICK1_UNLOCK_VAL (0xD172BC5A)
+#define SBL_UART_PLL_KICK_LOCK_VAL (0x0)
+#define SBL_ROM_UART_MODULE_INPUT_CLK (48000000U)
+#define SBL_SYSFW_UART_MODULE_INPUT_CLK (96000000U)
+
+#define SBL_MCU_UART_PADCONFIG_PULLUDEN_SHIFT (CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG18_PULLUDEN_SHIFT)
+#define SBL_MCU_UART_PADCONFIG_PULLTYPESEL_SHIFT (CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG18_PULLTYPESEL_SHIFT)
+#define SBL_MCU_UART_PADCONFIG_RXACTIVE_SHIFT (CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG18_RXACTIVE_SHIFT)
+#define SBL_MCU_UART_PADCONFIG_TX_DIS_SHIFT (CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG18_TX_DIS_SHIFT)
+#define SBL_MCU_UART_PADCONFIG_MUXMODE_SHIFT (CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG18_MUXMODE_SHIFT)
+#define SBL_MCU_UART_PADCONFIG_ADDR (CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG18)
+
+#define SBL_SYSFW_UART_PADCONFIG_PULLUDEN_SHIFT (CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG56_PULLUDEN_SHIFT)
+#define SBL_SYSFW_UART_PADCONFIG_PULLTYPESEL_SHIFT (CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG56_PULLTYPESEL_SHIFT)
+#define SBL_SYSFW_UART_PADCONFIG_RXACTIVE_SHIFT (CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG56_RXACTIVE_SHIFT)
+#define SBL_SYSFW_UART_PADCONFIG_TX_DIS_SHIFT (CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG56_TX_DIS_SHIFT)
+#define SBL_SYSFW_UART_PADCONFIG_MUXMODE_SHIFT (CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG56_MUXMODE_SHIFT)
+#define SBL_SYSFW_UART_PADCONFIG_ADDR (CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG56)
+
+#define SBL_VTM_CFG_BASE (CSL_WKUP_VTM0_MMR_VBUSP_CFG1_BASE)
+#define SBL_VTM_OPP_VID_MASK (CSL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_MASK)
+
+#define SBL_DEV_ID_OSPI0 (TISCI_DEV_MCU_FSS0_OSPI_0)
+#define SBL_CLK_ID_OSPI0 (TISCI_DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK)
+
+#define SBL_DEV_ID_OSPI1 (TISCI_DEV_MCU_FSS0_OSPI_1)
+#define SBL_CLK_ID_OSPI1 (TISCI_DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK)
+
+#define SBL_DEV_ID_RTI0 (TISCI_DEV_MCU_RTI0)
+#define SBL_DEV_ID_RTI1 (TISCI_DEV_MCU_RTI1)
+
+#define SBL_DEV_ID_MPU_CLUSTER0 (TISCI_DEV_A72SS0)
+#define SBL_DEV_ID_MPU_CLUSTER1 (0xBAD00000)
+
+#define SBL_PROC_ID_MPU1_CPU0 (SCICLIENT_PROC_ID_A72SS0_CORE0)
+#define SBL_DEV_ID_MPU1_CPU0 (TISCI_DEV_A72SS0_CORE0)
+#define SBL_CLK_ID_MPU1_CPU0 (TISCI_DEV_A72SS0_CORE0_ARM_CLK_CLK)
+#define SBL_MPU1_CPU0_FREQ_HZ (2000000000)
+
+#define SBL_PROC_ID_MPU1_CPU1 (SCICLIENT_PROC_ID_A72SS0_CORE1)
+#define SBL_DEV_ID_MPU1_CPU1 (TISCI_DEV_A72SS0_CORE1)
+#define SBL_CLK_ID_MPU1_CPU1 (TISCI_DEV_A72SS0_CORE1_ARM_CLK_CLK)
+
+#define SBL_MPU1_CPU1_FREQ_HZ (2000000000)
+
+#define SBL_PROC_ID_MPU2_CPU0 (0xBAD00000)
+#define SBL_DEV_ID_MPU2_CPU0 (0xBAD00000)
+#define SBL_CLK_ID_MPU2_CPU0 (0xBAD00000)
+#define SBL_MPU2_CPU0_FREQ_HZ (0xBAD00000)
+
+#define SBL_PROC_ID_MPU2_CPU1 (0xBAD00000)
+#define SBL_DEV_ID_MPU2_CPU1 (0xBAD00000)
+#define SBL_CLK_ID_MPU2_CPU1 (0xBAD00000)
+#define SBL_MPU2_CPU1_FREQ_HZ (0xBAD00000)
+
+#define SBL_PROC_ID_MCU1_CPU0 (SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0)
+#define SBL_DEV_ID_MCU1_CPU0 (TISCI_DEV_MCU_R5FSS0_CORE0)
+#define SBL_CLK_ID_MCU1_CPU0 (TISCI_DEV_MCU_R5FSS0_CORE0_CPU_CLK)
+#define SBL_MCU1_CPU0_FREQ_HZ (1000000000)
+
+#define SBL_PROC_ID_MCU1_CPU1 (SCICLIENT_PROC_ID_MCU_R5FSS0_CORE1)
+#define SBL_DEV_ID_MCU1_CPU1 (TISCI_DEV_MCU_R5FSS0_CORE1)
+#define SBL_CLK_ID_MCU1_CPU1 (TISCI_DEV_MCU_R5FSS0_CORE1_CPU_CLK)
+#define SBL_MCU1_CPU1_FREQ_HZ (1000000000)
+
+#define SBL_PROC_ID_MCU2_CPU0 (SCICLIENT_PROC_ID_R5FSS0_CORE0)
+#define SBL_DEV_ID_MCU2_CPU0 (TISCI_DEV_R5FSS0_CORE0)
+#define SBL_CLK_ID_MCU2_CPU0 (TISCI_DEV_R5FSS0_CORE0_CPU_CLK)
+#define SBL_MCU2_CPU0_FREQ_HZ (1000000000)
+
+#define SBL_PROC_ID_MCU2_CPU1 (SCICLIENT_PROC_ID_R5FSS0_CORE1)
+#define SBL_DEV_ID_MCU2_CPU1 (TISCI_DEV_R5FSS0_CORE1)
+#define SBL_CLK_ID_MCU2_CPU1 (TISCI_DEV_R5FSS0_CORE1_CPU_CLK)
+#define SBL_MCU2_CPU1_FREQ_HZ (1000000000)
+
+#define SBL_PROC_ID_MCU3_CPU0 (SCICLIENT_PROC_ID_R5FSS1_CORE0)
+#define SBL_DEV_ID_MCU3_CPU0 (TISCI_DEV_R5FSS1_CORE0)
+#define SBL_CLK_ID_MCU3_CPU0 (TISCI_DEV_R5FSS1_CORE0_CPU_CLK)
+#define SBL_MCU3_CPU0_FREQ_HZ (1000000000)
+
+#define SBL_PROC_ID_MCU3_CPU1 (SCICLIENT_PROC_ID_R5FSS1_CORE1)
+#define SBL_DEV_ID_MCU3_CPU1 (TISCI_DEV_R5FSS1_CORE1)
+#define SBL_CLK_ID_MCU3_CPU1 (TISCI_DEV_R5FSS1_CORE1_CPU_CLK)
+#define SBL_MCU3_CPU1_FREQ_HZ (1000000000)
+
+#define SBL_PROC_ID_DSP1_C66X (0xBAD00000)
+#define SBL_DEV_ID_DSP1_C66X (0xBAD00000)
+#define SBL_CLK_ID_DSP1_C66X (0xBAD00000)
+#define SBL_DSP1_C66X_FREQ_HZ (0xBAD00000)
+
+#define SBL_PROC_ID_DSP2_C66X (0xBAD00000)
+#define SBL_DEV_ID_DSP2_C66X (0xBAD00000)
+#define SBL_CLK_ID_DSP2_C66X (0xBAD00000)
+#define SBL_DSP2_C66X_FREQ_HZ (0xBAD00000)
+
+#define SBL_PROC_ID_DSP1_C7X (SCICLIENT_PROC_ID_COMPUTE_CLUSTER0_C71SS0_0)
+#define SBL_DEV_ID_DSP1_C7X (TISCI_DEV_COMPUTE_CLUSTER0_C71SS0_0)
+#define SBL_CLK_ID_DSP1_C7X (TISCI_DEV_COMPUTE_CLUSTER0_C71SS0_0_C7X_CLK)
+#define SBL_DSP1_C7X_FREQ_HZ (1000000000)
+
+#define SBL_PROC_ID_DSP2_C7X (SCICLIENT_PROC_ID_COMPUTE_CLUSTER0_C71SS1_0)
+#define SBL_DEV_ID_DSP2_C7X (TISCI_DEV_COMPUTE_CLUSTER0_C71SS1_0)
+#define SBL_CLK_ID_DSP2_C7X (TISCI_DEV_COMPUTE_CLUSTER0_C71SS1_0_C7X_CLK)
+#define SBL_DSP2_C7X_FREQ_HZ (1000000000)
+
+#define SBL_PROC_ID_M4F_CPU0 (0xBAD00000)
+#define SBL_DEV_ID_M4F_CPU0 (0xBAD00000)
+#define SBL_CLK_ID_M4F_CPU0 (0xBAD00000)
+#define SBL_M4F_CPU0_FREQ_HZ (0xBAD00000)
+
+#if defined (SBL_ENABLE_DEV_GRP_MCU)
+#define SBL_PLL_INIT (BOARD_INIT_PLL_MCU)
+#define SBL_CLOCK_INIT (BOARD_INIT_MODULE_CLOCK_MCU)
+#define SBL_DEVGRP (DEVGRP_00) /* MCU-wakeup DEVGRP */
+#else
+#define SBL_PLL_INIT (BOARD_INIT_PLL)
+#define SBL_CLOCK_INIT (BOARD_INIT_MODULE_CLOCK)
+#define SBL_DEVGRP (DEVGRP_ALL)
+#endif
+
+#define SBL_HYPERFLASH_BASE_ADDRESS (CSL_MCU_FSS0_DAT_REG1_BASE)
+#define SBL_HYPERFLASH_CTLR_BASE_ADDRESS (CSL_MCU_FSS0_HPB_CTRL_BASE)
+
+#endif /* if defined (SOC_J721S2) */
+
+
#if defined (SOC_AM64X)
#define SBL_MCU_ATCM_BASE (CSL_R5FSS0_ATCM_BASE)