diff --git a/packages/ti/diag/sdr/src/j721e/sdr_ecc_soc.h b/packages/ti/diag/sdr/src/j721e/sdr_ecc_soc.h
index 167eb4440378ec74f509766f45af154eb3f9cfcb..5ba16d096de845da53bb02c35f75124084709ddc 100644 (file)
#define SDR_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDR_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES (2U)
-#define SDR_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES (49U)
+#define SDR_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES (CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS)
+
+#define SDR_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES (CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS)
/** ------------------------------------------------------------------------------------
* @brief This structure holds the list of Ram Ids for each memory subtype in MCU domain
@@ -316,8 +318,8 @@ CSL_ecc_aggrRegs * SDR_ECC_aggrHighBaseAddressTableTrans[SDR_ECC_AGGREGATOR_MAX_
*/
/* Note: While this table lists all the possible RAM ID's for the MSMC AGGR0, only the following
* 2 RAM ID's have been tested:
- * CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_RAM_ID= 20 (Interconnect type)
- * CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_CLEC_SRAM_RAM_ID= 100 (Wrapper type) */
+ * CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_RAM_ID = 20 (Interconnect type)
+ * CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID = 100 (Wrapper type) */
const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES] =
{
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_RAM_ID,
@@ -338,11 +340,9 @@ const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TAB
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_ECC_TYPE }, // 5
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_ECC_TYPE }, // 6
-#endif
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 6
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_ECC_TYPE }, // 7
@@ -370,11 +370,9 @@ const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TAB
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_ECC_TYPE }, // 15
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ATTR_EDC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ATTR_EDC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ATTR_EDC_DUMMY_ECC_TYPE }, // 16
-#endif
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 16
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_ECC_TYPE }, // 17
@@ -414,52 +412,48 @@ const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TAB
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 29
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 30
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 31
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 32
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 33
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 34
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 35
-#endif
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 30
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 31
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 32
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 33
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 34
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 35
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 36
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 37
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 38
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 39
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 40
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 41
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 42
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 43
-#endif
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 38
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 39
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 40
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 41
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 42
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 43
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 44
@@ -478,62 +472,60 @@ const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TAB
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_ECC_TYPE }, // 49
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ECC_TYPE }, // 50
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 51
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 52
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_DATA_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_DATA_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_DATA_ECC_TYPE }, // 53
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_ECC_TYPE }, // 54
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ECC_TYPE }, // 55
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 56
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 57
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_DATA_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_DATA_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_DATA_ECC_TYPE }, // 58
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_ECC_TYPE }, // 59
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ECC_TYPE }, // 60
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 61
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 62
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_DATA_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_DATA_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_DATA_ECC_TYPE }, // 63
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_ECC_TYPE }, // 64
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ECC_TYPE }, // 65
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 66
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 67
-#endif
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 50
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 51
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 52
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 53
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 54
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 55
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 56
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 57
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 58
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 59
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 60
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 61
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 62
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 63
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 64
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 65
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 66
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 67
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_ECC_TYPE }, // 68
@@ -633,22 +625,18 @@ const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TAB
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ECC_TYPE }, // 100
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_ECC_TYPE }, // 101
-#endif
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 101
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE }, // 102
-#if 0
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_SLV_PIPE_BUSECC_DUMMY_RAM_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_SLV_PIPE_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_SLV_PIPE_BUSECC_DUMMY_ECC_TYPE }, // 103
- { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_MST_PIPE_BUSECC_DUMMY_ID,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_MST_PIPE_BUSECC_DUMMY_INJECT_TYPE,
- CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_MST_PIPE_BUSECC_DUMMY_ECC_TYPE }, // 104
-#endif
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 103
+ { SDR_ECC_RAMID_INVALID,
+ SDR_ECC_INJECTTYPE_INVALID,
+ SDR_ECC_ECC_TYPE_INVALD }, // 104
{ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_RAM_ID,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_INJECT_TYPE,
CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_ECC_TYPE }, // 105
@@ -698,63 +686,186 @@ const SDR_MemConfig_t SDR_ECC_MCUCBASSMemEntries[SDR_MCU_CBASS_WRAPPER_RAM_IDS_T
/** ----------------------------------------------------------------------------------
* @brief This structure holds the ECC interconnect Group Checker information for
- * SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_RAM_ID RAM ID
+ * SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID RAM ID
* -----------------------------------------------------------------------------------
*/
-const SDR_GrpChkConfig_t SDR_ECC_ramIdVbusM2AxiEdcVectorGrpEntries[SDR_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES] =
+const SDR_GrpChkConfig_t SDR_ECC_ramIdVbusM2AxiEdcVectorGrpEntries[SDR_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES] =
{
- {SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 12u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 4u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 12u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 23u, 2u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 10u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 3u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 3u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 4u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_EDC, 32u, 7u},
- {SDR_ECC_GROUP_CHECKER_TYPE_EDC, 32u, 7u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 8u, 2u},
- {SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 10u, 2u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 3u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 3u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 4u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 4u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 10u, 2u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 7u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
- {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_WIDTH},
+ {CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_CHECKER_TYPE,
+ CSL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_WIDTH},
};
-// TODO - NEED TO ADD MSMC INTERCONNECT GROUP CHECKER FOR MSMC RAM ID
-
+/** ----------------------------------------------------------------------------------
+ * @brief This structure holds the ECC interconnect Group Checker information for
+ * SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE RAM ID
+ * -----------------------------------------------------------------------------------
+ */
+const SDR_GrpChkConfig_t SDR_ECC_ramIdMsmcMrrBuseccGrpEntries[SDR_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES] =
+{
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_0_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_0_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_1_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_1_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_2_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_2_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_3_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_3_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_4_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_4_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_5_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_5_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_6_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_6_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_7_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_7_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_8_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_8_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_9_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_9_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_10_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_10_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_11_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_11_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_12_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_12_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_13_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_13_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_14_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_14_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_15_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_15_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_16_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_16_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_17_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_17_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_18_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_18_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_19_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_19_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_20_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_20_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_21_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_21_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_22_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_22_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_23_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_23_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_24_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_24_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_25_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_25_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_26_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_26_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_27_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_27_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_28_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_28_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_29_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_29_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_30_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_30_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_31_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_31_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_32_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_32_WIDTH},
+ {CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_33_CHECKER_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_33_WIDTH},
+};
#endif /* INCLUDE_SDR_ECC_SOC_H_ */